From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7AE245948; Mon, 9 Sep 2024 10:28:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2529140B9D; Mon, 9 Sep 2024 10:28:24 +0200 (CEST) Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by mails.dpdk.org (Postfix) with ESMTP id DD08240280 for ; Sat, 7 Sep 2024 01:38:30 +0200 (CEST) Received: from mail.cstnet.cn (unknown [180.213.162.185]) by APP-01 (Coremail) with SMTP id qwCowADHzqJukttmUVelAQ--.11761S2; Sat, 07 Sep 2024 07:38:22 +0800 (CST) From: Jie Liu To: anatoly.burakov@intel.com Cc: dev@dpdk.org, Jie Liu Subject: [PATCH v2] net/sxe: add net driver sxe Date: Sat, 7 Sep 2024 07:38:19 +0800 Message-ID: <20240906233821.1423-1-liujie5@linkdatatechnology.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <20240906233740.1405-1-liujie5@linkdatatechnology.com> References: <20240906233740.1405-1-liujie5@linkdatatechnology.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowADHzqJukttmUVelAQ--.11761S2 X-Coremail-Antispam: 1UD129KBjvAXoWDKFWkJw15JFWDZw18Gr4Durg_yoWkuFyxWo WxGF15uFWUZr1fXwnIg3WxGF43XF9F93W3Jan8Za909FWagF13Jry0q347Ja1vyw1Fk34k Ca47Z3WUAa4jgrn7n29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUU5D7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2 x7M28EF7xvwVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWU JVW8JwA2z4x0Y4vEx4A2jsIE14v26r1j6r4UM28EF7xvwVC2z280aVCY1x0267AKxVWUJV W8JwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AKxVWUAVWUtwCFx2IqxVCFs4IE 7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI 8E67AF67kF1VAFwI0_Jrv_JF1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv2 0xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2js IE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZE Xa7VUbhvttUUUUU== X-Originating-IP: [180.213.162.185] X-CM-SenderInfo: xolxyxrhv6zxpqngt3pdwhux5qro0w31of0z/ X-Mailman-Approved-At: Mon, 09 Sep 2024 10:28:18 +0200 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adjust code implementation according to code style requirements. Signed-off-by: Jie Liu --- MAINTAINERS | 2 +- doc/guides/nics/features/sxe.ini | 1 + drivers/net/sxe-dpdk-0.0.0.0-src.tar.gz | Bin 0 -> 196888 bytes drivers/net/sxe.zip | Bin 0 -> 193908 bytes drivers/net/sxe/Makefile | 14 + drivers/net/sxe/base/docker_version | 4 - drivers/net/sxe/base/sxe_common.c | 18 +- drivers/net/sxe/base/sxe_compat_platform.h | 23 +- drivers/net/sxe/base/sxe_compat_version.h | 303 +- drivers/net/sxe/base/sxe_errno.h | 78 +- drivers/net/sxe/base/sxe_hw.c | 1263 +++------ drivers/net/sxe/base/sxe_hw.h | 928 +++--- drivers/net/sxe/base/sxe_logs.h | 132 +- drivers/net/sxe/base/sxe_offload_common.c | 9 +- drivers/net/sxe/base/sxe_queue_common.c | 97 +- drivers/net/sxe/base/sxe_queue_common.h | 177 +- drivers/net/sxe/base/sxe_rx_common.c | 79 +- drivers/net/sxe/base/sxe_rx_common.h | 3 +- drivers/net/sxe/base/sxe_tx_common.c | 6 +- drivers/net/sxe/base/sxe_types.h | 2 +- drivers/net/sxe/base/sxevf_hw.c | 238 +- drivers/net/sxe/base/sxevf_hw.h | 139 +- drivers/net/sxe/base/sxevf_regs.h | 182 +- drivers/net/sxe/include/drv_msg.h | 6 +- drivers/net/sxe/include/sxe/mgl/sxe_port.h | 37 +- drivers/net/sxe/include/sxe/sxe_cli.h | 247 +- drivers/net/sxe/include/sxe/sxe_hdc.h | 46 +- drivers/net/sxe/include/sxe/sxe_ioctl.h | 10 +- drivers/net/sxe/include/sxe/sxe_msg.h | 124 +- drivers/net/sxe/include/sxe/sxe_regs.h | 880 +++--- drivers/net/sxe/include/sxe_type.h | 820 +++--- drivers/net/sxe/include/sxe_version.h | 31 +- drivers/net/sxe/meson.build | 14 + drivers/net/sxe/pf/sxe.h | 30 +- drivers/net/sxe/pf/sxe_dcb.c | 147 +- drivers/net/sxe/pf/sxe_dcb.h | 48 +- drivers/net/sxe/pf/sxe_ethdev.c | 117 +- drivers/net/sxe/pf/sxe_ethdev.h | 11 +- drivers/net/sxe/pf/sxe_filter.c | 125 +- drivers/net/sxe/pf/sxe_filter.h | 40 +- drivers/net/sxe/pf/sxe_filter_ctrl.c | 2951 ++++++++++++++++++++ drivers/net/sxe/pf/sxe_filter_ctrl.h | 153 + drivers/net/sxe/pf/sxe_flow_ctrl.c | 13 +- drivers/net/sxe/pf/sxe_flow_ctrl.h | 6 +- drivers/net/sxe/pf/sxe_fnav.c | 507 ++++ drivers/net/sxe/pf/sxe_fnav.h | 80 + drivers/net/sxe/pf/sxe_irq.c | 116 +- drivers/net/sxe/pf/sxe_irq.h | 15 +- drivers/net/sxe/pf/sxe_macsec.c | 260 ++ drivers/net/sxe/pf/sxe_macsec.h | 20 + drivers/net/sxe/pf/sxe_main.c | 27 +- drivers/net/sxe/pf/sxe_offload.c | 74 +- drivers/net/sxe/pf/sxe_offload.h | 4 +- drivers/net/sxe/pf/sxe_phy.c | 166 +- drivers/net/sxe/pf/sxe_phy.h | 57 +- drivers/net/sxe/pf/sxe_pmd_hdc.c | 168 +- drivers/net/sxe/pf/sxe_pmd_hdc.h | 28 +- drivers/net/sxe/pf/sxe_ptp.c | 14 +- drivers/net/sxe/pf/sxe_ptp.h | 4 +- drivers/net/sxe/pf/sxe_queue.c | 196 +- drivers/net/sxe/pf/sxe_queue.h | 34 +- drivers/net/sxe/pf/sxe_rx.c | 274 +- drivers/net/sxe/pf/sxe_rx.h | 41 +- drivers/net/sxe/pf/sxe_stats.c | 63 +- drivers/net/sxe/pf/sxe_stats.h | 8 +- drivers/net/sxe/pf/sxe_tm.c | 1115 ++++++++ drivers/net/sxe/pf/sxe_tm.h | 59 + drivers/net/sxe/pf/sxe_tx.c | 208 +- drivers/net/sxe/pf/sxe_tx.h | 2 +- drivers/net/sxe/pf/sxe_vec_common.h | 328 +++ drivers/net/sxe/pf/sxe_vec_neon.c | 606 ++++ drivers/net/sxe/pf/sxe_vec_sse.c | 634 +++++ drivers/net/sxe/pf/sxe_vf.c | 247 +- drivers/net/sxe/pf/sxe_vf.h | 114 +- drivers/net/sxe/rte_pmd_sxe_version.map | 2 +- drivers/net/sxe/version.map | 6 +- drivers/net/sxe/vf/sxevf.h | 8 +- drivers/net/sxe/vf/sxevf_ethdev.c | 169 +- drivers/net/sxe/vf/sxevf_filter.c | 119 +- drivers/net/sxe/vf/sxevf_filter.h | 35 +- drivers/net/sxe/vf/sxevf_irq.c | 90 +- drivers/net/sxe/vf/sxevf_irq.h | 4 +- drivers/net/sxe/vf/sxevf_main.c | 14 +- drivers/net/sxe/vf/sxevf_msg.c | 78 +- drivers/net/sxe/vf/sxevf_msg.h | 76 +- drivers/net/sxe/vf/sxevf_queue.c | 20 +- drivers/net/sxe/vf/sxevf_queue.h | 8 +- drivers/net/sxe/vf/sxevf_rx.c | 28 +- drivers/net/sxe/vf/sxevf_stats.c | 14 +- drivers/net/sxe/vf/sxevf_tx.c | 1 - 90 files changed, 10798 insertions(+), 4897 deletions(-) create mode 100644 drivers/net/sxe-dpdk-0.0.0.0-src.tar.gz create mode 100644 drivers/net/sxe.zip delete mode 100644 drivers/net/sxe/base/docker_version create mode 100644 drivers/net/sxe/pf/sxe_filter_ctrl.c create mode 100644 drivers/net/sxe/pf/sxe_filter_ctrl.h create mode 100644 drivers/net/sxe/pf/sxe_fnav.c create mode 100644 drivers/net/sxe/pf/sxe_fnav.h create mode 100644 drivers/net/sxe/pf/sxe_macsec.c create mode 100644 drivers/net/sxe/pf/sxe_macsec.h create mode 100644 drivers/net/sxe/pf/sxe_tm.c create mode 100644 drivers/net/sxe/pf/sxe_tm.h create mode 100644 drivers/net/sxe/pf/sxe_vec_common.h create mode 100644 drivers/net/sxe/pf/sxe_vec_neon.c create mode 100644 drivers/net/sxe/pf/sxe_vec_sse.c diff --git a/MAINTAINERS b/MAINTAINERS index 03adb4036f..e3d5c35093 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -982,7 +982,7 @@ F: doc/guides/nics/sfc_efx.rst F: doc/guides/nics/features/sfc.ini =20 Linkdata sxe -M: Jie Liu +M: Jie Li F: drivers/net/sxe/ F: doc/guides/nics/sxe.rst F: doc/guides/nics/features/sxe*.ini diff --git a/doc/guides/nics/features/sxe.ini b/doc/guides/nics/features/sx= e.ini index 5a18808ccf..b61ad7c699 100644 --- a/doc/guides/nics/features/sxe.ini +++ b/doc/guides/nics/features/sxe.ini @@ -35,6 +35,7 @@ VLAN offload =3D P QinQ offload =3D P L3 checksum offload =3D P L4 checksum offload =3D P +MACsec offload =3D P Inner L3 checksum =3D P Inner L4 checksum =3D P Packet type parsing =3D Y diff --git a/drivers/net/sxe-dpdk-0.0.0.0-src.tar.gz b/drivers/net/sxe-dpdk= -0.0.0.0-src.tar.gz new file mode 100644 index 0000000000000000000000000000000000000000..44a4c97fb4812e5dfaccd076888= a8c016231f80e GIT binary patch literal 196888 zcmV(^K-Iq=3DiwFSVJ=3Dtae1MEF(bK5qy{VM+oPCBzAdEG>$WLd4-%+Mrd^IETvl;hmq z9gHGTwytGKk?6$jw*UR&;6Z`_NIGrm-8&o3ZY-QP4h{|;1ksnT_K)$aZ~oG!iJy~` zWB6;H95=3DWl-%s~{VGw+N`&*q>^K1J*$0M{q{()wj`}@uMM0S(;gv z+C%Qxy+qDvFc=3DNd1wsekV$^aS7hn$_I&A|2GucgNFiO}wsu+$`sf(}M%}o5#*p z@ifD0m=3DhJbypI8acJXwD?)NFdxAA(uTpawXTj;NSr2hZmA%6JcS)jcCn`R5+^8LTl z>X=3D{q|8qRg(Ep_b@Mhvoyy6U?pfUS;wtASy#tYJ2f7!)6G(p?dG+AtR z_k{!>6GKe}I-Cp)<0r#9I`|!@ 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VLAN_PRIO_SHIFT 13 =20 static inline void set_bit(unsigned long nr, void *addr) { - int *m =3D ((int *)addr) + (nr >> 5); - *m |=3D 1 << (nr & 31); + int *m =3D ((int *)addr) + (nr >> 5); + *m |=3D 1 << (nr & 31); } =20 static inline int @@ -137,7 +137,6 @@ static inline u32 sxe_read_addr(const volatile void *ad= dr) static inline void sxe_write_addr(u32 value, volatile void *addr) { rte_write32((rte_cpu_to_le_32(value)), addr); - return; } =20 #endif diff --git a/drivers/net/sxe/base/sxe_compat_version.h b/drivers/net/sxe/ba= se/sxe_compat_version.h index 32d1a0862a..cf253309d8 100644 --- a/drivers/net/sxe/base/sxe_compat_version.h +++ b/drivers/net/sxe/base/sxe_compat_version.h @@ -19,7 +19,7 @@ int sxe_eth_dev_callback_process(struct rte_eth_dev *dev, =20 #define __rte_cold __attribute__((cold)) =20 -#define ETH_SPEED_NUM_UNKNOWN UINT32_MAX=20 +#define ETH_SPEED_NUM_UNKNOWN UINT32_MAX #ifdef RTE_ARCH_ARM64 #define RTE_ARCH_ARM #endif @@ -38,131 +38,129 @@ int sxe_eth_dev_callback_process(struct rte_eth_dev *= dev, =20 #if defined DPDK_20_11_5 || defined DPDK_19_11_6 =20 -#define RTE_ETH_RSS_IPV4 ETH_RSS_IPV4 -#define RTE_ETH_RSS_NONFRAG_IPV4_TCP ETH_RSS_NONFRAG_IPV4_TCP -#define RTE_ETH_RSS_NONFRAG_IPV4_UDP ETH_RSS_NONFRAG_IPV4_UDP -#define RTE_ETH_RSS_IPV6 ETH_RSS_IPV6 -#define RTE_ETH_RSS_NONFRAG_IPV6_TCP ETH_RSS_NONFRAG_IPV6_TCP -#define RTE_ETH_RSS_NONFRAG_IPV6_UDP ETH_RSS_NONFRAG_IPV6_UDP -#define RTE_ETH_RSS_IPV6_EX ETH_RSS_IPV6_EX -#define RTE_ETH_RSS_IPV6_TCP_EX ETH_RSS_IPV6_TCP_EX -#define RTE_ETH_RSS_IPV6_UDP_EX ETH_RSS_IPV6_UDP_EX +#define RTE_ETH_RSS_IPV4 ETH_RSS_IPV4 +#define RTE_ETH_RSS_NONFRAG_IPV4_TCP ETH_RSS_NONFRAG_IPV4_TCP +#define RTE_ETH_RSS_NONFRAG_IPV4_UDP ETH_RSS_NONFRAG_IPV4_UDP +#define RTE_ETH_RSS_IPV6 ETH_RSS_IPV6 +#define RTE_ETH_RSS_NONFRAG_IPV6_TCP ETH_RSS_NONFRAG_IPV6_TCP +#define RTE_ETH_RSS_NONFRAG_IPV6_UDP ETH_RSS_NONFRAG_IPV6_UDP +#define RTE_ETH_RSS_IPV6_EX ETH_RSS_IPV6_EX +#define RTE_ETH_RSS_IPV6_TCP_EX ETH_RSS_IPV6_TCP_EX +#define RTE_ETH_RSS_IPV6_UDP_EX ETH_RSS_IPV6_UDP_EX =20 =20 -#define RTE_ETH_VLAN_TYPE_UNKNOWN ETH_VLAN_TYPE_UNKNOWN -#define RTE_ETH_VLAN_TYPE_INNER ETH_VLAN_TYPE_INNER -#define RTE_ETH_VLAN_TYPE_OUTER ETH_VLAN_TYPE_OUTER -#define RTE_ETH_VLAN_TYPE_MAX ETH_VLAN_TYPE_MAX +#define RTE_ETH_VLAN_TYPE_UNKNOWN ETH_VLAN_TYPE_UNKNOWN +#define RTE_ETH_VLAN_TYPE_INNER ETH_VLAN_TYPE_INNER +#define RTE_ETH_VLAN_TYPE_OUTER ETH_VLAN_TYPE_OUTER +#define RTE_ETH_VLAN_TYPE_MAX ETH_VLAN_TYPE_MAX =20 =20 -#define RTE_ETH_8_POOLS ETH_8_POOLS -#define RTE_ETH_16_POOLS ETH_16_POOLS -#define RTE_ETH_32_POOLS ETH_32_POOLS -#define RTE_ETH_64_POOLS ETH_64_POOLS +#define RTE_ETH_8_POOLS ETH_8_POOLS +#define RTE_ETH_16_POOLS ETH_16_POOLS +#define RTE_ETH_32_POOLS ETH_32_POOLS +#define RTE_ETH_64_POOLS ETH_64_POOLS =20 =20 -#define RTE_ETH_4_TCS ETH_4_TCS -#define RTE_ETH_8_TCS ETH_8_TCS +#define RTE_ETH_4_TCS ETH_4_TCS +#define RTE_ETH_8_TCS ETH_8_TCS =20 =20 -#define RTE_ETH_MQ_RX_NONE ETH_MQ_RX_NONE -#define RTE_ETH_MQ_RX_RSS ETH_MQ_RX_RSS -#define RTE_ETH_MQ_RX_DCB ETH_MQ_RX_DCB -#define RTE_ETH_MQ_RX_DCB_RSS ETH_MQ_RX_DCB_RSS -#define RTE_ETH_MQ_RX_VMDQ_ONLY ETH_MQ_RX_VMDQ_ONLY -#define RTE_ETH_MQ_RX_VMDQ_RSS ETH_MQ_RX_VMDQ_RSS -#define RTE_ETH_MQ_RX_VMDQ_DCB ETH_MQ_RX_VMDQ_DCB +#define RTE_ETH_MQ_RX_NONE ETH_MQ_RX_NONE +#define RTE_ETH_MQ_RX_RSS ETH_MQ_RX_RSS +#define RTE_ETH_MQ_RX_DCB ETH_MQ_RX_DCB +#define RTE_ETH_MQ_RX_DCB_RSS ETH_MQ_RX_DCB_RSS +#define RTE_ETH_MQ_RX_VMDQ_ONLY ETH_MQ_RX_VMDQ_ONLY +#define RTE_ETH_MQ_RX_VMDQ_RSS ETH_MQ_RX_VMDQ_RSS +#define RTE_ETH_MQ_RX_VMDQ_DCB ETH_MQ_RX_VMDQ_DCB #define RTE_ETH_MQ_RX_VMDQ_DCB_RSS ETH_MQ_RX_VMDQ_DCB_RSS =20 =20 -#define RTE_ETH_MQ_TX_NONE ETH_MQ_TX_NONE -#define RTE_ETH_MQ_TX_DCB ETH_MQ_TX_DCB -#define RTE_ETH_MQ_TX_VMDQ_DCB ETH_MQ_TX_VMDQ_DCB -#define RTE_ETH_MQ_TX_VMDQ_ONLY ETH_MQ_TX_VMDQ_ONLY +#define RTE_ETH_MQ_TX_NONE ETH_MQ_TX_NONE +#define RTE_ETH_MQ_TX_DCB ETH_MQ_TX_DCB +#define RTE_ETH_MQ_TX_VMDQ_DCB ETH_MQ_TX_VMDQ_DCB +#define RTE_ETH_MQ_TX_VMDQ_ONLY ETH_MQ_TX_VMDQ_ONLY =20 =20 -#define RTE_ETH_FC_NONE RTE_FC_NONE -#define RTE_ETH_FC_RX_PAUSE RTE_FC_RX_PAUSE -#define RTE_ETH_FC_TX_PAUSE RTE_FC_TX_PAUSE -#define RTE_ETH_FC_FULL RTE_FC_FULL +#define RTE_ETH_FC_NONE RTE_FC_NONE +#define RTE_ETH_FC_RX_PAUSE RTE_FC_RX_PAUSE +#define RTE_ETH_FC_TX_PAUSE RTE_FC_TX_PAUSE +#define RTE_ETH_FC_FULL RTE_FC_FULL =20 =20 -#define RTE_ETH_MQ_RX_RSS_FLAG ETH_MQ_RX_RSS_FLAG -#define RTE_ETH_MQ_RX_DCB_FLAG ETH_MQ_RX_DCB_FLAG -#define RTE_ETH_MQ_RX_VMDQ_FLAG ETH_MQ_RX_VMDQ_FLAG +#define RTE_ETH_MQ_RX_RSS_FLAG ETH_MQ_RX_RSS_FLAG +#define RTE_ETH_MQ_RX_DCB_FLAG ETH_MQ_RX_DCB_FLAG +#define RTE_ETH_MQ_RX_VMDQ_FLAG ETH_MQ_RX_VMDQ_FLAG =20 =20 -#define RTE_ETH_RX_OFFLOAD_VLAN_STRIP DEV_RX_OFFLOAD_VLAN_STRIP -#define RTE_ETH_RX_OFFLOAD_IPV4_CKSUM DEV_RX_OFFLOAD_IPV4_CKSUM -#define RTE_ETH_RX_OFFLOAD_UDP_CKSUM DEV_RX_OFFLOAD_UDP_CKSUM -#define RTE_ETH_RX_OFFLOAD_TCP_CKSUM DEV_RX_OFFLOAD_TCP_CKSUM -#define RTE_ETH_RX_OFFLOAD_TCP_LRO DEV_RX_OFFLOAD_TCP_LRO -#define RTE_ETH_RX_OFFLOAD_QINQ_STRIP DEV_RX_OFFLOAD_QINQ_STRIP +#define RTE_ETH_RX_OFFLOAD_VLAN_STRIP DEV_RX_OFFLOAD_VLAN_STRIP +#define RTE_ETH_RX_OFFLOAD_IPV4_CKSUM DEV_RX_OFFLOAD_IPV4_CKSUM +#define RTE_ETH_RX_OFFLOAD_UDP_CKSUM DEV_RX_OFFLOAD_UDP_CKSUM +#define RTE_ETH_RX_OFFLOAD_TCP_CKSUM DEV_RX_OFFLOAD_TCP_CKSUM +#define RTE_ETH_RX_OFFLOAD_TCP_LRO DEV_RX_OFFLOAD_TCP_LRO +#define RTE_ETH_RX_OFFLOAD_QINQ_STRIP DEV_RX_OFFLOAD_QINQ_STRIP #define RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM -#define RTE_ETH_RX_OFFLOAD_MACSEC_STRIP DEV_RX_OFFLOAD_MACSEC_STRIP -#define RTE_ETH_RX_OFFLOAD_VLAN_FILTER DEV_RX_OFFLOAD_VLAN_FILTER -#define RTE_ETH_RX_OFFLOAD_VLAN_EXTEND DEV_RX_OFFLOAD_VLAN_EXTEND -#define RTE_ETH_RX_OFFLOAD_SCATTER DEV_RX_OFFLOAD_SCATTER -#define RTE_ETH_RX_OFFLOAD_TIMESTAMP DEV_RX_OFFLOAD_TIMESTAMP -#define RTE_ETH_RX_OFFLOAD_SECURITY DEV_RX_OFFLOAD_SECURITY -#define RTE_ETH_RX_OFFLOAD_KEEP_CRC DEV_RX_OFFLOAD_KEEP_CRC -#define RTE_ETH_RX_OFFLOAD_SCTP_CKSUM DEV_RX_OFFLOAD_SCTP_CKSUM +#define RTE_ETH_RX_OFFLOAD_MACSEC_STRIP DEV_RX_OFFLOAD_MACSEC_STRIP +#define RTE_ETH_RX_OFFLOAD_VLAN_FILTER DEV_RX_OFFLOAD_VLAN_FILTER +#define RTE_ETH_RX_OFFLOAD_VLAN_EXTEND DEV_RX_OFFLOAD_VLAN_EXTEND +#define RTE_ETH_RX_OFFLOAD_SCATTER DEV_RX_OFFLOAD_SCATTER +#define RTE_ETH_RX_OFFLOAD_TIMESTAMP DEV_RX_OFFLOAD_TIMESTAMP +#define RTE_ETH_RX_OFFLOAD_SECURITY DEV_RX_OFFLOAD_SECURITY +#define RTE_ETH_RX_OFFLOAD_KEEP_CRC DEV_RX_OFFLOAD_KEEP_CRC +#define RTE_ETH_RX_OFFLOAD_SCTP_CKSUM DEV_RX_OFFLOAD_SCTP_CKSUM #define RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM DEV_RX_OFFLOAD_OUTER_UDP_CKSUM -#define RTE_ETH_RX_OFFLOAD_RSS_HASH DEV_RX_OFFLOAD_RSS_HASH +#define RTE_ETH_RX_OFFLOAD_RSS_HASH DEV_RX_OFFLOAD_RSS_HASH =20 =20 -#define RTE_ETH_TX_OFFLOAD_VLAN_INSERT DEV_TX_OFFLOAD_VLAN_INSERT -#define RTE_ETH_TX_OFFLOAD_IPV4_CKSUM DEV_TX_OFFLOAD_IPV4_CKSUM -#define RTE_ETH_TX_OFFLOAD_UDP_CKSUM DEV_TX_OFFLOAD_UDP_CKSUM -#define RTE_ETH_TX_OFFLOAD_TCP_CKSUM DEV_TX_OFFLOAD_TCP_CKSUM -#define RTE_ETH_TX_OFFLOAD_SCTP_CKSUM DEV_TX_OFFLOAD_SCTP_CKSUM -#define RTE_ETH_TX_OFFLOAD_TCP_TSO DEV_TX_OFFLOAD_TCP_TSO -#define RTE_ETH_TX_OFFLOAD_UDP_TSO DEV_TX_OFFLOAD_UDP_TSO +#define RTE_ETH_TX_OFFLOAD_VLAN_INSERT DEV_TX_OFFLOAD_VLAN_INSERT +#define RTE_ETH_TX_OFFLOAD_IPV4_CKSUM DEV_TX_OFFLOAD_IPV4_CKSUM +#define RTE_ETH_TX_OFFLOAD_UDP_CKSUM DEV_TX_OFFLOAD_UDP_CKSUM +#define RTE_ETH_TX_OFFLOAD_TCP_CKSUM DEV_TX_OFFLOAD_TCP_CKSUM +#define RTE_ETH_TX_OFFLOAD_SCTP_CKSUM DEV_TX_OFFLOAD_SCTP_CKSUM +#define RTE_ETH_TX_OFFLOAD_TCP_TSO DEV_TX_OFFLOAD_TCP_TSO +#define RTE_ETH_TX_OFFLOAD_UDP_TSO DEV_TX_OFFLOAD_UDP_TSO #define RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM -#define RTE_ETH_TX_OFFLOAD_QINQ_INSERT DEV_TX_OFFLOAD_QINQ_INSERT -#define RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO DEV_TX_OFFLOAD_VXLAN_TNL_TSO -#define RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO DEV_TX_OFFLOAD_GRE_TNL_TSO -#define RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO DEV_TX_OFFLOAD_IPIP_TNL_TSO +#define RTE_ETH_TX_OFFLOAD_QINQ_INSERT DEV_TX_OFFLOAD_QINQ_INSERT +#define RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO DEV_TX_OFFLOAD_VXLAN_TNL_TSO +#define RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO DEV_TX_OFFLOAD_GRE_TNL_TSO +#define RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO DEV_TX_OFFLOAD_IPIP_TNL_TSO #define RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO DEV_TX_OFFLOAD_GENEVE_TNL_TSO -#define RTE_ETH_TX_OFFLOAD_MACSEC_INSERT DEV_TX_OFFLOAD_MACSEC_INSERT -#define RTE_ETH_TX_OFFLOAD_MT_LOCKFREE DEV_TX_OFFLOAD_MT_LOCKFREE -#define RTE_ETH_TX_OFFLOAD_MULTI_SEGS DEV_TX_OFFLOAD_MULTI_SEGS +#define RTE_ETH_TX_OFFLOAD_MACSEC_INSERT DEV_TX_OFFLOAD_MACSEC_INSERT +#define RTE_ETH_TX_OFFLOAD_MT_LOCKFREE DEV_TX_OFFLOAD_MT_LOCKFREE +#define RTE_ETH_TX_OFFLOAD_MULTI_SEGS DEV_TX_OFFLOAD_MULTI_SEGS #define RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE DEV_TX_OFFLOAD_MBUF_FAST_FREE -#define RTE_ETH_TX_OFFLOAD_SECURITY DEV_TX_OFFLOAD_SECURITY -#define RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO DEV_TX_OFFLOAD_UDP_TNL_TSO -#define RTE_ETH_TX_OFFLOAD_IP_TNL_TSO DEV_TX_OFFLOAD_IP_TNL_TSO +#define RTE_ETH_TX_OFFLOAD_SECURITY DEV_TX_OFFLOAD_SECURITY +#define RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO DEV_TX_OFFLOAD_UDP_TNL_TSO +#define RTE_ETH_TX_OFFLOAD_IP_TNL_TSO DEV_TX_OFFLOAD_IP_TNL_TSO #define RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM DEV_TX_OFFLOAD_OUTER_UDP_CKSUM #define RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP DEV_TX_OFFLOAD_SEND_ON_TIMEST= AMP =20 =20 -#define RTE_ETH_LINK_SPEED_AUTONEG ETH_LINK_SPEED_AUTONEG -#define RTE_ETH_LINK_SPEED_FIXED ETH_LINK_SPEED_FIXED -#define RTE_ETH_LINK_SPEED_1G ETH_LINK_SPEED_1G -#define RTE_ETH_LINK_SPEED_10G ETH_LINK_SPEED_10G +#define RTE_ETH_LINK_SPEED_AUTONEG ETH_LINK_SPEED_AUTONEG +#define RTE_ETH_LINK_SPEED_FIXED ETH_LINK_SPEED_FIXED +#define RTE_ETH_LINK_SPEED_1G ETH_LINK_SPEED_1G +#define RTE_ETH_LINK_SPEED_10G ETH_LINK_SPEED_10G =20 -#define RTE_ETH_SPEED_NUM_NONE ETH_SPEED_NUM_NONE -#define RTE_ETH_SPEED_NUM_1G ETH_SPEED_NUM_1G=20=20 -#define RTE_ETH_SPEED_NUM_10G ETH_SPEED_NUM_10G -#define RTE_ETH_SPEED_NUM_UNKNOWN ETH_SPEED_NUM_UNKNOWN +#define RTE_ETH_SPEED_NUM_NONE ETH_SPEED_NUM_NONE +#define RTE_ETH_SPEED_NUM_1G ETH_SPEED_NUM_1G +#define RTE_ETH_SPEED_NUM_10G ETH_SPEED_NUM_10G +#define RTE_ETH_SPEED_NUM_UNKNOWN ETH_SPEED_NUM_UNKNOWN =20 =20 -#define RTE_ETH_LINK_HALF_DUPLEX ETH_LINK_HALF_DUPLEX -#define RTE_ETH_LINK_FULL_DUPLEX ETH_LINK_FULL_DUPLEX -#define RTE_ETH_LINK_DOWN ETH_LINK_DOWN=20=20=20=20=20=20=20 -#define RTE_ETH_LINK_UP ETH_LINK_UP=20 +#define RTE_ETH_LINK_HALF_DUPLEX ETH_LINK_HALF_DUPLEX +#define RTE_ETH_LINK_FULL_DUPLEX ETH_LINK_FULL_DUPLEX +#define RTE_ETH_LINK_DOWN ETH_LINK_DOWN +#define RTE_ETH_LINK_UP ETH_LINK_UP =20 =20 -#define RTE_ETH_RSS_RETA_SIZE_128 ETH_RSS_RETA_SIZE_128 -#define RTE_ETH_RETA_GROUP_SIZE RTE_RETA_GROUP_SIZE - +#define RTE_ETH_RSS_RETA_SIZE_128 ETH_RSS_RETA_SIZE_128 +#define RTE_ETH_RETA_GROUP_SIZE RTE_RETA_GROUP_SIZE =20 #define RTE_ETH_VMDQ_MAX_VLAN_FILTERS ETH_VMDQ_MAX_VLAN_FILTERS #define RTE_ETH_DCB_NUM_USER_PRIORITIES ETH_DCB_NUM_USER_PRIORITIES -#define RTE_ETH_VMDQ_DCB_NUM_QUEUES ETH_VMDQ_DCB_NUM_QUEUES -#define RTE_ETH_DCB_NUM_QUEUES ETH_DCB_NUM_QUEUES - +#define RTE_ETH_VMDQ_DCB_NUM_QUEUES ETH_VMDQ_DCB_NUM_QUEUES +#define RTE_ETH_DCB_NUM_QUEUES ETH_DCB_NUM_QUEUES =20 -#define RTE_ETH_DCB_PFC_SUPPORT ETH_DCB_PFC_SUPPORT +#define RTE_ETH_DCB_PFC_SUPPORT ETH_DCB_PFC_SUPPORT =20 =20 #define RTE_ETH_VLAN_STRIP_OFFLOAD ETH_VLAN_STRIP_OFFLOAD @@ -170,74 +168,73 @@ int sxe_eth_dev_callback_process(struct rte_eth_dev *= dev, #define RTE_ETH_VLAN_EXTEND_OFFLOAD ETH_VLAN_EXTEND_OFFLOAD #define RTE_ETH_QINQ_STRIP_OFFLOAD ETH_QINQ_STRIP_OFFLOAD =20 -#define RTE_ETH_VLAN_STRIP_MASK ETH_VLAN_STRIP_MASK -#define RTE_ETH_VLAN_FILTER_MASK ETH_VLAN_FILTER_MASK -#define RTE_ETH_VLAN_EXTEND_MASK ETH_VLAN_EXTEND_MASK -#define RTE_ETH_QINQ_STRIP_MASK ETH_QINQ_STRIP_MASK -#define RTE_ETH_VLAN_ID_MAX ETH_VLAN_ID_MAX +#define RTE_ETH_VLAN_STRIP_MASK ETH_VLAN_STRIP_MASK +#define RTE_ETH_VLAN_FILTER_MASK ETH_VLAN_FILTER_MASK +#define RTE_ETH_VLAN_EXTEND_MASK ETH_VLAN_EXTEND_MASK +#define RTE_ETH_QINQ_STRIP_MASK ETH_QINQ_STRIP_MASK +#define RTE_ETH_VLAN_ID_MAX ETH_VLAN_ID_MAX =20 =20 #define RTE_ETH_NUM_RECEIVE_MAC_ADDR ETH_NUM_RECEIVE_MAC_ADDR #define RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY ETH_VMDQ_NUM_UC_HASH_ARRAY =20 -#define RTE_ETH_VMDQ_ACCEPT_UNTAG ETH_VMDQ_ACCEPT_UNTAG -#define RTE_ETH_VMDQ_ACCEPT_HASH_MC ETH_VMDQ_ACCEPT_HASH_MC -#define RTE_ETH_VMDQ_ACCEPT_HASH_UC ETH_VMDQ_ACCEPT_HASH_UC +#define RTE_ETH_VMDQ_ACCEPT_UNTAG ETH_VMDQ_ACCEPT_UNTAG +#define RTE_ETH_VMDQ_ACCEPT_HASH_MC ETH_VMDQ_ACCEPT_HASH_MC +#define RTE_ETH_VMDQ_ACCEPT_HASH_UC ETH_VMDQ_ACCEPT_HASH_UC #define RTE_ETH_VMDQ_ACCEPT_BROADCAST ETH_VMDQ_ACCEPT_BROADCAST #define RTE_ETH_VMDQ_ACCEPT_MULTICAST ETH_VMDQ_ACCEPT_MULTICAST =20 -#define RTE_VLAN_HLEN 4=20=20 - - -#define RTE_MBUF_F_RX_VLAN PKT_RX_VLAN -#define RTE_MBUF_F_RX_RSS_HASH PKT_RX_RSS_HASH -#define RTE_MBUF_F_RX_FDIR PKT_RX_FDIR -#define RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD PKT_RX_EIP_CKSUM_BAD -#define RTE_MBUF_F_RX_VLAN_STRIPPED PKT_RX_VLAN_STRIPPED -#define RTE_MBUF_F_RX_IP_CKSUM_MASK PKT_RX_IP_CKSUM_MASK -#define RTE_MBUF_F_RX_IP_CKSUM_UNKNOWN PKT_RX_IP_CKSUM_UNKNOWN -#define RTE_MBUF_F_RX_IP_CKSUM_BAD PKT_RX_IP_CKSUM_BAD -#define RTE_MBUF_F_RX_IP_CKSUM_GOOD PKT_RX_IP_CKSUM_GOOD -#define RTE_MBUF_F_RX_IP_CKSUM_NONE PKT_RX_IP_CKSUM_NONE -#define RTE_MBUF_F_RX_L4_CKSUM_MASK PKT_RX_L4_CKSUM_MASK -#define RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN PKT_RX_L4_CKSUM_UNKNOWN -#define RTE_MBUF_F_RX_L4_CKSUM_BAD PKT_RX_L4_CKSUM_BAD -#define RTE_MBUF_F_RX_L4_CKSUM_GOOD PKT_RX_L4_CKSUM_GOOD -#define RTE_MBUF_F_RX_L4_CKSUM_NONE PKT_RX_L4_CKSUM_NONE -#define RTE_MBUF_F_RX_IEEE1588_PTP PKT_RX_IEEE1588_PTP -#define RTE_MBUF_F_RX_IEEE1588_TMST PKT_RX_IEEE1588_TMST -#define RTE_MBUF_F_RX_FDIR_ID PKT_RX_FDIR_ID -#define RTE_MBUF_F_RX_FDIR_FLX PKT_RX_FDIR_FLX -#define RTE_MBUF_F_RX_QINQ_STRIPPED PKT_RX_QINQ_STRIPPED -#define RTE_MBUF_F_RX_LRO PKT_RX_LRO -#define RTE_MBUF_F_RX_SEC_OFFLOAD PKT_RX_SEC_OFFLOAD +#define RTE_VLAN_HLEN 4 + +#define RTE_MBUF_F_RX_VLAN PKT_RX_VLAN +#define RTE_MBUF_F_RX_RSS_HASH PKT_RX_RSS_HASH +#define RTE_MBUF_F_RX_FDIR PKT_RX_FDIR +#define RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD PKT_RX_EIP_CKSUM_BAD +#define RTE_MBUF_F_RX_VLAN_STRIPPED PKT_RX_VLAN_STRIPPED +#define RTE_MBUF_F_RX_IP_CKSUM_MASK PKT_RX_IP_CKSUM_MASK +#define RTE_MBUF_F_RX_IP_CKSUM_UNKNOWN PKT_RX_IP_CKSUM_UNKNOWN +#define RTE_MBUF_F_RX_IP_CKSUM_BAD PKT_RX_IP_CKSUM_BAD +#define RTE_MBUF_F_RX_IP_CKSUM_GOOD PKT_RX_IP_CKSUM_GOOD +#define RTE_MBUF_F_RX_IP_CKSUM_NONE PKT_RX_IP_CKSUM_NONE +#define RTE_MBUF_F_RX_L4_CKSUM_MASK PKT_RX_L4_CKSUM_MASK +#define RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN PKT_RX_L4_CKSUM_UNKNOWN +#define RTE_MBUF_F_RX_L4_CKSUM_BAD PKT_RX_L4_CKSUM_BAD +#define RTE_MBUF_F_RX_L4_CKSUM_GOOD PKT_RX_L4_CKSUM_GOOD +#define RTE_MBUF_F_RX_L4_CKSUM_NONE PKT_RX_L4_CKSUM_NONE +#define RTE_MBUF_F_RX_IEEE1588_PTP PKT_RX_IEEE1588_PTP +#define RTE_MBUF_F_RX_IEEE1588_TMST PKT_RX_IEEE1588_TMST +#define RTE_MBUF_F_RX_FDIR_ID PKT_RX_FDIR_ID +#define RTE_MBUF_F_RX_FDIR_FLX PKT_RX_FDIR_FLX +#define RTE_MBUF_F_RX_QINQ_STRIPPED PKT_RX_QINQ_STRIPPED +#define RTE_MBUF_F_RX_LRO PKT_RX_LRO +#define RTE_MBUF_F_RX_SEC_OFFLOAD PKT_RX_SEC_OFFLOAD #define RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED PKT_RX_SEC_OFFLOAD_FAILED -#define RTE_MBUF_F_RX_QINQ PKT_RX_QINQ - -#define RTE_MBUF_F_TX_SEC_OFFLOAD PKT_TX_SEC_OFFLOAD -#define RTE_MBUF_F_TX_MACSEC PKT_TX_MACSEC -#define RTE_MBUF_F_TX_QINQ PKT_TX_QINQ -#define RTE_MBUF_F_TX_TCP_SEG PKT_TX_TCP_SEG -#define RTE_MBUF_F_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST -#define RTE_MBUF_F_TX_L4_NO_CKSUM PKT_TX_L4_NO_CKSUM -#define RTE_MBUF_F_TX_TCP_CKSUM PKT_TX_TCP_CKSUM -#define RTE_MBUF_F_TX_SCTP_CKSUM PKT_TX_SCTP_CKSUM -#define RTE_MBUF_F_TX_UDP_CKSUM PKT_TX_UDP_CKSUM -#define RTE_MBUF_F_TX_L4_MASK PKT_TX_L4_MASK -#define RTE_MBUF_F_TX_IP_CKSUM PKT_TX_IP_CKSUM -#define RTE_MBUF_F_TX_IPV4 PKT_TX_IPV4 -#define RTE_MBUF_F_TX_IPV6 PKT_TX_IPV6 -#define RTE_MBUF_F_TX_VLAN PKT_TX_VLAN -#define RTE_MBUF_F_TX_OUTER_IP_CKSUM PKT_TX_OUTER_IP_CKSUM -#define RTE_MBUF_F_TX_OUTER_IPV4 PKT_TX_OUTER_IPV4 -#define RTE_MBUF_F_TX_OUTER_IPV6 PKT_TX_OUTER_IPV6 - -#define RTE_MBUF_F_TX_OFFLOAD_MASK PKT_TX_OFFLOAD_MASK - -#define RTE_ETH_8_POOLS ETH_8_POOLS -#define RTE_ETH_16_POOLS ETH_16_POOLS -#define RTE_ETH_32_POOLS ETH_32_POOLS -#define RTE_ETH_64_POOLS ETH_64_POOLS +#define RTE_MBUF_F_RX_QINQ PKT_RX_QINQ + +#define RTE_MBUF_F_TX_SEC_OFFLOAD PKT_TX_SEC_OFFLOAD +#define RTE_MBUF_F_TX_MACSEC PKT_TX_MACSEC +#define RTE_MBUF_F_TX_QINQ PKT_TX_QINQ +#define RTE_MBUF_F_TX_TCP_SEG PKT_TX_TCP_SEG +#define RTE_MBUF_F_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST +#define RTE_MBUF_F_TX_L4_NO_CKSUM PKT_TX_L4_NO_CKSUM +#define RTE_MBUF_F_TX_TCP_CKSUM PKT_TX_TCP_CKSUM +#define RTE_MBUF_F_TX_SCTP_CKSUM PKT_TX_SCTP_CKSUM +#define RTE_MBUF_F_TX_UDP_CKSUM PKT_TX_UDP_CKSUM +#define RTE_MBUF_F_TX_L4_MASK PKT_TX_L4_MASK +#define RTE_MBUF_F_TX_IP_CKSUM PKT_TX_IP_CKSUM +#define RTE_MBUF_F_TX_IPV4 PKT_TX_IPV4 +#define RTE_MBUF_F_TX_IPV6 PKT_TX_IPV6 +#define RTE_MBUF_F_TX_VLAN PKT_TX_VLAN +#define RTE_MBUF_F_TX_OUTER_IP_CKSUM PKT_TX_OUTER_IP_CKSUM +#define RTE_MBUF_F_TX_OUTER_IPV4 PKT_TX_OUTER_IPV4 +#define RTE_MBUF_F_TX_OUTER_IPV6 PKT_TX_OUTER_IPV6 + +#define RTE_MBUF_F_TX_OFFLOAD_MASK PKT_TX_OFFLOAD_MASK + +#define RTE_ETH_8_POOLS ETH_8_POOLS +#define RTE_ETH_16_POOLS ETH_16_POOLS +#define RTE_ETH_32_POOLS ETH_32_POOLS +#define RTE_ETH_64_POOLS ETH_64_POOLS =20 #ifdef RTE_LIBRTE_ETHDEV_DEBUG #define RTE_ETHDEV_DEBUG_RX @@ -248,7 +245,7 @@ int sxe_eth_dev_callback_process(struct rte_eth_dev *de= v, =20 #if defined DPDK_20_11_5 || defined DPDK_19_11_6 #define rte_eth_fdir_pballoc_type rte_fdir_pballoc_type -#define rte_eth_fdir_conf rte_fdir_conf +#define rte_eth_fdir_conf rte_fdir_conf =20 #define RTE_ETH_FDIR_PBALLOC_64K RTE_FDIR_PBALLOC_64K #define RTE_ETH_FDIR_PBALLOC_128K RTE_FDIR_PBALLOC_128K @@ -261,15 +258,15 @@ int sxe_eth_dev_callback_process(struct rte_eth_dev *= dev, (&((pci_dev)->intr_handle)) =20 #define SXE_DEV_FNAV_CONF(dev) \ - (&((dev)->data->dev_conf.fdir_conf))=20 + (&((dev)->data->dev_conf.fdir_conf)) #define SXE_GET_FRAME_SIZE(dev) \ (dev->data->dev_conf.rxmode.max_rx_pkt_len) -=09 + #elif defined DPDK_21_11_5 #define SXE_PCI_INTR_HANDLE(pci_dev) \ ((pci_dev)->intr_handle) #define SXE_DEV_FNAV_CONF(dev) \ - (&((dev)->data->dev_conf.fdir_conf))=20 + (&((dev)->data->dev_conf.fdir_conf)) #define SXE_GET_FRAME_SIZE(dev) \ (dev->data->mtu + SXE_ETH_OVERHEAD) =20 @@ -277,7 +274,7 @@ int sxe_eth_dev_callback_process(struct rte_eth_dev *de= v, #define SXE_PCI_INTR_HANDLE(pci_dev) \ ((pci_dev)->intr_handle) #define SXE_DEV_FNAV_CONF(dev) \ - (&((struct sxe_adapter *)(dev)->data->dev_private)->fnav_conf)=20 + (&((struct sxe_adapter *)(dev)->data->dev_private)->fnav_conf) #define RTE_ADAPTER_HAVE_FNAV_CONF #define SXE_GET_FRAME_SIZE(dev) \ (dev->data->mtu + SXE_ETH_OVERHEAD) diff --git a/drivers/net/sxe/base/sxe_errno.h b/drivers/net/sxe/base/sxe_er= rno.h index e4de8bef29..3d14e0794c 100644 --- a/drivers/net/sxe/base/sxe_errno.h +++ b/drivers/net/sxe/base/sxe_errno.h @@ -17,45 +17,45 @@ #define SXE_ERR_VF(errcode) SXE_ERR_MODULE(SXE_ERR_MODULE_VF, errcode) #define SXE_ERR_HDC(errcode) SXE_ERR_MODULE(SXE_ERR_MODULE_HDC, errcode) =20 -#define SXE_ERR_CONFIG EINVAL -#define SXE_ERR_PARAM EINVAL -#define SXE_ERR_RESET_FAILED EPERM -#define SXE_ERR_NO_SPACE ENOSPC -#define SXE_ERR_FNAV_CMD_INCOMPLETE EBUSY -#define SXE_ERR_MBX_LOCK_FAIL EBUSY -#define SXE_ERR_OPRATION_NOT_PERM EPERM -#define SXE_ERR_LINK_STATUS_INVALID EINVAL -#define SXE_ERR_LINK_SPEED_INVALID EINVAL -#define SXE_ERR_DEVICE_NOT_SUPPORTED EOPNOTSUPP -#define SXE_ERR_HDC_LOCK_BUSY EBUSY -#define SXE_ERR_HDC_FW_OV_TIMEOUT ETIMEDOUT -#define SXE_ERR_MDIO_CMD_TIMEOUT ETIMEDOUT -#define SXE_ERR_INVALID_LINK_SETTINGS EINVAL -#define SXE_ERR_FNAV_REINIT_FAILED EIO -#define SXE_ERR_CLI_FAILED EIO -#define SXE_ERR_MASTER_REQUESTS_PENDING SXE_ERR_PF(1) -#define SXE_ERR_SFP_NO_INIT_SEQ_PRESENT SXE_ERR_PF(2) -#define SXE_ERR_ENABLE_SRIOV_FAIL SXE_ERR_PF(3) -#define SXE_ERR_IPSEC_SA_STATE_NOT_EXSIT SXE_ERR_PF(4) -#define SXE_ERR_SFP_NOT_PERSENT SXE_ERR_PF(5) -#define SXE_ERR_PHY_NOT_PERSENT SXE_ERR_PF(6) -#define SXE_ERR_PHY_RESET_FAIL SXE_ERR_PF(7) -#define SXE_ERR_FC_NOT_NEGOTIATED SXE_ERR_PF(8) -#define SXE_ERR_SFF_NOT_SUPPORTED SXE_ERR_PF(9) +#define SXE_ERR_CONFIG EINVAL +#define SXE_ERR_PARAM EINVAL +#define SXE_ERR_RESET_FAILED EPERM +#define SXE_ERR_NO_SPACE ENOSPC +#define SXE_ERR_FNAV_CMD_INCOMPLETE EBUSY +#define SXE_ERR_MBX_LOCK_FAIL EBUSY +#define SXE_ERR_OPRATION_NOT_PERM EPERM +#define SXE_ERR_LINK_STATUS_INVALID EINVAL +#define SXE_ERR_LINK_SPEED_INVALID EINVAL +#define SXE_ERR_DEVICE_NOT_SUPPORTED EOPNOTSUPP +#define SXE_ERR_HDC_LOCK_BUSY EBUSY +#define SXE_ERR_HDC_FW_OV_TIMEOUT ETIMEDOUT +#define SXE_ERR_MDIO_CMD_TIMEOUT ETIMEDOUT +#define SXE_ERR_INVALID_LINK_SETTINGS EINVAL +#define SXE_ERR_FNAV_REINIT_FAILED EIO +#define SXE_ERR_CLI_FAILED EIO +#define SXE_ERR_MASTER_REQUESTS_PENDING SXE_ERR_PF(1) +#define SXE_ERR_SFP_NO_INIT_SEQ_PRESENT SXE_ERR_PF(2) +#define SXE_ERR_ENABLE_SRIOV_FAIL SXE_ERR_PF(3) +#define SXE_ERR_IPSEC_SA_STATE_NOT_EXSIT SXE_ERR_PF(4) +#define SXE_ERR_SFP_NOT_PERSENT SXE_ERR_PF(5) +#define SXE_ERR_PHY_NOT_PERSENT SXE_ERR_PF(6) +#define SXE_ERR_PHY_RESET_FAIL SXE_ERR_PF(7) +#define SXE_ERR_FC_NOT_NEGOTIATED SXE_ERR_PF(8) +#define SXE_ERR_SFF_NOT_SUPPORTED SXE_ERR_PF(9) =20 -#define SXEVF_ERR_MAC_ADDR_INVALID EINVAL -#define SXEVF_ERR_RESET_FAILED EIO -#define SXEVF_ERR_ARGUMENT_INVALID EINVAL -#define SXEVF_ERR_NOT_READY EBUSY -#define SXEVF_ERR_POLL_ACK_FAIL EIO -#define SXEVF_ERR_POLL_MSG_FAIL EIO -#define SXEVF_ERR_MBX_LOCK_FAIL EBUSY -#define SXEVF_ERR_REPLY_INVALID EINVAL -#define SXEVF_ERR_IRQ_NUM_INVALID EINVAL -#define SXEVF_ERR_PARAM EINVAL -#define SXEVF_ERR_MAILBOX_FAIL SXE_ERR_VF(1) -#define SXEVF_ERR_MSG_HANDLE_ERR SXE_ERR_VF(2) -#define SXEVF_ERR_DEVICE_NOT_SUPPORTED SXE_ERR_VF(3) -#define SXEVF_ERR_IPSEC_SA_STATE_NOT_EXSIT SXE_ERR_VF(4) +#define SXEVF_ERR_MAC_ADDR_INVALID EINVAL +#define SXEVF_ERR_RESET_FAILED EIO +#define SXEVF_ERR_ARGUMENT_INVALID EINVAL +#define SXEVF_ERR_NOT_READY EBUSY +#define SXEVF_ERR_POLL_ACK_FAIL EIO +#define SXEVF_ERR_POLL_MSG_FAIL EIO +#define SXEVF_ERR_MBX_LOCK_FAIL EBUSY +#define SXEVF_ERR_REPLY_INVALID EINVAL +#define SXEVF_ERR_IRQ_NUM_INVALID EINVAL +#define SXEVF_ERR_PARAM EINVAL +#define SXEVF_ERR_MAILBOX_FAIL SXE_ERR_VF(1) +#define SXEVF_ERR_MSG_HANDLE_ERR SXE_ERR_VF(2) +#define SXEVF_ERR_DEVICE_NOT_SUPPORTED SXE_ERR_VF(3) +#define SXEVF_ERR_IPSEC_SA_STATE_NOT_EXSIT SXE_ERR_VF(4) =20 #endif diff --git a/drivers/net/sxe/base/sxe_hw.c b/drivers/net/sxe/base/sxe_hw.c index 14d1d67456..78c56d2bd9 100644 --- a/drivers/net/sxe/base/sxe_hw.c +++ b/drivers/net/sxe/base/sxe_hw.c @@ -4,7 +4,7 @@ #ifdef SXE_PHY_CONFIGURE #include #endif -#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST) +#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST) #include "sxe_pci.h" #include "sxe_log.h" #include "sxe_debug.h" @@ -24,25 +24,25 @@ =20 #define SXE_MSGID_MASK (0xFFFFFFFF) =20 -#define SXE_CTRL_MSG_MASK (0x700) +#define SXE_CTRL_MSG_MASK (0x700) =20 -#define SXE_RING_WAIT_LOOP 10 -#define SXE_REG_NAME_LEN 16 +#define SXE_RING_WAIT_LOOP 10 +#define SXE_REG_NAME_LEN 16 #define SXE_DUMP_REG_STRING_LEN 73 -#define SXE_DUMP_REGS_NUM 64 -#define SXE_MAX_RX_DESC_POLL 10 -#define SXE_LPBK_EN 0x00000001 -#define SXE_MACADDR_LOW_4_BYTE 4 +#define SXE_DUMP_REGS_NUM 64 +#define SXE_MAX_RX_DESC_POLL 10 +#define SXE_LPBK_EN 0x00000001 +#define SXE_MACADDR_LOW_4_BYTE 4 #define SXE_MACADDR_HIGH_2_BYTE 2 -#define SXE_RSS_FIELD_MASK 0xffff0000 -#define SXE_MRQE_MASK 0x0000000f +#define SXE_RSS_FIELD_MASK 0xffff0000 +#define SXE_MRQE_MASK 0x0000000f =20 -#define SXE_HDC_DATA_LEN_MAX 256 +#define SXE_HDC_DATA_LEN_MAX 256 =20 #define SXE_8_TC_MSB (0x11111111) =20 -STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg); -STATIC void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value); +static u32 sxe_read_reg(struct sxe_hw *hw, u32 reg); +static void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value); static void sxe_write_reg64(struct sxe_hw *hw, u32 reg, u64 value); =20 #define SXE_WRITE_REG_ARRAY_32(a, reg, offset, value) \ @@ -50,7 +50,7 @@ static void sxe_write_reg64(struct sxe_hw *hw, u32 reg, u= 64 value); #define SXE_READ_REG_ARRAY_32(a, reg, offset) \ sxe_read_reg(a, reg + (offset << 2)) =20 -#define SXE_REG_READ(hw, addr) sxe_read_reg(hw, addr) +#define SXE_REG_READ(hw, addr) sxe_read_reg(hw, addr) #define SXE_REG_WRITE(hw, reg, value) sxe_write_reg(hw, reg, value) #define SXE_WRITE_FLUSH(a) sxe_read_reg(a, SXE_STATUS) #define SXE_REG_WRITE_ARRAY(hw, reg, offset, value) \ @@ -90,26 +90,21 @@ u16 sxe_mac_reg_num_get(void) } =20 =20 -#ifndef SXE_DPDK=20 +#ifndef SXE_DPDK =20 void sxe_hw_fault_handle(struct sxe_hw *hw) { struct sxe_adapter *adapter =3D hw->adapter; =20 - if (test_bit(SXE_HW_FAULT, &hw->state)) { - goto l_ret; - } + if (test_bit(SXE_HW_FAULT, &hw->state)) + return; =20 set_bit(SXE_HW_FAULT, &hw->state); =20 LOG_DEV_ERR("sxe nic hw fault\n"); =20 - if ((hw->fault_handle !=3D NULL) && (hw->priv !=3D NULL) ) { + if ((hw->fault_handle !=3D NULL) && (hw->priv !=3D NULL)) hw->fault_handle(hw->priv); - } - -l_ret: - return; } =20 static u32 sxe_hw_fault_check(struct sxe_hw *hw, u32 reg) @@ -118,32 +113,29 @@ static u32 sxe_hw_fault_check(struct sxe_hw *hw, u32 = reg) u8 __iomem *base_addr =3D hw->reg_base_addr; struct sxe_adapter *adapter =3D hw->adapter; =20 - if (sxe_is_hw_fault(hw)) { + if (sxe_is_hw_fault(hw)) goto l_out; - } =20 for (i =3D 0; i < SXE_REG_READ_RETRY; i++) { value =3D hw->reg_read(base_addr + SXE_STATUS); - if (value !=3D SXE_REG_READ_FAIL) { + if (value !=3D SXE_REG_READ_FAIL) break; - } =20 mdelay(3); } =20 - if (SXE_REG_READ_FAIL =3D=3D value) { + if (value =3D=3D SXE_REG_READ_FAIL) { LOG_ERROR_BDF("read registers multiple times failed, ret=3D%#x\n", value= ); sxe_hw_fault_handle(hw); - } else { + } else value =3D hw->reg_read(base_addr + reg); - } =20 return value; l_out: return SXE_REG_READ_FAIL; } =20 -STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg) +static u32 sxe_read_reg(struct sxe_hw *hw, u32 reg) { u32 value; u8 __iomem *base_addr =3D hw->reg_base_addr; @@ -155,7 +147,7 @@ STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg) } =20 value =3D hw->reg_read(base_addr + reg); - if (unlikely(SXE_REG_READ_FAIL =3D=3D value)) { + if (unlikely(value =3D=3D SXE_REG_READ_FAIL)) { LOG_ERROR_BDF("reg[0x%x] read failed, ret=3D%#x\n", reg, value); value =3D sxe_hw_fault_check(hw, reg); } @@ -164,32 +156,29 @@ STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg) return value; } =20 -STATIC void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value) +static void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value) { u8 __iomem *base_addr =3D hw->reg_base_addr; =20 - if (sxe_is_hw_fault(hw)) { - goto l_ret; - } + if (sxe_is_hw_fault(hw)) + return; =20 hw->reg_write(value, base_addr + reg); =20 -l_ret: - return; } =20 -#else=20 +#else =20 -STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg) +static u32 sxe_read_reg(struct sxe_hw *hw, u32 reg) { u32 i, value; u8 __iomem *base_addr =3D hw->reg_base_addr; =20 value =3D rte_le_to_cpu_32(rte_read32(base_addr + reg)); - if (unlikely(SXE_REG_READ_FAIL =3D=3D value)) { + if (unlikely(value =3D=3D SXE_REG_READ_FAIL)) { =20 value =3D rte_le_to_cpu_32(rte_read32(base_addr + SXE_STATUS)); - if (unlikely(SXE_REG_READ_FAIL !=3D value)) { + if (unlikely(value !=3D SXE_REG_READ_FAIL)) { =20 value =3D rte_le_to_cpu_32(rte_read32(base_addr + reg)); } else { @@ -198,16 +187,15 @@ STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg) for (i =3D 0; i < SXE_REG_READ_RETRY; i++) { =20 value =3D rte_le_to_cpu_32(rte_read32(base_addr + SXE_STATUS)); - if (unlikely(SXE_REG_READ_FAIL !=3D value)) { + if (unlikely(value !=3D SXE_REG_READ_FAIL)) { =20 value =3D rte_le_to_cpu_32(rte_read32(base_addr + reg)); LOG_INFO("reg[0x%x] read ok, value=3D%#x\n", reg, value); break; - } else { - LOG_ERROR("reg[0x%x] and reg[0x%x] read failed, ret=3D%#x\n", - reg, SXE_STATUS, value); } + LOG_ERROR("reg[0x%x] and reg[0x%x] read failed, ret=3D%#x\n", + reg, SXE_STATUS, value); =20 mdelay(3); } @@ -217,13 +205,12 @@ STATIC u32 sxe_read_reg(struct sxe_hw *hw, u32 reg) return value; } =20 -STATIC void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value) +static void sxe_write_reg(struct sxe_hw *hw, u32 reg, u32 value) { u8 __iomem *base_addr =3D hw->reg_base_addr; =20 rte_write32((rte_cpu_to_le_32(value)), (base_addr + reg)); =20 - return; } #endif =20 @@ -231,14 +218,11 @@ static void sxe_write_reg64(struct sxe_hw *hw, u32 re= g, u64 value) { u8 __iomem *reg_addr =3D hw->reg_base_addr; =20 - if (sxe_is_hw_fault(hw)) { - goto l_ret; - } + if (sxe_is_hw_fault(hw)) + return; =20 writeq(value, reg_addr + reg); =20 -l_ret: - return; } =20 =20 @@ -251,7 +235,6 @@ void sxe_hw_no_snoop_disable(struct sxe_hw *hw) SXE_REG_WRITE(hw, SXE_CTRL_EXT, ctrl_ext); SXE_WRITE_FLUSH(hw); =20 - return; } =20 s32 sxe_hw_uc_addr_pool_enable(struct sxe_hw *hw, @@ -291,21 +274,19 @@ static s32 sxe_hw_uc_addr_pool_disable(struct sxe_hw = *hw, u8 rar_idx) hi =3D SXE_REG_READ(hw, SXE_MPSAR_HIGH(rar_idx)); low =3D SXE_REG_READ(hw, SXE_MPSAR_LOW(rar_idx)); =20 - if (sxe_is_hw_fault(hw)) { + if (sxe_is_hw_fault(hw)) goto l_end; - } =20 if (!hi & !low) { LOG_DEBUG_BDF("no need clear rar-pool relation register.\n"); goto l_end; } =20 - if (low) { + if (low) SXE_REG_WRITE(hw, SXE_MPSAR_LOW(rar_idx), 0); - } - if (hi) { + + if (hi) SXE_REG_WRITE(hw, SXE_MPSAR_HIGH(rar_idx), 0); - } =20 =20 l_end: @@ -328,9 +309,9 @@ s32 sxe_hw_nic_reset(struct sxe_hw *hw) =20 for (i =3D 0; i < 10; i++) { ctrl =3D SXE_REG_READ(hw, SXE_CTRL); - if (!(ctrl & SXE_CTRL_RST_MASK)) { + if (!(ctrl & SXE_CTRL_RST_MASK)) break; - } + udelay(1); } =20 @@ -350,13 +331,11 @@ void sxe_hw_pf_rst_done_set(struct sxe_hw *hw) value |=3D SXE_CTRL_EXT_PFRSTD; SXE_REG_WRITE(hw, SXE_CTRL_EXT, value); =20 - return; } =20 static void sxe_hw_regs_flush(struct sxe_hw *hw) { SXE_WRITE_FLUSH(hw); - return; } =20 static const struct sxe_reg_info sxe_reg_info_tbl[] =3D { @@ -397,74 +376,74 @@ static void sxe_hw_reg_print(struct sxe_hw *hw, =20 switch (reginfo->addr) { case SXE_SRRCTL(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_SRRCTL(i)); - } + break; case SXE_RDLEN(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_RDLEN(i)); - } + break; case SXE_RDH(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_RDH(i)); - } + break; case SXE_RDT(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_RDT(i)); - } + break; case SXE_RXDCTL(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_RXDCTL(i)); - } + break; case SXE_RDBAL(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_RDBAL(i)); - } + break; case SXE_RDBAH(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_RDBAH(i)); - } + break; case SXE_TDBAL(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_TDBAL(i)); - } + break; case SXE_TDBAH(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_TDBAH(i)); - } + break; case SXE_TDLEN(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_TDLEN(i)); - } + break; case SXE_TDH(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_TDH(i)); - } + break; case SXE_TDT(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_TDT(i)); - } + break; case SXE_TXDCTL(0): - for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) { + for (i =3D 0; i < SXE_DUMP_REGS_NUM; i++) regs[i] =3D SXE_REG_READ(hw, SXE_TXDCTL(i)); - } + break; default: LOG_DEV_INFO("%-15s %08x\n", reginfo->name, SXE_REG_READ(hw, reginfo->addr)); - goto l_end; + return; } =20 while (first_reg_idx < SXE_DUMP_REGS_NUM) { @@ -473,15 +452,12 @@ static void sxe_hw_reg_print(struct sxe_hw *hw, "%s[%d-%d]", reginfo->name, first_reg_idx, (first_reg_idx + 7)); =20 - for (j =3D 0; j < 8; j++) { + for (j =3D 0; j < 8; j++) value +=3D sprintf(value, " %08x", regs[first_reg_idx++]); - } =20 LOG_DEV_ERR("%-15s%s\n", reg_name, buf); } =20 -l_end: - return; } =20 static void sxe_hw_reg_dump(struct sxe_hw *hw) @@ -489,11 +465,10 @@ static void sxe_hw_reg_dump(struct sxe_hw *hw) const struct sxe_reg_info *reginfo; =20 for (reginfo =3D (const struct sxe_reg_info *)sxe_reg_info_tbl; - reginfo->name; reginfo++) { + reginfo->name; reginfo++) { sxe_hw_reg_print(hw, reginfo); } =20 - return; } =20 static s32 sxe_hw_status_reg_test(struct sxe_hw *hw) @@ -539,22 +514,22 @@ struct sxe_self_test_reg { static const struct sxe_self_test_reg self_test_reg[] =3D { { SXE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFE0, 0x8007FFF0 }, { SXE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFE0, 0x8007FFF0 }, - { SXE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, + { SXE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, { SXE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, { SXE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, { SXE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, { SXE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, { SXE_RDLEN(0), 4, PATTERN_TEST, 0x000FFFFF, 0x000FFFFF }, { SXE_RXDCTL(0), 4, WRITE_NO_TEST, 0, SXE_RXDCTL_ENABLE }, - { SXE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, + { SXE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, { SXE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, { SXE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, { SXE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, { SXE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, - { SXE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, - { SXE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, - { SXE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, - { SXE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, + { SXE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, + { SXE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, + { SXE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, + { SXE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, { .reg =3D 0 } }; =20 @@ -625,7 +600,7 @@ static s32 sxe_hw_reg_set_and_check(struct sxe_hw *hw, = int reg, return ret; } =20 -STATIC s32 sxe_hw_regs_test(struct sxe_hw *hw) +static s32 sxe_hw_regs_test(struct sxe_hw *hw) { u32 i; s32 ret =3D 0; @@ -676,9 +651,8 @@ STATIC s32 sxe_hw_regs_test(struct sxe_hw *hw) break; } =20 - if (ret) { + if (ret) goto l_end; - } =20 } test++; @@ -716,7 +690,6 @@ static void sxe_hw_ring_irq_enable(struct sxe_hw *hw, u= 64 qmask) SXE_REG_WRITE(hw, SXE_EIMS_EX(1), mask1); } =20 - return; } =20 u32 sxe_hw_pending_irq_read_clear(struct sxe_hw *hw) @@ -727,7 +700,6 @@ u32 sxe_hw_pending_irq_read_clear(struct sxe_hw *hw) void sxe_hw_pending_irq_write_clear(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_EICR, value); - return; } =20 u32 sxe_hw_irq_cause_get(struct sxe_hw *hw) @@ -739,7 +711,6 @@ static void sxe_hw_event_irq_trigger(struct sxe_hw *hw) { SXE_REG_WRITE(hw, SXE_EICS, (SXE_EICS_TCP_TIMER | SXE_EICS_OTHER)); =20 - return; } =20 static void sxe_hw_ring_irq_trigger(struct sxe_hw *hw, u64 eics) @@ -750,7 +721,6 @@ static void sxe_hw_ring_irq_trigger(struct sxe_hw *hw, = u64 eics) SXE_REG_WRITE(hw, SXE_EICS_EX(0), mask); mask =3D (eics >> 32); SXE_REG_WRITE(hw, SXE_EICS_EX(1), mask); - return; } =20 void sxe_hw_ring_irq_auto_disable(struct sxe_hw *hw, @@ -763,14 +733,12 @@ void sxe_hw_ring_irq_auto_disable(struct sxe_hw *hw, SXE_REG_WRITE(hw, SXE_EIAM, SXE_EICS_RTX_QUEUE); } =20 - return; } =20 void sxe_hw_irq_general_reg_set(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_GPIE, value); =20 - return; } =20 u32 sxe_hw_irq_general_reg_get(struct sxe_hw *hw) @@ -782,7 +750,6 @@ static void sxe_hw_set_eitrsel(struct sxe_hw *hw, u32 v= alue) { SXE_REG_WRITE(hw, SXE_EITRSEL, value); =20 - return; } =20 void sxe_hw_event_irq_map(struct sxe_hw *hw, u8 offset, u16 irq_idx) @@ -800,7 +767,6 @@ void sxe_hw_event_irq_map(struct sxe_hw *hw, u8 offset,= u16 irq_idx) =20 SXE_REG_WRITE(hw, SXE_IVAR_MISC, ivar); =20 - return; } =20 void sxe_hw_ring_irq_map(struct sxe_hw *hw, bool is_tx, @@ -819,7 +785,6 @@ void sxe_hw_ring_irq_map(struct sxe_hw *hw, bool is_tx, =20 SXE_REG_WRITE(hw, SXE_IVAR(reg_idx >> 1), ivar); =20 - return; } =20 void sxe_hw_ring_irq_interval_set(struct sxe_hw *hw, @@ -831,7 +796,6 @@ void sxe_hw_ring_irq_interval_set(struct sxe_hw *hw, =20 SXE_REG_WRITE(hw, SXE_EITR(irq_idx), eitr); =20 - return; } =20 static void sxe_hw_event_irq_interval_set(struct sxe_hw *hw, @@ -839,28 +803,24 @@ static void sxe_hw_event_irq_interval_set(struct sxe_= hw *hw, { SXE_REG_WRITE(hw, SXE_EITR(irq_idx), value); =20 - return; } =20 void sxe_hw_event_irq_auto_clear_set(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_EIAC, value); =20 - return; } =20 void sxe_hw_specific_irq_disable(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_EIMC, value); =20 - return; } =20 void sxe_hw_specific_irq_enable(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_EIMS, value); =20 - return; } =20 void sxe_hw_all_irq_disable(struct sxe_hw *hw) @@ -872,7 +832,6 @@ void sxe_hw_all_irq_disable(struct sxe_hw *hw) =20 SXE_WRITE_FLUSH(hw); =20 - return; } =20 static void sxe_hw_spp_configure(struct sxe_hw *hw, u32 hw_spp_proc_delay_= us) @@ -882,7 +841,6 @@ static void sxe_hw_spp_configure(struct sxe_hw *hw, u32= hw_spp_proc_delay_us) ~SXE_SPP_PROC_DELAY_US_MASK) | hw_spp_proc_delay_us); =20 - return; } =20 static s32 sxe_hw_irq_test(struct sxe_hw *hw, u32 *icr, bool shared) @@ -985,13 +943,12 @@ u32 sxe_hw_link_speed_get(struct sxe_hw *hw) struct sxe_adapter *adapter =3D hw->adapter; value =3D SXE_REG_READ(hw, SXE_COMCTRL); =20 - if ((value & SXE_COMCTRL_SPEED_10G) =3D=3D SXE_COMCTRL_SPEED_10G) { + if ((value & SXE_COMCTRL_SPEED_10G) =3D=3D SXE_COMCTRL_SPEED_10G) speed =3D SXE_LINK_SPEED_10GB_FULL; - } else if ((value & SXE_COMCTRL_SPEED_1G) =3D=3D SXE_COMCTRL_SPEED_1G) { + else if ((value & SXE_COMCTRL_SPEED_1G) =3D=3D SXE_COMCTRL_SPEED_1G) speed =3D SXE_LINK_SPEED_1GB_FULL; - } else { + else speed =3D SXE_LINK_SPEED_UNKNOWN; - } =20 LOG_DEBUG_BDF("hw link speed=3D%x, (0x80=3D10G, 0x20=3D1G)\n, reg=3D%x", speed, value); @@ -1005,18 +962,17 @@ void sxe_hw_link_speed_set(struct sxe_hw *hw, u32 sp= eed) =20 ctrl =3D SXE_REG_READ(hw, SXE_COMCTRL); =20 - if (SXE_LINK_SPEED_1GB_FULL =3D=3D speed) { + if (speed =3D=3D SXE_LINK_SPEED_1GB_FULL) { ctrl |=3D SXE_COMCTRL_SPEED_1G; - } else if (SXE_LINK_SPEED_10GB_FULL =3D=3D speed) { + } else if (speed =3D=3D SXE_LINK_SPEED_10GB_FULL) { ctrl |=3D SXE_COMCTRL_SPEED_10G; } =20 SXE_REG_WRITE(hw, SXE_COMCTRL, ctrl); =20 - return; } =20 -STATIC bool sxe_hw_1g_link_up_check(struct sxe_hw *hw) +static bool sxe_hw_1g_link_up_check(struct sxe_hw *hw) { return (SXE_REG_READ(hw, SXE_LINKS) & SXE_LINKS_UP) ? true : false; } @@ -1036,9 +992,9 @@ bool sxe_hw_is_link_state_up(struct sxe_hw *hw) =20 link_speed =3D sxe_hw_link_speed_get(hw); if ((link_speed =3D=3D SXE_LINK_SPEED_10GB_FULL) && - (links_reg & SXE_10G_LINKS_DOWN)) { + (links_reg & SXE_10G_LINKS_DOWN)) ret =3D false; - } + } =20 return ret; @@ -1052,7 +1008,6 @@ void sxe_hw_mac_pad_enable(struct sxe_hw *hw) ctl |=3D SXE_MACCFG_PAD_EN; SXE_REG_WRITE(hw, SXE_MACCFG, ctl); =20 - return; } =20 s32 sxe_hw_fc_enable(struct sxe_hw *hw) @@ -1066,7 +1021,7 @@ s32 sxe_hw_fc_enable(struct sxe_hw *hw) =20 flctrl_val =3D SXE_REG_READ(hw, SXE_FLCTRL); flctrl_val &=3D ~(SXE_FCTRL_TFCE_MASK | SXE_FCTRL_RFCE_MASK | - SXE_FCTRL_TFCE_FCEN_MASK | SXE_FCTRL_TFCE_XONE_MASK); + SXE_FCTRL_TFCE_FCEN_MASK | SXE_FCTRL_TFCE_XONE_MASK); =20 switch (hw->fc.current_mode) { case SXE_FC_NONE: @@ -1089,7 +1044,7 @@ s32 sxe_hw_fc_enable(struct sxe_hw *hw) =20 for (i =3D 0; i < MAX_TRAFFIC_CLASS; i++) { if ((hw->fc.current_mode & SXE_FC_TX_PAUSE) && - hw->fc.high_water[i]) { + hw->fc.high_water[i]) { fcrtl =3D (hw->fc.low_water[i] << 9) | SXE_FCRTL_XONE; SXE_REG_WRITE(hw, SXE_FCRTL(i), fcrtl); fcrth =3D (hw->fc.high_water[i] << 9) | SXE_FCRTH_FCEN; @@ -1103,9 +1058,8 @@ s32 sxe_hw_fc_enable(struct sxe_hw *hw) =20 flctrl_val |=3D SXE_FCTRL_TFCE_DPF_EN; =20 - if ((hw->fc.current_mode & SXE_FC_TX_PAUSE)) { + if ((hw->fc.current_mode & SXE_FC_TX_PAUSE)) flctrl_val |=3D (SXE_FCTRL_TFCE_FCEN_MASK | SXE_FCTRL_TFCE_XONE_MASK); - } =20 SXE_REG_WRITE(hw, SXE_FLCTRL, flctrl_val); =20 @@ -1116,9 +1070,8 @@ s32 sxe_hw_fc_enable(struct sxe_hw *hw) SXE_REG_WRITE(hw, SXE_PFCTOP, reg); =20 reg =3D hw->fc.pause_time * 0x00010001U; - for (i =3D 0; i < (MAX_TRAFFIC_CLASS / 2); i++) { + for (i =3D 0; i < (MAX_TRAFFIC_CLASS / 2); i++) SXE_REG_WRITE(hw, SXE_FCTTV(i), reg); - } =20 SXE_REG_WRITE(hw, SXE_FCRTV, hw->fc.pause_time / 2); =20 @@ -1130,9 +1083,8 @@ void sxe_fc_autoneg_localcap_set(struct sxe_hw *hw) { u32 reg =3D 0; =20 - if (hw->fc.requested_mode =3D=3D SXE_FC_DEFAULT) { + if (hw->fc.requested_mode =3D=3D SXE_FC_DEFAULT) hw->fc.requested_mode =3D SXE_FC_FULL; - } =20 reg =3D SXE_REG_READ(hw, SXE_PCS1GANA); =20 @@ -1154,7 +1106,6 @@ void sxe_fc_autoneg_localcap_set(struct sxe_hw *hw) } =20 SXE_REG_WRITE(hw, SXE_PCS1GANA, reg); - return; } =20 s32 sxe_hw_pfc_enable(struct sxe_hw *hw, u8 tc_idx) @@ -1169,20 +1120,18 @@ s32 sxe_hw_pfc_enable(struct sxe_hw *hw, u8 tc_idx) =20 flctrl_val =3D SXE_REG_READ(hw, SXE_FLCTRL); flctrl_val &=3D ~(SXE_FCTRL_TFCE_MASK | SXE_FCTRL_RFCE_MASK | - SXE_FCTRL_TFCE_FCEN_MASK | SXE_FCTRL_TFCE_XONE_MASK); + SXE_FCTRL_TFCE_FCEN_MASK | SXE_FCTRL_TFCE_XONE_MASK); =20 switch (hw->fc.current_mode) { case SXE_FC_NONE: rx_en_num =3D 0; for (i =3D 0; i < MAX_TRAFFIC_CLASS; i++) { reg =3D SXE_REG_READ(hw, SXE_FCRTH(i)); - if (reg & SXE_FCRTH_FCEN) { + if (reg & SXE_FCRTH_FCEN) rx_en_num++; - } } - if (rx_en_num > 1) { + if (rx_en_num > 1) flctrl_val |=3D SXE_FCTRL_TFCE_PFC_EN; - } =20 break; =20 @@ -1192,14 +1141,12 @@ s32 sxe_hw_pfc_enable(struct sxe_hw *hw, u8 tc_idx) rx_en_num =3D 0; for (i =3D 0; i < MAX_TRAFFIC_CLASS; i++) { reg =3D SXE_REG_READ(hw, SXE_FCRTH(i)); - if (reg & SXE_FCRTH_FCEN) { + if (reg & SXE_FCRTH_FCEN) rx_en_num++; - } } =20 - if (rx_en_num > 1) { + if (rx_en_num > 1) flctrl_val |=3D SXE_FCTRL_TFCE_PFC_EN; - } =20 break; case SXE_FC_TX_PAUSE: @@ -1216,7 +1163,7 @@ s32 sxe_hw_pfc_enable(struct sxe_hw *hw, u8 tc_idx) } =20 if ((hw->fc.current_mode & SXE_FC_TX_PAUSE) && - hw->fc.high_water[tc_idx]) { + hw->fc.high_water[tc_idx]) { fcrtl =3D (hw->fc.low_water[tc_idx] << 9) | SXE_FCRTL_XONE; SXE_REG_WRITE(hw, SXE_FCRTL(tc_idx), fcrtl); fcrth =3D (hw->fc.high_water[tc_idx] << 9) | SXE_FCRTH_FCEN; @@ -1243,9 +1190,8 @@ s32 sxe_hw_pfc_enable(struct sxe_hw *hw, u8 tc_idx) SXE_REG_WRITE(hw, SXE_PFCTOP, reg); =20 reg =3D hw->fc.pause_time * 0x00010001U; - for (i =3D 0; i < (MAX_TRAFFIC_CLASS / 2); i++) { + for (i =3D 0; i < (MAX_TRAFFIC_CLASS / 2); i++) SXE_REG_WRITE(hw, SXE_FCTTV(i), reg); - } =20 SXE_REG_WRITE(hw, SXE_FCRTV, hw->fc.pause_time / 2); =20 @@ -1260,7 +1206,6 @@ void sxe_hw_crc_configure(struct sxe_hw *hw) ctrl |=3D SXE_PCCTRL_TXCE | SXE_PCCTRL_RXCE | SXE_PCCTRL_PCSC_ALL; SXE_REG_WRITE(hw, SXE_PCCTRL, ctrl); =20 - return; } =20 void sxe_hw_loopback_switch(struct sxe_hw *hw, bool is_enable) @@ -1271,7 +1216,6 @@ void sxe_hw_loopback_switch(struct sxe_hw *hw, bool i= s_enable) =20 SXE_REG_WRITE(hw, SXE_LPBKCTRL, value); =20 - return; } =20 void sxe_hw_mac_txrx_enable(struct sxe_hw *hw) @@ -1282,7 +1226,6 @@ void sxe_hw_mac_txrx_enable(struct sxe_hw *hw) ctl |=3D SXE_COMCTRL_TXEN | SXE_COMCTRL_RXEN | SXE_COMCTRL_EDSEL; SXE_REG_WRITE(hw, SXE_COMCTRL, ctl); =20 - return; } =20 void sxe_hw_mac_max_frame_set(struct sxe_hw *hw, u32 max_frame) @@ -1297,7 +1240,6 @@ void sxe_hw_mac_max_frame_set(struct sxe_hw *hw, u32 = max_frame) maxfs |=3D SXE_MAXFS_RFSEL | SXE_MAXFS_TFSEL; SXE_REG_WRITE(hw, SXE_MAXFS, maxfs); =20 - return; } =20 u32 sxe_hw_mac_max_frame_get(struct sxe_hw *hw) @@ -1324,14 +1266,13 @@ bool sxe_device_supports_autoneg_fc(struct sxe_hw *= hw) return supported; } =20 -STATIC void sxe_hw_fc_param_init(struct sxe_hw *hw) +static void sxe_hw_fc_param_init(struct sxe_hw *hw) { hw->fc.requested_mode =3D SXE_FC_FULL; - hw->fc.current_mode =3D SXE_FC_FULL;=09 + hw->fc.current_mode =3D SXE_FC_FULL; hw->fc.pause_time =3D SXE_DEFAULT_FCPAUSE; =20 hw->fc.disable_fc_autoneg =3D true; - return; } =20 void sxe_hw_fc_tc_high_water_mark_set(struct sxe_hw *hw, @@ -1339,7 +1280,6 @@ void sxe_hw_fc_tc_high_water_mark_set(struct sxe_hw *= hw, { hw->fc.high_water[tc_idx] =3D mark; =20 - return; } =20 void sxe_hw_fc_tc_low_water_mark_set(struct sxe_hw *hw, @@ -1347,7 +1287,6 @@ void sxe_hw_fc_tc_low_water_mark_set(struct sxe_hw *h= w, { hw->fc.low_water[tc_idx] =3D mark; =20 - return; } =20 bool sxe_hw_is_fc_autoneg_disabled(struct sxe_hw *hw) @@ -1359,7 +1298,6 @@ void sxe_hw_fc_autoneg_disable_set(struct sxe_hw *hw, bool is_disabled) { hw->fc.disable_fc_autoneg =3D is_disabled; - return; } =20 static enum sxe_fc_mode sxe_hw_fc_current_mode_get(struct sxe_hw *hw) @@ -1376,7 +1314,6 @@ void sxe_hw_fc_requested_mode_set(struct sxe_hw *hw, enum sxe_fc_mode mode) { hw->fc.requested_mode =3D mode; - return; } =20 static const struct sxe_mac_operations sxe_mac_ops =3D { @@ -1415,14 +1352,12 @@ u32 sxe_hw_pool_rx_mode_get(struct sxe_hw *hw, u16 = pool_idx) void sxe_hw_rx_mode_set(struct sxe_hw *hw, u32 filter_ctrl) { SXE_REG_WRITE(hw, SXE_FCTRL, filter_ctrl); - return; } =20 void sxe_hw_pool_rx_mode_set(struct sxe_hw *hw, u32 vmolr, u16 pool_idx) { SXE_REG_WRITE(hw, SXE_VMOLR(pool_idx), vmolr); - return; } =20 void sxe_hw_rx_lro_enable(struct sxe_hw *hw, bool is_enable) @@ -1430,12 +1365,10 @@ void sxe_hw_rx_lro_enable(struct sxe_hw *hw, bool i= s_enable) u32 rfctl =3D SXE_REG_READ(hw, SXE_RFCTL); rfctl &=3D ~SXE_RFCTL_LRO_DIS; =20 - if (!is_enable) { + if (!is_enable) rfctl |=3D SXE_RFCTL_LRO_DIS; - } =20 SXE_REG_WRITE(hw, SXE_RFCTL, rfctl); - return; } =20 void sxe_hw_rx_nfs_filter_disable(struct sxe_hw *hw) @@ -1444,7 +1377,6 @@ void sxe_hw_rx_nfs_filter_disable(struct sxe_hw *hw) =20 rfctl |=3D (SXE_RFCTL_NFSW_DIS | SXE_RFCTL_NFSR_DIS); SXE_REG_WRITE(hw, SXE_RFCTL, rfctl); - return; } =20 void sxe_hw_rx_udp_frag_checksum_disable(struct sxe_hw *hw) @@ -1454,7 +1386,6 @@ void sxe_hw_rx_udp_frag_checksum_disable(struct sxe_h= w *hw) rxcsum =3D SXE_REG_READ(hw, SXE_RXCSUM); rxcsum |=3D SXE_RXCSUM_PCSD; SXE_REG_WRITE(hw, SXE_RXCSUM, rxcsum); - return; } =20 void sxe_hw_fc_mac_addr_set(struct sxe_hw *hw, u8 *mac_addr) @@ -1462,16 +1393,15 @@ void sxe_hw_fc_mac_addr_set(struct sxe_hw *hw, u8 *= mac_addr) u32 mac_addr_h, mac_addr_l; =20 mac_addr_l =3D ((u32)mac_addr[5] | - ((u32)mac_addr[4] << 8) | - ((u32)mac_addr[3] << 16) | - ((u32)mac_addr[2] << 24)); + ((u32)mac_addr[4] << 8) | + ((u32)mac_addr[3] << 16) | + ((u32)mac_addr[2] << 24)); mac_addr_h =3D (((u32)mac_addr[1] << 16) | - ((u32)mac_addr[0] << 24)); + ((u32)mac_addr[0] << 24)); =20 SXE_REG_WRITE(hw, SXE_SACONH, mac_addr_h); SXE_REG_WRITE(hw, SXE_SACONL, mac_addr_l); =20 - return; } =20 s32 sxe_hw_uc_addr_add(struct sxe_hw *hw, u32 rar_idx, @@ -1542,7 +1472,6 @@ void sxe_hw_mta_hash_table_set(struct sxe_hw *hw, u8 index, u32 value) { SXE_REG_WRITE(hw, SXE_MTA(index), value); - return; } =20 void sxe_hw_mta_hash_table_update(struct sxe_hw *hw, @@ -1555,7 +1484,6 @@ void sxe_hw_mta_hash_table_update(struct sxe_hw *hw, LOG_INFO("mta update value:0x%x.\n", value); SXE_REG_WRITE(hw, SXE_MTA(reg_idx), value); =20 - return; } =20 void sxe_hw_mc_filter_enable(struct sxe_hw *hw) @@ -1564,7 +1492,6 @@ void sxe_hw_mc_filter_enable(struct sxe_hw *hw) =20 SXE_REG_WRITE(hw, SXE_MCSTCTRL, value); =20 - return; } =20 static void sxe_hw_mc_filter_disable(struct sxe_hw *hw) @@ -1575,7 +1502,6 @@ static void sxe_hw_mc_filter_disable(struct sxe_hw *h= w) =20 SXE_REG_WRITE(hw, SXE_MCSTCTRL, value); =20 - return; } =20 void sxe_hw_uc_addr_clear(struct sxe_hw *hw) @@ -1594,26 +1520,22 @@ void sxe_hw_uc_addr_clear(struct sxe_hw *hw) =20 LOG_DEV_DEBUG("clear %u uta filter addr register\n", SXE_UTA_ENTRY_NUM_MAX); - for (i =3D 0; i < SXE_UTA_ENTRY_NUM_MAX; i++) { + for (i =3D 0; i < SXE_UTA_ENTRY_NUM_MAX; i++) SXE_REG_WRITE(hw, SXE_UTA(i), 0); - } =20 SXE_REG_WRITE(hw, SXE_MCSTCTRL, SXE_MC_FILTER_TYPE0); =20 LOG_DEV_DEBUG("clear %u mta filter addr register\n", SXE_MTA_ENTRY_NUM_MAX); - for (i =3D 0; i < SXE_MTA_ENTRY_NUM_MAX; i++) { + for (i =3D 0; i < SXE_MTA_ENTRY_NUM_MAX; i++) SXE_REG_WRITE(hw, SXE_MTA(i), 0); - } =20 - return; } =20 static void sxe_hw_ethertype_filter_set(struct sxe_hw *hw, u8 filter_type, u32 value) { SXE_REG_WRITE(hw, SXE_ETQF(filter_type), value); - return; } =20 void sxe_hw_vt_ctrl_cfg(struct sxe_hw *hw, u8 default_pool) @@ -1622,14 +1544,13 @@ void sxe_hw_vt_ctrl_cfg(struct sxe_hw *hw, u8 defau= lt_pool) =20 ctrl =3D SXE_REG_READ(hw, SXE_VT_CTL); =20 - ctrl |=3D SXE_VT_CTL_VT_ENABLE;=20 + ctrl |=3D SXE_VT_CTL_VT_ENABLE; ctrl &=3D ~SXE_VT_CTL_POOL_MASK; ctrl |=3D default_pool << SXE_VT_CTL_POOL_SHIFT; - ctrl |=3D SXE_VT_CTL_REPLEN;=20 + ctrl |=3D SXE_VT_CTL_REPLEN; =20 SXE_REG_WRITE(hw, SXE_VT_CTL, ctrl); =20 - return; } =20 void sxe_hw_vt_disable(struct sxe_hw *hw) @@ -1640,7 +1561,6 @@ void sxe_hw_vt_disable(struct sxe_hw *hw) vmdctl &=3D ~SXE_VMD_CTL_POOL_EN; SXE_REG_WRITE(hw, SXE_VT_CTL, vmdctl); =20 - return; } =20 #ifdef SXE_WOL_CONFIGURE @@ -1649,7 +1569,6 @@ static void sxe_hw_wol_status_set(struct sxe_hw *hw) { SXE_REG_WRITE(hw, SXE_WUS, ~0); =20 - return; } =20 static void sxe_hw_wol_mode_set(struct sxe_hw *hw, u32 wol_status) @@ -1660,16 +1579,14 @@ static void sxe_hw_wol_mode_set(struct sxe_hw *hw, = u32 wol_status) =20 fctrl =3D SXE_REG_READ(hw, SXE_FCTRL); fctrl |=3D SXE_FCTRL_BAM; - if (wol_status & SXE_WUFC_MC) { + if (wol_status & SXE_WUFC_MC) fctrl |=3D SXE_FCTRL_MPE; - } =20 SXE_REG_WRITE(hw, SXE_FCTRL, fctrl); =20 SXE_REG_WRITE(hw, SXE_WUFC, wol_status); sxe_hw_wol_status_set(hw); =20 - return; } =20 static void sxe_hw_wol_mode_clean(struct sxe_hw *hw) @@ -1677,7 +1594,6 @@ static void sxe_hw_wol_mode_clean(struct sxe_hw *hw) SXE_REG_WRITE(hw, SXE_WUC, 0); SXE_REG_WRITE(hw, SXE_WUFC, 0); =20 - return; } #endif =20 @@ -1708,7 +1624,7 @@ static const struct sxe_filter_mac_operations sxe_fil= ter_mac_ops =3D { .wol_status_set =3D sxe_hw_wol_status_set, #endif =20 - .vt_disable =3D sxe_hw_vt_disable, + .vt_disable =3D sxe_hw_vt_disable, }; =20 u32 sxe_hw_vlan_pool_filter_read(struct sxe_hw *hw, u16 reg_index) @@ -1720,7 +1636,6 @@ static void sxe_hw_vlan_pool_filter_write(struct sxe_= hw *hw, u16 reg_index, u32 value) { SXE_REG_WRITE(hw, SXE_VLVF(reg_index), value); - return; } =20 static u32 sxe_hw_vlan_pool_filter_bitmap_read(struct sxe_hw *hw, @@ -1733,14 +1648,12 @@ static void sxe_hw_vlan_pool_filter_bitmap_write(st= ruct sxe_hw *hw, u16 reg_index, u32 value) { SXE_REG_WRITE(hw, SXE_VLVFB(reg_index), value); - return; } =20 void sxe_hw_vlan_filter_array_write(struct sxe_hw *hw, u16 reg_index, u32 value) { SXE_REG_WRITE(hw, SXE_VFTA(reg_index), value); - return; } =20 u32 sxe_hw_vlan_filter_array_read(struct sxe_hw *hw, u16 reg_index) @@ -1753,14 +1666,12 @@ void sxe_hw_vlan_filter_switch(struct sxe_hw *hw, b= ool is_enable) u32 vlnctrl; =20 vlnctrl =3D SXE_REG_READ(hw, SXE_VLNCTRL); - if (is_enable) { + if (is_enable) vlnctrl |=3D SXE_VLNCTRL_VFE; - } else { + else vlnctrl &=3D ~SXE_VLNCTRL_VFE; - } =20 SXE_REG_WRITE(hw, SXE_VLNCTRL, vlnctrl); - return; } =20 static void sxe_hw_vlan_untagged_pkts_rcv_switch(struct sxe_hw *hw, @@ -1768,15 +1679,13 @@ static void sxe_hw_vlan_untagged_pkts_rcv_switch(st= ruct sxe_hw *hw, { u32 vmolr =3D SXE_REG_READ(hw, SXE_VMOLR(vf)); vmolr |=3D SXE_VMOLR_BAM; - if (accept) { + if (accept) vmolr |=3D SXE_VMOLR_AUPE; - } else { + else vmolr &=3D ~SXE_VMOLR_AUPE; - } =20 LOG_WARN("vf:%u value:0x%x.\n", vf, vmolr); SXE_REG_WRITE(hw, SXE_VMOLR(vf), vmolr); - return; } =20 s32 sxe_hw_vlvf_slot_find(struct sxe_hw *hw, u32 vlan, bool vlvf_bypass) @@ -1801,14 +1710,12 @@ s32 sxe_hw_vlvf_slot_find(struct sxe_hw *hw, u32 vl= an, bool vlvf_bypass) goto l_end; } =20 - if (!first_empty_slot && !bits) { + if (!first_empty_slot && !bits) first_empty_slot =3D regindex; - } } =20 - if (!first_empty_slot) { + if (!first_empty_slot) LOG_DEV_WARN("no space in VLVF.\n"); - } =20 ret =3D first_empty_slot ? : -SXE_ERR_NO_SPACE; l_end: @@ -1839,15 +1746,13 @@ s32 sxe_hw_vlan_filter_configure(struct sxe_hw *hw, vfta_delta &=3D vlan_on ? ~vfta : vfta; vfta ^=3D vfta_delta; =20 - if (!(SXE_REG_READ(hw, SXE_VT_CTL) & SXE_VT_CTL_VT_ENABLE)) { + if (!(SXE_REG_READ(hw, SXE_VT_CTL) & SXE_VT_CTL_VT_ENABLE)) goto vfta_update; - } =20 vlvf_index =3D sxe_hw_vlvf_slot_find(hw, vid, vlvf_bypass); if (vlvf_index < 0) { - if (vlvf_bypass) { + if (vlvf_bypass) goto vfta_update; - } =20 ret =3D vlvf_index; goto l_end; @@ -1856,17 +1761,15 @@ s32 sxe_hw_vlan_filter_configure(struct sxe_hw *hw, bits =3D SXE_REG_READ(hw, SXE_VLVFB(vlvf_index * 2 + pool / 32)); =20 bits |=3D BIT(pool % 32); - if (vlan_on) { + if (vlan_on) goto vlvf_update; - } =20 bits ^=3D BIT(pool % 32); =20 if (!bits && - !SXE_REG_READ(hw, SXE_VLVFB(vlvf_index * 2 + 1 - pool / 32))) { - if (vfta_delta) { + !SXE_REG_READ(hw, SXE_VLVFB(vlvf_index * 2 + 1 - pool / 32))) { + if (vfta_delta) SXE_REG_WRITE(hw, SXE_VFTA(regidx), vfta); - } =20 SXE_REG_WRITE(hw, SXE_VLVF(vlvf_index), 0); SXE_REG_WRITE(hw, SXE_VLVFB(vlvf_index * 2 + pool / 32), 0); @@ -1881,9 +1784,8 @@ s32 sxe_hw_vlan_filter_configure(struct sxe_hw *hw, SXE_REG_WRITE(hw, SXE_VLVF(vlvf_index), SXE_VLVF_VIEN | vid); =20 vfta_update: - if (vfta_delta) { + if (vfta_delta) SXE_REG_WRITE(hw, SXE_VFTA(regidx), vfta); - } =20 l_end: return ret; @@ -1893,9 +1795,8 @@ void sxe_hw_vlan_filter_array_clear(struct sxe_hw *hw) { u32 offset; =20 - for (offset =3D 0; offset < SXE_VFT_TBL_SIZE; offset++) { + for (offset =3D 0; offset < SXE_VFT_TBL_SIZE; offset++) SXE_REG_WRITE(hw, SXE_VFTA(offset), 0); - } =20 for (offset =3D 0; offset < SXE_VLVF_ENTRIES; offset++) { SXE_REG_WRITE(hw, SXE_VLVF(offset), 0); @@ -1903,7 +1804,6 @@ void sxe_hw_vlan_filter_array_clear(struct sxe_hw *hw) SXE_REG_WRITE(hw, SXE_VLVFB(offset * 2 + 1), 0); } =20 - return; } =20 static const struct sxe_filter_vlan_operations sxe_filter_vlan_ops =3D { @@ -1924,56 +1824,51 @@ static void sxe_hw_rx_pkt_buf_switch(struct sxe_hw = *hw, bool is_on) { u32 dbucfg =3D SXE_REG_READ(hw, SXE_DRXCFG); =20 - if (is_on) { + if (is_on) dbucfg |=3D SXE_DRXCFG_DBURX_START; - } else { + else dbucfg &=3D ~SXE_DRXCFG_DBURX_START; - } =20 SXE_REG_WRITE(hw, SXE_DRXCFG, dbucfg); =20 - return; } =20 static void sxe_hw_rx_pkt_buf_size_configure(struct sxe_hw *hw, - u8 num_pb, - u32 headroom, - u16 strategy) + u8 num_pb, + u32 headroom, + u16 strategy) { u16 total_buf_size =3D (SXE_RX_PKT_BUF_SIZE - headroom); u32 rx_buf_size; u16 i =3D 0; =20 - if (!num_pb) { + if (!num_pb) num_pb =3D 1; - } =20 switch (strategy) { case (PBA_STRATEGY_WEIGHTED): rx_buf_size =3D ((total_buf_size * 5 * 2) / (num_pb * 8)); total_buf_size -=3D rx_buf_size * (num_pb / 2); rx_buf_size <<=3D SXE_RX_PKT_BUF_SIZE_SHIFT; - for (i =3D 0; i < (num_pb / 2); i++) { + for (i =3D 0; i < (num_pb / 2); i++) SXE_REG_WRITE(hw, SXE_RXPBSIZE(i), rx_buf_size); - } + fallthrough; case (PBA_STRATEGY_EQUAL): rx_buf_size =3D (total_buf_size / (num_pb - i)) << SXE_RX_PKT_BUF_SIZE_SHIFT; - for (; i < num_pb; i++) { + for (; i < num_pb; i++) SXE_REG_WRITE(hw, SXE_RXPBSIZE(i), rx_buf_size); - } + break; =20 default: break; } =20 - for (; i < SXE_PKG_BUF_NUM_MAX; i++) { + for (; i < SXE_PKG_BUF_NUM_MAX; i++) SXE_REG_WRITE(hw, SXE_RXPBSIZE(i), 0); - } =20 - return; } =20 u32 sxe_hw_rx_pkt_buf_size_get(struct sxe_hw *hw, u8 pb) @@ -1990,28 +1885,27 @@ void sxe_hw_rx_multi_ring_configure(struct sxe_hw *= hw, mrqc &=3D ~SXE_MRQE_MASK; =20 if (sriov_enable) { - if (tcs > 4) { - mrqc |=3D SXE_MRQC_VMDQRT8TCEN;=09 - } else if (tcs > 1) { - mrqc |=3D SXE_MRQC_VMDQRT4TCEN;=09 - } else if (is_4q_per_pool =3D=3D true) { + if (tcs > 4) + mrqc |=3D SXE_MRQC_VMDQRT8TCEN; + else if (tcs > 1) + mrqc |=3D SXE_MRQC_VMDQRT4TCEN; + else if (is_4q_per_pool =3D=3D true) mrqc |=3D SXE_MRQC_VMDQRSS32EN; - } else { + else mrqc |=3D SXE_MRQC_VMDQRSS64EN; - } + } else { - if (tcs > 4) { + if (tcs > 4) mrqc |=3D SXE_MRQC_RTRSS8TCEN; - } else if (tcs > 1) { + else if (tcs > 1) mrqc |=3D SXE_MRQC_RTRSS4TCEN; - } else { + else mrqc |=3D SXE_MRQC_RSSEN; - } + } =20 SXE_REG_WRITE(hw, SXE_MRQC, mrqc); =20 - return; } =20 static void sxe_hw_rss_hash_pkt_type_set(struct sxe_hw *hw, u32 version) @@ -2020,21 +1914,19 @@ static void sxe_hw_rss_hash_pkt_type_set(struct sxe= _hw *hw, u32 version) u32 rss_field =3D 0; =20 rss_field |=3D SXE_MRQC_RSS_FIELD_IPV4 | - SXE_MRQC_RSS_FIELD_IPV4_TCP | - SXE_MRQC_RSS_FIELD_IPV6 | - SXE_MRQC_RSS_FIELD_IPV6_TCP; + SXE_MRQC_RSS_FIELD_IPV4_TCP | + SXE_MRQC_RSS_FIELD_IPV6 | + SXE_MRQC_RSS_FIELD_IPV6_TCP; =20 - if (version =3D=3D SXE_RSS_IP_VER_4) { + if (version =3D=3D SXE_RSS_IP_VER_4) rss_field |=3D SXE_MRQC_RSS_FIELD_IPV4_UDP; - } - if (version =3D=3D SXE_RSS_IP_VER_6) { + + if (version =3D=3D SXE_RSS_IP_VER_6) rss_field |=3D SXE_MRQC_RSS_FIELD_IPV6_UDP; - } =20 mrqc |=3D rss_field; SXE_REG_WRITE(hw, SXE_MRQC, mrqc); =20 - return; } =20 static void sxe_hw_rss_hash_pkt_type_update(struct sxe_hw *hw, @@ -2045,23 +1937,21 @@ static void sxe_hw_rss_hash_pkt_type_update(struct = sxe_hw *hw, mrqc =3D SXE_REG_READ(hw, SXE_MRQC); =20 mrqc |=3D SXE_MRQC_RSS_FIELD_IPV4 - | SXE_MRQC_RSS_FIELD_IPV4_TCP - | SXE_MRQC_RSS_FIELD_IPV6 - | SXE_MRQC_RSS_FIELD_IPV6_TCP; + | SXE_MRQC_RSS_FIELD_IPV4_TCP + | SXE_MRQC_RSS_FIELD_IPV6 + | SXE_MRQC_RSS_FIELD_IPV6_TCP; =20 mrqc &=3D ~(SXE_MRQC_RSS_FIELD_IPV4_UDP | SXE_MRQC_RSS_FIELD_IPV6_UDP); =20 - if (version =3D=3D SXE_RSS_IP_VER_4) { + if (version =3D=3D SXE_RSS_IP_VER_4) mrqc |=3D SXE_MRQC_RSS_FIELD_IPV4_UDP; - } - if (version =3D=3D SXE_RSS_IP_VER_6) { + + if (version =3D=3D SXE_RSS_IP_VER_6) mrqc |=3D SXE_MRQC_RSS_FIELD_IPV6_UDP; - } =20 SXE_REG_WRITE(hw, SXE_MRQC, mrqc); =20 - return; } =20 static void sxe_hw_rss_rings_used_set(struct sxe_hw *hw, u32 rss_num, @@ -2069,35 +1959,29 @@ static void sxe_hw_rss_rings_used_set(struct sxe_hw= *hw, u32 rss_num, { u32 psrtype =3D 0; =20 - if (rss_num > 3) { + if (rss_num > 3) psrtype |=3D 2u << 29; - } else if (rss_num > 1) { + else if (rss_num > 1) psrtype |=3D 1u << 29; - } =20 - while (pool--) { + while (pool--) SXE_REG_WRITE(hw, SXE_PSRTYPE(pf_offset + pool), psrtype); - } =20 - return; } =20 void sxe_hw_rss_key_set_all(struct sxe_hw *hw, u32 *rss_key) { u32 i; =20 - for (i =3D 0; i < SXE_MAX_RSS_KEY_ENTRIES; i++) { + for (i =3D 0; i < SXE_MAX_RSS_KEY_ENTRIES; i++) SXE_REG_WRITE(hw, SXE_RSSRK(i), rss_key[i]); - } =20 - return; } =20 void sxe_hw_rss_redir_tbl_reg_write(struct sxe_hw *hw, u16 reg_idx, u32 value) { SXE_REG_WRITE(hw, SXE_RETA(reg_idx >> 2), value); - return; } =20 void sxe_hw_rss_redir_tbl_set_all(struct sxe_hw *hw, u8 *redir_tbl) @@ -2114,7 +1998,6 @@ void sxe_hw_rss_redir_tbl_set_all(struct sxe_hw *hw, = u8 *redir_tbl) tbl =3D 0; } } - return; } =20 void sxe_hw_rx_cap_switch_on(struct sxe_hw *hw) @@ -2132,7 +2015,6 @@ void sxe_hw_rx_cap_switch_on(struct sxe_hw *hw) rxctrl |=3D SXE_RXCTRL_RXEN; SXE_REG_WRITE(hw, SXE_RXCTRL, rxctrl); =20 - return; } =20 void sxe_hw_rx_cap_switch_off(struct sxe_hw *hw) @@ -2153,7 +2035,6 @@ void sxe_hw_rx_cap_switch_off(struct sxe_hw *hw) SXE_REG_WRITE(hw, SXE_RXCTRL, rxctrl); } =20 - return; } =20 static void sxe_hw_rx_func_switch_on(struct sxe_hw *hw) @@ -2164,7 +2045,6 @@ static void sxe_hw_rx_func_switch_on(struct sxe_hw *h= w) rxctrl |=3D SXE_COMCTRL_RXEN | SXE_COMCTRL_EDSEL; SXE_REG_WRITE(hw, SXE_COMCTRL, rxctrl); =20 - return; } =20 void sxe_hw_tx_pkt_buf_switch(struct sxe_hw *hw, bool is_on) @@ -2182,27 +2062,22 @@ void sxe_hw_tx_pkt_buf_switch(struct sxe_hw *hw, bo= ol is_on) SXE_REG_WRITE(hw, SXE_DTXCFG, dbucfg); } =20 - return; } =20 void sxe_hw_tx_pkt_buf_size_configure(struct sxe_hw *hw, u8 num_pb) { u32 i, tx_pkt_size; =20 - if (!num_pb){ + if (!num_pb) num_pb =3D 1; - } =20 tx_pkt_size =3D SXE_TX_PBSIZE_MAX / num_pb; - for (i =3D 0; i < num_pb; i++) { + for (i =3D 0; i < num_pb; i++) SXE_REG_WRITE(hw, SXE_TXPBSIZE(i), tx_pkt_size); - } =20 - for (; i < SXE_PKG_BUF_NUM_MAX; i++) { + for (; i < SXE_PKG_BUF_NUM_MAX; i++) SXE_REG_WRITE(hw, SXE_TXPBSIZE(i), 0); - } =20 - return; } =20 void sxe_hw_rx_lro_ack_switch(struct sxe_hw *hw, bool is_on) @@ -2217,7 +2092,6 @@ void sxe_hw_rx_lro_ack_switch(struct sxe_hw *hw, bool= is_on) =20 SXE_REG_WRITE(hw, SXE_LRODBU, lro_dbu); =20 - return; } =20 static void sxe_hw_vf_rx_switch(struct sxe_hw *hw, @@ -2232,10 +2106,9 @@ static void sxe_hw_vf_rx_switch(struct sxe_hw *hw, =20 SXE_REG_WRITE(hw, SXE_VFRE(reg_offset), vfre); =20 - return; } =20 -STATIC s32 sxe_hw_fnav_wait_init_done(struct sxe_hw *hw) +static s32 sxe_hw_fnav_wait_init_done(struct sxe_hw *hw) { u32 i; s32 ret =3D 0; @@ -2266,16 +2139,15 @@ void sxe_hw_fnav_enable(struct sxe_hw *hw, u32 fnav= ctrl) SXE_REG_WRITE(hw, SXE_FNAVSKEY, SXE_FNAV_SAMPLE_HASH_KEY); =20 fnavctrl_ori =3D SXE_REG_READ(hw, SXE_FNAVCTRL); - if((fnavctrl_ori & 0x13) !=3D (fnavctrl & 0x13)) { + if ((fnavctrl_ori & 0x13) !=3D (fnavctrl & 0x13)) is_clear_stat =3D true; - } =20 SXE_REG_WRITE(hw, SXE_FNAVCTRL, fnavctrl); SXE_WRITE_FLUSH(hw); =20 sxe_hw_fnav_wait_init_done(hw); =20 - if(is_clear_stat) { + if (is_clear_stat) { SXE_REG_READ(hw, SXE_FNAVUSTAT); SXE_REG_READ(hw, SXE_FNAVFSTAT); SXE_REG_READ(hw, SXE_FNAVMATCH); @@ -2283,7 +2155,6 @@ void sxe_hw_fnav_enable(struct sxe_hw *hw, u32 fnavct= rl) SXE_REG_READ(hw, SXE_FNAVLEN); } =20 - return; } =20 static s32 sxe_hw_fnav_mode_init(struct sxe_hw *hw, @@ -2295,8 +2166,8 @@ static s32 sxe_hw_fnav_mode_init(struct sxe_hw *hw, =20 if ((sxe_fnav_mode !=3D SXE_FNAV_SAMPLE_MODE) && (sxe_fnav_mode !=3D SXE_FNAV_SPECIFIC_MODE)) { - LOG_ERROR_BDF("mode[%u] a error fnav mode, fnav do not work. please use" - "SXE_FNAV_SAMPLE_MODE or SXE_FNAV_SPECIFIC_MODE\n", + LOG_ERROR_BDF("mode[%u] a error fnav mode, fnav do not work. please" + " use SXE_FNAV_SAMPLE_MODE or SXE_FNAV_SPECIFIC_MODE\n", sxe_fnav_mode); goto l_end; } @@ -2307,8 +2178,8 @@ static s32 sxe_hw_fnav_mode_init(struct sxe_hw *hw, } =20 fnavctrl |=3D (0x6 << SXE_FNAVCTRL_FLEX_SHIFT) | - (0xA << SXE_FNAVCTRL_MAX_LENGTH_SHIFT) | - (4 << SXE_FNAVCTRL_FULL_THRESH_SHIFT); + (0xA << SXE_FNAVCTRL_MAX_LENGTH_SHIFT) | + (4 << SXE_FNAVCTRL_FULL_THRESH_SHIFT); =20 sxe_hw_fnav_enable(hw, fnavctrl); =20 @@ -2359,7 +2230,7 @@ static s32 sxe_hw_fnav_flow_type_mask_get(struct sxe_= hw *hw, case 0x0: *fnavm |=3D SXE_FNAVM_L4P; if (input_mask->ntuple.dst_port || - input_mask->ntuple.src_port) { + input_mask->ntuple.src_port) { LOG_DEV_ERR("error on src/dst port mask\n"); ret =3D -SXE_ERR_CONFIG; goto l_ret; @@ -2423,7 +2294,7 @@ static s32 sxe_hw_fnav_flex_bytes_mask_get(struct sxe= _hw *hw, } =20 s32 sxe_hw_fnav_specific_rule_mask_set(struct sxe_hw *hw, - union sxe_fnav_rule_info *input_mask) + union sxe_fnav_rule_info *input_mask) { s32 ret; u32 fnavm =3D SXE_FNAVM_DIPv6; @@ -2431,44 +2302,39 @@ s32 sxe_hw_fnav_specific_rule_mask_set(struct sxe_h= w *hw, struct sxe_adapter *adapter =3D hw->adapter; =20 =20 - if (input_mask->ntuple.bkt_hash) { + if (input_mask->ntuple.bkt_hash) LOG_DEV_ERR("bucket hash should always be 0 in mask\n"); - } =20 ret =3D sxe_hw_fnav_vm_pool_mask_get(hw, input_mask->ntuple.vm_pool, &fna= vm); - if (ret) { + if (ret) goto l_err_config; - } =20 ret =3D sxe_hw_fnav_flow_type_mask_get(hw, input_mask, &fnavm); - if (ret) { + if (ret) goto l_err_config; - } =20 ret =3D sxe_hw_fnav_vlan_mask_get(hw, input_mask->ntuple.vlan_id, &fnavm); - if (ret) { + if (ret) goto l_err_config; - } =20 ret =3D sxe_hw_fnav_flex_bytes_mask_get(hw, input_mask->ntuple.flex_bytes= , &fnavm); - if (ret) { + if (ret) goto l_err_config; - } =20 LOG_DEBUG_BDF("fnavm =3D 0x%x\n", fnavm); SXE_REG_WRITE(hw, SXE_FNAVM, fnavm); =20 fnavtcpm =3D sxe_hw_fnav_port_mask_get(input_mask->ntuple.src_port, - input_mask->ntuple.dst_port); + input_mask->ntuple.dst_port); =20 LOG_DEBUG_BDF("fnavtcpm =3D 0x%x\n", fnavtcpm); SXE_REG_WRITE(hw, SXE_FNAVTCPM, ~fnavtcpm); SXE_REG_WRITE(hw, SXE_FNAVUDPM, ~fnavtcpm); =20 SXE_REG_WRITE_BE32(hw, SXE_FNAVSIP4M, - ~input_mask->ntuple.src_ip[0]); + ~input_mask->ntuple.src_ip[0]); SXE_REG_WRITE_BE32(hw, SXE_FNAVDIP4M, - ~input_mask->ntuple.dst_ip[0]); + ~input_mask->ntuple.dst_ip[0]); =20 return 0; =20 @@ -2476,16 +2342,15 @@ s32 sxe_hw_fnav_specific_rule_mask_set(struct sxe_h= w *hw, return -SXE_ERR_CONFIG; } =20 -STATIC s32 sxe_hw_fnav_cmd_complete_check(struct sxe_hw *hw, +static s32 sxe_hw_fnav_cmd_complete_check(struct sxe_hw *hw, u32 *fnavcmd) { u32 i; =20 for (i =3D 0; i < SXE_FNAVCMD_CMD_POLL * 10; i++) { *fnavcmd =3D SXE_REG_READ(hw, SXE_FNAVCMD); - if (!(*fnavcmd & SXE_FNAVCMD_CMD_MASK)) { + if (!(*fnavcmd & SXE_FNAVCMD_CMD_MASK)) return 0; - } =20 udelay(10); } @@ -2497,17 +2362,16 @@ static void sxe_hw_fnav_filter_ip_set(struct sxe_hw= *hw, union sxe_fnav_rule_info *input) { SXE_REG_WRITE_BE32(hw, SXE_FNAVSIPv6(0), - input->ntuple.src_ip[0]); + input->ntuple.src_ip[0]); SXE_REG_WRITE_BE32(hw, SXE_FNAVSIPv6(1), - input->ntuple.src_ip[1]); + input->ntuple.src_ip[1]); SXE_REG_WRITE_BE32(hw, SXE_FNAVSIPv6(2), - input->ntuple.src_ip[2]); + input->ntuple.src_ip[2]); =20 SXE_REG_WRITE_BE32(hw, SXE_FNAVIPSA, input->ntuple.src_ip[0]); =20 SXE_REG_WRITE_BE32(hw, SXE_FNAVIPDA, input->ntuple.dst_ip[0]); =20 - return; } =20 static void sxe_hw_fnav_filter_port_set(struct sxe_hw *hw, @@ -2520,7 +2384,6 @@ static void sxe_hw_fnav_filter_port_set(struct sxe_hw= *hw, fnavport |=3D be16_to_cpu(input->ntuple.src_port); SXE_REG_WRITE(hw, SXE_FNAVPORT, fnavport); =20 - return; } =20 static void sxe_hw_fnav_filter_vlan_set(struct sxe_hw *hw, @@ -2533,7 +2396,6 @@ static void sxe_hw_fnav_filter_vlan_set(struct sxe_hw= *hw, fnavvlan |=3D ntohs(input->ntuple.vlan_id); SXE_REG_WRITE(hw, SXE_FNAVVLAN, fnavvlan); =20 - return; } =20 static void sxe_hw_fnav_filter_bkt_hash_set(struct sxe_hw *hw, @@ -2546,7 +2408,6 @@ static void sxe_hw_fnav_filter_bkt_hash_set(struct sx= e_hw *hw, fnavhash |=3D soft_id << SXE_FNAVHASH_SIG_SW_INDEX_SHIFT; SXE_REG_WRITE(hw, SXE_FNAVHASH, fnavhash); =20 - return; } =20 static s32 sxe_hw_fnav_filter_cmd_set(struct sxe_hw *hw, @@ -2561,9 +2422,8 @@ static s32 sxe_hw_fnav_filter_cmd_set(struct sxe_hw *= hw, SXE_FNAVCMD_LAST | SXE_FNAVCMD_QUEUE_EN; =20 #ifndef SXE_DPDK - if (queue =3D=3D SXE_FNAV_DROP_QUEUE) { + if (queue =3D=3D SXE_FNAV_DROP_QUEUE) fnavcmd |=3D SXE_FNAVCMD_DROP; - } #endif =20 fnavcmd |=3D input->ntuple.flow_type << SXE_FNAVCMD_FLOW_TYPE_SHIFT; @@ -2572,9 +2432,8 @@ static s32 sxe_hw_fnav_filter_cmd_set(struct sxe_hw *= hw, =20 SXE_REG_WRITE(hw, SXE_FNAVCMD, fnavcmd); ret =3D sxe_hw_fnav_cmd_complete_check(hw, &fnavcmd); - if (ret) { + if (ret) LOG_DEV_ERR("flow navigator command did not complete!\n"); - } =20 return ret; } @@ -2597,9 +2456,8 @@ s32 sxe_hw_fnav_specific_rule_add(struct sxe_hw *hw, SXE_WRITE_FLUSH(hw); =20 ret =3D sxe_hw_fnav_filter_cmd_set(hw, input, queue); - if (ret) { + if (ret) LOG_ERROR_BDF("set fnav filter cmd error. ret=3D%d\n", ret); - } =20 return ret; } @@ -2656,7 +2514,6 @@ void sxe_hw_fnav_sample_rule_configure(struct sxe_hw = *hw, =20 LOG_DEV_DEBUG("tx queue=3D%x hash=3D%x\n", queue, (u32)fnavhashcmd); =20 - return; } =20 static u64 sxe_hw_fnav_sample_rule_hash_get(struct sxe_hw *hw, @@ -2787,7 +2644,6 @@ static void sxe_hw_fnav_sample_stats_reinit(struct sx= e_hw *hw) SXE_REG_READ(hw, SXE_FNAVMISS); SXE_REG_READ(hw, SXE_FNAVLEN); =20 - return; } =20 static void sxe_hw_ptp_freq_adjust(struct sxe_hw *hw, u32 adj_freq) @@ -2796,7 +2652,6 @@ static void sxe_hw_ptp_freq_adjust(struct sxe_hw *hw,= u32 adj_freq) SXE_REG_WRITE(hw, SXE_TIMADJH, adj_freq); SXE_WRITE_FLUSH(hw); =20 - return; } =20 u64 sxe_hw_ptp_systime_get(struct sxe_hw *hw) @@ -2822,7 +2677,6 @@ void sxe_hw_ptp_systime_init(struct sxe_hw *hw) SXE_REG_WRITE(hw, SXE_SYSTIMH, 0); =20 SXE_WRITE_FLUSH(hw); - return; } =20 void sxe_hw_ptp_init(struct sxe_hw *hw) @@ -2834,21 +2688,19 @@ void sxe_hw_ptp_init(struct sxe_hw *hw) SXE_TSCTRL_L4_UNICAST; =20 regval =3D SXE_REG_READ(hw, SXE_TSCTRL); - regval &=3D ~SXE_TSCTRL_ONESTEP;=09 - regval &=3D ~SXE_TSCTRL_CSEN;=09 + regval &=3D ~SXE_TSCTRL_ONESTEP; + regval &=3D ~SXE_TSCTRL_CSEN; regval |=3D tsctl; SXE_REG_WRITE(hw, SXE_TSCTRL, regval); =20 SXE_REG_WRITE(hw, SXE_TIMINC, SXE_TIMINC_SET(SXE_INCPD, SXE_IV_NS, SXE_IV_SNS)); =20 - return; } =20 void sxe_hw_ptp_rx_timestamp_clear(struct sxe_hw *hw) { SXE_REG_READ(hw, SXE_RXSTMPH); - return; } =20 void sxe_hw_ptp_tx_timestamp_get(struct sxe_hw *hw, @@ -2878,13 +2730,11 @@ void sxe_hw_ptp_tx_timestamp_get(struct sxe_hw *hw, *ts_ns =3D (sec_8bit << 24) | ((reg_ns & 0xFFFFFF00) >> 8); =20 if (unlikely((sec_24bit - systimm_24bit) >=3D 0x00FFFFF0)) { - if (systimm_8bit >=3D 1) { + if (systimm_8bit >=3D 1) systimm_8bit -=3D 1; - } } =20 *ts_sec =3D systimm_8bit | sec_24bit; - return; } =20 u64 sxe_hw_ptp_rx_timestamp_get(struct sxe_hw *hw) @@ -2909,9 +2759,8 @@ bool sxe_hw_ptp_is_rx_timestamp_valid(struct sxe_hw *= hw) u32 tsyncrxctl; =20 tsyncrxctl =3D SXE_REG_READ(hw, SXE_TSYNCRXCTL); - if (tsyncrxctl & SXE_TSYNCRXCTL_RXTT) { + if (tsyncrxctl & SXE_TSYNCRXCTL_RXTT) rx_tmstamp_valid =3D true; - } =20 return rx_tmstamp_valid; } @@ -2923,9 +2772,9 @@ void sxe_hw_ptp_timestamp_mode_set(struct sxe_hw *hw, =20 if (is_l2) { SXE_REG_WRITE(hw, SXE_ETQF(SXE_ETQF_FILTER_1588), - (SXE_ETQF_FILTER_EN |=20=20=20 - SXE_ETQF_1588 |=09 - ETH_P_1588));=09=09 + (SXE_ETQF_FILTER_EN | + SXE_ETQF_1588 | + ETH_P_1588)); } else { SXE_REG_WRITE(hw, SXE_ETQF(SXE_ETQF_FILTER_1588), 0); } @@ -2940,7 +2789,6 @@ void sxe_hw_ptp_timestamp_mode_set(struct sxe_hw *hw, =20 SXE_WRITE_FLUSH(hw); =20 - return; } =20 void sxe_hw_ptp_timestamp_enable(struct sxe_hw *hw) @@ -2954,7 +2802,6 @@ void sxe_hw_ptp_timestamp_enable(struct sxe_hw *hw) SXE_TSYNCRXCTL_REN)); SXE_WRITE_FLUSH(hw); =20 - return; } =20 static void sxe_hw_dcb_tc_rss_configure(struct sxe_hw *hw, u16 rss) @@ -2991,9 +2838,8 @@ static void sxe_hw_tx_ring_disable(struct sxe_hw *hw,= u8 reg_idx, wait_delay +=3D delay_interval * 2; txdctl =3D SXE_REG_READ(hw, SXE_TXDCTL(reg_idx)); =20 - if (!(txdctl & SXE_TXDCTL_ENABLE)) { + if (!(txdctl & SXE_TXDCTL_ENABLE)) return; - } } =20 LOG_MSG_ERR(drv, "register TXDCTL.ENABLE not cleared within the polling p= eriod\n"); @@ -3037,7 +2883,6 @@ static u32 sxe_hw_tx_dbu_fc_status_get(struct sxe_hw = *hw) static void sxe_hw_fnav_sample_hash_set(struct sxe_hw *hw, u64 hash) { SXE_REG64_WRITE(hw, SXE_FNAVHASH, hash); - return; } =20 static const struct sxe_dbu_operations sxe_dbu_ops =3D { @@ -3088,19 +2933,12 @@ static const struct sxe_dbu_operations sxe_dbu_ops = =3D { }; =20 =20 -void sxe_hw_rx_dma_ctrl_init(struct sxe_hw *hw, bool crc_strip_on) +void sxe_hw_rx_dma_ctrl_init(struct sxe_hw *hw) { u32 rx_dma_ctrl =3D SXE_REG_READ(hw, SXE_RDRXCTL); =20 - if (crc_strip_on) { - rx_dma_ctrl |=3D SXE_RDRXCTL_CRCSTRIP; - } else { - rx_dma_ctrl &=3D ~SXE_RDRXCTL_CRCSTRIP; - } - rx_dma_ctrl &=3D ~SXE_RDRXCTL_LROFRSTSIZE; SXE_REG_WRITE(hw, SXE_RDRXCTL, rx_dma_ctrl); - return; } =20 void sxe_hw_rx_dma_lro_ctrl_set(struct sxe_hw *hw) @@ -3109,7 +2947,6 @@ void sxe_hw_rx_dma_lro_ctrl_set(struct sxe_hw *hw) =20 rx_dma_ctrl |=3D SXE_RDRXCTL_LROACKC; SXE_REG_WRITE(hw, SXE_RDRXCTL, rx_dma_ctrl); - return; } =20 void sxe_hw_rx_desc_thresh_set(struct sxe_hw *hw, u8 reg_idx) @@ -3121,7 +2958,6 @@ void sxe_hw_rx_desc_thresh_set(struct sxe_hw *hw, u8 = reg_idx) rxdctl |=3D 0x10; SXE_REG_WRITE(hw, SXE_RXDCTL(reg_idx), rxdctl); =20 - return; } =20 void sxe_hw_rx_ring_switch(struct sxe_hw *hw, u8 reg_idx, bool is_on) @@ -3156,7 +2992,6 @@ void sxe_hw_rx_ring_switch(struct sxe_hw *hw, u8 reg_= idx, bool is_on) "the polling period\n", reg_idx, is_on); } =20 - return; } =20 void sxe_hw_rx_ring_switch_not_polling(struct sxe_hw *hw, u8 reg_idx, bool= is_on) @@ -3172,7 +3007,6 @@ void sxe_hw_rx_ring_switch_not_polling(struct sxe_hw = *hw, u8 reg_idx, bool is_on =20 SXE_WRITE_FLUSH(hw); =20 - return; } =20 void sxe_hw_rx_queue_desc_reg_configure(struct sxe_hw *hw, @@ -3181,21 +3015,18 @@ void sxe_hw_rx_queue_desc_reg_configure(struct sxe_= hw *hw, { SXE_REG_WRITE(hw, SXE_RDH(reg_idx), rdh_value); SXE_REG_WRITE(hw, SXE_RDT(reg_idx), rdt_value); - return; } =20 static void sxe_hw_rx_ring_head_init(struct sxe_hw *hw, u8 reg_idx) { SXE_REG_WRITE(hw, SXE_RDH(reg_idx), 0); =20 - return; } =20 static void sxe_hw_rx_ring_tail_init(struct sxe_hw *hw, u8 reg_idx) { SXE_REG_WRITE(hw, SXE_RDT(reg_idx), 0); =20 - return; } =20 void sxe_hw_rx_ring_desc_configure(struct sxe_hw *hw, @@ -3212,12 +3043,10 @@ void sxe_hw_rx_ring_desc_configure(struct sxe_hw *h= w, sxe_hw_rx_ring_head_init(hw, reg_idx); sxe_hw_rx_ring_tail_init(hw, reg_idx); =20 - return; } =20 void sxe_hw_rx_rcv_ctl_configure(struct sxe_hw *hw, u8 reg_idx, - u32 header_buf_len, u32 pkg_buf_len - ) + u32 header_buf_len, u32 pkg_buf_len) { u32 srrctl; =20 @@ -3228,7 +3057,6 @@ void sxe_hw_rx_rcv_ctl_configure(struct sxe_hw *hw, u= 8 reg_idx, =20 SXE_REG_WRITE(hw, SXE_SRRCTL(reg_idx), srrctl); =20 - return; } =20 void sxe_hw_rx_lro_ctl_configure(struct sxe_hw *hw, @@ -3240,7 +3068,6 @@ void sxe_hw_rx_lro_ctl_configure(struct sxe_hw *hw, lroctrl |=3D max_desc; SXE_REG_WRITE(hw, SXE_LROCTL(reg_idx), lroctrl); =20 - return; } =20 static u32 sxe_hw_rx_desc_ctrl_get(struct sxe_hw *hw, u8 reg_idx) @@ -3264,7 +3091,6 @@ static void sxe_hw_dcb_arbiter_set(struct sxe_hw *hw,= bool is_enable) SXE_REG_WRITE(hw, SXE_RTTDCS, rttdcs); } =20 - return; } =20 =20 @@ -3291,11 +3117,10 @@ static void sxe_hw_tx_multi_ring_configure(struct s= xe_hw *hw, u8 tcs, } else if (tcs > SXE_DCB_1_TC) { mtqc =3D SXE_MTQC_RT_ENA | SXE_MTQC_4TC_4TQ; } else { - if (max_txq > 63) { + if (max_txq > 63) mtqc =3D SXE_MTQC_RT_ENA | SXE_MTQC_4TC_4TQ; - } else { + else mtqc =3D SXE_MTQC_64Q_1PB; - } } } =20 @@ -3303,21 +3128,18 @@ static void sxe_hw_tx_multi_ring_configure(struct s= xe_hw *hw, u8 tcs, =20 sxe_hw_dcb_arbiter_set(hw, true); =20 - return; } =20 void sxe_hw_tx_ring_head_init(struct sxe_hw *hw, u8 reg_idx) { SXE_REG_WRITE(hw, SXE_TDH(reg_idx), 0); =20 - return; } =20 void sxe_hw_tx_ring_tail_init(struct sxe_hw *hw, u8 reg_idx) { SXE_REG_WRITE(hw, SXE_TDT(reg_idx), 0); =20 - return; } =20 void sxe_hw_tx_ring_desc_configure(struct sxe_hw *hw, @@ -3328,14 +3150,12 @@ void sxe_hw_tx_ring_desc_configure(struct sxe_hw *h= w, =20 SXE_WRITE_FLUSH(hw); =20 - SXE_REG_WRITE(hw, SXE_TDBAL(reg_idx), (desc_dma_addr & \ - DMA_BIT_MASK(32))); + SXE_REG_WRITE(hw, SXE_TDBAL(reg_idx), (desc_dma_addr & DMA_BIT_MASK(32))); SXE_REG_WRITE(hw, SXE_TDBAH(reg_idx), (desc_dma_addr >> 32)); SXE_REG_WRITE(hw, SXE_TDLEN(reg_idx), desc_mem_len); sxe_hw_tx_ring_head_init(hw, reg_idx); sxe_hw_tx_ring_tail_init(hw, reg_idx); =20 - return; } =20 void sxe_hw_tx_desc_thresh_set( @@ -3352,7 +3172,6 @@ void sxe_hw_tx_desc_thresh_set( =20 SXE_REG_WRITE(hw, SXE_TXDCTL(reg_idx), txdctl); =20 - return; } =20 void sxe_hw_all_ring_disable(struct sxe_hw *hw, u32 ring_max) @@ -3372,7 +3191,6 @@ void sxe_hw_all_ring_disable(struct sxe_hw *hw, u32 r= ing_max) SXE_WRITE_FLUSH(hw); usleep_range(1000, 2000); =20 - return; } =20 void sxe_hw_tx_ring_switch(struct sxe_hw *hw, u8 reg_idx, bool is_on) @@ -3404,7 +3222,6 @@ void sxe_hw_tx_ring_switch(struct sxe_hw *hw, u8 reg_= idx, bool is_on) "the polling period\n", reg_idx, is_on); } =20 - return; } =20 void sxe_hw_tx_ring_switch_not_polling(struct sxe_hw *hw, u8 reg_idx, bool= is_on) @@ -3418,7 +3235,6 @@ void sxe_hw_tx_ring_switch_not_polling(struct sxe_hw = *hw, u8 reg_idx, bool is_on SXE_REG_WRITE(hw, SXE_TXDCTL(reg_idx), txdctl); } =20 - return; } =20 void sxe_hw_tx_pkt_buf_thresh_configure(struct sxe_hw *hw, @@ -3426,26 +3242,21 @@ void sxe_hw_tx_pkt_buf_thresh_configure(struct sxe_= hw *hw, { u32 i, tx_pkt_size, tx_pb_thresh; =20 - if (!num_pb){ + if (!num_pb) num_pb =3D 1; - } =20 tx_pkt_size =3D SXE_TX_PBSIZE_MAX / num_pb; - if (true =3D=3D dcb_enable) { + if (true =3D=3D dcb_enable) tx_pb_thresh =3D (tx_pkt_size / 1024) - SXE_TX_PKT_SIZE_MAX; - } else { + else tx_pb_thresh =3D (tx_pkt_size / 1024) - SXE_NODCB_TX_PKT_SIZE_MAX; - } =20 - for (i =3D 0; i < num_pb; i++) { + for (i =3D 0; i < num_pb; i++) SXE_REG_WRITE(hw, SXE_TXPBTHRESH(i), tx_pb_thresh); - } =20 - for (; i < SXE_PKG_BUF_NUM_MAX; i++) { + for (; i < SXE_PKG_BUF_NUM_MAX; i++) SXE_REG_WRITE(hw, SXE_TXPBTHRESH(i), 0); - } =20 - return; } =20 void sxe_hw_tx_enable(struct sxe_hw *hw) @@ -3456,7 +3267,6 @@ void sxe_hw_tx_enable(struct sxe_hw *hw) ctl |=3D SXE_DMATXCTL_TE; SXE_REG_WRITE(hw, SXE_DMATXCTL, ctl); =20 - return; } =20 static u32 sxe_hw_tx_desc_ctrl_get(struct sxe_hw *hw, u8 reg_idx) @@ -3476,7 +3286,6 @@ static void sxe_hw_tx_desc_wb_thresh_clear(struct sxe= _hw *hw, u8 reg_idx) reg_data |=3D SXE_TXDCTL_ENABLE; SXE_REG_WRITE(hw, SXE_TXDCTL(reg_idx), reg_data); =20 - return; } =20 void sxe_hw_vlan_tag_strip_switch(struct sxe_hw *hw, @@ -3486,15 +3295,13 @@ void sxe_hw_vlan_tag_strip_switch(struct sxe_hw *hw, =20 rxdctl =3D SXE_REG_READ(hw, SXE_RXDCTL(reg_index)); =20 - if (is_enable) { + if (is_enable) rxdctl |=3D SXE_RXDCTL_VME; - } else { + else rxdctl &=3D ~SXE_RXDCTL_VME; - } =20 SXE_REG_WRITE(hw, SXE_RXDCTL(reg_index), rxdctl); =20 - return; } =20 static void sxe_hw_tx_vlan_tag_set(struct sxe_hw *hw, @@ -3503,13 +3310,11 @@ static void sxe_hw_tx_vlan_tag_set(struct sxe_hw *h= w, u32 vmvir =3D vid | (qos << VLAN_PRIO_SHIFT) | SXE_VMVIR_VLANA_DEFAULT; =20 SXE_REG_WRITE(hw, SXE_VMVIR(vf), vmvir); - return; } =20 void sxe_hw_tx_vlan_tag_clear(struct sxe_hw *hw, u32 vf) { SXE_REG_WRITE(hw, SXE_VMVIR(vf), 0); - return; } =20 u32 sxe_hw_tx_vlan_insert_get(struct sxe_hw *hw, u32 vf) @@ -3523,42 +3328,39 @@ void sxe_hw_tx_ring_info_get(struct sxe_hw *hw, *head =3D SXE_REG_READ(hw, SXE_TDH(idx)); *tail =3D SXE_REG_READ(hw, SXE_TDT(idx)); =20 - return; } =20 void sxe_hw_dcb_rx_bw_alloc_configure(struct sxe_hw *hw, - u16 *refill, - u16 *max, - u8 *bwg_id, - u8 *prio_type, - u8 *prio_tc, - u8 max_priority) -{ - u32 reg; - u32 credit_refill; - u32 credit_max; - u8 i; + u16 *refill, + u16 *max, + u8 *bwg_id, + u8 *prio_type, + u8 *prio_tc, + u8 max_priority) +{ + u32 reg; + u32 credit_refill; + u32 credit_max; + u8 i; =20 reg =3D SXE_RTRPCS_RRM | SXE_RTRPCS_RAC | SXE_RTRPCS_ARBDIS; SXE_REG_WRITE(hw, SXE_RTRPCS, reg); =20 reg =3D 0; - for (i =3D 0; i < max_priority; i++) { + for (i =3D 0; i < max_priority; i++) reg |=3D (prio_tc[i] << (i * SXE_RTRUP2TC_UP_SHIFT)); - } =20 SXE_REG_WRITE(hw, SXE_RTRUP2TC, reg); =20 for (i =3D 0; i < MAX_TRAFFIC_CLASS; i++) { credit_refill =3D refill[i]; - credit_max =3D max[i]; + credit_max =3D max[i]; reg =3D credit_refill | (credit_max << SXE_RTRPT4C_MCL_SHIFT); =20 reg |=3D (u32)(bwg_id[i]) << SXE_RTRPT4C_BWG_SHIFT; =20 - if (prio_type[i] =3D=3D PRIO_LINK) { + if (prio_type[i] =3D=3D PRIO_LINK) reg |=3D SXE_RTRPT4C_LSP; - } =20 SXE_REG_WRITE(hw, SXE_RTRPT4C(i), reg); } @@ -3566,7 +3368,6 @@ void sxe_hw_dcb_rx_bw_alloc_configure(struct sxe_hw *= hw, reg =3D SXE_RTRPCS_RRM | SXE_RTRPCS_RAC; SXE_REG_WRITE(hw, SXE_RTRPCS, reg); =20 - return; } =20 void sxe_hw_dcb_tx_desc_bw_alloc_configure(struct sxe_hw *hw, @@ -3575,8 +3376,8 @@ void sxe_hw_dcb_tx_desc_bw_alloc_configure(struct sxe= _hw *hw, u8 *bwg_id, u8 *prio_type) { - u32 reg, max_credits; - u8 i; + u32 reg, max_credits; + u8 i; =20 for (i =3D 0; i < 128; i++) { SXE_REG_WRITE(hw, SXE_RTTDQSEL, i); @@ -3589,13 +3390,11 @@ void sxe_hw_dcb_tx_desc_bw_alloc_configure(struct s= xe_hw *hw, reg |=3D refill[i]; reg |=3D (u32)(bwg_id[i]) << SXE_RTTDT2C_BWG_SHIFT; =20 - if (prio_type[i] =3D=3D PRIO_GROUP) { + if (prio_type[i] =3D=3D PRIO_GROUP) reg |=3D SXE_RTTDT2C_GSP; - } =20 - if (prio_type[i] =3D=3D PRIO_LINK) { + if (prio_type[i] =3D=3D PRIO_LINK) reg |=3D SXE_RTTDT2C_LSP; - } =20 SXE_REG_WRITE(hw, SXE_RTTDT2C(i), reg); } @@ -3603,7 +3402,6 @@ void sxe_hw_dcb_tx_desc_bw_alloc_configure(struct sxe= _hw *hw, reg =3D SXE_RTTDCS_TDPAC | SXE_RTTDCS_TDRM; SXE_REG_WRITE(hw, SXE_RTTDCS, reg); =20 - return; } =20 void sxe_hw_dcb_tx_data_bw_alloc_configure(struct sxe_hw *hw, @@ -3618,14 +3416,13 @@ void sxe_hw_dcb_tx_data_bw_alloc_configure(struct s= xe_hw *hw, u8 i; =20 reg =3D SXE_RTTPCS_TPPAC | SXE_RTTPCS_TPRM | - (SXE_RTTPCS_ARBD_DCB << SXE_RTTPCS_ARBD_SHIFT) | - SXE_RTTPCS_ARBDIS; + (SXE_RTTPCS_ARBD_DCB << SXE_RTTPCS_ARBD_SHIFT) | + SXE_RTTPCS_ARBDIS; SXE_REG_WRITE(hw, SXE_RTTPCS, reg); =20 reg =3D 0; - for (i =3D 0; i < max_priority; i++) { + for (i =3D 0; i < max_priority; i++) reg |=3D (prio_tc[i] << (i * SXE_RTTUP2TC_UP_SHIFT)); - } =20 SXE_REG_WRITE(hw, SXE_RTTUP2TC, reg); =20 @@ -3634,22 +3431,19 @@ void sxe_hw_dcb_tx_data_bw_alloc_configure(struct s= xe_hw *hw, reg |=3D (u32)(max[i]) << SXE_RTTPT2C_MCL_SHIFT; reg |=3D (u32)(bwg_id[i]) << SXE_RTTPT2C_BWG_SHIFT; =20 - if (prio_type[i] =3D=3D PRIO_GROUP) { + if (prio_type[i] =3D=3D PRIO_GROUP) reg |=3D SXE_RTTPT2C_GSP; - } =20 - if (prio_type[i] =3D=3D PRIO_LINK) { + if (prio_type[i] =3D=3D PRIO_LINK) reg |=3D SXE_RTTPT2C_LSP; - } =20 SXE_REG_WRITE(hw, SXE_RTTPT2C(i), reg); } =20 reg =3D SXE_RTTPCS_TPPAC | SXE_RTTPCS_TPRM | - (SXE_RTTPCS_ARBD_DCB << SXE_RTTPCS_ARBD_SHIFT); + (SXE_RTTPCS_ARBD_DCB << SXE_RTTPCS_ARBD_SHIFT); SXE_REG_WRITE(hw, SXE_RTTPCS, reg); =20 - return; } =20 void sxe_hw_dcb_pfc_configure(struct sxe_hw *hw, @@ -3682,9 +3476,8 @@ void sxe_hw_dcb_pfc_configure(struct sxe_hw *hw, SXE_REG_WRITE(hw, SXE_PFCTOP, reg_val); =20 for (i =3D 0; i < max_priority; i++) { - if (prio_tc[i] > max_tc) { + if (prio_tc[i] > max_tc) max_tc =3D prio_tc[i]; - } } =20 for (i =3D 0; i <=3D max_tc; i++) { @@ -3716,13 +3509,11 @@ void sxe_hw_dcb_pfc_configure(struct sxe_hw *hw, } =20 reg =3D hw->fc.pause_time * 0x00010001; - for (i =3D 0; i < (MAX_TRAFFIC_CLASS / 2); i++) { + for (i =3D 0; i < (MAX_TRAFFIC_CLASS / 2); i++) SXE_REG_WRITE(hw, SXE_FCTTV(i), reg); - } =20 SXE_REG_WRITE(hw, SXE_FCRTV, hw->fc.pause_time / 2); =20 - return; } =20 static void sxe_hw_dcb_8tc_vmdq_off_stats_configure(struct sxe_hw *hw) @@ -3736,28 +3527,26 @@ static void sxe_hw_dcb_8tc_vmdq_off_stats_configure= (struct sxe_hw *hw) } =20 for (i =3D 0; i < 32; i++) { - if (i < 8) { + if (i < 8) reg =3D 0x00000000; - } else if (i < 16) { + else if (i < 16) reg =3D 0x01010101; - } else if (i < 20) { + else if (i < 20) reg =3D 0x02020202; - } else if (i < 24) { + else if (i < 24) reg =3D 0x03030303; - } else if (i < 26) { + else if (i < 26) reg =3D 0x04040404; - } else if (i < 28) { + else if (i < 28) reg =3D 0x05050505; - } else if (i < 30) { + else if (i < 30) reg =3D 0x06060606; - } else { + else reg =3D 0x07070707; - } =20 SXE_REG_WRITE(hw, SXE_TQSM(i), reg); } =20 - return; } =20 static void sxe_hw_dcb_rx_up_tc_map_set(struct sxe_hw *hw, u8 tc) @@ -3771,28 +3560,23 @@ static void sxe_hw_dcb_rx_up_tc_map_set(struct sxe_= hw *hw, u8 tc) for (i =3D 0; i < MAX_TRAFFIC_CLASS; i++) { u8 up2tc =3D reg >> (i * SXE_RTRUP2TC_UP_SHIFT); =20 - if (up2tc > tc) { + if (up2tc > tc) reg &=3D ~(0x7 << SXE_RTRUP2TC_UP_MASK); - } } =20 - if (reg !=3D rsave) { + if (reg !=3D rsave) SXE_REG_WRITE(hw, SXE_RTRUP2TC, reg); - } =20 - return; } =20 void sxe_hw_vt_pool_loopback_switch(struct sxe_hw *hw, bool is_enable) { - if (true =3D=3D is_enable) { + if (true =3D=3D is_enable) SXE_REG_WRITE(hw, SXE_PFDTXGSWC, SXE_PFDTXGSWC_VT_LBEN); - } else { + else SXE_REG_WRITE(hw, SXE_PFDTXGSWC, 0); - } =20 - return; } =20 void sxe_hw_pool_rx_ring_drop_enable(struct sxe_hw *hw, u8 vf_idx, @@ -3801,12 +3585,10 @@ void sxe_hw_pool_rx_ring_drop_enable(struct sxe_hw = *hw, u8 vf_idx, u32 qde =3D SXE_QDE_ENABLE; u8 i; =20 - if (pf_vlan) { + if (pf_vlan) qde |=3D SXE_QDE_HIDE_VLAN; - } =20 - for (i =3D (vf_idx * ring_per_pool); i < ((vf_idx + 1) * ring_per_pool); = i++) - { + for (i =3D (vf_idx * ring_per_pool); i < ((vf_idx + 1) * ring_per_pool); = i++) { u32 value; =20 SXE_WRITE_FLUSH(hw); @@ -3817,7 +3599,6 @@ void sxe_hw_pool_rx_ring_drop_enable(struct sxe_hw *h= w, u8 vf_idx, SXE_REG_WRITE(hw, SXE_QDE, value); } =20 - return; } =20 u32 sxe_hw_rx_pool_bitmap_get(struct sxe_hw *hw, u8 reg_idx) @@ -3830,7 +3611,6 @@ void sxe_hw_rx_pool_bitmap_set(struct sxe_hw *hw, { SXE_REG_WRITE(hw, SXE_VFRE(reg_idx), bitmap); =20 - return; } =20 u32 sxe_hw_tx_pool_bitmap_get(struct sxe_hw *hw, u8 reg_idx) @@ -3843,14 +3623,12 @@ void sxe_hw_tx_pool_bitmap_set(struct sxe_hw *hw, { SXE_REG_WRITE(hw, SXE_VFTE(reg_idx), bitmap); =20 - return; } =20 void sxe_hw_dcb_max_mem_window_set(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_RTTBCNRM, value); =20 - return; } =20 void sxe_hw_dcb_tx_ring_rate_factor_set(struct sxe_hw *hw, @@ -3859,7 +3637,6 @@ void sxe_hw_dcb_tx_ring_rate_factor_set(struct sxe_hw= *hw, SXE_REG_WRITE(hw, SXE_RTTDQSEL, ring_idx); SXE_REG_WRITE(hw, SXE_RTTBCNRC, rate); =20 - return; } =20 void sxe_hw_spoof_count_enable(struct sxe_hw *hw, @@ -3871,7 +3648,6 @@ void sxe_hw_spoof_count_enable(struct sxe_hw *hw, =20 SXE_REG_WRITE(hw, SXE_VMECM(reg_idx), value); =20 - return; } =20 void sxe_hw_pool_mac_anti_spoof_set(struct sxe_hw *hw, @@ -3883,15 +3659,13 @@ void sxe_hw_pool_mac_anti_spoof_set(struct sxe_hw *= hw, =20 value =3D SXE_REG_READ(hw, SXE_SPOOF(reg_index)); =20 - if (status) { + if (status) value |=3D BIT(bit_index); - } else { + else value &=3D ~BIT(bit_index); - } =20 SXE_REG_WRITE(hw, SXE_SPOOF(reg_index), value); =20 - return; } =20 static void sxe_hw_dcb_rx_up_tc_map_get(struct sxe_hw *hw, u8 *map) @@ -3904,22 +3678,19 @@ static void sxe_hw_dcb_rx_up_tc_map_get(struct sxe_= hw *hw, u8 *map) (reg >> (i * SXE_RTRUP2TC_UP_SHIFT)); } =20 - return; } =20 void sxe_hw_rx_drop_switch(struct sxe_hw *hw, u8 idx, bool is_enable) { u32 srrctl =3D SXE_REG_READ(hw, SXE_SRRCTL(idx)); =20 - if (true =3D=3D is_enable) { + if (true =3D=3D is_enable) srrctl |=3D SXE_SRRCTL_DROP_EN; - } else { + else srrctl &=3D ~SXE_SRRCTL_DROP_EN; - } =20 SXE_REG_WRITE(hw, SXE_SRRCTL(idx), srrctl); =20 - return; } =20 static void sxe_hw_pool_vlan_anti_spoof_set(struct sxe_hw *hw, @@ -3931,15 +3702,13 @@ static void sxe_hw_pool_vlan_anti_spoof_set(struct = sxe_hw *hw, =20 value =3D SXE_REG_READ(hw, SXE_SPOOF(reg_index)); =20 - if (status) { + if (status) value |=3D BIT(bit_index); - } else { + else value &=3D ~BIT(bit_index); - } =20 SXE_REG_WRITE(hw, SXE_SPOOF(reg_index), value); =20 - return; } =20 static void sxe_hw_vf_tx_desc_addr_clear(struct sxe_hw *hw, @@ -3952,7 +3721,6 @@ static void sxe_hw_vf_tx_desc_addr_clear(struct sxe_h= w *hw, SXE_REG_WRITE(hw, SXE_PVFTDWBAH_N(ring_per_pool, vf_idx, i), 0); } =20 - return; } =20 static void sxe_hw_vf_tx_ring_disable(struct sxe_hw *hw, @@ -3974,7 +3742,6 @@ static void sxe_hw_vf_tx_ring_disable(struct sxe_hw *= hw, =20 SXE_WRITE_FLUSH(hw); =20 - return; } =20 void sxe_hw_dcb_rate_limiter_clear(struct sxe_hw *hw, u8 ring_max) @@ -3987,7 +3754,6 @@ void sxe_hw_dcb_rate_limiter_clear(struct sxe_hw *hw,= u8 ring_max) } SXE_WRITE_FLUSH(hw); =20 - return; } =20 static void sxe_hw_tx_tph_update(struct sxe_hw *hw, u8 ring_idx, u8 cpu) @@ -3996,12 +3762,11 @@ static void sxe_hw_tx_tph_update(struct sxe_hw *hw,= u8 ring_idx, u8 cpu) =20 value <<=3D SXE_TPH_TXCTRL_CPUID_SHIFT; =20 - value |=3D SXE_TPH_TXCTRL_DESC_RRO_EN | \ - SXE_TPH_TXCTRL_DATA_RRO_EN | \ - SXE_TPH_TXCTRL_DESC_TPH_EN; + value |=3D (SXE_TPH_TXCTRL_DESC_RRO_EN | + SXE_TPH_TXCTRL_DATA_RRO_EN | + SXE_TPH_TXCTRL_DESC_TPH_EN); =20 SXE_REG_WRITE(hw, SXE_TPH_TXCTRL(ring_idx), value); - return; } =20 static void sxe_hw_rx_tph_update(struct sxe_hw *hw, u8 ring_idx, u8 cpu) @@ -4010,29 +3775,26 @@ static void sxe_hw_rx_tph_update(struct sxe_hw *hw,= u8 ring_idx, u8 cpu) =20 value <<=3D SXE_TPH_RXCTRL_CPUID_SHIFT; =20 - value |=3D SXE_TPH_RXCTRL_DESC_RRO_EN | \ - SXE_TPH_RXCTRL_DATA_TPH_EN | \ - SXE_TPH_RXCTRL_DESC_TPH_EN; + value |=3D (SXE_TPH_RXCTRL_DESC_RRO_EN | + SXE_TPH_RXCTRL_DATA_TPH_EN | + SXE_TPH_RXCTRL_DESC_TPH_EN); =20 SXE_REG_WRITE(hw, SXE_TPH_RXCTRL(ring_idx), value); - return; } =20 static void sxe_hw_tph_switch(struct sxe_hw *hw, bool is_enable) { - if (is_enable =3D=3D true) { + if (is_enable =3D=3D true) SXE_REG_WRITE(hw, SXE_TPH_CTRL, SXE_TPH_CTRL_MODE_CB2); - } else { + else SXE_REG_WRITE(hw, SXE_TPH_CTRL, SXE_TPH_CTRL_DISABLE); - } =20 - return; } =20 static const struct sxe_dma_operations sxe_dma_ops =3D { - .rx_dma_ctrl_init =3D sxe_hw_rx_dma_ctrl_init, - .rx_ring_switch =3D sxe_hw_rx_ring_switch, - .rx_ring_switch_not_polling =3D sxe_hw_rx_ring_switch_not_polling, + .rx_dma_ctrl_init =3D sxe_hw_rx_dma_ctrl_init, + .rx_ring_switch =3D sxe_hw_rx_ring_switch, + .rx_ring_switch_not_polling =3D sxe_hw_rx_ring_switch_not_polling, .rx_ring_desc_configure =3D sxe_hw_rx_ring_desc_configure, .rx_desc_thresh_set =3D sxe_hw_rx_desc_thresh_set, .rx_rcv_ctl_configure =3D sxe_hw_rx_rcv_ctl_configure, @@ -4049,7 +3811,7 @@ static const struct sxe_dma_operations sxe_dma_ops = =3D { .tx_desc_thresh_set =3D sxe_hw_tx_desc_thresh_set, .tx_desc_wb_thresh_clear =3D sxe_hw_tx_desc_wb_thresh_clear, .tx_ring_switch =3D sxe_hw_tx_ring_switch, - .tx_ring_switch_not_polling =3D sxe_hw_tx_ring_switch_not_polling, + .tx_ring_switch_not_polling =3D sxe_hw_tx_ring_switch_not_polling, .tx_pkt_buf_thresh_configure =3D sxe_hw_tx_pkt_buf_thresh_configure, .tx_desc_ctrl_get =3D sxe_hw_tx_desc_ctrl_get, .tx_ring_info_get =3D sxe_hw_tx_ring_info_get, @@ -4084,9 +3846,9 @@ static const struct sxe_dma_operations sxe_dma_ops = =3D { .max_dcb_memory_window_set =3D sxe_hw_dcb_max_mem_window_set, .spoof_count_enable =3D sxe_hw_spoof_count_enable, =20 - .vf_tx_ring_disable =3D sxe_hw_vf_tx_ring_disable, - .all_ring_disable =3D sxe_hw_all_ring_disable, - .tx_ring_tail_init =3D sxe_hw_tx_ring_tail_init, + .vf_tx_ring_disable =3D sxe_hw_vf_tx_ring_disable, + .all_ring_disable =3D sxe_hw_all_ring_disable, + .tx_ring_tail_init =3D sxe_hw_tx_ring_tail_init, }; =20 =20 @@ -4099,16 +3861,15 @@ static void sxe_hw_ipsec_rx_sa_load(struct sxe_hw *= hw, u16 idx, =20 reg &=3D SXE_RXTXIDX_IPS_EN; reg |=3D type << SXE_RXIDX_TBL_SHIFT | - idx << SXE_RXTXIDX_IDX_SHIFT | - SXE_RXTXIDX_WRITE; + idx << SXE_RXTXIDX_IDX_SHIFT | + SXE_RXTXIDX_WRITE; SXE_REG_WRITE(hw, SXE_IPSRXIDX, reg); SXE_WRITE_FLUSH(hw); =20 - return; } =20 static void sxe_hw_ipsec_rx_ip_store(struct sxe_hw *hw, - __be32 *ip_addr, u8 ip_len, u8 ip_idx) + __be32 *ip_addr, u8 ip_len, u8 ip_idx) { u8 i; =20 @@ -4119,11 +3880,10 @@ static void sxe_hw_ipsec_rx_ip_store(struct sxe_hw = *hw, SXE_WRITE_FLUSH(hw); sxe_hw_ipsec_rx_sa_load(hw, ip_idx, SXE_IPSEC_IP_TABLE); =20 - return; } =20 static void sxe_hw_ipsec_rx_spi_store(struct sxe_hw *hw, - __be32 spi, u8 ip_idx, u16 sa_idx) + __be32 spi, u8 ip_idx, u16 sa_idx) { SXE_REG_WRITE(hw, SXE_IPSRXSPI, (__force u32)cpu_to_le32((__force u32)spi= )); =20 @@ -4133,7 +3893,6 @@ static void sxe_hw_ipsec_rx_spi_store(struct sxe_hw *= hw, =20 sxe_hw_ipsec_rx_sa_load(hw, sa_idx, SXE_IPSEC_SPI_TABLE); =20 - return; } =20 static void sxe_hw_ipsec_rx_key_store(struct sxe_hw *hw, @@ -4152,7 +3911,6 @@ static void sxe_hw_ipsec_rx_key_store(struct sxe_hw *= hw, =20 sxe_hw_ipsec_rx_sa_load(hw, sa_idx, SXE_IPSEC_KEY_TABLE); =20 - return; } =20 static void sxe_hw_ipsec_tx_sa_load(struct sxe_hw *hw, u16 idx) @@ -4164,7 +3922,6 @@ static void sxe_hw_ipsec_tx_sa_load(struct sxe_hw *hw= , u16 idx) SXE_REG_WRITE(hw, SXE_IPSTXIDX, reg); SXE_WRITE_FLUSH(hw); =20 - return; } =20 static void sxe_hw_ipsec_tx_key_store(struct sxe_hw *hw, u32 *key, @@ -4181,7 +3938,6 @@ static void sxe_hw_ipsec_tx_key_store(struct sxe_hw *= hw, u32 *key, =20 sxe_hw_ipsec_tx_sa_load(hw, sa_idx); =20 - return; } =20 static void sxe_hw_ipsec_sec_data_stop(struct sxe_hw *hw, bool is_linkup) @@ -4200,9 +3956,8 @@ static void sxe_hw_ipsec_sec_data_stop(struct sxe_hw = *hw, bool is_linkup) =20 tx_empty =3D SXE_REG_READ(hw, SXE_SECTXSTAT) & SXE_SECTXSTAT_SECTX_RDY; rx_empty =3D SXE_REG_READ(hw, SXE_SECRXSTAT) & SXE_SECRXSTAT_SECRX_RDY; - if (tx_empty && rx_empty) { - goto l_out; - } + if (tx_empty && rx_empty) + return; =20 if (!is_linkup) { SXE_REG_WRITE(hw, SXE_LPBKCTRL, SXE_LPBKCTRL_EN); @@ -4213,11 +3968,11 @@ static void sxe_hw_ipsec_sec_data_stop(struct sxe_h= w *hw, bool is_linkup) =20 limit =3D 20; do { - mdelay(10); - tx_empty =3D SXE_REG_READ(hw, SXE_SECTXSTAT) & - SXE_SECTXSTAT_SECTX_RDY; + mdelay(10); + tx_empty =3D SXE_REG_READ(hw, SXE_SECTXSTAT) & + SXE_SECTXSTAT_SECTX_RDY; rx_empty =3D SXE_REG_READ(hw, SXE_SECRXSTAT) & - SXE_SECRXSTAT_SECRX_RDY; + SXE_SECRXSTAT_SECRX_RDY; } while (!(tx_empty && rx_empty) && limit--); =20 if (!is_linkup) { @@ -4226,8 +3981,6 @@ static void sxe_hw_ipsec_sec_data_stop(struct sxe_hw = *hw, bool is_linkup) SXE_WRITE_FLUSH(hw); } =20 -l_out: - return; } =20 static void sxe_hw_ipsec_engine_start(struct sxe_hw *hw, bool is_linkup) @@ -4252,7 +4005,6 @@ static void sxe_hw_ipsec_engine_start(struct sxe_hw *= hw, bool is_linkup) =20 SXE_WRITE_FLUSH(hw); =20 - return; } =20 static void sxe_hw_ipsec_engine_stop(struct sxe_hw *hw, bool is_linkup) @@ -4273,18 +4025,17 @@ static void sxe_hw_ipsec_engine_stop(struct sxe_hw = *hw, bool is_linkup) reg |=3D SXE_SECRXCTRL_SECRX_DIS; SXE_REG_WRITE(hw, SXE_SECRXCTRL, reg); =20 - SXE_REG_WRITE(hw, SXE_SECTXBUFFAF, 0x250); + SXE_REG_WRITE(hw, SXE_SECTXBUFFAF, 0x250); =20 - reg =3D SXE_REG_READ(hw, SXE_SECTXMINIFG); - reg =3D (reg & 0xfffffff0) | 0x1; - SXE_REG_WRITE(hw, SXE_SECTXMINIFG, reg); + reg =3D SXE_REG_READ(hw, SXE_SECTXMINIFG); + reg =3D (reg & 0xfffffff0) | 0x1; + SXE_REG_WRITE(hw, SXE_SECTXMINIFG, reg); =20 - SXE_REG_WRITE(hw, SXE_SECTXCTRL, SXE_SECTXCTRL_SECTX_DIS); - SXE_REG_WRITE(hw, SXE_SECRXCTRL, SXE_SECRXCTRL_SECRX_DIS); + SXE_REG_WRITE(hw, SXE_SECTXCTRL, SXE_SECTXCTRL_SECTX_DIS); + SXE_REG_WRITE(hw, SXE_SECRXCTRL, SXE_SECRXCTRL_SECRX_DIS); =20 - SXE_WRITE_FLUSH(hw); + SXE_WRITE_FLUSH(hw); =20 - return; } =20 bool sxe_hw_ipsec_offload_is_disable(struct sxe_hw *hw) @@ -4294,7 +4045,7 @@ bool sxe_hw_ipsec_offload_is_disable(struct sxe_hw *h= w) bool ret =3D false; =20 if ((tx_dis & SXE_SECTXSTAT_SECTX_OFF_DIS) || - (rx_dis & SXE_SECRXSTAT_SECRX_OFF_DIS)) { + (rx_dis & SXE_SECRXSTAT_SECRX_OFF_DIS)) { ret =3D true; } =20 @@ -4306,7 +4057,6 @@ void sxe_hw_ipsec_sa_disable(struct sxe_hw *hw) SXE_REG_WRITE(hw, SXE_IPSRXIDX, 0); SXE_REG_WRITE(hw, SXE_IPSTXIDX, 0); =20 - return; } =20 static const struct sxe_sec_operations sxe_sec_ops =3D { @@ -4344,18 +4094,18 @@ void sxe_hw_stats_regs_clean(struct sxe_hw *hw) SXE_REG_READ(hw, SXE_TXDGPC); SXE_REG_READ(hw, SXE_TXDGBCH); SXE_REG_READ(hw, SXE_TXDGBCL); - SXE_REG_READ(hw,SXE_RXDDGPC); + SXE_REG_READ(hw, SXE_RXDDGPC); SXE_REG_READ(hw, SXE_RXDDGBCH); - SXE_REG_READ(hw,SXE_RXDDGBCL); - SXE_REG_READ(hw,SXE_RXLPBKGPC); + SXE_REG_READ(hw, SXE_RXDDGBCL); + SXE_REG_READ(hw, SXE_RXLPBKGPC); SXE_REG_READ(hw, SXE_RXLPBKGBCH); - SXE_REG_READ(hw,SXE_RXLPBKGBCL); - SXE_REG_READ(hw,SXE_RXDLPBKGPC); + SXE_REG_READ(hw, SXE_RXLPBKGBCL); + SXE_REG_READ(hw, SXE_RXDLPBKGPC); SXE_REG_READ(hw, SXE_RXDLPBKGBCH); - SXE_REG_READ(hw,SXE_RXDLPBKGBCL); - SXE_REG_READ(hw,SXE_RXTPCIN); - SXE_REG_READ(hw,SXE_RXTPCOUT); - SXE_REG_READ(hw,SXE_RXPRDDC); + SXE_REG_READ(hw, SXE_RXDLPBKGBCL); + SXE_REG_READ(hw, SXE_RXTPCIN); + SXE_REG_READ(hw, SXE_RXTPCOUT); + SXE_REG_READ(hw, SXE_RXPRDDC); SXE_REG_READ(hw, SXE_TXSWERR); SXE_REG_READ(hw, SXE_TXSWITCH); SXE_REG_READ(hw, SXE_TXREPEAT); @@ -4382,9 +4132,9 @@ void sxe_hw_stats_regs_clean(struct sxe_hw *hw) SXE_REG_READ(hw, SXE_RFC); SXE_REG_READ(hw, SXE_ROC); SXE_REG_READ(hw, SXE_RJC); - for (i =3D 0; i < 8; i++) { + for (i =3D 0; i < 8; i++) SXE_REG_READ(hw, SXE_PRCPF(i)); - } + SXE_REG_READ(hw, SXE_TORL); SXE_REG_READ(hw, SXE_TORH); SXE_REG_READ(hw, SXE_TPR); @@ -4397,11 +4147,9 @@ void sxe_hw_stats_regs_clean(struct sxe_hw *hw) SXE_REG_READ(hw, SXE_PTC1522); SXE_REG_READ(hw, SXE_MPTC); SXE_REG_READ(hw, SXE_BPTC); - for (i =3D 0; i < 8; i++) { + for (i =3D 0; i < 8; i++) SXE_REG_READ(hw, SXE_PFCT(i)); - } =20 - return; } =20 static void sxe_hw_stats_seq_get(struct sxe_hw *hw, struct sxe_mac_stats *= stats) @@ -4414,8 +4162,8 @@ static void sxe_hw_stats_seq_get(struct sxe_hw *hw, s= truct sxe_mac_stats *stats) #endif =20 for (i =3D 0; i < 8; i++) { - stats->prcpf[i] +=3D SXE_REG_READ(hw,SXE_PRCPF(i)); - tx_pfc_num =3D SXE_REG_READ(hw,SXE_PFCT(i)); + stats->prcpf[i] +=3D SXE_REG_READ(hw, SXE_PRCPF(i)); + tx_pfc_num =3D SXE_REG_READ(hw, SXE_PFCT(i)); stats->pfct[i] +=3D tx_pfc_num; stats->total_tx_pause +=3D tx_pfc_num; } @@ -4433,7 +4181,6 @@ static void sxe_hw_stats_seq_get(struct sxe_hw *hw, s= truct sxe_mac_stats *stats) } #endif =20 - return; } =20 void sxe_hw_stats_seq_clean(struct sxe_hw *hw, struct sxe_mac_stats *stats) @@ -4453,15 +4200,13 @@ void sxe_hw_stats_seq_clean(struct sxe_hw *hw, stru= ct sxe_mac_stats *stats) if (gotch !=3D 0) { LOG_INFO("GOTCH is not clear!\n"); } -=09 for (i =3D 0; i < 8; i++) { - stats->prcpf[i] +=3D SXE_REG_READ(hw,SXE_PRCPF(i)); - tx_pfc_num =3D SXE_REG_READ(hw,SXE_PFCT(i)); + stats->prcpf[i] +=3D SXE_REG_READ(hw, SXE_PRCPF(i)); + tx_pfc_num =3D SXE_REG_READ(hw, SXE_PFCT(i)); stats->pfct[i] +=3D tx_pfc_num; stats->total_tx_pause +=3D tx_pfc_num; } =20 - return; } =20 void sxe_hw_stats_get(struct sxe_hw *hw, struct sxe_mac_stats *stats) @@ -4497,20 +4242,20 @@ void sxe_hw_stats_get(struct sxe_hw *hw, struct sxe= _mac_stats *stats) stats->txdgbc +=3D (((u64)SXE_REG_READ(hw, SXE_TXDGBCH) << 32) + SXE_REG_READ(hw, SXE_TXDGBCL)); =20 - stats->rxddpc +=3D SXE_REG_READ(hw,SXE_RXDDGPC); + stats->rxddpc +=3D SXE_REG_READ(hw, SXE_RXDDGPC); stats->rxddbc +=3D ((u64)SXE_REG_READ(hw, SXE_RXDDGBCH) << 32) + - (SXE_REG_READ(hw,SXE_RXDDGBCL)); + (SXE_REG_READ(hw, SXE_RXDDGBCL)); =20 - stats->rxlpbkpc +=3D SXE_REG_READ(hw,SXE_RXLPBKGPC); + stats->rxlpbkpc +=3D SXE_REG_READ(hw, SXE_RXLPBKGPC); stats->rxlpbkbc +=3D ((u64)SXE_REG_READ(hw, SXE_RXLPBKGBCH) << 32) + - (SXE_REG_READ(hw,SXE_RXLPBKGBCL)); + (SXE_REG_READ(hw, SXE_RXLPBKGBCL)); =20 - stats->rxdlpbkpc +=3D SXE_REG_READ(hw,SXE_RXDLPBKGPC); + stats->rxdlpbkpc +=3D SXE_REG_READ(hw, SXE_RXDLPBKGPC); stats->rxdlpbkbc +=3D ((u64)SXE_REG_READ(hw, SXE_RXDLPBKGBCH) << 32) + - (SXE_REG_READ(hw,SXE_RXDLPBKGBCL)); - stats->rxtpcing +=3D SXE_REG_READ(hw,SXE_RXTPCIN); - stats->rxtpceng +=3D SXE_REG_READ(hw,SXE_RXTPCOUT); - stats->prddc +=3D SXE_REG_READ(hw,SXE_RXPRDDC); + (SXE_REG_READ(hw, SXE_RXDLPBKGBCL)); + stats->rxtpcing +=3D SXE_REG_READ(hw, SXE_RXTPCIN); + stats->rxtpceng +=3D SXE_REG_READ(hw, SXE_RXTPCOUT); + stats->prddc +=3D SXE_REG_READ(hw, SXE_RXPRDDC); stats->txswerr +=3D SXE_REG_READ(hw, SXE_TXSWERR); stats->txswitch +=3D SXE_REG_READ(hw, SXE_TXSWITCH); stats->txrepeat +=3D SXE_REG_READ(hw, SXE_TXREPEAT); @@ -4522,8 +4267,8 @@ void sxe_hw_stats_get(struct sxe_hw *hw, struct sxe_m= ac_stats *stats) stats->dburxgdreecnt[i] +=3D SXE_REG_READ(hw, SXE_DBUDREECNT(i)); rx_dbu_drop =3D SXE_REG_READ(hw, SXE_DBUDROFPCNT(i)); stats->dburxdrofpcnt[i] +=3D rx_dbu_drop; - stats->dbutxtcin[i] +=3D SXE_REG_READ(hw,SXE_DBUDTTCICNT(i)); - stats->dbutxtcout[i] +=3D SXE_REG_READ(hw,SXE_DBUDTTCOCNT(i)); + stats->dbutxtcin[i] +=3D SXE_REG_READ(hw, SXE_DBUDTTCICNT(i)); + stats->dbutxtcout[i] +=3D SXE_REG_READ(hw, SXE_DBUDTTCOCNT(i)); } =20 stats->fnavadd +=3D (SXE_REG_READ(hw, SXE_FNAVUSTAT) & 0xFFFF); @@ -4602,7 +4347,6 @@ void sxe_hw_stats_get(struct sxe_hw *hw, struct sxe_m= ac_stats *stats) stats->gotc =3D stats->total_gotc; #endif =20 - return; } =20 static u32 sxe_hw_tx_packets_num_get(struct sxe_hw *hw) @@ -4620,9 +4364,8 @@ static u32 sxe_hw_mac_stats_dump(struct sxe_hw *hw, u= 32 *regs_buff, u32 buf_size u32 i; u32 regs_num =3D buf_size / sizeof(u32); =20 - for (i =3D 0; i < regs_num; i++) { + for (i =3D 0; i < regs_num; i++) regs_buff[i] =3D SXE_REG_READ(hw, mac_regs[i]); - } =20 return i; } @@ -4649,11 +4392,10 @@ void sxe_hw_mbx_init(struct sxe_hw *hw) =20 hw->mbx.stats.rcv_msgs =3D 0; hw->mbx.stats.send_msgs =3D 0; - hw->mbx.stats.acks =3D 0; - hw->mbx.stats.reqs =3D 0; - hw->mbx.stats.rsts =3D 0; + hw->mbx.stats.acks =3D 0; + hw->mbx.stats.reqs =3D 0; + hw->mbx.stats.rsts =3D 0; =20 - return; } =20 static bool sxe_hw_vf_irq_check(struct sxe_hw *hw, u32 mask, u32 index) @@ -4752,7 +4494,7 @@ s32 sxe_hw_rcv_msg_from_vf(struct sxe_hw *hw, u32 *ms= g, for (i =3D 0; i < msg_entry; i++) { msg[i] =3D SXE_REG_READ(hw, (SXE_PFMBMEM(index) + (i << 2))); LOG_DEBUG_BDF("vf_idx:%u read mbx mem[%u]:0x%x.\n", - index, i, msg[i]); + index, i, msg[i]); } =20 SXE_REG_WRITE(hw, SXE_PFMAILBOX(index), SXE_PFMAILBOX_ACK); @@ -4788,16 +4530,15 @@ s32 sxe_hw_send_msg_to_vf(struct sxe_hw *hw, u32 *m= sg, =20 old =3D SXE_REG_READ(hw, (SXE_PFMBMEM(index))); LOG_DEBUG_BDF("original send msg:0x%x. mbx mem[0]:0x%x\n", *msg, old); - if (msg[0] & SXE_CTRL_MSG_MASK) { + if (msg[0] & SXE_CTRL_MSG_MASK) msg[0] |=3D (old & SXE_MSGID_MASK); - } else { + else msg[0] |=3D (old & SXE_PFMSG_MASK); - } =20 for (i =3D 0; i < msg_len; i++) { SXE_REG_WRITE(hw, (SXE_PFMBMEM(index) + (i << 2)), msg[i]); LOG_DEBUG_BDF("vf_idx:%u write mbx mem[%u]:0x%x.\n", - index, i, msg[i]); + index, i, msg[i]); } =20 SXE_REG_WRITE(hw, SXE_PFMAILBOX(index), SXE_PFMAILBOX_STS); @@ -4811,14 +4552,12 @@ void sxe_hw_mbx_mem_clear(struct sxe_hw *hw, u8 vf_= idx) { u8 msg_idx; struct sxe_adapter *adapter =3D hw->adapter; - for (msg_idx =3D 0; msg_idx < hw->mbx.msg_len; msg_idx++) { + for (msg_idx =3D 0; msg_idx < hw->mbx.msg_len; msg_idx++) SXE_REG_WRITE_ARRAY(hw, SXE_PFMBMEM(vf_idx), msg_idx, 0); - } =20 SXE_WRITE_FLUSH(hw); =20 LOG_INFO_BDF("vf_idx:%u clear mbx mem.\n", vf_idx); - return; } =20 static const struct sxe_mbx_operations sxe_mbx_ops =3D { @@ -4838,7 +4577,6 @@ void sxe_hw_pcie_vt_mode_set(struct sxe_hw *hw, u32 v= alue) { SXE_REG_WRITE(hw, SXE_GCR_EXT, value); =20 - return; } =20 static const struct sxe_pcie_operations sxe_pcie_ops =3D { @@ -4857,9 +4595,8 @@ s32 sxe_hw_hdc_lock_get(struct sxe_hw *hw, u32 tryloc= k) =20 for (i =3D 0; i < trylock; i++) { val =3D SXE_REG_READ(hw, SXE_HDC_SW_LK) & SXE_HDC_SW_LK_BIT; - if (!val) { + if (!val) break; - } =20 udelay(10); } @@ -4898,9 +4635,8 @@ void sxe_hw_hdc_lock_release(struct sxe_hw *hw, u32 r= etry_cnt) hw->hdc.pf_lock_val =3D 0; break; } - } while((retry_cnt--) > 0); + } while ((retry_cnt--) > 0); =20 - return; } =20 void sxe_hw_hdc_fw_ov_clear(struct sxe_hw *hw) @@ -4912,9 +4648,8 @@ bool sxe_hw_hdc_is_fw_over_set(struct sxe_hw *hw) { bool fw_ov =3D false; =20 - if (SXE_REG_READ(hw, SXE_HDC_FW_OV) & SXE_HDC_FW_OV_BIT) { + if (SXE_REG_READ(hw, SXE_HDC_FW_OV) & SXE_HDC_FW_OV_BIT) fw_ov =3D true; - } =20 return fw_ov; } @@ -4924,21 +4659,18 @@ void sxe_hw_hdc_packet_send_done(struct sxe_hw *hw) SXE_REG_WRITE(hw, SXE_HDC_SW_OV, SXE_HDC_SW_OV_BIT); SXE_WRITE_FLUSH(hw); =20 - return; } =20 void sxe_hw_hdc_packet_header_send(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_HDC_PACKET_HEAD0, value); =20 - return; } =20 void sxe_hw_hdc_packet_data_dword_send(struct sxe_hw *hw, u16 dword_index, u32 value) { SXE_WRITE_REG_ARRAY_32(hw, SXE_HDC_PACKET_DATA0, dword_index, value); - return; } =20 u32 sxe_hw_hdc_fw_ack_header_get(struct sxe_hw *hw) @@ -4965,7 +4697,6 @@ u32 sxe_hw_hdc_fw_status_get(struct sxe_hw *hw) void sxe_hw_hdc_drv_status_set(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_DRV_STATUS_REG, value); - return; } =20 u32 sxe_hw_hdc_channel_state_get(struct sxe_hw *hw) @@ -4979,7 +4710,7 @@ u32 sxe_hw_hdc_channel_state_get(struct sxe_hw *hw) return state; } =20 -STATIC u32 sxe_hw_hdc_irq_event_get(struct sxe_hw *hw) +static u32 sxe_hw_hdc_irq_event_get(struct sxe_hw *hw) { u32 status =3D SXE_REG_READ(hw, SXE_HDC_MSI_STATUS_REG); struct sxe_adapter *adapter =3D hw->adapter; @@ -4999,7 +4730,6 @@ static void sxe_hw_hdc_irq_event_clear(struct sxe_hw = *hw, u32 event) status &=3D ~event; SXE_REG_WRITE(hw, SXE_HDC_MSI_STATUS_REG, status); =20 - return; } =20 static void sxe_hw_hdc_resource_clean(struct sxe_hw *hw) @@ -5008,33 +4738,31 @@ static void sxe_hw_hdc_resource_clean(struct sxe_hw= *hw) =20 SXE_REG_WRITE(hw, SXE_HDC_SW_LK, 0x0); SXE_REG_WRITE(hw, SXE_HDC_PACKET_HEAD0, 0x0); - for (i =3D 0; i < SXE_HDC_DATA_LEN_MAX; i++) { + for (i =3D 0; i < SXE_HDC_DATA_LEN_MAX; i++) SXE_WRITE_REG_ARRAY_32(hw, SXE_HDC_PACKET_DATA0, i, 0x0); - } =20 - return; } =20 static const struct sxe_hdc_operations sxe_hdc_ops =3D { - .pf_lock_get =3D sxe_hw_hdc_lock_get, - .pf_lock_release =3D sxe_hw_hdc_lock_release, - .is_fw_over_set =3D sxe_hw_hdc_is_fw_over_set, - .fw_ack_header_rcv =3D sxe_hw_hdc_fw_ack_header_get, - .packet_send_done =3D sxe_hw_hdc_packet_send_done, - .packet_header_send =3D sxe_hw_hdc_packet_header_send, + .pf_lock_get =3D sxe_hw_hdc_lock_get, + .pf_lock_release =3D sxe_hw_hdc_lock_release, + .is_fw_over_set =3D sxe_hw_hdc_is_fw_over_set, + .fw_ack_header_rcv =3D sxe_hw_hdc_fw_ack_header_get, + .packet_send_done =3D sxe_hw_hdc_packet_send_done, + .packet_header_send =3D sxe_hw_hdc_packet_header_send, .packet_data_dword_send =3D sxe_hw_hdc_packet_data_dword_send, .packet_data_dword_rcv =3D sxe_hw_hdc_packet_data_dword_rcv, - .fw_status_get =3D sxe_hw_hdc_fw_status_get, - .drv_status_set =3D sxe_hw_hdc_drv_status_set, - .irq_event_get =3D sxe_hw_hdc_irq_event_get, - .irq_event_clear =3D sxe_hw_hdc_irq_event_clear, - .fw_ov_clear =3D sxe_hw_hdc_fw_ov_clear, - .channel_state_get =3D sxe_hw_hdc_channel_state_get, - .resource_clean =3D sxe_hw_hdc_resource_clean, + .fw_status_get =3D sxe_hw_hdc_fw_status_get, + .drv_status_set =3D sxe_hw_hdc_drv_status_set, + .irq_event_get =3D sxe_hw_hdc_irq_event_get, + .irq_event_clear =3D sxe_hw_hdc_irq_event_clear, + .fw_ov_clear =3D sxe_hw_hdc_fw_ov_clear, + .channel_state_get =3D sxe_hw_hdc_channel_state_get, + .resource_clean =3D sxe_hw_hdc_resource_clean, }; =20 #ifdef SXE_PHY_CONFIGURE -#define SXE_MDIO_COMMAND_TIMEOUT 100=20 +#define SXE_MDIO_COMMAND_TIMEOUT 100 =20 static s32 sxe_hw_phy_reg_write(struct sxe_hw *hw, s32 prtad, u32 reg_addr, u32 device_type, u16 phy_data) @@ -5056,9 +4784,9 @@ static s32 sxe_hw_phy_reg_write(struct sxe_hw *hw, s3= 2 prtad, u32 reg_addr, udelay(10); =20 command =3D SXE_REG_READ(hw, SXE_MSCA); - if ((command & SXE_MSCA_MDI_CMD_ON_PROG) =3D=3D 0) { + if ((command & SXE_MSCA_MDI_CMD_ON_PROG) =3D=3D 0) break; - } + } =20 if ((command & SXE_MSCA_MDI_CMD_ON_PROG) !=3D 0) { @@ -5079,9 +4807,8 @@ static s32 sxe_hw_phy_reg_write(struct sxe_hw *hw, s3= 2 prtad, u32 reg_addr, udelay(10); =20 command =3D SXE_REG_READ(hw, SXE_MSCA); - if ((command & SXE_MSCA_MDI_CMD_ON_PROG) =3D=3D 0) { + if ((command & SXE_MSCA_MDI_CMD_ON_PROG) =3D=3D 0) break; - } } =20 if ((command & SXE_MSCA_MDI_CMD_ON_PROG) !=3D 0) { @@ -5112,9 +4839,8 @@ static s32 sxe_hw_phy_reg_read(struct sxe_hw *hw, s32= prtad, u32 reg_addr, udelay(10); =20 command =3D SXE_REG_READ(hw, SXE_MSCA); - if ((command & SXE_MSCA_MDI_CMD_ON_PROG) =3D=3D 0) { + if ((command & SXE_MSCA_MDI_CMD_ON_PROG) =3D=3D 0) break; - } } =20 if ((command & SXE_MSCA_MDI_CMD_ON_PROG) !=3D 0) { @@ -5166,7 +4892,7 @@ static s32 sxe_hw_phy_id_get(struct sxe_hw *hw, u32 p= rtad, u32 *id) =20 =20 ret =3D sxe_hw_phy_reg_read(hw, prtad, MDIO_DEVID1, MDIO_MMD_PMAPMD, - &phy_id_low); + &phy_id_low); =20 if (ret) { LOG_ERROR("get phy id upper 16 bits failed, prtad=3D%d\n", prtad); @@ -5193,7 +4919,7 @@ s32 sxe_hw_phy_link_cap_get(struct sxe_hw *hw, u32 pr= tad, u32 *speed) u16 speed_ability; =20 ret =3D hw->phy.ops->reg_read(hw, prtad, MDIO_SPEED, MDIO_MMD_PMAPMD, - &speed_ability); + &speed_ability); if (ret) { *speed =3D 0; LOG_ERROR("get phy link cap failed, ret=3D%d, prtad=3D%d\n", @@ -5201,17 +4927,14 @@ s32 sxe_hw_phy_link_cap_get(struct sxe_hw *hw, u32 = prtad, u32 *speed) goto l_end; } =20 - if (speed_ability & MDIO_SPEED_10G) { + if (speed_ability & MDIO_SPEED_10G) *speed |=3D SXE_LINK_SPEED_10GB_FULL; - } =20 - if (speed_ability & MDIO_PMA_SPEED_1000) { + if (speed_ability & MDIO_PMA_SPEED_1000) *speed |=3D SXE_LINK_SPEED_1GB_FULL; - } =20 - if (speed_ability & MDIO_PMA_SPEED_100) { + if (speed_ability & MDIO_PMA_SPEED_100) *speed |=3D SXE_LINK_SPEED_100_FULL; - } =20 l_end: return ret; @@ -5234,9 +4957,8 @@ static s32 sxe_hw_phy_ctrl_reset(struct sxe_hw *hw, u= 32 prtad) msleep(100); ret =3D sxe_hw_phy_reg_read(hw, prtad, MDIO_CTRL1, MDIO_MMD_PHYXS, &ctrl); - if (ret) { + if (ret) goto l_end; - } =20 if (!(ctrl & MDIO_CTRL1_RESET)) { udelay(2); @@ -5275,23 +4997,21 @@ void sxe_hw_ops_init(struct sxe_hw *hw) hw->pcie.ops =3D &sxe_pcie_ops; hw->hdc.ops =3D &sxe_hdc_ops; #ifdef SXE_PHY_CONFIGURE - hw->phy.ops =3D &sxe_phy_hw_ops; + hw->phy.ops =3D &sxe_phy_hw_ops; #endif =20 hw->filter.mac.ops =3D &sxe_filter_mac_ops; hw->filter.vlan.ops =3D &sxe_filter_vlan_ops; - return; } =20 u32 sxe_hw_rss_key_get_by_idx(struct sxe_hw *hw, u8 reg_idx) { u32 rss_key; =20 - if (reg_idx >=3D SXE_MAX_RSS_KEY_ENTRIES) { + if (reg_idx >=3D SXE_MAX_RSS_KEY_ENTRIES) rss_key =3D 0; - } else { + else rss_key =3D SXE_REG_READ(hw, SXE_RSSRK(reg_idx)); - } =20 return rss_key; } @@ -5300,9 +5020,8 @@ bool sxe_hw_is_rss_enabled(struct sxe_hw *hw) { bool rss_enable =3D false; u32 mrqc =3D SXE_REG_READ(hw, SXE_MRQC); - if (mrqc & SXE_MRQC_RSSEN) { + if (mrqc & SXE_MRQC_RSSEN) rss_enable =3D true; - } =20 return rss_enable; } @@ -5318,15 +5037,28 @@ u32 sxe_hw_rss_field_get(struct sxe_hw *hw) return (mrqc & SXE_RSS_FIELD_MASK); } =20 -#ifdef SXE_DPDK=20 +#ifdef SXE_DPDK =20 #define SXE_TRAFFIC_CLASS_MAX 8 =20 -#define SXE_MR_VLAN_MSB_REG_OFFSET 4 +#define SXE_MR_VLAN_MSB_REG_OFFSET 4 #define SXE_MR_VIRTUAL_POOL_MSB_REG_OFFSET 4 =20 -#define SXE_MR_TYPE_MASK 0x0F -#define SXE_MR_DST_POOL_OFFSET 8 +#define SXE_MR_TYPE_MASK 0x0F +#define SXE_MR_DST_POOL_OFFSET 8 + +void sxe_hw_crc_strip_config(struct sxe_hw *hw, bool keep_crc) +{ + u32 crcflag =3D SXE_REG_READ(hw, SXE_CRC_STRIP_REG); + + if (keep_crc) { + crcflag |=3D SXE_KEEP_CRC_EN; + } else { + crcflag &=3D ~SXE_KEEP_CRC_EN; + } + + SXE_REG_WRITE(hw, SXE_CRC_STRIP_REG, crcflag); +} =20 void sxe_hw_rx_pkt_buf_size_set(struct sxe_hw *hw, u8 tc_idx, u16 pbsize) { @@ -5336,7 +5068,6 @@ void sxe_hw_rx_pkt_buf_size_set(struct sxe_hw *hw, u8= tc_idx, u16 pbsize) SXE_REG_WRITE(hw, SXE_RXPBSIZE(tc_idx), rxpbsize); sxe_hw_rx_pkt_buf_switch(hw, true); =20 - return; } =20 void sxe_hw_dcb_vmdq_mq_configure(struct sxe_hw *hw, u8 num_pools) @@ -5349,13 +5080,11 @@ void sxe_hw_dcb_vmdq_mq_configure(struct sxe_hw *hw= , u8 num_pools) =20 pbsize =3D (u8)(SXE_RX_PKT_BUF_SIZE / nb_tcs); =20 - for (i =3D 0; i < nb_tcs; i++) { + for (i =3D 0; i < nb_tcs; i++) sxe_hw_rx_pkt_buf_size_set(hw, i, pbsize); - } =20 - for (i =3D nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) { + for (i =3D nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) sxe_hw_rx_pkt_buf_size_set(hw, i, 0); - } =20 mrqc =3D (num_pools =3D=3D RTE_ETH_16_POOLS) ? SXE_MRQC_VMDQRT8TCEN : SXE_MRQC_VMDQRT4TCEN; @@ -5363,7 +5092,6 @@ void sxe_hw_dcb_vmdq_mq_configure(struct sxe_hw *hw, = u8 num_pools) =20 SXE_REG_WRITE(hw, SXE_RTRPCS, SXE_RTRPCS_RRM); =20 - return; } =20 static const struct sxe_reg_info sxe_regs_general_group[] =3D { @@ -5468,9 +5196,8 @@ static u32 sxe_regs_group_count(const struct sxe_reg_= info *regs) int i =3D 0; int count =3D 0; =20 - while (regs[i].count) { + while (regs[i].count) count +=3D regs[i++].count; - } =20 return count; }; @@ -5487,7 +5214,7 @@ static u32 sxe_hw_regs_group_read(struct sxe_hw *hw, reg_buf[count + j] =3D SXE_REG_READ(hw, regs[i].addr + j * regs[i].stride); LOG_INFO("regs=3D %s, regs_addr=3D%x, regs_value=3D%04x\n", - regs[i].name , regs[i].addr, reg_buf[count + j]); + regs[i].name, regs[i].addr, reg_buf[count + j]); } =20 i++; @@ -5504,9 +5231,8 @@ u32 sxe_hw_all_regs_group_num_get(void) const struct sxe_reg_info *reg_group; const struct sxe_reg_info **reg_set =3D sxe_regs_group; =20 - while ((reg_group =3D reg_set[i++])) { + while ((reg_group =3D reg_set[i++])) count +=3D sxe_regs_group_count(reg_group); - } =20 return count; } @@ -5517,14 +5243,12 @@ void sxe_hw_all_regs_group_read(struct sxe_hw *hw, = u32 *data) const struct sxe_reg_info *reg_group; const struct sxe_reg_info **reg_set =3D sxe_regs_group; =20 - while ((reg_group =3D reg_set[i++])) { + while ((reg_group =3D reg_set[i++])) count +=3D sxe_hw_regs_group_read(hw, reg_group, &data[count]); - } =20 LOG_INFO("read regs cnt=3D%u, regs num=3D%u\n", count, sxe_hw_all_regs_group_num_get()); =20 - return; } =20 static void sxe_hw_default_pool_configure(struct sxe_hw *hw, @@ -5534,14 +5258,12 @@ static void sxe_hw_default_pool_configure(struct sx= e_hw *hw, u32 vt_ctl; =20 vt_ctl =3D SXE_VT_CTL_VT_ENABLE | SXE_VT_CTL_REPLEN; - if (default_pool_enabled) { + if (default_pool_enabled) vt_ctl |=3D (default_pool_idx << SXE_VT_CTL_POOL_SHIFT); - } else { + else vt_ctl |=3D SXE_VT_CTL_DIS_DEFPL; - } =20 SXE_REG_WRITE(hw, SXE_VT_CTL, vt_ctl); - return; } =20 void sxe_hw_dcb_vmdq_default_pool_configure(struct sxe_hw *hw, @@ -5549,31 +5271,27 @@ void sxe_hw_dcb_vmdq_default_pool_configure(struct = sxe_hw *hw, u8 default_pool_idx) { sxe_hw_default_pool_configure(hw, default_pool_enabled, default_pool_idx); - return; } =20 u32 sxe_hw_ring_irq_switch_get(struct sxe_hw *hw, u8 idx) { u32 mask; =20 - if (idx =3D=3D 0) { + if (idx =3D=3D 0) mask =3D SXE_REG_READ(hw, SXE_EIMS_EX(0)); - } else { + else mask =3D SXE_REG_READ(hw, SXE_EIMS_EX(1)); - } =20 return mask; } =20 void sxe_hw_ring_irq_switch_set(struct sxe_hw *hw, u8 idx, u32 value) { - if (idx =3D=3D 0) { + if (idx =3D=3D 0) SXE_REG_WRITE(hw, SXE_EIMS_EX(0), value); - } else { + else SXE_REG_WRITE(hw, SXE_EIMS_EX(1), value); - } =20 - return; } =20 void sxe_hw_dcb_vmdq_up_2_tc_configure(struct sxe_hw *hw, @@ -5583,13 +5301,11 @@ void sxe_hw_dcb_vmdq_up_2_tc_configure(struct sxe_h= w *hw, u8 i; =20 up2tc =3D 0; - for (i =3D 0; i < MAX_USER_PRIORITY; i++) { + for (i =3D 0; i < MAX_USER_PRIORITY; i++) up2tc |=3D ((tc_arr[i] & 0x07) << (i * 3)); - } =20 SXE_REG_WRITE(hw, SXE_RTRUP2TC, up2tc); =20 - return; } =20 u32 sxe_hw_uta_hash_table_get(struct sxe_hw *hw, u8 reg_idx) @@ -5602,7 +5318,6 @@ void sxe_hw_uta_hash_table_set(struct sxe_hw *hw, { SXE_REG_WRITE(hw, SXE_UTA(reg_idx), value); =20 - return; } =20 u32 sxe_hw_vlan_type_get(struct sxe_hw *hw) @@ -5613,7 +5328,6 @@ u32 sxe_hw_vlan_type_get(struct sxe_hw *hw) void sxe_hw_vlan_type_set(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_VLNCTRL, value); - return; } =20 void sxe_hw_dcb_vmdq_vlan_configure(struct sxe_hw *hw, @@ -5626,9 +5340,8 @@ void sxe_hw_dcb_vmdq_vlan_configure(struct sxe_hw *hw, vlanctrl |=3D SXE_VLNCTRL_VFE; SXE_REG_WRITE(hw, SXE_VLNCTRL, vlanctrl); =20 - for (i =3D 0; i < SXE_VFT_TBL_SIZE; i++) { + for (i =3D 0; i < SXE_VFT_TBL_SIZE; i++) SXE_REG_WRITE(hw, SXE_VFTA(i), 0xFFFFFFFF); - } =20 SXE_REG_WRITE(hw, SXE_VFRE(0), num_pools =3D=3D RTE_ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF); @@ -5636,13 +5349,11 @@ void sxe_hw_dcb_vmdq_vlan_configure(struct sxe_hw *= hw, SXE_REG_WRITE(hw, SXE_MPSAR_LOW(0), 0xFFFFFFFF); SXE_REG_WRITE(hw, SXE_MPSAR_HIGH(0), 0xFFFFFFFF); =20 - return; } =20 void sxe_hw_vlan_ext_type_set(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_EXVET, value); - return; } =20 u32 sxe_hw_txctl_vlan_type_get(struct sxe_hw *hw) @@ -5653,7 +5364,6 @@ u32 sxe_hw_txctl_vlan_type_get(struct sxe_hw *hw) void sxe_hw_txctl_vlan_type_set(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_DMATXCTL, value); - return; } =20 u32 sxe_hw_ext_vlan_get(struct sxe_hw *hw) @@ -5664,13 +5374,11 @@ u32 sxe_hw_ext_vlan_get(struct sxe_hw *hw) void sxe_hw_ext_vlan_set(struct sxe_hw *hw, u32 value) { SXE_REG_WRITE(hw, SXE_CTRL_EXT, value); - return; } =20 void sxe_hw_rxq_stat_map_set(struct sxe_hw *hw, u8 idx, u32 value) { SXE_REG_WRITE(hw, SXE_RQSMR(idx), value); - return; } =20 void sxe_hw_dcb_vmdq_pool_configure(struct sxe_hw *hw, @@ -5682,13 +5390,11 @@ void sxe_hw_dcb_vmdq_pool_configure(struct sxe_hw *= hw, =20 SXE_REG_WRITE(hw, SXE_VLVFB(pool_idx * 2), pools_map); =20 - return; } =20 void sxe_hw_txq_stat_map_set(struct sxe_hw *hw, u8 idx, u32 value) { SXE_REG_WRITE(hw, SXE_TQSM(idx), value); - return; } =20 void sxe_hw_dcb_rx_configure(struct sxe_hw *hw, bool is_vt_on, @@ -5746,14 +5452,12 @@ void sxe_hw_dcb_rx_configure(struct sxe_hw *hw, boo= l is_vt_on, vlanctrl |=3D SXE_VLNCTRL_VFE; SXE_REG_WRITE(hw, SXE_VLNCTRL, vlanctrl); =20 - for (i =3D 0; i < SXE_VFT_TBL_SIZE; i++) { + for (i =3D 0; i < SXE_VFT_TBL_SIZE; i++) SXE_REG_WRITE(hw, SXE_VFTA(i), 0xFFFFFFFF); - } =20 reg =3D SXE_RTRPCS_RRM | SXE_RTRPCS_RAC; SXE_REG_WRITE(hw, SXE_RTRPCS, reg); =20 - return; } =20 void sxe_hw_fc_status_get(struct sxe_hw *hw, @@ -5762,19 +5466,16 @@ void sxe_hw_fc_status_get(struct sxe_hw *hw, u32 flctrl; =20 flctrl =3D SXE_REG_READ(hw, SXE_FLCTRL); - if (flctrl & (SXE_FCTRL_RFCE_PFC_EN | SXE_FCTRL_RFCE_LFC_EN)) { + if (flctrl & (SXE_FCTRL_RFCE_PFC_EN | SXE_FCTRL_RFCE_LFC_EN)) *rx_pause_on =3D true; - } else { + else *rx_pause_on =3D false; - } =20 - if (flctrl & (SXE_FCTRL_TFCE_PFC_EN | SXE_FCTRL_TFCE_LFC_EN)) { + if (flctrl & (SXE_FCTRL_TFCE_PFC_EN | SXE_FCTRL_TFCE_LFC_EN)) *tx_pause_on =3D true; - } else { + else *tx_pause_on =3D false; - } =20 - return; } =20 void sxe_hw_fc_base_init(struct sxe_hw *hw) @@ -5792,7 +5493,6 @@ void sxe_hw_fc_base_init(struct sxe_hw *hw) } =20 hw->fc.send_xon =3D 1; - return; } =20 u32 sxe_hw_fc_tc_high_water_mark_get(struct sxe_hw *hw, u8 tc_idx) @@ -5813,7 +5513,6 @@ u16 sxe_hw_fc_send_xon_get(struct sxe_hw *hw) void sxe_hw_fc_send_xon_set(struct sxe_hw *hw, u16 send_xon) { hw->fc.send_xon =3D send_xon; - return; } =20 u16 sxe_hw_fc_pause_time_get(struct sxe_hw *hw) @@ -5824,7 +5523,6 @@ u16 sxe_hw_fc_pause_time_get(struct sxe_hw *hw) void sxe_hw_fc_pause_time_set(struct sxe_hw *hw, u16 pause_time) { hw->fc.pause_time =3D pause_time; - return; } =20 void sxe_hw_dcb_tx_configure(struct sxe_hw *hw, bool is_vt_on, u8 tc_num) @@ -5835,15 +5533,13 @@ void sxe_hw_dcb_tx_configure(struct sxe_hw *hw, boo= l is_vt_on, u8 tc_num) reg |=3D SXE_RTTDCS_ARBDIS; SXE_REG_WRITE(hw, SXE_RTTDCS, reg); =20 - if (tc_num =3D=3D 8) { + if (tc_num =3D=3D 8) reg =3D SXE_MTQC_RT_ENA | SXE_MTQC_8TC_8TQ; - } else { + else reg =3D SXE_MTQC_RT_ENA | SXE_MTQC_4TC_4TQ; - } =20 - if (is_vt_on) { + if (is_vt_on) reg |=3D SXE_MTQC_VT_ENA; - } =20 SXE_REG_WRITE(hw, SXE_MTQC, reg); =20 @@ -5852,7 +5548,6 @@ void sxe_hw_dcb_tx_configure(struct sxe_hw *hw, bool = is_vt_on, u8 tc_num) SXE_REG_WRITE(hw, SXE_RTTDCS, reg); =20 =20 - return; } =20 void sxe_hw_rx_ip_checksum_offload_switch(struct sxe_hw *hw, @@ -5861,36 +5556,31 @@ void sxe_hw_rx_ip_checksum_offload_switch(struct sx= e_hw *hw, u32 rxcsum; =20 rxcsum =3D SXE_REG_READ(hw, SXE_RXCSUM); - if (is_on) { + if (is_on) rxcsum |=3D SXE_RXCSUM_IPPCSE; - } else { + else rxcsum &=3D ~SXE_RXCSUM_IPPCSE; - } =20 SXE_REG_WRITE(hw, SXE_RXCSUM, rxcsum); =20 - return; } =20 void sxe_hw_rss_cap_switch(struct sxe_hw *hw, bool is_on) { u32 mrqc =3D SXE_REG_READ(hw, SXE_MRQC); - if (is_on) { + if (is_on) mrqc |=3D SXE_MRQC_RSSEN; - } else { + else mrqc &=3D ~SXE_MRQC_RSSEN; - } =20 SXE_REG_WRITE(hw, SXE_MRQC, mrqc); =20 - return; } =20 void sxe_hw_pool_xmit_enable(struct sxe_hw *hw, u16 reg_idx, u8 pool_num) { SXE_REG_WRITE(hw, SXE_VFTE(reg_idx), pool_num =3D=3D RTE_ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF); - return; } =20 void sxe_hw_rss_field_set(struct sxe_hw *hw, u32 rss_field) @@ -5901,7 +5591,6 @@ void sxe_hw_rss_field_set(struct sxe_hw *hw, u32 rss_= field) mrqc |=3D rss_field; SXE_REG_WRITE(hw, SXE_MRQC, mrqc); =20 - return; } =20 static void sxe_hw_dcb_4tc_vmdq_off_stats_configure(struct sxe_hw *hw) @@ -5910,44 +5599,38 @@ static void sxe_hw_dcb_4tc_vmdq_off_stats_configure= (struct sxe_hw *hw) u8 i; =20 for (i =3D 0; i < 32; i++) { - if (i % 8 > 3) { + if (i % 8 > 3) continue; - } =20 reg =3D 0x01010101 * (i / 8); SXE_REG_WRITE(hw, SXE_RQSMR(i), reg); } for (i =3D 0; i < 32; i++) { - if (i < 16) { + if (i < 16) reg =3D 0x00000000; - } else if (i < 24) { + else if (i < 24) reg =3D 0x01010101; - } else if (i < 28) { + else if (i < 28) reg =3D 0x02020202; - } else { + else reg =3D 0x03030303; - } =20 SXE_REG_WRITE(hw, SXE_TQSM(i), reg); } =20 - return; } =20 static void sxe_hw_dcb_4tc_vmdq_on_stats_configure(struct sxe_hw *hw) { u8 i; =20 - for (i =3D 0; i < 32; i++) { + for (i =3D 0; i < 32; i++) SXE_REG_WRITE(hw, SXE_RQSMR(i), 0x03020100); - } =20 =20 - for (i =3D 0; i < 32; i++) { + for (i =3D 0; i < 32; i++) SXE_REG_WRITE(hw, SXE_TQSM(i), 0x03020100); - } =20 - return; } =20 void sxe_hw_rss_redir_tbl_set_by_idx(struct sxe_hw *hw, @@ -5969,21 +5652,18 @@ u32 sxe_hw_rss_redir_tbl_get_by_idx(struct sxe_hw *= hw, u16 reg_idx) void sxe_hw_ptp_time_inc_stop(struct sxe_hw *hw) { SXE_REG_WRITE(hw, SXE_TIMINC, 0); - return; } =20 void sxe_hw_dcb_tc_stats_configure(struct sxe_hw *hw, u8 tc_num, bool vmdq_active) { - if (tc_num =3D=3D 8 && vmdq_active =3D=3D false) { + if (tc_num =3D=3D 8 && vmdq_active =3D=3D false) sxe_hw_dcb_8tc_vmdq_off_stats_configure(hw); - } else if (tc_num =3D=3D 4 && vmdq_active =3D=3D false) { + else if (tc_num =3D=3D 4 && vmdq_active =3D=3D false) sxe_hw_dcb_4tc_vmdq_off_stats_configure(hw); - } else if (tc_num =3D=3D 4 && vmdq_active =3D=3D true) { + else if (tc_num =3D=3D 4 && vmdq_active =3D=3D true) sxe_hw_dcb_4tc_vmdq_on_stats_configure(hw); - } =20 - return; } =20 void sxe_hw_ptp_timestamp_disable(struct sxe_hw *hw) @@ -5997,7 +5677,6 @@ void sxe_hw_ptp_timestamp_disable(struct sxe_hw *hw) ~SXE_TSYNCRXCTL_REN)); SXE_WRITE_FLUSH(hw); =20 - return; } =20 void sxe_hw_mac_pool_clear(struct sxe_hw *hw, u8 rar_idx) @@ -6007,14 +5686,12 @@ void sxe_hw_mac_pool_clear(struct sxe_hw *hw, u8 ra= r_idx) if (rar_idx > SXE_UC_ENTRY_NUM_MAX) { LOG_ERROR_BDF("rar_idx:%d invalid.(err:%d)\n", rar_idx, SXE_ERR_PARAM); - goto l_end; + return; } =20 SXE_REG_WRITE(hw, SXE_MPSAR_LOW(rar_idx), 0); SXE_REG_WRITE(hw, SXE_MPSAR_HIGH(rar_idx), 0); =20 -l_end: - return; } =20 void sxe_hw_vmdq_mq_configure(struct sxe_hw *hw) @@ -6024,7 +5701,6 @@ void sxe_hw_vmdq_mq_configure(struct sxe_hw *hw) mrqc =3D SXE_MRQC_VMDQEN; SXE_REG_WRITE(hw, SXE_MRQC, mrqc); =20 - return; } =20 void sxe_hw_vmdq_default_pool_configure(struct sxe_hw *hw, @@ -6032,7 +5708,6 @@ void sxe_hw_vmdq_default_pool_configure(struct sxe_hw= *hw, u8 default_pool_idx) { sxe_hw_default_pool_configure(hw, default_pool_enabled, default_pool_idx); - return; } =20 void sxe_hw_vmdq_vlan_configure(struct sxe_hw *hw, @@ -6045,24 +5720,20 @@ void sxe_hw_vmdq_vlan_configure(struct sxe_hw *hw, vlanctrl |=3D SXE_VLNCTRL_VFE; SXE_REG_WRITE(hw, SXE_VLNCTRL, vlanctrl); =20 - for (i =3D 0; i < SXE_VFT_TBL_SIZE; i++) { + for (i =3D 0; i < SXE_VFT_TBL_SIZE; i++) SXE_REG_WRITE(hw, SXE_VFTA(i), 0xFFFFFFFF); - } =20 SXE_REG_WRITE(hw, SXE_VFRE(0), 0xFFFFFFFF); - if (num_pools =3D=3D RTE_ETH_64_POOLS) { + if (num_pools =3D=3D RTE_ETH_64_POOLS) SXE_REG_WRITE(hw, SXE_VFRE(1), 0xFFFFFFFF); - } =20 - for (i =3D 0; i < num_pools; i++) { + for (i =3D 0; i < num_pools; i++) SXE_REG_WRITE(hw, SXE_VMOLR(i), rx_mode); - } =20 SXE_REG_WRITE(hw, SXE_MPSAR_LOW(0), 0xFFFFFFFF); SXE_REG_WRITE(hw, SXE_MPSAR_HIGH(0), 0xFFFFFFFF); =20 SXE_WRITE_FLUSH(hw); - return; } =20 u32 sxe_hw_pcie_vt_mode_get(struct sxe_hw *hw) @@ -6082,7 +5753,6 @@ void sxe_rx_fc_threshold_set(struct sxe_hw *hw) SXE_REG_WRITE(hw, SXE_FCRTH(i), high); } =20 - return; } =20 void sxe_hw_vmdq_pool_configure(struct sxe_hw *hw, @@ -6101,19 +5771,16 @@ void sxe_hw_vmdq_pool_configure(struct sxe_hw *hw, } =20 SXE_WRITE_FLUSH(hw); - return; } =20 void sxe_hw_vmdq_loopback_configure(struct sxe_hw *hw) { u8 i; SXE_REG_WRITE(hw, SXE_PFDTXGSWC, SXE_PFDTXGSWC_VT_LBEN); - for (i =3D 0; i < SXE_VMTXSW_REGISTER_COUNT; i++) { + for (i =3D 0; i < SXE_VMTXSW_REGISTER_COUNT; i++) SXE_REG_WRITE(hw, SXE_VMTXSW(i), 0xFFFFFFFF); - } =20 SXE_WRITE_FLUSH(hw); - return; } =20 void sxe_hw_tx_multi_queue_configure(struct sxe_hw *hw, @@ -6145,7 +5812,7 @@ void sxe_hw_tx_multi_queue_configure(struct sxe_hw *h= w, SXE_REG_WRITE(hw, SXE_VFTE(1), UINT32_MAX); =20 for (queue_idx =3D 0; queue_idx < SXE_HW_TXRX_RING_NUM_MAX; - queue_idx++) { + queue_idx++) { SXE_REG_WRITE(hw, SXE_QDE, (SXE_QDE_WRITE | (queue_idx << SXE_QDE_IDX_SHIFT))); @@ -6161,7 +5828,6 @@ void sxe_hw_tx_multi_queue_configure(struct sxe_hw *h= w, =20 sxe_hw_dcb_arbiter_set(hw, true); =20 - return; } =20 void sxe_hw_vf_queue_drop_enable(struct sxe_hw *hw, u8 vf_idx, @@ -6170,8 +5836,7 @@ void sxe_hw_vf_queue_drop_enable(struct sxe_hw *hw, u= 8 vf_idx, u32 value; u8 i; =20 - for (i =3D (vf_idx * ring_per_pool); i < ((vf_idx + 1) * ring_per_pool); = i++) - { + for (i =3D (vf_idx * ring_per_pool); i < ((vf_idx + 1) * ring_per_pool); = i++) { value =3D SXE_QDE_ENABLE | SXE_QDE_WRITE; SXE_WRITE_FLUSH(hw); =20 @@ -6180,7 +5845,6 @@ void sxe_hw_vf_queue_drop_enable(struct sxe_hw *hw, u= 8 vf_idx, SXE_REG_WRITE(hw, SXE_QDE, value); } =20 - return; } =20 bool sxe_hw_vt_status(struct sxe_hw *hw) @@ -6188,17 +5852,16 @@ bool sxe_hw_vt_status(struct sxe_hw *hw) bool ret; u32 vt_ctl =3D SXE_REG_READ(hw, SXE_VT_CTL); =20 - if (vt_ctl & SXE_VMD_CTL_POOL_EN) { + if (vt_ctl & SXE_VMD_CTL_POOL_EN) ret =3D true; - } else { + else ret =3D false; - } =20 return ret; } =20 void sxe_hw_mirror_ctl_set(struct sxe_hw *hw, u8 rule_id, - u8 mirror_type, u8 dst_pool, bool on) + u8 mirror_type, u8 dst_pool, bool on) { u32 mr_ctl; =20 @@ -6214,23 +5877,20 @@ void sxe_hw_mirror_ctl_set(struct sxe_hw *hw, u8 ru= le_id, =20 SXE_REG_WRITE(hw, SXE_MRCTL(rule_id), mr_ctl); =20 - return; } =20 -void sxe_hw_mirror_virtual_pool_set(struct sxe_hw *hw, u8 rule_id,u32 lsb,= u32 msb) +void sxe_hw_mirror_virtual_pool_set(struct sxe_hw *hw, u8 rule_id, u32 lsb= , u32 msb) { SXE_REG_WRITE(hw, SXE_VMRVM(rule_id), lsb); SXE_REG_WRITE(hw, SXE_VMRVM(rule_id + SXE_MR_VIRTUAL_POOL_MSB_REG_OFFSET= ), msb); =20 - return; } =20 -void sxe_hw_mirror_vlan_set(struct sxe_hw *hw, u8 rule_id,u32 lsb, u32 msb) +void sxe_hw_mirror_vlan_set(struct sxe_hw *hw, u8 rule_id, u32 lsb, u32 ms= b) { SXE_REG_WRITE(hw, SXE_VMRVLAN(rule_id), lsb); SXE_REG_WRITE(hw, SXE_VMRVLAN(rule_id + SXE_MR_VLAN_MSB_REG_OFFSET), msb= ); =20 - return; } =20 void sxe_hw_mirror_rule_clear(struct sxe_hw *hw, u8 rule_id) @@ -6243,7 +5903,6 @@ void sxe_hw_mirror_rule_clear(struct sxe_hw *hw, u8 r= ule_id) SXE_REG_WRITE(hw, SXE_VMRVM(rule_id), 0); SXE_REG_WRITE(hw, SXE_VMRVM(rule_id + SXE_MR_VIRTUAL_POOL_MSB_REG_OFFSET= ), 0); =20 - return; } =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL @@ -6266,28 +5925,29 @@ void sxe_hw_fivetuple_filter_add(struct rte_eth_dev= *dev, ftqf |=3D (u32)((filter->filter_info.priority & SXE_FTQF_PRIORITY_MASK) << SXE_FTQF_PRIORITY_SHIFT); =20 - if (filter->filter_info.src_ip_mask =3D=3D 0) { + if (filter->filter_info.src_ip_mask =3D=3D 0) mask &=3D SXE_FTQF_SOURCE_ADDR_MASK; - } - if (filter->filter_info.dst_ip_mask =3D=3D 0) { + + if (filter->filter_info.dst_ip_mask =3D=3D 0) mask &=3D SXE_FTQF_DEST_ADDR_MASK; - } - if (filter->filter_info.src_port_mask =3D=3D 0) { + + if (filter->filter_info.src_port_mask =3D=3D 0) mask &=3D SXE_FTQF_SOURCE_PORT_MASK; - } - if (filter->filter_info.dst_port_mask =3D=3D 0) { + + if (filter->filter_info.dst_port_mask =3D=3D 0) mask &=3D SXE_FTQF_DEST_PORT_MASK; - } - if (filter->filter_info.proto_mask =3D=3D 0) { + + if (filter->filter_info.proto_mask =3D=3D 0) mask &=3D SXE_FTQF_PROTOCOL_COMP_MASK; - } + ftqf |=3D mask << SXE_FTQF_5TUPLE_MASK_SHIFT; ftqf |=3D SXE_FTQF_POOL_MASK_EN; ftqf |=3D SXE_FTQF_QUEUE_ENABLE; =20 LOG_DEBUG("add fivetuple filter, index[%u], src_ip[0x%x], dst_ip[0x%x]" - "src_port[%u], dst_port[%u], ftqf[0x%x], queue[%u]", i, filter->filter_i= nfo.src_ip, - filter->filter_info.dst_ip, filter->filter_info.src_port, filter->filter= _info.dst_port, + "src_port[%u], dst_port[%u], ftqf[0x%x], queue[%u]", i, + filter->filter_info.src_ip, filter->filter_info.dst_ip, + filter->filter_info.src_port, filter->filter_info.dst_port, ftqf, filter->queue); =20 SXE_REG_WRITE(hw, SXE_DAQF(i), filter->filter_info.dst_ip); @@ -6299,7 +5959,6 @@ void sxe_hw_fivetuple_filter_add(struct rte_eth_dev *= dev, l34timir |=3D (u32)(filter->queue << SXE_L34T_IMIR_QUEUE_SHIFT); SXE_REG_WRITE(hw, SXE_L34T_IMIR(i), l34timir); =20 - return; } =20 void sxe_hw_fivetuple_filter_del(struct sxe_hw *hw, u16 reg_index) @@ -6310,7 +5969,6 @@ void sxe_hw_fivetuple_filter_del(struct sxe_hw *hw, u= 16 reg_index) SXE_REG_WRITE(hw, SXE_FTQF(reg_index), 0); SXE_REG_WRITE(hw, SXE_L34T_IMIR(reg_index), 0); =20 - return; } =20 void sxe_hw_ethertype_filter_add(struct sxe_hw *hw, @@ -6329,7 +5987,6 @@ void sxe_hw_ethertype_filter_add(struct sxe_hw *hw, SXE_REG_WRITE(hw, SXE_ETQS(reg_index), etqs); SXE_WRITE_FLUSH(hw); =20 - return; } =20 void sxe_hw_ethertype_filter_del(struct sxe_hw *hw, u8 filter_type) @@ -6338,7 +5995,6 @@ void sxe_hw_ethertype_filter_del(struct sxe_hw *hw, u= 8 filter_type) SXE_REG_WRITE(hw, SXE_ETQS(filter_type), 0); SXE_WRITE_FLUSH(hw); =20 - return; } =20 void sxe_hw_syn_filter_add(struct sxe_hw *hw, u16 queue, u8 priority) @@ -6348,16 +6004,14 @@ void sxe_hw_syn_filter_add(struct sxe_hw *hw, u16 q= ueue, u8 priority) synqf =3D (u32)(((queue << SXE_SYN_FILTER_QUEUE_SHIFT) & SXE_SYN_FILTER_QUEUE) | SXE_SYN_FILTER_ENABLE); =20 - if (priority) { + if (priority) synqf |=3D SXE_SYN_FILTER_SYNQFP; - } else { + else synqf &=3D ~SXE_SYN_FILTER_SYNQFP; - } =20 SXE_REG_WRITE(hw, SXE_SYNQF, synqf); SXE_WRITE_FLUSH(hw); =20 - return; } =20 void sxe_hw_syn_filter_del(struct sxe_hw *hw) @@ -6370,7 +6024,6 @@ void sxe_hw_syn_filter_del(struct sxe_hw *hw) SXE_REG_WRITE(hw, SXE_SYNQF, synqf); SXE_WRITE_FLUSH(hw); =20 - return; } =20 void sxe_hw_fnav_rx_pkt_buf_size_reset(struct sxe_hw *hw, u32 pbsize) @@ -6378,11 +6031,9 @@ void sxe_hw_fnav_rx_pkt_buf_size_reset(struct sxe_hw= *hw, u32 pbsize) S32 i; =20 SXE_REG_WRITE(hw, SXE_RXPBSIZE(0), (SXE_REG_READ(hw, SXE_RXPBSIZE(0)) - p= bsize)); - for (i =3D 1; i < 8; i++) { + for (i =3D 1; i < 8; i++) SXE_REG_WRITE(hw, SXE_RXPBSIZE(i), 0); - } =20 - return; } =20 void sxe_hw_fnav_flex_mask_set(struct sxe_hw *hw, u16 flex_mask) @@ -6390,12 +6041,10 @@ void sxe_hw_fnav_flex_mask_set(struct sxe_hw *hw, u= 16 flex_mask) u32 fnavm; =20 fnavm =3D SXE_REG_READ(hw, SXE_FNAVM); - if (flex_mask =3D=3D UINT16_MAX) { + if (flex_mask =3D=3D UINT16_MAX) fnavm &=3D ~SXE_FNAVM_FLEX; - } =20 SXE_REG_WRITE(hw, SXE_FNAVM, fnavm); - return; } =20 void sxe_hw_fnav_ipv6_mask_set(struct sxe_hw *hw, u16 src_mask, u16 dst_ma= sk) @@ -6405,7 +6054,6 @@ void sxe_hw_fnav_ipv6_mask_set(struct sxe_hw *hw, u16= src_mask, u16 dst_mask) fnavipv6m =3D (dst_mask << 16) | src_mask; SXE_REG_WRITE(hw, SXE_FNAVIP6M, ~fnavipv6m); =20 - return; } =20 s32 sxe_hw_fnav_flex_offset_set(struct sxe_hw *hw, u16 offset) @@ -6425,7 +6073,6 @@ s32 sxe_hw_fnav_flex_offset_set(struct sxe_hw *hw, u1= 6 offset) if (ret) { LOG_ERROR("flow director signature poll time exceeded!\n"); } - return ret; } #endif @@ -6450,9 +6097,9 @@ static void sxe_macsec_stop_data(struct sxe_hw *hw, b= ool link) SXE_SECTXSTAT_SECTX_RDY; r_rdy =3D SXE_REG_READ(hw, SXE_SECRXSTAT) & SXE_SECRXSTAT_SECRX_RDY; - if (t_rdy && r_rdy) + if (t_rdy && r_rdy) { return; - + } if (!link) { SXE_REG_WRITE(hw, SXE_LPBKCTRL, 0x1); =20 @@ -6474,13 +6121,11 @@ static void sxe_macsec_stop_data(struct sxe_hw *hw,= bool link) SXE_WRITE_FLUSH(hw); } =20 - return; } void sxe_hw_rx_queue_mode_set(struct sxe_hw *hw, u32 mrqc) { SXE_REG_WRITE(hw, SXE_MRQC, mrqc); =20 - return; } =20 void sxe_hw_macsec_enable(struct sxe_hw *hw, bool is_up, u32 tx_mode, @@ -6527,7 +6172,6 @@ void sxe_hw_macsec_enable(struct sxe_hw *hw, bool is_= up, u32 tx_mode, =20 SXE_WRITE_FLUSH(hw); =20 - return; } =20 void sxe_hw_macsec_disable(struct sxe_hw *hw, bool is_up) @@ -6555,7 +6199,6 @@ void sxe_hw_macsec_disable(struct sxe_hw *hw, bool is= _up) SXE_REG_WRITE(hw, SXE_SECRXCTRL, SXE_SECRXCTRL_SECRX_DIS); =20 SXE_WRITE_FLUSH(hw); - return; } =20 void sxe_hw_macsec_txsc_set(struct sxe_hw *hw, u32 scl, u32 sch) @@ -6564,7 +6207,6 @@ void sxe_hw_macsec_txsc_set(struct sxe_hw *hw, u32 sc= l, u32 sch) SXE_REG_WRITE(hw, SXE_LSECTXSCH, sch); =20 SXE_WRITE_FLUSH(hw); - return; } =20 void sxe_hw_macsec_rxsc_set(struct sxe_hw *hw, u32 scl, u32 sch, u16 pi) @@ -6577,7 +6219,6 @@ void sxe_hw_macsec_rxsc_set(struct sxe_hw *hw, u32 sc= l, u32 sch, u16 pi) SXE_REG_WRITE(hw, SXE_LSECRXSCH, reg); =20 SXE_WRITE_FLUSH(hw); - return; =20 } =20 @@ -6594,9 +6235,9 @@ void sxe_hw_macsec_tx_sa_configure(struct sxe_hw *hw,= u8 sa_idx, SXE_WRITE_FLUSH(hw); =20 SXE_REG_WRITE(hw, SXE_LSECTXPN(sa_idx), pn); - for (i =3D 0; i < 4; i++) { + for (i =3D 0; i < 4; i++) SXE_REG_WRITE(hw, SXE_LSECTXKEY(sa_idx, i), keys[i]); - } + SXE_WRITE_FLUSH(hw); =20 reg =3D SXE_REG_READ(hw, SXE_LSECTXSA); @@ -6613,7 +6254,6 @@ void sxe_hw_macsec_tx_sa_configure(struct sxe_hw *hw,= u8 sa_idx, } =20 SXE_WRITE_FLUSH(hw); - return; } =20 void sxe_hw_macsec_rx_sa_configure(struct sxe_hw *hw, u8 sa_idx, @@ -6632,16 +6272,15 @@ void sxe_hw_macsec_rx_sa_configure(struct sxe_hw *h= w, u8 sa_idx, =20 SXE_REG_WRITE(hw, SXE_LSECRXPN(sa_idx), pn); =20 - for (i =3D 0; i < 4; i++) { + for (i =3D 0; i < 4; i++) SXE_REG_WRITE(hw, SXE_LSECRXKEY(sa_idx, i), keys[i]); - } + SXE_WRITE_FLUSH(hw); =20 reg =3D ((an << SXE_LSECRXSA_AN_SHIFT) & SXE_LSECRXSA_AN_MASK) | SXE_LSEC= RXSA_SAV; SXE_REG_WRITE(hw, SXE_LSECRXSA(sa_idx), reg); SXE_WRITE_FLUSH(hw); - return; } -=09=09=09=09 -#endif=20 -#endif=20 + +#endif +#endif diff --git a/drivers/net/sxe/base/sxe_hw.h b/drivers/net/sxe/base/sxe_hw.h index 8adc9fc15b..aa19817d96 100644 --- a/drivers/net/sxe/base/sxe_hw.h +++ b/drivers/net/sxe/base/sxe_hw.h @@ -5,7 +5,7 @@ #ifndef __SXE_HW_H__ #define __SXE_HW_H__ =20 -#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST) +#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST) #include #include #else @@ -20,17 +20,17 @@ =20 #include "sxe_regs.h" =20 -#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST) +#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST) #define SXE_PRIU64 "llu" #define SXE_PRIX64 "llx" #define SXE_PRID64 "lld" -#define SXE_RMB() rmb() +#define SXE_RMB() rmb() /* verify reading before check ****/ =20 #else #define SXE_PRIU64 PRIu64 #define SXE_PRIX64 PRIx64 #define SXE_PRID64 PRId64 -#define SXE_RMB() rte_rmb() +#define SXE_RMB() rte_rmb() #endif =20 struct sxe_hw; @@ -40,29 +40,29 @@ struct sxe_fc_info; #define SXE_MAC_ADDR_LEN 6 #define SXE_QUEUE_STATS_MAP_REG_NUM 32 =20 -#define SXE_FC_DEFAULT_HIGH_WATER_MARK 0x80 -#define SXE_FC_DEFAULT_LOW_WATER_MARK 0x40 +#define SXE_FC_DEFAULT_HIGH_WATER_MARK 0x80 +#define SXE_FC_DEFAULT_LOW_WATER_MARK 0x40 =20 #define SXE_MC_ADDR_EXTRACT_MASK (0xFFF) -#define SXE_MC_ADDR_SHIFT (5)=20=20=20=20 -#define SXE_MC_ADDR_REG_MASK (0x7F)=20 -#define SXE_MC_ADDR_BIT_MASK (0x1F)=20 +#define SXE_MC_ADDR_SHIFT (5) +#define SXE_MC_ADDR_REG_MASK (0x7F) +#define SXE_MC_ADDR_BIT_MASK (0x1F) =20 #define SXE_TXTS_POLL_CHECK 3 #define SXE_TXTS_POLL 5 #define SXE_TIME_TO_NS(ns, sec) (((u64)(ns)) + (u64)(((u64)(sec)) * NSEC_P= ER_SEC)) =20 enum sxe_strict_prio_type { - PRIO_NONE =3D 0,=20 - PRIO_GROUP,=20=20=20=20 - PRIO_LINK=20=20=20=20=20=20 + PRIO_NONE =3D 0, + PRIO_GROUP, + PRIO_LINK }; =20 enum sxe_mc_filter_type { - SXE_MC_FILTER_TYPE0 =3D 0,=20=20 - SXE_MC_FILTER_TYPE1,=20=20=20=20=20=20 - SXE_MC_FILTER_TYPE2,=20=20=20=20=20=20 - SXE_MC_FILTER_TYPE3=20=20=20=20=20=20=20 + SXE_MC_FILTER_TYPE0 =3D 0, + SXE_MC_FILTER_TYPE1, + SXE_MC_FILTER_TYPE2, + SXE_MC_FILTER_TYPE3 }; =20 #define SXE_POOLS_NUM_MAX 64 @@ -84,57 +84,57 @@ enum sxe_mc_filter_type { #define SXE_VF_NUM_16 16 #define SXE_VF_NUM_32 32 =20 -#define SXE_TX_DESC_EOP_MASK 0x01000000=20=20=20 -#define SXE_TX_DESC_RS_MASK 0x08000000=20=20=20 -#define SXE_TX_DESC_STAT_DD 0x00000001=20=20=20 -#define SXE_TX_DESC_CMD (SXE_TX_DESC_EOP_MASK | SXE_TX_DESC_RS_MASK) -#define SXE_TX_DESC_TYPE_DATA 0x00300000=20=20=20 -#define SXE_TX_DESC_DEXT 0x20000000=20=20=20 -#define SXE_TX_DESC_IFCS 0x02000000=20=20=20 -#define SXE_TX_DESC_VLE 0x40000000=20 -#define SXE_TX_DESC_TSTAMP 0x00080000=20 -#define SXE_TX_DESC_FLAGS (SXE_TX_DESC_TYPE_DATA | \ +#define SXE_TX_DESC_EOP_MASK 0x01000000 +#define SXE_TX_DESC_RS_MASK 0x08000000 +#define SXE_TX_DESC_STAT_DD 0x00000001 +#define SXE_TX_DESC_CMD (SXE_TX_DESC_EOP_MASK | SXE_TX_DESC_RS_MASK) +#define SXE_TX_DESC_TYPE_DATA 0x00300000 +#define SXE_TX_DESC_DEXT 0x20000000 +#define SXE_TX_DESC_IFCS 0x02000000 +#define SXE_TX_DESC_VLE 0x40000000 +#define SXE_TX_DESC_TSTAMP 0x00080000 +#define SXE_TX_DESC_FLAGS (SXE_TX_DESC_TYPE_DATA | \ SXE_TX_DESC_IFCS | \ SXE_TX_DESC_DEXT| \ SXE_TX_DESC_EOP_MASK) -#define SXE_TXD_DTYP_CTXT 0x00200000=20 -#define SXE_TXD_DCMD_TSE 0x80000000=20 -#define SXE_TXD_MAC_LINKSEC 0x00040000=20 -#define SXE_TXD_MAC_1588 0x00080000=20 -#define SXE_TX_DESC_PAYLEN_SHIFT 14 -#define SXE_TX_OUTERIPCS_SHIFT 17=20 +#define SXE_TXD_DTYP_CTXT 0x00200000 +#define SXE_TXD_DCMD_TSE 0x80000000 +#define SXE_TXD_MAC_LINKSEC 0x00040000 +#define SXE_TXD_MAC_1588 0x00080000 +#define SXE_TX_DESC_PAYLEN_SHIFT 14 +#define SXE_TX_OUTERIPCS_SHIFT 17 =20 #define SXE_TX_POPTS_IXSM 0x01 #define SXE_TX_POPTS_TXSM 0x02 -#define SXE_TXD_POPTS_SHIFT 8=20=20 +#define SXE_TXD_POPTS_SHIFT 8 #define SXE_TXD_POPTS_IXSM (SXE_TX_POPTS_IXSM << SXE_TXD_POPTS_SHIFT) #define SXE_TXD_POPTS_TXSM (SXE_TX_POPTS_TXSM << SXE_TXD_POPTS_SHIFT) #define SXE_TXD_POPTS_IPSEC (0x00000400) =20 -#define SXE_TX_CTXTD_DTYP_CTXT 0x00200000=20 -#define SXE_TX_CTXTD_TUCMD_IPV6 0x00000000=20 -#define SXE_TX_CTXTD_TUCMD_IPV4 0x00000400=20 -#define SXE_TX_CTXTD_TUCMD_L4T_UDP 0x00000000=20 -#define SXE_TX_CTXTD_TUCMD_L4T_TCP 0x00000800=20 -#define SXE_TX_CTXTD_TUCMD_L4T_SCTP 0x00001000=20 -#define SXE_TX_CTXTD_TUCMD_L4T_RSV 0x00001800=20 -#define SXE_TX_CTXTD_TUCMD_IPSEC_TYPE_ESP 0x00002000=20 -#define SXE_TX_CTXTD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000=20 - -#define SXE_TX_CTXTD_L4LEN_SHIFT 8=20=20 -#define SXE_TX_CTXTD_MSS_SHIFT 16=20 -#define SXE_TX_CTXTD_MACLEN_SHIFT 9=20=20 -#define SXE_TX_CTXTD_VLAN_SHIFT 16 -#define SXE_TX_CTXTD_VLAN_MASK 0xffff0000 -#define SXE_TX_CTXTD_MACLEN_MASK 0x0000fE00 -#define SXE_TX_CTXTD_OUTER_IPLEN_SHIFT 16=20 -#define SXE_TX_CTXTD_TUNNEL_LEN_SHIFT 24=20 - -#define SXE_VLAN_TAG_SIZE 4 - -#define SXE_RSS_KEY_SIZE (40)=20=20 -#define SXE_MAX_RSS_KEY_ENTRIES (10)=20=20 -#define SXE_MAX_RETA_ENTRIES (128)=20 +#define SXE_TX_CTXTD_DTYP_CTXT 0x00200000 +#define SXE_TX_CTXTD_TUCMD_IPV6 0x00000000 +#define SXE_TX_CTXTD_TUCMD_IPV4 0x00000400 +#define SXE_TX_CTXTD_TUCMD_L4T_UDP 0x00000000 +#define SXE_TX_CTXTD_TUCMD_L4T_TCP 0x00000800 +#define SXE_TX_CTXTD_TUCMD_L4T_SCTP 0x00001000 +#define SXE_TX_CTXTD_TUCMD_L4T_RSV 0x00001800 +#define SXE_TX_CTXTD_TUCMD_IPSEC_TYPE_ESP 0x00002000 +#define SXE_TX_CTXTD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 + +#define SXE_TX_CTXTD_L4LEN_SHIFT 8 +#define SXE_TX_CTXTD_MSS_SHIFT 16 +#define SXE_TX_CTXTD_MACLEN_SHIFT 9 +#define SXE_TX_CTXTD_VLAN_SHIFT 16 +#define SXE_TX_CTXTD_VLAN_MASK 0xffff0000 +#define SXE_TX_CTXTD_MACLEN_MASK 0x0000fE00 +#define SXE_TX_CTXTD_OUTER_IPLEN_SHIFT 16 +#define SXE_TX_CTXTD_TUNNEL_LEN_SHIFT 24 + +#define SXE_VLAN_TAG_SIZE 4 + +#define SXE_RSS_KEY_SIZE (40) +#define SXE_MAX_RSS_KEY_ENTRIES (10) +#define SXE_MAX_RETA_ENTRIES (128) =20 #define SXE_TIMINC_IV_NS_SHIFT 8 #define SXE_TIMINC_INCPD_SHIFT 24 @@ -142,49 +142,49 @@ enum sxe_mc_filter_type { (((incpd) << SXE_TIMINC_INCPD_SHIFT) | \ ((iv_ns) << SXE_TIMINC_IV_NS_SHIFT) | (iv_sns)) =20 -#define PBA_STRATEGY_EQUAL (0)=20=20=20=20 -#define PBA_STRATEGY_WEIGHTED (1)=09 -#define SXE_PKG_BUF_NUM_MAX (8) +#define PBA_STRATEGY_EQUAL (0) +#define PBA_STRATEGY_WEIGHTED (1) +#define SXE_PKG_BUF_NUM_MAX (8) #define SXE_HW_TXRX_RING_NUM_MAX 128 #define SXE_VMDQ_DCB_NUM_QUEUES SXE_HW_TXRX_RING_NUM_MAX -#define SXE_RX_PKT_BUF_SIZE (512) +#define SXE_RX_PKT_BUF_SIZE (512) =20 #define SXE_UC_ENTRY_NUM_MAX 128 #define SXE_HW_TX_NONE_MODE_Q_NUM 64 =20 -#define SXE_MBX_MSG_NUM 16 +#define SXE_MBX_MSG_NUM 16 #define SXE_MBX_RETRY_INTERVAL 500 -#define SXE_MBX_RETRY_COUNT 2000 +#define SXE_MBX_RETRY_COUNT 2000 =20 #define SXE_VF_UC_ENTRY_NUM_MAX 10 #define SXE_VF_MC_ENTRY_NUM_MAX 30 =20 #define SXE_UTA_ENTRY_NUM_MAX 128 #define SXE_MTA_ENTRY_NUM_MAX 128 -#define SXE_HASH_UC_NUM_MAX 4096=20 +#define SXE_HASH_UC_NUM_MAX 4096 =20 -#define SXE_MAC_ADDR_EXTRACT_MASK (0xFFF)=20 -#define SXE_MAC_ADDR_SHIFT (5)=20=20=20=20=20 -#define SXE_MAC_ADDR_REG_MASK (0x7F)=20=20 -#define SXE_MAC_ADDR_BIT_MASK (0x1F)=20=20 +#define SXE_MAC_ADDR_EXTRACT_MASK (0xFFF) +#define SXE_MAC_ADDR_SHIFT (5) +#define SXE_MAC_ADDR_REG_MASK (0x7F) +#define SXE_MAC_ADDR_BIT_MASK (0x1F) =20 -#define SXE_VFT_TBL_SIZE (128)=20=20=20 -#define SXE_VLAN_ID_SHIFT (5)=20=20=20=20=20 -#define SXE_VLAN_ID_REG_MASK (0x7F)=20=20 -#define SXE_VLAN_ID_BIT_MASK (0x1F)=20=20 +#define SXE_VFT_TBL_SIZE (128) +#define SXE_VLAN_ID_SHIFT (5) +#define SXE_VLAN_ID_REG_MASK (0x7F) +#define SXE_VLAN_ID_BIT_MASK (0x1F) =20 -#define SXE_TX_PBSIZE_MAX 0x00028000=20 -#define SXE_TX_PKT_SIZE_MAX 0xA=20=20=20=20=20=20=20=20 -#define SXE_NODCB_TX_PKT_SIZE_MAX 0x14=20 +#define SXE_TX_PBSIZE_MAX 0x00028000 +#define SXE_TX_PKT_SIZE_MAX 0xA +#define SXE_NODCB_TX_PKT_SIZE_MAX 0x14 #define SXE_RING_ENABLE_WAIT_LOOP 10 =20 -#define VFTA_BLOCK_SIZE 8 -#define VF_BLOCK_BITS (32) +#define VFTA_BLOCK_SIZE 8 +#define VF_BLOCK_BITS (32) #define SXE_MAX_MAC_HDR_LEN 127 #define SXE_MAX_NETWORK_HDR_LEN 511 #define SXE_MAC_ADDR_LEN 6 =20 -#define SXE_FNAV_BUCKET_HASH_KEY 0x3DAD14E2 +#define SXE_FNAV_BUCKET_HASH_KEY 0x3DAD14E2 #define SXE_FNAV_SAMPLE_HASH_KEY 0x174D3614 #define SXE_SAMPLE_COMMON_HASH_KEY \ (SXE_FNAV_BUCKET_HASH_KEY & SXE_FNAV_SAMPLE_HASH_KEY) @@ -202,11 +202,11 @@ enum sxe_mc_filter_type { #define SXE_SAMPLE_VLAN_MASK 0xEFFF #define SXE_SAMPLE_FLEX_BYTES_MASK 0xFFFF =20 -#define SXE_FNAV_INIT_DONE_POLL 10 -#define SXE_FNAV_DROP_QUEUE 127 +#define SXE_FNAV_INIT_DONE_POLL 10 +#define SXE_FNAV_DROP_QUEUE 127 =20 -#define MAX_TRAFFIC_CLASS 8 -#define DEF_TRAFFIC_CLASS 1 +#define MAX_TRAFFIC_CLASS 8 +#define DEF_TRAFFIC_CLASS 1 =20 #define SXE_LINK_SPEED_UNKNOWN 0 #define SXE_LINK_SPEED_10_FULL 0x0002 @@ -245,176 +245,176 @@ enum sxe_sample_type { }; =20 enum { - SXE_DIAG_TEST_PASSED =3D 0, - SXE_DIAG_TEST_BLOCKED =3D 1, - SXE_DIAG_STATS_REG_TEST_ERR =3D 2, - SXE_DIAG_REG_PATTERN_TEST_ERR =3D 3, - SXE_DIAG_CHECK_REG_TEST_ERR =3D 4, - SXE_DIAG_DISABLE_IRQ_TEST_ERR =3D 5, - SXE_DIAG_ENABLE_IRQ_TEST_ERR =3D 6, + SXE_DIAG_TEST_PASSED =3D 0, + SXE_DIAG_TEST_BLOCKED =3D 1, + SXE_DIAG_STATS_REG_TEST_ERR =3D 2, + SXE_DIAG_REG_PATTERN_TEST_ERR =3D 3, + SXE_DIAG_CHECK_REG_TEST_ERR =3D 4, + SXE_DIAG_DISABLE_IRQ_TEST_ERR =3D 5, + SXE_DIAG_ENABLE_IRQ_TEST_ERR =3D 6, SXE_DIAG_DISABLE_OTHER_IRQ_TEST_ERR =3D 7, - SXE_DIAG_TX_RING_CONFIGURE_ERR =3D 8, - SXE_DIAG_RX_RING_CONFIGURE_ERR =3D 9, - SXE_DIAG_ALLOC_SKB_ERR =3D 10, - SXE_DIAG_LOOPBACK_SEND_TEST_ERR =3D 11, - SXE_DIAG_LOOPBACK_RECV_TEST_ERR =3D 12, + SXE_DIAG_TX_RING_CONFIGURE_ERR =3D 8, + SXE_DIAG_RX_RING_CONFIGURE_ERR =3D 9, + SXE_DIAG_ALLOC_SKB_ERR =3D 10, + SXE_DIAG_LOOPBACK_SEND_TEST_ERR =3D 11, + SXE_DIAG_LOOPBACK_RECV_TEST_ERR =3D 12, }; =20 -#define SXE_RXD_STAT_DD 0x01=20=20=20=20 -#define SXE_RXD_STAT_EOP 0x02=20=20=20=20 -#define SXE_RXD_STAT_FLM 0x04=20=20=20=20 -#define SXE_RXD_STAT_VP 0x08=20=20=20=20 -#define SXE_RXDADV_NEXTP_MASK 0x000FFFF0=20 +#define SXE_RXD_STAT_DD 0x01 +#define SXE_RXD_STAT_EOP 0x02 +#define SXE_RXD_STAT_FLM 0x04 +#define SXE_RXD_STAT_VP 0x08 +#define SXE_RXDADV_NEXTP_MASK 0x000FFFF0 #define SXE_RXDADV_NEXTP_SHIFT 0x00000004 -#define SXE_RXD_STAT_UDPCS 0x10=20=20=20=20 -#define SXE_RXD_STAT_L4CS 0x20=20=20=20=20 -#define SXE_RXD_STAT_IPCS 0x40=20=20=20=20 -#define SXE_RXD_STAT_PIF 0x80=20=20=20=20 -#define SXE_RXD_STAT_CRCV 0x100=20=20=20 -#define SXE_RXD_STAT_OUTERIPCS 0x100=20 -#define SXE_RXD_STAT_VEXT 0x200=20=20=20 -#define SXE_RXD_STAT_UDPV 0x400=20=20=20 -#define SXE_RXD_STAT_DYNINT 0x800=20=20=20 -#define SXE_RXD_STAT_LLINT 0x800=20=20=20 -#define SXE_RXD_STAT_TSIP 0x08000=20 -#define SXE_RXD_STAT_TS 0x10000=20 -#define SXE_RXD_STAT_SECP 0x20000=20 -#define SXE_RXD_STAT_LB 0x40000=20 -#define SXE_RXD_STAT_ACK 0x8000=20=20 -#define SXE_RXD_ERR_CE 0x01=20=20=20=20 -#define SXE_RXD_ERR_LE 0x02=20=20=20=20 -#define SXE_RXD_ERR_PE 0x08=20=20=20=20 -#define SXE_RXD_ERR_OSE 0x10=20=20=20=20 -#define SXE_RXD_ERR_USE 0x20=20=20=20=20 -#define SXE_RXD_ERR_TCPE 0x40=20=20=20=20 -#define SXE_RXD_ERR_IPE 0x80=20=20=20=20 -#define SXE_RXDADV_ERR_MASK 0xfff00000=20 -#define SXE_RXDADV_ERR_SHIFT 20=20=20=20=20=20=20=20=20=20 -#define SXE_RXDADV_ERR_OUTERIPER 0x04000000=20 -#define SXE_RXDADV_ERR_FCEOFE 0x80000000=20 -#define SXE_RXDADV_ERR_FCERR 0x00700000=20 -#define SXE_RXDADV_ERR_FNAV_LEN 0x00100000=20 -#define SXE_RXDADV_ERR_FNAV_DROP 0x00200000=20 -#define SXE_RXDADV_ERR_FNAV_COLL 0x00400000=20 -#define SXE_RXDADV_ERR_HBO 0x00800000=20 -#define SXE_RXDADV_ERR_CE 0x01000000=20 -#define SXE_RXDADV_ERR_LE 0x02000000=20 -#define SXE_RXDADV_ERR_PE 0x08000000=20 -#define SXE_RXDADV_ERR_OSE 0x10000000=20 -#define SXE_RXDADV_ERR_IPSEC_INV_PROTOCOL 0x08000000=20 -#define SXE_RXDADV_ERR_IPSEC_INV_LENGTH 0x10000000=20 +#define SXE_RXD_STAT_UDPCS 0x10 +#define SXE_RXD_STAT_L4CS 0x20 +#define SXE_RXD_STAT_IPCS 0x40 +#define SXE_RXD_STAT_PIF 0x80 +#define SXE_RXD_STAT_CRCV 0x100 +#define SXE_RXD_STAT_OUTERIPCS 0x100 +#define SXE_RXD_STAT_VEXT 0x200 +#define SXE_RXD_STAT_UDPV 0x400 +#define SXE_RXD_STAT_DYNINT 0x800 +#define SXE_RXD_STAT_LLINT 0x800 +#define SXE_RXD_STAT_TSIP 0x08000 +#define SXE_RXD_STAT_TS 0x10000 +#define SXE_RXD_STAT_SECP 0x20000 +#define SXE_RXD_STAT_LB 0x40000 +#define SXE_RXD_STAT_ACK 0x8000 +#define SXE_RXD_ERR_CE 0x01 +#define SXE_RXD_ERR_LE 0x02 +#define SXE_RXD_ERR_PE 0x08 +#define SXE_RXD_ERR_OSE 0x10 +#define SXE_RXD_ERR_USE 0x20 +#define SXE_RXD_ERR_TCPE 0x40 +#define SXE_RXD_ERR_IPE 0x80 +#define SXE_RXDADV_ERR_MASK 0xfff00000 +#define SXE_RXDADV_ERR_SHIFT 20 +#define SXE_RXDADV_ERR_OUTERIPER 0x04000000 +#define SXE_RXDADV_ERR_FCEOFE 0x80000000 +#define SXE_RXDADV_ERR_FCERR 0x00700000 +#define SXE_RXDADV_ERR_FNAV_LEN 0x00100000 +#define SXE_RXDADV_ERR_FNAV_DROP 0x00200000 +#define SXE_RXDADV_ERR_FNAV_COLL 0x00400000 +#define SXE_RXDADV_ERR_HBO 0x00800000 +#define SXE_RXDADV_ERR_CE 0x01000000 +#define SXE_RXDADV_ERR_LE 0x02000000 +#define SXE_RXDADV_ERR_PE 0x08000000 +#define SXE_RXDADV_ERR_OSE 0x10000000 +#define SXE_RXDADV_ERR_IPSEC_INV_PROTOCOL 0x08000000 +#define SXE_RXDADV_ERR_IPSEC_INV_LENGTH 0x10000000 #define SXE_RXDADV_ERR_IPSEC_AUTH_FAILED 0x18000000 -#define SXE_RXDADV_ERR_USE 0x20000000=20 -#define SXE_RXDADV_ERR_L4E 0x40000000=20 -#define SXE_RXDADV_ERR_IPE 0x80000000=20 -#define SXE_RXD_VLAN_ID_MASK 0x0FFF=20=20 -#define SXE_RXD_PRI_MASK 0xE000=20=20 -#define SXE_RXD_PRI_SHIFT 13 -#define SXE_RXD_CFI_MASK 0x1000=20=20 -#define SXE_RXD_CFI_SHIFT 12 -#define SXE_RXDADV_LROCNT_MASK 0x001E0000 -#define SXE_RXDADV_LROCNT_SHIFT 17 - -#define SXE_RXDADV_STAT_DD SXE_RXD_STAT_DD=20=20 -#define SXE_RXDADV_STAT_EOP SXE_RXD_STAT_EOP=20 -#define SXE_RXDADV_STAT_FLM SXE_RXD_STAT_FLM=20 -#define SXE_RXDADV_STAT_VP SXE_RXD_STAT_VP=20=20 -#define SXE_RXDADV_STAT_MASK 0x000fffff=20 -#define SXE_RXDADV_STAT_TS 0x00010000=20 -#define SXE_RXDADV_STAT_SECP 0x00020000=20 - -#define SXE_RXDADV_PKTTYPE_NONE 0x00000000 -#define SXE_RXDADV_PKTTYPE_IPV4 0x00000010=20 -#define SXE_RXDADV_PKTTYPE_IPV4_EX 0x00000020=20 -#define SXE_RXDADV_PKTTYPE_IPV6 0x00000040=20 -#define SXE_RXDADV_PKTTYPE_IPV6_EX 0x00000080=20 -#define SXE_RXDADV_PKTTYPE_TCP 0x00000100=20 -#define SXE_RXDADV_PKTTYPE_UDP 0x00000200=20 -#define SXE_RXDADV_PKTTYPE_SCTP 0x00000400=20 -#define SXE_RXDADV_PKTTYPE_NFS 0x00000800=20 -#define SXE_RXDADV_PKTTYPE_VXLAN 0x00000800=20 -#define SXE_RXDADV_PKTTYPE_TUNNEL 0x00010000=20 -#define SXE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000=20 -#define SXE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000=20 -#define SXE_RXDADV_PKTTYPE_LINKSEC 0x00004000=20 -#define SXE_RXDADV_PKTTYPE_ETQF 0x00008000=20 -#define SXE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070=20 -#define SXE_RXDADV_PKTTYPE_ETQF_SHIFT 4=20=20=20=20=20=20=20=20=20=20 +#define SXE_RXDADV_ERR_USE 0x20000000 +#define SXE_RXDADV_ERR_L4E 0x40000000 +#define SXE_RXDADV_ERR_IPE 0x80000000 +#define SXE_RXD_VLAN_ID_MASK 0x0FFF +#define SXE_RXD_PRI_MASK 0xE000 +#define SXE_RXD_PRI_SHIFT 13 +#define SXE_RXD_CFI_MASK 0x1000 +#define SXE_RXD_CFI_SHIFT 12 +#define SXE_RXDADV_LROCNT_MASK 0x001E0000 +#define SXE_RXDADV_LROCNT_SHIFT 17 + +#define SXE_RXDADV_STAT_DD SXE_RXD_STAT_DD +#define SXE_RXDADV_STAT_EOP SXE_RXD_STAT_EOP +#define SXE_RXDADV_STAT_FLM SXE_RXD_STAT_FLM +#define SXE_RXDADV_STAT_VP SXE_RXD_STAT_VP +#define SXE_RXDADV_STAT_MASK 0x000fffff +#define SXE_RXDADV_STAT_TS 0x00010000 +#define SXE_RXDADV_STAT_SECP 0x00020000 + +#define SXE_RXDADV_PKTTYPE_NONE 0x00000000 +#define SXE_RXDADV_PKTTYPE_IPV4 0x00000010 +#define SXE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 +#define SXE_RXDADV_PKTTYPE_IPV6 0x00000040 +#define SXE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 +#define SXE_RXDADV_PKTTYPE_TCP 0x00000100 +#define SXE_RXDADV_PKTTYPE_UDP 0x00000200 +#define SXE_RXDADV_PKTTYPE_SCTP 0x00000400 +#define SXE_RXDADV_PKTTYPE_NFS 0x00000800 +#define SXE_RXDADV_PKTTYPE_VXLAN 0x00000800 +#define SXE_RXDADV_PKTTYPE_TUNNEL 0x00010000 +#define SXE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 +#define SXE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 +#define SXE_RXDADV_PKTTYPE_LINKSEC 0x00004000 +#define SXE_RXDADV_PKTTYPE_ETQF 0x00008000 +#define SXE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 +#define SXE_RXDADV_PKTTYPE_ETQF_SHIFT 4 =20 struct sxe_mac_stats { - u64 crcerrs;=20=20=20=20=20=20=20=20=20=20=20 - u64 errbc;=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 rlec;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 prc64;=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 prc127;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 prc255;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 prc511;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 prc1023;=20=20=20=20=20=20=20=20=20=20=20 - u64 prc1522;=20=20=20=20=20=20=20=20=20=20=20 - u64 gprc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 bprc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 mprc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 gptc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 gorc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 gotc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 ruc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 rfc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 roc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 rjc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 tor;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 tpr;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 tpt;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 ptc64;=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 ptc127;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 ptc255;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 ptc511;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 ptc1023;=20=20=20=20=20=20=20=20=20=20=20 - u64 ptc1522;=20=20=20=20=20=20=20=20=20=20=20 - u64 mptc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 bptc;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 qprc[16];=20=20=20=20=20=20=20=20=20=20 - u64 qptc[16];=20=20=20=20=20=20=20=20=20=20 - u64 qbrc[16];=20=20=20=20=20=20=20=20=20=20 - u64 qbtc[16];=20=20=20=20=20=20=20=20=20=20 - u64 qprdc[16];=20=20=20=20=20=20=20=20=20 - u64 dburxtcin[8];=20=20=20=20=20=20 - u64 dburxtcout[8];=20=20=20=20=20 - u64 dburxgdreecnt[8];=20=20 - u64 dburxdrofpcnt[8];=20=20 - u64 dbutxtcin[8];=20=20=20=20=20=20 - u64 dbutxtcout[8];=20=20=20=20=20 - u64 rxdgpc;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 rxdgbc;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 rxddpc;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 rxddbc;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 rxtpcing;=20=20=20=20=20=20=20=20=20=20 - u64 rxtpceng;=20=20=20=20=20=20=20=20=20=20 - u64 rxlpbkpc;=20=20=20=20=20=20=20=20=20=20 - u64 rxlpbkbc;=20=20=20=20=20=20=20=20=20=20 - u64 rxdlpbkpc;=20=20=20=20=20=20=20=20=20 - u64 rxdlpbkbc;=20=20=20=20=20=20=20=20=20 - u64 prddc;=20=20=20=20=20=20=20=20=20=20=20=20=20 - u64 txdgpc;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 txdgbc;=20=20=20=20=20=20=20=20=20=20=20=20 - u64 txswerr;=20=20=20=20=20=20=20=20=20=20=20 - u64 txswitch;=20=20=20=20=20=20=20=20=20=20 - u64 txrepeat;=20=20=20=20=20=20=20=20=20=20 - u64 txdescerr;=20=20=20=20=20=20=20=20=20 - - u64 fnavadd;=20=20=20=20=20=20=20=20=20=20=20 - u64 fnavrmv;=20=20=20=20=20=20=20=20=20=20=20 - u64 fnavadderr;=20=20=20=20=20=20=20=20 - u64 fnavrmverr;=20=20=20=20=20=20=20=20 - u64 fnavmatch;=20=20=20=20=20=20=20=20=20 - u64 fnavmiss;=20=20=20=20=20=20=20=20=20=20 - u64 hw_rx_no_dma_resources;=20 - u64 prcpf[8];=20=20=20=20=20=20=20=20=20=20 - u64 pfct[8];=20=20=20=20=20=20=20=20=20=20=20 - u64 mpc[8];=20=20=20=20=20=20=20=20=20=20=20=20 - - u64 total_tx_pause;=20=20=20=20 - u64 total_gptc;=20=20=20=20=20=20=20=20 - u64 total_gotc;=20=20=20=20=20=20=20=20 + u64 crcerrs; + u64 errbc; + u64 rlec; + u64 prc64; + u64 prc127; + u64 prc255; + u64 prc511; + u64 prc1023; + u64 prc1522; + u64 gprc; + u64 bprc; + u64 mprc; + u64 gptc; + u64 gorc; + u64 gotc; + u64 ruc; + u64 rfc; + u64 roc; + u64 rjc; + u64 tor; + u64 tpr; + u64 tpt; + u64 ptc64; + u64 ptc127; + u64 ptc255; + u64 ptc511; + u64 ptc1023; + u64 ptc1522; + u64 mptc; + u64 bptc; + u64 qprc[16]; + u64 qptc[16]; + u64 qbrc[16]; + u64 qbtc[16]; + u64 qprdc[16]; + u64 dburxtcin[8]; + u64 dburxtcout[8]; + u64 dburxgdreecnt[8]; + u64 dburxdrofpcnt[8]; + u64 dbutxtcin[8]; + u64 dbutxtcout[8]; + u64 rxdgpc; + u64 rxdgbc; + u64 rxddpc; + u64 rxddbc; + u64 rxtpcing; + u64 rxtpceng; + u64 rxlpbkpc; + u64 rxlpbkbc; + u64 rxdlpbkpc; + u64 rxdlpbkbc; + u64 prddc; + u64 txdgpc; + u64 txdgbc; + u64 txswerr; + u64 txswitch; + u64 txrepeat; + u64 txdescerr; + + u64 fnavadd; + u64 fnavrmv; + u64 fnavadderr; + u64 fnavrmverr; + u64 fnavmatch; + u64 fnavmiss; + u64 hw_rx_no_dma_resources; + u64 prcpf[8]; + u64 pfct[8]; + u64 mpc[8]; + + u64 total_tx_pause; + u64 total_gptc; + u64 total_gotc; }; =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL @@ -440,16 +440,16 @@ struct sxe_fivetuple_filter_info { }; =20 struct sxe_fivetuple_node_info { - u16 index;=20=20 - u16 queue;=20=20 + u16 index; + u16 queue; struct sxe_fivetuple_filter_info filter_info; }; #endif =20 union sxe_fnav_rule_info { struct { - u8 vm_pool; - u8 flow_type; + u8 vm_pool; + u8 flow_type; __be16 vlan_id; __be32 dst_ip[4]; __be32 src_ip[4]; @@ -480,21 +480,21 @@ void sxe_hw_ops_init(struct sxe_hw *hw); =20 =20 struct sxe_reg_info { - u32 addr;=20=20=20=20=20=20=20=20 - u32 count;=20=20=20=20=20=20=20 - u32 stride;=20=20=20=20=20=20 - const s8 *name;=20=20 + u32 addr; + u32 count; + u32 stride; + const s8 *name; }; =20 struct sxe_setup_operations { - s32 (*reset)(struct sxe_hw *); - void (*pf_rst_done_set)(struct sxe_hw *); - void (*no_snoop_disable)(struct sxe_hw *); - u32 (*reg_read)(struct sxe_hw *, u32); - void (*reg_write)(struct sxe_hw *, u32, u32); - void (*regs_dump)(struct sxe_hw *); - void (*regs_flush)(struct sxe_hw *); - s32 (*regs_test)(struct sxe_hw *); + s32 (*reset)(struct sxe_hw *hw); + void (*pf_rst_done_set)(struct sxe_hw *hw); + void (*no_snoop_disable)(struct sxe_hw *hw); + u32 (*reg_read)(struct sxe_hw *hw, u32 reg); + void (*reg_write)(struct sxe_hw *hw, u32 reg, u32 val); + void (*regs_dump)(struct sxe_hw *hw); + void (*regs_flush)(struct sxe_hw *hw); + s32 (*regs_test)(struct sxe_hw *hw); }; =20 struct sxe_hw_setup { @@ -503,20 +503,22 @@ struct sxe_hw_setup { =20 struct sxe_irq_operations { u32 (*pending_irq_read_clear)(struct sxe_hw *hw); - void (*pending_irq_write_clear)(struct sxe_hw * hw, u32 value); + void (*pending_irq_write_clear)(struct sxe_hw *hw, u32 value); void (*irq_general_reg_set)(struct sxe_hw *hw, u32 value); u32 (*irq_general_reg_get)(struct sxe_hw *hw); void (*ring_irq_auto_disable)(struct sxe_hw *hw, bool is_misx); void (*set_eitrsel)(struct sxe_hw *hw, u32 value); - void (*ring_irq_interval_set)(struct sxe_hw *hw, u16 irq_idx, u32 interva= l); - void (*event_irq_interval_set)(struct sxe_hw * hw, u16 irq_idx, u32 value= ); + void (*ring_irq_interval_set)(struct sxe_hw *hw, u16 irq_idx, + u32 interval); + void (*event_irq_interval_set)(struct sxe_hw *hw, u16 irq_idx, + u32 value); void (*event_irq_auto_clear_set)(struct sxe_hw *hw, u32 value); void (*ring_irq_map)(struct sxe_hw *hw, bool is_tx, - u16 reg_idx, u16 irq_idx); + u16 reg_idx, u16 irq_idx); void (*event_irq_map)(struct sxe_hw *hw, u8 offset, u16 irq_idx); - void (*ring_irq_enable)(struct sxe_hw * hw, u64 qmask); - u32 (*irq_cause_get)(struct sxe_hw * hw); - void (*event_irq_trigger)(struct sxe_hw * hw); + void (*ring_irq_enable)(struct sxe_hw *hw, u64 qmask); + u32 (*irq_cause_get)(struct sxe_hw *hw); + void (*event_irq_trigger)(struct sxe_hw *hw); void (*ring_irq_trigger)(struct sxe_hw *hw, u64 eics); void (*specific_irq_disable)(struct sxe_hw *hw, u32 value); void (*specific_irq_enable)(struct sxe_hw *hw, u32 value); @@ -530,26 +532,26 @@ struct sxe_irq_info { }; =20 struct sxe_mac_operations { - bool (*link_up_1g_check)(struct sxe_hw *); - bool (*link_state_is_up)(struct sxe_hw *); - u32 (*link_speed_get)(struct sxe_hw *); - void (*link_speed_set)(struct sxe_hw *, u32 speed); - void (*pad_enable)(struct sxe_hw *); - s32 (*fc_enable)(struct sxe_hw *); - void (*crc_configure)(struct sxe_hw *); - void (*loopback_switch)(struct sxe_hw *, bool); + bool (*link_up_1g_check)(struct sxe_hw *hw); + bool (*link_state_is_up)(struct sxe_hw *hw); + u32 (*link_speed_get)(struct sxe_hw *hw); + void (*link_speed_set)(struct sxe_hw *hw, u32 speed); + void (*pad_enable)(struct sxe_hw *hw); + s32 (*fc_enable)(struct sxe_hw *hw); + void (*crc_configure)(struct sxe_hw *hw); + void (*loopback_switch)(struct sxe_hw *hw, bool val); void (*txrx_enable)(struct sxe_hw *hw); - void (*max_frame_set)(struct sxe_hw *, u32); - u32 (*max_frame_get)(struct sxe_hw *); - void (*fc_autoneg_localcap_set)(struct sxe_hw *); - void (*fc_tc_high_water_mark_set)(struct sxe_hw *, u8, u32); - void (*fc_tc_low_water_mark_set)(struct sxe_hw *, u8, u32); - void (*fc_param_init)(struct sxe_hw *); - enum sxe_fc_mode (*fc_current_mode_get)(struct sxe_hw *); - enum sxe_fc_mode (*fc_requested_mode_get)(struct sxe_hw *); - void (*fc_requested_mode_set)(struct sxe_hw *, enum sxe_fc_mode); - bool (*is_fc_autoneg_disabled)(struct sxe_hw *); - void (*fc_autoneg_disable_set)(struct sxe_hw *, bool); + void (*max_frame_set)(struct sxe_hw *hw, u32 val); + u32 (*max_frame_get)(struct sxe_hw *hw); + void (*fc_autoneg_localcap_set)(struct sxe_hw *hw); + void (*fc_tc_high_water_mark_set)(struct sxe_hw *hw, u8 tc_idx, u32 val); + void (*fc_tc_low_water_mark_set)(struct sxe_hw *hw, u8 tc_idx, u32 val); + void (*fc_param_init)(struct sxe_hw *hw); + enum sxe_fc_mode (*fc_current_mode_get)(struct sxe_hw *hw); + enum sxe_fc_mode (*fc_requested_mode_get)(struct sxe_hw *hw); + void (*fc_requested_mode_set)(struct sxe_hw *hw, enum sxe_fc_mode e); + bool (*is_fc_autoneg_disabled)(struct sxe_hw *hw); + void (*fc_autoneg_disable_set)(struct sxe_hw *hw, bool val); }; =20 #define SXE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 @@ -562,25 +564,26 @@ struct sxe_mac_info { }; =20 struct sxe_filter_mac_operations { - u32 (*rx_mode_get)(struct sxe_hw *); - void (*rx_mode_set)(struct sxe_hw *, u32); - u32 (*pool_rx_mode_get)(struct sxe_hw *, u16); - void (*pool_rx_mode_set)(struct sxe_hw *, u32, u16); - void (*rx_lro_enable) (struct sxe_hw *, bool); - void (*rx_udp_frag_checksum_disable) (struct sxe_hw *); - s32 (*uc_addr_add)(struct sxe_hw *, u32, u8 *, u32); - s32 (*uc_addr_del)(struct sxe_hw *, u32); - void (*uc_addr_clear)(struct sxe_hw *); + u32 (*rx_mode_get)(struct sxe_hw *hw); + void (*rx_mode_set)(struct sxe_hw *hw, u32 filter_ctrl); + u32 (*pool_rx_mode_get)(struct sxe_hw *hw, u16 idx); + void (*pool_rx_mode_set)(struct sxe_hw *hw, u32 vmolr, u16 idx); + void (*rx_lro_enable)(struct sxe_hw *hw, bool is_enable); + void (*rx_udp_frag_checksum_disable)(struct sxe_hw *hw); + s32 (*uc_addr_add)(struct sxe_hw *hw, u32 rar_idx, + u8 *addr, u32 pool_idx); + s32 (*uc_addr_del)(struct sxe_hw *hw, u32 idx); + void (*uc_addr_clear)(struct sxe_hw *hw); void (*mta_hash_table_set)(struct sxe_hw *hw, u8 index, u32 value); void (*mta_hash_table_update)(struct sxe_hw *hw, u8 reg_idx, u8 bit_idx); void (*fc_mac_addr_set)(struct sxe_hw *hw, u8 *mac_addr); =20 - void (*mc_filter_enable)(struct sxe_hw *); + void (*mc_filter_enable)(struct sxe_hw *hw); =20 void (*mc_filter_disable)(struct sxe_hw *hw); =20 - void (*rx_nfs_filter_disable)(struct sxe_hw *); - void (*ethertype_filter_set)(struct sxe_hw *, u8, u32); + void (*rx_nfs_filter_disable)(struct sxe_hw *hw); + void (*ethertype_filter_set)(struct sxe_hw *hw, u8 filter_type, u32 val); =20 void (*vt_ctrl_configure)(struct sxe_hw *hw, u8 num_vfs); =20 @@ -600,16 +603,17 @@ struct sxe_filter_mac { }; =20 struct sxe_filter_vlan_operations { - u32 (*pool_filter_read)(struct sxe_hw *, u16); - void (*pool_filter_write)(struct sxe_hw *, u16, u32); - u32 (*pool_filter_bitmap_read)(struct sxe_hw *, u16); - void (*pool_filter_bitmap_write)(struct sxe_hw *, u16, u32); - void (*filter_array_write)(struct sxe_hw *, u16, u32); - u32 (*filter_array_read)(struct sxe_hw *, u16); - void (*filter_array_clear)(struct sxe_hw *); - void (*filter_switch)(struct sxe_hw *,bool); - void (*untagged_pkts_rcv_switch)(struct sxe_hw *, u32, bool); - s32 (*filter_configure)(struct sxe_hw *, u32, u32, bool, bool); + u32 (*pool_filter_read)(struct sxe_hw *hw, u16 reg_idx); + void (*pool_filter_write)(struct sxe_hw *hw, u16 reg_idx, u32 val); + u32 (*pool_filter_bitmap_read)(struct sxe_hw *hw, u16 reg_idx); + void (*pool_filter_bitmap_write)(struct sxe_hw *hw, u16 reg_idx, u32 val); + void (*filter_array_write)(struct sxe_hw *hw, u16 reg_idx, u32 val); + u32 (*filter_array_read)(struct sxe_hw *hw, u16 reg_idx); + void (*filter_array_clear)(struct sxe_hw *hw); + void (*filter_switch)(struct sxe_hw *hw, bool enable); + void (*untagged_pkts_rcv_switch)(struct sxe_hw *hw, u32 vf, bool accept); + s32 (*filter_configure)(struct sxe_hw *hw, u32 vid, u32 pool, + bool vlan_on, bool vlvf_bypass); }; =20 struct sxe_filter_vlan { @@ -622,55 +626,63 @@ struct sxe_filter_info { }; =20 struct sxe_dbu_operations { - void (*rx_pkt_buf_size_configure)(struct sxe_hw *, u8, u32, u16); - void (*rx_pkt_buf_switch)(struct sxe_hw *, bool); - void (*rx_multi_ring_configure)(struct sxe_hw *, u8, bool, bool); - void (*rss_key_set_all)(struct sxe_hw *, u32 *); - void (*rss_redir_tbl_set_all)(struct sxe_hw *, u8 *); - void (*rx_cap_switch_on)(struct sxe_hw *); - void (*rss_hash_pkt_type_set)(struct sxe_hw *, u32); - void (*rss_hash_pkt_type_update)(struct sxe_hw *, u32); - void (*rss_rings_used_set)(struct sxe_hw *, u32, u16, u16); - void (*lro_ack_switch)(struct sxe_hw *, bool); - void (*vf_rx_switch)(struct sxe_hw *, u32, u32, bool); - - s32 (*fnav_mode_init)(struct sxe_hw *, u32, u32); - s32 (*fnav_specific_rule_mask_set)(struct sxe_hw *, - union sxe_fnav_rule_info *); - s32 (*fnav_specific_rule_add)(struct sxe_hw *, - union sxe_fnav_rule_info *, - u16, u8); - s32 (*fnav_specific_rule_del)(struct sxe_hw *, - union sxe_fnav_rule_info *, u16); - s32 (*fnav_sample_hash_cmd_get)(struct sxe_hw *, - u8, u32, u8, u64 *); + void (*rx_pkt_buf_size_configure)(struct sxe_hw *hw, u8 num_pb, + u32 headroom, u16 strategy); + void (*rx_pkt_buf_switch)(struct sxe_hw *hw, bool is_on); + void (*rx_multi_ring_configure)(struct sxe_hw *hw, u8 tcs, + bool is_4q, bool sriov_enable); + void (*rss_key_set_all)(struct sxe_hw *hw, u32 *rss_key); + void (*rss_redir_tbl_set_all)(struct sxe_hw *hw, u8 *redir_tbl); + void (*rx_cap_switch_on)(struct sxe_hw *hw); + void (*rss_hash_pkt_type_set)(struct sxe_hw *hw, u32 version); + void (*rss_hash_pkt_type_update)(struct sxe_hw *hw, u32 version); + void (*rss_rings_used_set)(struct sxe_hw *hw, u32 rss_num, + u16 pool, u16 pf_offset); + void (*lro_ack_switch)(struct sxe_hw *hw, bool is_on); + void (*vf_rx_switch)(struct sxe_hw *hw, u32 reg_offset, + u32 vf_index, bool is_off); + + s32 (*fnav_mode_init)(struct sxe_hw *hw, u32 fnavctrl, u32 fnav_mode); + s32 (*fnav_specific_rule_mask_set)(struct sxe_hw *hw, + union sxe_fnav_rule_info *mask); + s32 (*fnav_specific_rule_add)(struct sxe_hw *hw, + union sxe_fnav_rule_info *input, + u16 soft_id, u8 queue); + s32 (*fnav_specific_rule_del)(struct sxe_hw *hw, + union sxe_fnav_rule_info *input, u16 soft_id); + s32 (*fnav_sample_hash_cmd_get)(struct sxe_hw *hw, + u8 flow_type, u32 hash_value, + u8 queue, u64 *hash_cmd); void (*fnav_sample_stats_reinit)(struct sxe_hw *hw); void (*fnav_sample_hash_set)(struct sxe_hw *hw, u64 hash); - s32 (*fnav_single_sample_rule_del)(struct sxe_hw *,u32); - - void (*ptp_init)(struct sxe_hw *); - void (*ptp_freq_adjust)(struct sxe_hw *, u32); - void (*ptp_systime_init)(struct sxe_hw *); - u64 (*ptp_systime_get)(struct sxe_hw *); - void (*ptp_tx_timestamp_get)(struct sxe_hw *, u32 *ts_sec, u32 *ts_ns); - void (*ptp_timestamp_mode_set)(struct sxe_hw *, bool, u32, u32); - void (*ptp_rx_timestamp_clear)(struct sxe_hw *); - u64 (*ptp_rx_timestamp_get)(struct sxe_hw *); - bool (*ptp_is_rx_timestamp_valid)(struct sxe_hw *); - void (*ptp_timestamp_enable)(struct sxe_hw *); - - void (*tx_pkt_buf_switch)(struct sxe_hw *, bool); + s32 (*fnav_single_sample_rule_del)(struct sxe_hw *hw, u32 hash); + + void (*ptp_init)(struct sxe_hw *hw); + void (*ptp_freq_adjust)(struct sxe_hw *hw, u32 adj_freq); + void (*ptp_systime_init)(struct sxe_hw *hw); + u64 (*ptp_systime_get)(struct sxe_hw *hw); + void (*ptp_tx_timestamp_get)(struct sxe_hw *hw, u32 *ts_sec, u32 *ts_ns); + void (*ptp_timestamp_mode_set)(struct sxe_hw *hw, bool is_l2, + u32 tsctl, u32 tses); + void (*ptp_rx_timestamp_clear)(struct sxe_hw *hw); + u64 (*ptp_rx_timestamp_get)(struct sxe_hw *hw); + bool (*ptp_is_rx_timestamp_valid)(struct sxe_hw *hw); + void (*ptp_timestamp_enable)(struct sxe_hw *hw); + + void (*tx_pkt_buf_switch)(struct sxe_hw *hw, bool is_on); =20 void (*dcb_tc_rss_configure)(struct sxe_hw *hw, u16 rss_i); =20 - void (*tx_pkt_buf_size_configure)(struct sxe_hw *, u8); + void (*tx_pkt_buf_size_configure)(struct sxe_hw *hw, u8 num_pb); =20 - void (*rx_cap_switch_off)(struct sxe_hw *); - u32 (*rx_pkt_buf_size_get)(struct sxe_hw *, u8); + void (*rx_cap_switch_off)(struct sxe_hw *hw); + u32 (*rx_pkt_buf_size_get)(struct sxe_hw *hw, u8 pb); void (*rx_func_switch_on)(struct sxe_hw *hw); =20 - void (*tx_ring_disable)(struct sxe_hw *, u8, unsigned long); - void (*rx_ring_disable)(struct sxe_hw *, u8, unsigned long); + void (*tx_ring_disable)(struct sxe_hw *hw, u8 reg_idx, + unsigned long timeout); + void (*rx_ring_disable)(struct sxe_hw *hw, u8 reg_idx, + unsigned long timeout); =20 u32 (*tx_dbu_fc_status_get)(struct sxe_hw *hw); }; @@ -681,44 +693,50 @@ struct sxe_dbu_info { =20 =20 struct sxe_dma_operations { - void (*rx_dma_ctrl_init)(struct sxe_hw *, bool); - void (*rx_ring_disable)(struct sxe_hw *, u8); - void (*rx_ring_switch)(struct sxe_hw *, u8, bool); - void (*rx_ring_switch_not_polling)(struct sxe_hw *, u8, bool); - void (*rx_ring_desc_configure)(struct sxe_hw *, u32, u64, u8); - void (*rx_desc_thresh_set)(struct sxe_hw *, u8); - void (*rx_rcv_ctl_configure)(struct sxe_hw *, u8, u32, u32); - void (*rx_lro_ctl_configure)(struct sxe_hw *, u8, u32); - u32 (*rx_desc_ctrl_get)(struct sxe_hw *, u8); - void (*rx_dma_lro_ctl_set)(struct sxe_hw *); - void (*rx_drop_switch)(struct sxe_hw *, u8, bool); + void (*rx_dma_ctrl_init)(struct sxe_hw *hw); + void (*rx_ring_disable)(struct sxe_hw *hw, u8 ring_idx); + void (*rx_ring_switch)(struct sxe_hw *hw, u8 reg_idx, bool is_on); + void (*rx_ring_switch_not_polling)(struct sxe_hw *hw, u8 reg_idx, + bool is_on); + void (*rx_ring_desc_configure)(struct sxe_hw *hw, u32 desc_mem_len, + u64 desc_dma_addr, u8 reg_idx); + void (*rx_desc_thresh_set)(struct sxe_hw *hw, u8 reg_idx); + void (*rx_rcv_ctl_configure)(struct sxe_hw *hw, u8 reg_idx, + u32 header_buf_len, u32 pkg_buf_len); + void (*rx_lro_ctl_configure)(struct sxe_hw *hw, u8 reg_idx, u32 max_desc); + u32 (*rx_desc_ctrl_get)(struct sxe_hw *hw, u8 reg_idx); + void (*rx_dma_lro_ctl_set)(struct sxe_hw *hw); + void (*rx_drop_switch)(struct sxe_hw *hw, u8 idx, bool is_enable); void (*rx_tph_update)(struct sxe_hw *hw, u8 ring_idx, u8 cpu); =20 - void (*tx_enable)(struct sxe_hw *); - void (*tx_multi_ring_configure)(struct sxe_hw *, u8, u16, bool, u16); - void (*tx_ring_desc_configure)(struct sxe_hw *, u32, u64, u8); - void (*tx_desc_thresh_set)(struct sxe_hw *, u8, u32, u32, u32); - void (*tx_ring_switch)(struct sxe_hw *, u8, bool); - void (*tx_ring_switch_not_polling)(struct sxe_hw *, u8, bool); - void (*tx_pkt_buf_thresh_configure)(struct sxe_hw *, u8, bool); - u32 (*tx_desc_ctrl_get)(struct sxe_hw *, u8); - void (*tx_ring_info_get)(struct sxe_hw *, u8, u32 *, u32 *); - void (*tx_desc_wb_thresh_clear)(struct sxe_hw *, u8); - - void (*vlan_tag_strip_switch)(struct sxe_hw *, u16, bool); - void (*tx_vlan_tag_set)(struct sxe_hw *, u16, u16, u32); - void (*tx_vlan_tag_clear)(struct sxe_hw *, u32); + void (*tx_enable)(struct sxe_hw *hw); + void (*tx_multi_ring_configure)(struct sxe_hw *hw, u8 tcs, u16 pool_mask, + bool sriov_enable, u16 max_txq); + void (*tx_ring_desc_configure)(struct sxe_hw *hw, u32 desc_mem_len, + u64 desc_dma_addr, u8 reg_idx); + void (*tx_desc_thresh_set)(struct sxe_hw *hw, u8 reg_idx, u32 wb_thresh, + u32 host_thresh, u32 prefech_thresh); + void (*tx_ring_switch)(struct sxe_hw *hw, u8 reg_idx, bool is_on); + void (*tx_ring_switch_not_polling)(struct sxe_hw *hw, u8 reg_idx, bool is= _on); + void (*tx_pkt_buf_thresh_configure)(struct sxe_hw *hw, u8 num_pb, bool dc= b_enable); + u32 (*tx_desc_ctrl_get)(struct sxe_hw *hw, u8 reg_idx); + void (*tx_ring_info_get)(struct sxe_hw *hw, u8 idx, u32 *head, u32 *tail); + void (*tx_desc_wb_thresh_clear)(struct sxe_hw *hw, u8 reg_idx); + + void (*vlan_tag_strip_switch)(struct sxe_hw *hw, u16 reg_index, bool is_e= nable); + void (*tx_vlan_tag_set)(struct sxe_hw *hw, u16 vid, u16 qos, u32 vf); + void (*tx_vlan_tag_clear)(struct sxe_hw *hw, u32 vf); void (*tx_tph_update)(struct sxe_hw *hw, u8 ring_idx, u8 cpu); =20 void (*tph_switch)(struct sxe_hw *hw, bool is_enable); =20 void (*dcb_rx_bw_alloc_configure)(struct sxe_hw *hw, - u16 *refill, - u16 *max, - u8 *bwg_id, - u8 *prio_type, - u8 *prio_tc, - u8 max_priority); + u16 *refill, + u16 *max, + u8 *bwg_id, + u8 *prio_type, + u8 *prio_tc, + u8 max_priority); void (*dcb_tx_desc_bw_alloc_configure)(struct sxe_hw *hw, u16 *refill, u16 *max, @@ -766,7 +784,8 @@ struct sxe_dma_info { struct sxe_sec_operations { void (*ipsec_rx_ip_store)(struct sxe_hw *hw, __be32 *ip_addr, u8 ip_len, = u8 ip_idx); void (*ipsec_rx_spi_store)(struct sxe_hw *hw, __be32 spi, u8 ip_idx, u16 = idx); - void (*ipsec_rx_key_store)(struct sxe_hw *hw, u32 *key, u8 key_len, u32 = salt, u32 mode, u16 idx); + void (*ipsec_rx_key_store)(struct sxe_hw *hw, u32 *key, u8 key_len, + u32 salt, u32 mode, u16 idx); void (*ipsec_tx_key_store)(struct sxe_hw *hw, u32 *key, u8 key_len, u32 = salt, u16 idx); void (*ipsec_sec_data_stop)(struct sxe_hw *hw, bool is_linkup); void (*ipsec_engine_start)(struct sxe_hw *hw, bool is_linkup); @@ -780,12 +799,12 @@ struct sxe_sec_info { }; =20 struct sxe_stat_operations { - void (*stats_clear)(struct sxe_hw *); - void (*stats_get)(struct sxe_hw *, struct sxe_mac_stats *); + void (*stats_clear)(struct sxe_hw *hw); + void (*stats_get)(struct sxe_hw *hw, struct sxe_mac_stats *st); =20 u32 (*tx_packets_num_get)(struct sxe_hw *hw); u32 (*unsecurity_packets_num_get)(struct sxe_hw *hw); - u32 (*mac_stats_dump)(struct sxe_hw *, u32 *, u32); + u32 (*mac_stats_dump)(struct sxe_hw *hw, u32 *regs_buff, u32 buf_size); u32 (*tx_dbu_to_mac_stats)(struct sxe_hw *hw); }; =20 @@ -807,20 +826,20 @@ struct sxe_mbx_operations { }; =20 struct sxe_mbx_stats { - u32 send_msgs;=20 - u32 rcv_msgs;=20=20 + u32 send_msgs; + u32 rcv_msgs; =20 - u32 reqs;=20=20=20=20=20=20 - u32 acks;=20=20=20=20=20=20 - u32 rsts;=20=20=20=20=20=20 + u32 reqs; + u32 acks; + u32 rsts; }; =20 struct sxe_mbx_info { - const struct sxe_mbx_operations *ops;=20 - struct sxe_mbx_stats stats;=20 - u32 retry;=20=20=20=20 - u32 interval;=20 - u32 msg_len;=20 + const struct sxe_mbx_operations *ops; + struct sxe_mbx_stats stats; + u32 retry; + u32 interval; + u32 msg_len; }; =20 struct sxe_pcie_operations { @@ -828,7 +847,7 @@ struct sxe_pcie_operations { }; =20 struct sxe_pcie_info { - const struct sxe_pcie_operations *ops;=20 + const struct sxe_pcie_operations *ops; }; =20 enum sxe_hw_state { @@ -845,40 +864,41 @@ enum sxe_fc_mode { }; =20 struct sxe_fc_info { - u32 high_water[MAX_TRAFFIC_CLASS];=20 - u32 low_water[MAX_TRAFFIC_CLASS];=20 - u16 pause_time;=20 - bool strict_ieee;=20 - bool disable_fc_autoneg;=20 - u16 send_xon;=20 - enum sxe_fc_mode current_mode;=20 - enum sxe_fc_mode requested_mode;=20 + u32 high_water[MAX_TRAFFIC_CLASS]; + u32 low_water[MAX_TRAFFIC_CLASS]; + u16 pause_time; + bool strict_ieee; + bool disable_fc_autoneg; + u16 send_xon; + enum sxe_fc_mode current_mode; + enum sxe_fc_mode requested_mode; }; =20 struct sxe_fc_nego_mode { - u32 adv_sym;=20 - u32 adv_asm;=20 - u32 lp_sym;=20=20 - u32 lp_asm;=20=20 + u32 adv_sym; + u32 adv_asm; + u32 lp_sym; + u32 lp_asm; =20 }; =20 struct sxe_hdc_operations { - s32 (*pf_lock_get)(struct sxe_hw *, u32); - void (*pf_lock_release)(struct sxe_hw *, u32); - bool (*is_fw_over_set)(struct sxe_hw *); - u32 (*fw_ack_header_rcv)(struct sxe_hw *); - void (*packet_send_done)(struct sxe_hw *); - void (*packet_header_send)(struct sxe_hw *, u32); - void (*packet_data_dword_send)(struct sxe_hw *, u16, u32); - u32 (*packet_data_dword_rcv)(struct sxe_hw *, u16); - u32 (*fw_status_get)(struct sxe_hw *); - void (*drv_status_set)(struct sxe_hw *, u32); - u32 (*irq_event_get)(struct sxe_hw *); - void (*irq_event_clear)(struct sxe_hw *, u32); - void (*fw_ov_clear)(struct sxe_hw *); - u32 (*channel_state_get)(struct sxe_hw *); - void (*resource_clean)(struct sxe_hw *); + s32 (*pf_lock_get)(struct sxe_hw *hw, u32 trylock); + void (*pf_lock_release)(struct sxe_hw *hw, u32 retry_cnt); + bool (*is_fw_over_set)(struct sxe_hw *hw); + u32 (*fw_ack_header_rcv)(struct sxe_hw *hw); + void (*packet_send_done)(struct sxe_hw *hw); + void (*packet_header_send)(struct sxe_hw *hw, u32 value); + void (*packet_data_dword_send)(struct sxe_hw *hw, + u16 dword_index, u32 value); + u32 (*packet_data_dword_rcv)(struct sxe_hw *hw, u16 dword_index); + u32 (*fw_status_get)(struct sxe_hw *hw); + void (*drv_status_set)(struct sxe_hw *hw, u32 value); + u32 (*irq_event_get)(struct sxe_hw *hw); + void (*irq_event_clear)(struct sxe_hw *hw, u32 event); + void (*fw_ov_clear)(struct sxe_hw *hw); + u32 (*channel_state_get)(struct sxe_hw *hw); + void (*resource_clean)(struct sxe_hw *hw); }; =20 struct sxe_hdc_info { @@ -901,29 +921,29 @@ struct sxe_phy_reg_info { }; =20 struct sxe_hw { - u8 __iomem *reg_base_addr;=20=20=20=20=20=20=20=20=20=20=20=20 + u8 __iomem *reg_base_addr; =20 void *adapter; void *priv; - unsigned long state;=20=20=20 + unsigned long state; void (*fault_handle)(void *priv); u32 (*reg_read)(const volatile void *reg); void (*reg_write)(u32 value, volatile void *reg); =20 - struct sxe_hw_setup setup;=20=20=20=20=20=20=20=20=20=20=20 - struct sxe_irq_info irq;=20=20=20=20=20=20=20=20=20=20=20=20=20 - struct sxe_mac_info mac;=20=20=20=20=20=20=20=20=20=20=20=20=20 - struct sxe_filter_info filter;=20=20=20=20=20=20=20=20 - struct sxe_dbu_info dbu;=20=20=20=20=20=20=20=20=20=20=20=20=20 - struct sxe_dma_info dma;=20=20=20=20=20=20=20=20=20=20=20=20=20 - struct sxe_sec_info sec;=20=20=20=20=20=20=20=20=20=20=20=20=20 - struct sxe_stat_info stat;=20=20=20=20=20=20=20=20=20=20=20=20 + struct sxe_hw_setup setup; + struct sxe_irq_info irq; + struct sxe_mac_info mac; + struct sxe_filter_info filter; + struct sxe_dbu_info dbu; + struct sxe_dma_info dma; + struct sxe_sec_info sec; + struct sxe_stat_info stat; struct sxe_fc_info fc; =20 - struct sxe_mbx_info mbx;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - struct sxe_pcie_info pcie;=20=20=20=20=20=20=20=20=20=20=20=20 - struct sxe_hdc_info hdc;=20=20=20=20=20=20=20=20=20=20=20=20=20 - struct sxe_phy_reg_info phy;=20=20=20=20=20=20=20=20=20=20 + struct sxe_mbx_info mbx; + struct sxe_pcie_info pcie; + struct sxe_hdc_info hdc; + struct sxe_phy_reg_info phy; }; =20 u16 sxe_mac_reg_num_get(void); @@ -951,7 +971,6 @@ static inline void sxe_hw_fault_handle_init(struct sxe_= hw *hw, hw->priv =3D priv; hw->fault_handle =3D handle; =20 - return; } =20 static inline void sxe_hw_reg_handle_init(struct sxe_hw *hw, @@ -961,10 +980,11 @@ static inline void sxe_hw_reg_handle_init(struct sxe_= hw *hw, hw->reg_read =3D read; hw->reg_write =3D write; =20 - return; } =20 -#ifdef SXE_DPDK=20 +#ifdef SXE_DPDK + +void sxe_hw_crc_strip_config(struct sxe_hw *hw, bool keep_crc); =20 void sxe_hw_stats_seq_clean(struct sxe_hw *hw, struct sxe_mac_stats *stats= ); =20 @@ -1117,12 +1137,12 @@ void sxe_hw_rss_field_set(struct sxe_hw *hw, u32 rs= s_field); =20 void sxe_hw_rss_redir_tbl_set_all(struct sxe_hw *hw, u8 *redir_tbl); =20 -u32 sxe_hw_rss_redir_tbl_get_by_idx(struct sxe_hw *hw, u16); +u32 sxe_hw_rss_redir_tbl_get_by_idx(struct sxe_hw *hw, u16 reg_idx); =20 void sxe_hw_rss_redir_tbl_set_by_idx(struct sxe_hw *hw, u16 reg_idx, u32 value); =20 -void sxe_hw_rx_dma_ctrl_init(struct sxe_hw *hw, bool crc_strip_on); +void sxe_hw_rx_dma_ctrl_init(struct sxe_hw *hw); =20 void sxe_hw_mac_max_frame_set(struct sxe_hw *hw, u32 max_frame); =20 @@ -1291,12 +1311,12 @@ void sxe_hw_dcb_tc_stats_configure(struct sxe_hw *h= w, u8 tc_count, bool vmdq_active); =20 void sxe_hw_dcb_rx_bw_alloc_configure(struct sxe_hw *hw, - u16 *refill, - u16 *max, - u8 *bwg_id, - u8 *prio_type, - u8 *prio_tc, - u8 max_priority); + u16 *refill, + u16 *max, + u8 *bwg_id, + u8 *prio_type, + u8 *prio_tc, + u8 max_priority); =20 void sxe_hw_dcb_tx_desc_bw_alloc_configure(struct sxe_hw *hw, u16 *refill, @@ -1411,12 +1431,12 @@ s32 sxe_hw_vlvf_slot_find(struct sxe_hw *hw, u32 vl= an, bool vlvf_bypass); =20 u32 sxe_hw_vlan_pool_filter_read(struct sxe_hw *hw, u16 reg_index); =20 -void sxe_hw_mirror_vlan_set(struct sxe_hw *hw, u8 idx,u32 lsb, u32 msb); +void sxe_hw_mirror_vlan_set(struct sxe_hw *hw, u8 idx, u32 lsb, u32 msb); =20 -void sxe_hw_mirror_virtual_pool_set(struct sxe_hw *hw, u8 idx,u32 lsb, u32= msb); +void sxe_hw_mirror_virtual_pool_set(struct sxe_hw *hw, u8 idx, u32 lsb, u3= 2 msb); =20 void sxe_hw_mirror_ctl_set(struct sxe_hw *hw, u8 rule_id, - u8 mirror_type, u8 dst_pool, bool on); + u8 mirror_type, u8 dst_pool, bool on); =20 void sxe_hw_mirror_rule_clear(struct sxe_hw *hw, u8 rule_id); =20 @@ -1470,7 +1490,7 @@ void sxe_hw_syn_filter_add(struct sxe_hw *hw, u16 que= ue, u8 priority); void sxe_hw_syn_filter_del(struct sxe_hw *hw); =20 void sxe_hw_rss_key_set_all(struct sxe_hw *hw, u32 *rss_key); -#endif=20 +#endif =20 void sxe_hw_fnav_enable(struct sxe_hw *hw, u32 fnavctrl); =20 @@ -1493,7 +1513,7 @@ void sxe_hw_rss_redir_tbl_reg_write(struct sxe_hw *hw, u32 sxe_hw_fnav_port_mask_get(__be16 src_port_mask, __be16 dst_port_mask); =20 s32 sxe_hw_fnav_specific_rule_mask_set(struct sxe_hw *hw, - union sxe_fnav_rule_info *input_mask); + union sxe_fnav_rule_info *input_mask); =20 s32 sxe_hw_vlan_filter_configure(struct sxe_hw *hw, u32 vid, u32 pool, @@ -1501,5 +1521,5 @@ s32 sxe_hw_vlan_filter_configure(struct sxe_hw *hw, =20 void sxe_hw_ptp_systime_init(struct sxe_hw *hw); =20 -#endif=20 +#endif #endif diff --git a/drivers/net/sxe/base/sxe_logs.h b/drivers/net/sxe/base/sxe_log= s.h index 510d7aae5c..81088c2fc8 100644 --- a/drivers/net/sxe/base/sxe_logs.h +++ b/drivers/net/sxe/base/sxe_logs.h @@ -11,9 +11,9 @@ =20 #include "sxe_types.h" =20 -#define LOG_FILE_NAME_LEN 256 -#define LOG_FILE_PATH "/var/log/" -#define LOG_FILE_PREFIX "sxepmd.log" +#define LOG_FILE_NAME_LEN 256 +#define LOG_FILE_PATH "/var/log/" +#define LOG_FILE_PREFIX "sxepmd.log" =20 extern s32 sxe_log_init; extern s32 sxe_log_rx; @@ -36,9 +36,9 @@ extern s32 sxe_log_hw; gettimeofday(&tv, NULL); \ td =3D localtime(&tv.tv_sec); \ strftime(log_time, sizeof(log_time), "%Y-%m-%d-%H:%M:%S", td); \ - } while(0) + } while (0) =20 -#define filename_printf(x) strrchr((x),'/')?strrchr((x),'/')+1:(x) +#define filename_printf(x) (strrchr((x), '/')?strrchr((x), '/')+1:(x)) =20 #ifdef SXE_DPDK_DEBUG #define PMD_LOG_DEBUG(logtype, fmt, ...) \ @@ -50,7 +50,7 @@ extern s32 sxe_log_hw; "DEBUG", log_time, pthread_self(), \ filename_printf(__FILE__), __LINE__, \ __func__, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define PMD_LOG_INFO(logtype, fmt, ...) \ do { \ @@ -61,7 +61,7 @@ extern s32 sxe_log_hw; "INFO", log_time, pthread_self(), \ filename_printf(__FILE__), __LINE__, \ __func__, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define PMD_LOG_NOTICE(logtype, fmt, ...) \ do { \ @@ -72,7 +72,7 @@ extern s32 sxe_log_hw; "NOTICE", log_time, pthread_self(), \ filename_printf(__FILE__), __LINE__, \ __func__, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define PMD_LOG_WARN(logtype, fmt, ...) \ do { \ @@ -83,7 +83,7 @@ extern s32 sxe_log_hw; "WARN", log_time, pthread_self(), \ filename_printf(__FILE__), __LINE__, \ __func__, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define PMD_LOG_ERR(logtype, fmt, ...) \ do { \ @@ -94,7 +94,7 @@ extern s32 sxe_log_hw; "ERR", log_time, pthread_self(), \ filename_printf(__FILE__), __LINE__, \ __func__, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define PMD_LOG_CRIT(logtype, fmt, ...) \ do { \ @@ -105,7 +105,7 @@ extern s32 sxe_log_hw; "CRIT", log_time, pthread_self(), \ filename_printf(__FILE__), __LINE__, \ __func__, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define PMD_LOG_ALERT(logtype, fmt, ...) \ do { \ @@ -116,7 +116,7 @@ extern s32 sxe_log_hw; "ALERT", log_time, pthread_self(), \ filename_printf(__FILE__), __LINE__, \ __func__, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define PMD_LOG_EMERG(logtype, fmt, ...) \ do { \ @@ -127,56 +127,40 @@ extern s32 sxe_log_hw; "EMERG", log_time, pthread_self(), \ filename_printf(__FILE__), __LINE__, \ __func__, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #else #define PMD_LOG_DEBUG(logtype, fmt, ...) \ - do { \ rte_log(RTE_LOG_DEBUG, logtype, "%s(): " \ - fmt "\n", __func__, ##__VA_ARGS__); \ - } while(0) + fmt "\n", __func__, ##__VA_ARGS__) =20 #define PMD_LOG_INFO(logtype, fmt, ...) \ - do { \ rte_log(RTE_LOG_INFO, logtype, "%s(): " \ - fmt "\n", __func__, ##__VA_ARGS__); \ - } while(0) + fmt "\n", __func__, ##__VA_ARGS__) =20 #define PMD_LOG_NOTICE(logtype, fmt, ...) \ - do { \ rte_log(RTE_LOG_NOTICE, logtype, "%s(): " \ - fmt "\n", __func__, ##__VA_ARGS__); \ - } while(0) + fmt "\n", __func__, ##__VA_ARGS__) =20 #define PMD_LOG_WARN(logtype, fmt, ...) \ - do { \ rte_log(RTE_LOG_WARNING, logtype, "%s(): " \ - fmt "\n", __func__, ##__VA_ARGS__); \ - } while(0) + fmt "\n", __func__, ##__VA_ARGS__) =20 #define PMD_LOG_ERR(logtype, fmt, ...) \ - do { \ rte_log(RTE_LOG_ERR, logtype, "%s(): " \ - fmt "\n", __func__, ##__VA_ARGS__); \ - } while(0) + fmt "\n", __func__, ##__VA_ARGS__) =20 #define PMD_LOG_CRIT(logtype, fmt, ...) \ - do { \ rte_log(RTE_LOG_CRIT, logtype, "%s(): " \ - fmt "\n", __func__, ##__VA_ARGS__); \ - } while(0) + fmt "\n", __func__, ##__VA_ARGS__) =20 #define PMD_LOG_ALERT(logtype, fmt, ...) \ - do { \ rte_log(RTE_LOG_ALERT, logtype, "%s(): " \ - fmt "\n", __func__, ##__VA_ARGS__); \ - } while(0) + fmt "\n", __func__, ##__VA_ARGS__) =20 #define PMD_LOG_EMERG(logtype, fmt, ...) \ - do { \ rte_log(RTE_LOG_EMERG, logtype, "%s(): " \ - fmt "\n", __func__, ##__VA_ARGS__); \ - } while(0) + fmt "\n", __func__, ##__VA_ARGS__) =20 #endif =20 @@ -184,54 +168,38 @@ extern s32 sxe_log_hw; =20 #ifdef SXE_DPDK_DEBUG #define LOG_DEBUG(fmt, ...) \ - do { \ - PMD_LOG_DEBUG(DRV, fmt, ##__VA_ARGS__); \ - } while(0) + PMD_LOG_DEBUG(DRV, fmt, ##__VA_ARGS__) =20 #define LOG_INFO(fmt, ...) \ - do { \ - PMD_LOG_INFO(DRV, fmt, ##__VA_ARGS__); \ - } while(0) + PMD_LOG_INFO(DRV, fmt, ##__VA_ARGS__) =20 #define LOG_WARN(fmt, ...) \ - do { \ - PMD_LOG_WARN(DRV, fmt, ##__VA_ARGS__); \ - } while(0) + PMD_LOG_WARN(DRV, fmt, ##__VA_ARGS__) =20 #define LOG_ERROR(fmt, ...) \ - do { \ - PMD_LOG_ERR(DRV, fmt, ##__VA_ARGS__); \ - } while(0) + PMD_LOG_ERR(DRV, fmt, ##__VA_ARGS__) =20 #define LOG_DEBUG_BDF(fmt, ...) \ - do { \ - PMD_LOG_DEBUG(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__); \ - } while(0) + PMD_LOG_DEBUG(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__) =20 #define LOG_INFO_BDF(fmt, ...) \ - do { \ - PMD_LOG_INFO(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__); \ - } while(0) + PMD_LOG_INFO(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__) =20 #define LOG_WARN_BDF(fmt, ...) \ - do { \ - PMD_LOG_WARN(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__); \ - } while(0) + PMD_LOG_WARN(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__) =20 #define LOG_ERROR_BDF(fmt, ...) \ - do { \ - PMD_LOG_ERR(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__); \ - } while(0) + PMD_LOG_ERR(HW, "[%s]" fmt, adapter->name, ##__VA_ARGS__) =20 #else #define LOG_DEBUG(fmt, ...) #define LOG_INFO(fmt, ...) #define LOG_WARN(fmt, ...) #define LOG_ERROR(fmt, ...) -#define LOG_DEBUG_BDF(fmt, ...) do { UNUSED(adapter); } while(0) -#define LOG_INFO_BDF(fmt, ...) do { UNUSED(adapter); } while(0) -#define LOG_WARN_BDF(fmt, ...) do { UNUSED(adapter); } while(0) -#define LOG_ERROR_BDF(fmt, ...) do { UNUSED(adapter); } while(0) +#define LOG_DEBUG_BDF(fmt, ...) UNUSED(adapter) +#define LOG_INFO_BDF(fmt, ...) UNUSED(adapter) +#define LOG_WARN_BDF(fmt, ...) UNUSED(adapter) +#define LOG_ERROR_BDF(fmt, ...) UNUSED(adapter) #endif =20 #ifdef SXE_DPDK_DEBUG @@ -239,61 +207,61 @@ extern s32 sxe_log_hw; do { \ UNUSED(adapter); \ LOG_DEBUG_BDF(fmt, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define LOG_DEV_INFO(fmt, ...) \ do { \ UNUSED(adapter); \ LOG_INFO_BDF(fmt, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define LOG_DEV_WARN(fmt, ...) \ do { \ UNUSED(adapter); \ LOG_WARN_BDF(fmt, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define LOG_DEV_ERR(fmt, ...) \ do { \ UNUSED(adapter); \ LOG_ERROR_BDF(fmt, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define LOG_MSG_DEBUG(msglvl, fmt, ...) \ do { \ UNUSED(adapter); \ LOG_DEBUG_BDF(fmt, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define LOG_MSG_INFO(msglvl, fmt, ...) \ do { \ UNUSED(adapter); \ LOG_INFO_BDF(fmt, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define LOG_MSG_WARN(msglvl, fmt, ...) \ do { \ UNUSED(adapter); \ LOG_WARN_BDF(fmt, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #define LOG_MSG_ERR(msglvl, fmt, ...) \ do { \ UNUSED(adapter); \ LOG_ERROR_BDF(fmt, ##__VA_ARGS__); \ - } while(0) + } while (0) =20 #else -#define LOG_DEV_DEBUG(fmt, ...) do { UNUSED(adapter); } while(0) -#define LOG_DEV_INFO(fmt, ...) do { UNUSED(adapter); } while(0) -#define LOG_DEV_WARN(fmt, ...) do { UNUSED(adapter); } while(0) -#define LOG_DEV_ERR(fmt, ...) do { UNUSED(adapter); } while(0) -#define LOG_MSG_DEBUG(msglvl, fmt, ...) do { UNUSED(adapter); } while(0) -#define LOG_MSG_INFO(msglvl, fmt, ...) do { UNUSED(adapter); } while(0) -#define LOG_MSG_WARN(msglvl, fmt, ...) do { UNUSED(adapter); } while(0) -#define LOG_MSG_ERR(msglvl, fmt, ...) do { UNUSED(adapter); } while(0) +#define LOG_DEV_DEBUG(fmt, ...) UNUSED(adapter) +#define LOG_DEV_INFO(fmt, ...) UNUSED(adapter) +#define LOG_DEV_WARN(fmt, ...) UNUSED(adapter) +#define LOG_DEV_ERR(fmt, ...) UNUSED(adapter) +#define LOG_MSG_DEBUG(msglvl, fmt, ...) UNUSED(adapter) +#define LOG_MSG_INFO(msglvl, fmt, ...) UNUSED(adapter) +#define LOG_MSG_WARN(msglvl, fmt, ...) UNUSED(adapter) +#define LOG_MSG_ERR(msglvl, fmt, ...) UNUSED(adapter) #endif =20 void sxe_log_stream_init(void); =20 -#endif=20 +#endif diff --git a/drivers/net/sxe/base/sxe_offload_common.c b/drivers/net/sxe/ba= se/sxe_offload_common.c index a7075b4669..b8d7597b84 100644 --- a/drivers/net/sxe/base/sxe_offload_common.c +++ b/drivers/net/sxe/base/sxe_offload_common.c @@ -30,18 +30,17 @@ u64 __sxe_rx_port_offload_capa_get(struct rte_eth_dev *= dev) rx_offload_capa =3D RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_TCP_CKSUM | - RTE_ETH_RX_OFFLOAD_KEEP_CRC | + RTE_ETH_RX_OFFLOAD_KEEP_CRC | #ifdef DEV_RX_JUMBO_FRAME DEV_RX_OFFLOAD_JUMBO_FRAME | #endif RTE_ETH_RX_OFFLOAD_VLAN_FILTER | - RTE_ETH_RX_OFFLOAD_VLAN_EXTEND |=20 + RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | RTE_ETH_RX_OFFLOAD_SCATTER | RTE_ETH_RX_OFFLOAD_RSS_HASH; =20 - if (!RTE_ETH_DEV_SRIOV(dev).active) { + if (!RTE_ETH_DEV_SRIOV(dev).active) rx_offload_capa |=3D RTE_ETH_RX_OFFLOAD_TCP_LRO; - } =20 return rx_offload_capa; } @@ -57,7 +56,7 @@ u64 __sxe_tx_port_offload_capa_get(struct rte_eth_dev *de= v) RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM | RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | - RTE_ETH_TX_OFFLOAD_TCP_TSO | + RTE_ETH_TX_OFFLOAD_TCP_TSO | RTE_ETH_TX_OFFLOAD_MULTI_SEGS | RTE_ETH_TX_OFFLOAD_MACSEC_INSERT; =20 diff --git a/drivers/net/sxe/base/sxe_queue_common.c b/drivers/net/sxe/base= /sxe_queue_common.c index eda73c3f79..6f6ba98dbe 100644 --- a/drivers/net/sxe/base/sxe_queue_common.c +++ b/drivers/net/sxe/base/sxe_queue_common.c @@ -46,7 +46,6 @@ static void sxe_tx_queues_clear(struct rte_eth_dev *dev) } } =20 - return; } =20 static void sxe_rx_queues_clear(struct rte_eth_dev *dev, bool rx_batch_all= oc_allowed) @@ -62,7 +61,6 @@ static void sxe_rx_queues_clear(struct rte_eth_dev *dev, = bool rx_batch_alloc_all } } =20 - return; } =20 s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *rx_setup, bool is_vf) @@ -90,7 +88,7 @@ s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *rx_s= etup, bool is_vf) if (desc_num % SXE_RX_DESC_RING_ALIGN !=3D 0 || (desc_num > SXE_MAX_RING_DESC) || (desc_num < SXE_MIN_RING_DESC)) { - PMD_LOG_ERR(INIT, "desc_num %u error",desc_num); + PMD_LOG_ERR(INIT, "desc_num %u error", desc_num); ret =3D -EINVAL; goto l_end; } @@ -115,11 +113,10 @@ s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *= rx_setup, bool is_vf) rxq->reg_idx =3D (u16)((RTE_ETH_DEV_SRIOV(dev).active =3D=3D 0) ? queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx); rxq->port_id =3D dev->data->port_id; - if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) { + if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) rxq->crc_len =3D RTE_ETHER_CRC_LEN; - } else { + else rxq->crc_len =3D 0; - } =20 rxq->drop_en =3D rx_conf->rx_drop_en; rxq->deferred_start =3D rx_conf->rx_deferred_start; @@ -140,13 +137,12 @@ s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *= rx_setup, bool is_vf) =20 memset(rx_mz->addr, 0, SXE_RX_RING_SIZE); =20 - if (is_vf) { + if (is_vf) rxq->rdt_reg_addr =3D (volatile u32 *)(rx_setup->reg_base_addr + SXE_VFRDT(rxq->reg_idx)); - } else { + else rxq->rdt_reg_addr =3D (volatile u32 *)(rx_setup->reg_base_addr + SXE_RDT(rxq->reg_idx)); - } =20 rxq->base_addr =3D rx_mz->iova; =20 @@ -160,9 +156,8 @@ s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *rx= _setup, bool is_vf) } =20 len =3D desc_num; - if (*rx_setup->rx_batch_alloc_allowed) { + if (*rx_setup->rx_batch_alloc_allowed) len +=3D RTE_PMD_SXE_MAX_RX_BURST; - } =20 rxq->buffer_ring =3D rte_zmalloc_socket("rxq->sw_ring", sizeof(struct sxe_rx_buffer) * len, @@ -186,21 +181,21 @@ s32 __rte_cold __sxe_rx_queue_setup(struct rx_setup *= rx_setup, bool is_vf) } =20 PMD_LOG_DEBUG(INIT, "buffer_ring=3D%p sc_buffer_ring=3D%p desc_ring=3D%p " - "dma_addr=3D0x%"SXE_PRIX64, - rxq->buffer_ring, rxq->sc_buffer_ring, rxq->desc_ring, - rxq->base_addr); + "dma_addr=3D0x%"SXE_PRIX64, + rxq->buffer_ring, rxq->sc_buffer_ring, rxq->desc_ring, + rxq->base_addr); =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD if (!rte_is_power_of_2(desc_num)) { PMD_LOG_DEBUG(INIT, "queue[%d] doesn't meet Vector Rx " - "preconditions - canceling the feature for " - "the whole port[%d]", - rxq->queue_id, rxq->port_id); - if (is_vf) { + "preconditions - canceling the feature for " + "the whole port[%d]", + rxq->queue_id, rxq->port_id); + if (is_vf) vf_adapter->rx_vec_allowed =3D false; - } else { + else pf_adapter->rx_vec_allowed =3D false; - } + } else { sxe_rxq_vec_setup(rxq); } @@ -245,29 +240,29 @@ int __rte_cold __sxe_tx_queue_setup(struct tx_setup *= tx_setup, bool is_vf) goto l_end; } =20 - txq->ops =3D sxe_tx_default_ops_get(); - txq->ring_depth =3D ring_depth; - txq->queue_idx =3D tx_queue_id; - txq->port_id =3D dev->data->port_id; - txq->pthresh =3D tx_conf->tx_thresh.pthresh; - txq->hthresh =3D tx_conf->tx_thresh.hthresh; - txq->wthresh =3D tx_conf->tx_thresh.wthresh; - txq->rs_thresh =3D rs_thresh; - txq->free_thresh =3D free_thresh; + txq->ops =3D sxe_tx_default_ops_get(); + txq->ring_depth =3D ring_depth; + txq->queue_idx =3D tx_queue_id; + txq->port_id =3D dev->data->port_id; + txq->pthresh =3D tx_conf->tx_thresh.pthresh; + txq->hthresh =3D tx_conf->tx_thresh.hthresh; + txq->wthresh =3D tx_conf->tx_thresh.wthresh; + txq->rs_thresh =3D rs_thresh; + txq->free_thresh =3D free_thresh; txq->tx_deferred_start =3D tx_conf->tx_deferred_start; - txq->reg_idx =3D (u16)((RTE_ETH_DEV_SRIOV(dev).active =3D=3D 0)= ? + txq->reg_idx =3D (u16)((RTE_ETH_DEV_SRIOV(dev).active =3D=3D 0) ? tx_queue_id : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + tx_queue_id); - txq->offloads =3D tx_conf->offloads | dev->data->dev_conf.txmode= .offloads; + txq->offloads =3D tx_conf->offloads | dev->data->dev_conf.txmode.offlo= ads; =20 - if (is_vf) { - txq->tdt_reg_addr =3D (volatile u32 *)(tx_setup->reg_base_addr + SXE_VFT= DT(txq->reg_idx)); - } else { - txq->tdt_reg_addr =3D (u32 *)(tx_setup->reg_base_addr + SXE_TDT(txq->reg= _idx)); - } + if (is_vf) + txq->tdt_reg_addr =3D (volatile u32 *)(tx_setup->reg_base_addr + + SXE_VFTDT(txq->reg_idx)); + else + txq->tdt_reg_addr =3D (u32 *)(tx_setup->reg_base_addr + + SXE_TDT(txq->reg_idx)); =20 PMD_LOG_INFO(INIT, "buffer_ring=3D%p desc_ring=3D%p dma_addr=3D0x%"PRIx64, - txq->buffer_ring, txq->desc_ring, - (long unsigned int)txq->base_addr); + txq->buffer_ring, txq->desc_ring, (u64)txq->base_addr); sxe_tx_function_set(dev, txq); =20 txq->ops->init(txq); @@ -294,7 +289,6 @@ void __sxe_rx_queue_info_get(struct rte_eth_dev *dev, u= 16 queue_id, qinfo->conf.rx_deferred_start =3D rxq->deferred_start; qinfo->conf.offloads =3D rxq->offloads; =20 - return; } =20 void __sxe_tx_queue_info_get(struct rte_eth_dev *dev, u16 queue_id, @@ -313,23 +307,22 @@ void __sxe_tx_queue_info_get(struct rte_eth_dev *dev,= u16 queue_id, q_info->conf.offloads =3D txq->offloads; q_info->conf.tx_deferred_start =3D txq->tx_deferred_start; =20 - return; } =20 s32 __sxe_tx_done_cleanup(void *tx_queue, u32 free_cnt) { int ret; struct sxe_tx_queue *txq =3D (struct sxe_tx_queue *)tx_queue; - if (txq->offloads =3D=3D 0 && \ + if (txq->offloads =3D=3D 0 && txq->rs_thresh >=3D RTE_PMD_SXE_MAX_TX_BURST) { #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD if (txq->rs_thresh <=3D RTE_SXE_MAX_TX_FREE_BUF_SZ && #ifndef DPDK_19_11_6 - rte_vect_get_max_simd_bitwidth() >=3D RTE_VECT_SIMD_128 && + rte_vect_get_max_simd_bitwidth() >=3D RTE_VECT_SIMD_128 && #endif - (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || - txq->buffer_ring_vec !=3D NULL)) { - ret =3D sxe_tx_done_cleanup_vec(txq, free_cnt); + (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || + txq->buffer_ring_vec !=3D NULL)) { + ret =3D sxe_tx_done_cleanup_vec(txq, free_cnt); } else{ ret =3D sxe_tx_done_cleanup_simple(txq, free_cnt); } @@ -357,7 +350,7 @@ s32 __rte_cold __sxe_rx_queue_mbufs_alloc(struct sxe_rx= _queue *rxq) =20 if (mbuf =3D=3D NULL) { PMD_LOG_ERR(DRV, "rx mbuf alloc failed queue_id=3D%u", - (unsigned) rxq->queue_id); + (u16)rxq->queue_id); ret =3D -ENOMEM; goto l_end; } @@ -386,7 +379,6 @@ void __rte_cold __sxe_rx_queue_free(struct sxe_rx_queue= *rxq) rte_memzone_free(rxq->mz); rte_free(rxq); } - return; } =20 void __rte_cold __sxe_tx_queue_free(struct sxe_tx_queue *txq) @@ -398,7 +390,6 @@ void __rte_cold __sxe_tx_queue_free(struct sxe_tx_queue= *txq) rte_free(txq); } =20 - return; } =20 void __rte_cold __sxe_txrx_queues_clear(struct rte_eth_dev *dev, bool rx_b= atch_alloc_allowed) @@ -409,12 +400,11 @@ void __rte_cold __sxe_txrx_queues_clear(struct rte_et= h_dev *dev, bool rx_batch_a =20 sxe_rx_queues_clear(dev, rx_batch_alloc_allowed); =20 - return; } =20 void __sxe_queues_free(struct rte_eth_dev *dev) { - unsigned i; + unsigned int i; =20 PMD_INIT_FUNC_TRACE(); =20 @@ -430,10 +420,10 @@ void __sxe_queues_free(struct rte_eth_dev *dev) } dev->data->nb_tx_queues =3D 0; =20 - return; } =20 -void __sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, bool rx_batch_= alloc_allowed, bool *rx_vec_allowed) +void __sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, + bool rx_batch_alloc_allowed, bool *rx_vec_allowed) { struct sxe_tx_queue *txq; if (eth_dev->data->tx_queues) { @@ -441,10 +431,9 @@ void __sxe_secondary_proc_init(struct rte_eth_dev *eth= _dev, bool rx_batch_alloc_ sxe_tx_function_set(eth_dev, txq); } else { PMD_LOG_NOTICE(INIT, "No TX queues configured yet. " - "Using default TX function."); + "Using default TX function."); } =20 sxe_rx_function_set(eth_dev, rx_batch_alloc_allowed, rx_vec_allowed); - return; } =20 diff --git a/drivers/net/sxe/base/sxe_queue_common.h b/drivers/net/sxe/base= /sxe_queue_common.h index a38113b643..40867449db 100644 --- a/drivers/net/sxe/base/sxe_queue_common.h +++ b/drivers/net/sxe/base/sxe_queue_common.h @@ -15,9 +15,9 @@ #define RTE_PMD_SXE_MAX_RX_BURST 32 =20 enum sxe_ctxt_num { - SXE_CTXT_DESC_0 =3D 0,=20 - SXE_CTXT_DESC_1 =3D 1,=20 - SXE_CTXT_DESC_NUM =3D 2,=20 + SXE_CTXT_DESC_0 =3D 0, + SXE_CTXT_DESC_1 =3D 1, + SXE_CTXT_DESC_NUM =3D 2, }; =20 struct rx_setup { @@ -42,7 +42,7 @@ struct tx_setup { =20 union sxe_tx_data_desc { struct { - __le64 buffer_addr;=20 + __le64 buffer_addr; __le32 cmd_type_len; __le32 olinfo_status; } read; @@ -63,142 +63,142 @@ struct sxe_rx_queue_stats { =20 union sxe_rx_data_desc { struct { - __le64 pkt_addr;=20 - __le64 hdr_addr;=20 + __le64 pkt_addr; + __le64 hdr_addr; } read; struct { struct { union { __le32 data; struct { - __le16 pkt_info;=20 - __le16 hdr_info;=20 + __le16 pkt_info; + __le16 hdr_info; } hs_rss; } lo_dword; union { - __le32 rss;=20 + __le32 rss; struct { - __le16 ip_id;=20 - __le16 csum;=20 + __le16 ip_id; + __le16 csum; } csum_ip; } hi_dword; } lower; struct { - __le32 status_error;=20 - __le16 length;=20 - __le16 vlan;=20 + __le32 status_error; + __le16 length; + __le16 vlan; } upper; } wb; - }; +}; =20 struct sxe_tx_buffer { - struct rte_mbuf *mbuf;=20 - u16 next_id;=20=20=20=20=20=20=20=20=20=20=20=20=20 - u16 last_id;=20=20=20=20=20=20=20=20=20=20=20=20=20 + struct rte_mbuf *mbuf; + u16 next_id; + u16 last_id; }; =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD struct sxe_tx_buffer_vec { - struct rte_mbuf *mbuf;=20 + struct rte_mbuf *mbuf; }; #endif =20 union sxe_tx_offload { u64 data[2]; struct { - u64 l2_len:7;=20=20=20=20=20 - u64 l3_len:9;=20=20=20=20=20 - u64 l4_len:8;=20=20=20=20=20 - u64 tso_segsz:16;=20 - u64 vlan_tci:16;=20=20 - - u64 outer_l3_len:8;=20 - u64 outer_l2_len:8;=20 + u64 l2_len:7; + u64 l3_len:9; + u64 l4_len:8; + u64 tso_segsz:16; + u64 vlan_tci:16; + + u64 outer_l3_len:8; + u64 outer_l2_len:8; }; }; =20 struct sxe_ctxt_info { - u64 flags;=20=20 + u64 flags; union sxe_tx_offload tx_offload; union sxe_tx_offload tx_offload_mask; }; =20 struct sxe_tx_queue { volatile union sxe_tx_data_desc *desc_ring; - u64 base_addr;=20=20=20=20=20=20=20=20=20=20 + u64 base_addr; #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD union { - struct sxe_tx_buffer *buffer_ring;=20=20=20=20=20=20=20=20=20=20 - struct sxe_tx_buffer_vec *buffer_ring_vec;=20=20 + struct sxe_tx_buffer *buffer_ring; + struct sxe_tx_buffer_vec *buffer_ring_vec; }; #else - struct sxe_tx_buffer *buffer_ring;=09 + struct sxe_tx_buffer *buffer_ring; #endif - volatile u32 *tdt_reg_addr;=20=20=20=20=20=20=20 - u16 ring_depth;=20=20=20=20=20=20=20=20=20=20 - u16 next_to_use;=20=20=20=20=20=20=20=20=20 - u16 free_thresh;=20=20=20=20=20=20=20=20=20 - - u16 rs_thresh; - - u16 desc_used_num; - u16 next_to_clean;=20=20 - u16 desc_free_num;=20=20=20 - u16 next_dd;=20=20=20=20=20=20=20=20 - u16 next_rs;=20=20=20=20=20=20=20=20 - u16 queue_idx;=20=20=20=20=20=20 - u16 reg_idx;=20=20=20=20=20=20=20=20 - u16 port_id;=20=20=20=20=20=20=20=20 - u8 pthresh;=20=20=20=20=20=20=20=20 - u8 hthresh;=20=20=20=20=20=20=20=20 - - u8 wthresh; - u64 offloads;=20=20=20=20=20=20=20 - u32 ctx_curr;=20=20=20=20=20=20=20 - struct sxe_ctxt_info ctx_cache[SXE_CTXT_DESC_NUM];=20 - const struct sxe_txq_ops *ops;=20 - u8 tx_deferred_start;=20=20=20=20=20=20 + volatile u32 *tdt_reg_addr; + u16 ring_depth; + u16 next_to_use; + u16 free_thresh; + + u16 rs_thresh; + + u16 desc_used_num; + u16 next_to_clean; + u16 desc_free_num; + u16 next_dd; + u16 next_rs; + u16 queue_idx; + u16 reg_idx; + u16 port_id; + u8 pthresh; + u8 hthresh; + + u8 wthresh; + u64 offloads; + u32 ctx_curr; + struct sxe_ctxt_info ctx_cache[SXE_CTXT_DESC_NUM]; + const struct sxe_txq_ops *ops; + u8 tx_deferred_start; const struct rte_memzone *mz; }; =20 struct sxe_rx_queue { - struct rte_mempool *mb_pool;=20=20=20 - volatile union sxe_rx_data_desc *desc_ring;=20 - u64 base_addr;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - volatile u32 *rdt_reg_addr;=20=20=20 - struct sxe_rx_buffer *buffer_ring;=20 - struct sxe_rx_buffer *sc_buffer_ring;=20 + struct rte_mempool *mb_pool; + volatile union sxe_rx_data_desc *desc_ring; + u64 base_addr; + volatile u32 *rdt_reg_addr; + struct sxe_rx_buffer *buffer_ring; + struct sxe_rx_buffer *sc_buffer_ring; #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD - struct rte_mbuf *pkt_first_seg;=20 - struct rte_mbuf *pkt_last_seg;=20=20 - u64 mbuf_init_value;=09=09 - u8 is_using_sse;=09=09 + struct rte_mbuf *pkt_first_seg; + struct rte_mbuf *pkt_last_seg; + u64 mbuf_init_value; + u8 is_using_sse; #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM) - u16 realloc_num;=20=09=09 - u16 realloc_start;=09=09 + u16 realloc_num; + u16 realloc_start; #endif #endif - u16 ring_depth;=20=20=20=20=20=20=20=20=20=20=20 - u16 processing_idx;=20=20=20=20=20 - u16 hold_num;=20=20=20=20=20=20=20=20=20=20=20=20 - u16 completed_pkts_num;=20=20=20=20=20 - u16 next_ret_pkg;=20=20=20=20=20=20=20=20=20 - u16 batch_alloc_trigger;=20=20 - - u16 batch_alloc_size; - u16 queue_id;=20=20=20=20=20=20=20=20=20=20=20=20 - u16 reg_idx;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u16 pkt_type_mask;=20=20=20=20=20=20=20=20 - u16 port_id;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u8 crc_len;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u8 drop_en;=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u8 deferred_start;=20=20=20=20=20=20=20 - u64 vlan_flags;=20=20=20=20=20=20=20=20=20=20=20 - u64 offloads;=20=20=20=20=20=20=20=20=20=20=20=20=20 - struct rte_mbuf fake_mbuf;=20=20=20 + u16 ring_depth; + u16 processing_idx; + u16 hold_num; + u16 completed_pkts_num; + u16 next_ret_pkg; + u16 batch_alloc_trigger; + + u16 batch_alloc_size; + u16 queue_id; + u16 reg_idx; + u16 pkt_type_mask; + u16 port_id; + u8 crc_len; + u8 drop_en; + u8 deferred_start; + u64 vlan_flags; + u64 offloads; + struct rte_mbuf fake_mbuf; struct rte_mbuf *completed_ring[RTE_PMD_SXE_MAX_RX_BURST * 2]; const struct rte_memzone *mz; - struct sxe_rx_queue_stats rx_stats;=20=20 + struct sxe_rx_queue_stats rx_stats; }; =20 struct sxe_txq_ops { @@ -231,6 +231,7 @@ void __rte_cold __sxe_txrx_queues_clear(struct rte_eth_= dev *dev, bool rx_batch_a =20 void __sxe_queues_free(struct rte_eth_dev *dev); =20 -void __sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, bool rx_batch_= alloc_allowed, bool *rx_vec_allowed); +void __sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, + bool rx_batch_alloc_allowed, bool *rx_vec_allowed); =20 #endif diff --git a/drivers/net/sxe/base/sxe_rx_common.c b/drivers/net/sxe/base/sx= e_rx_common.c index 4472058a29..b6ca690ec8 100644 --- a/drivers/net/sxe/base/sxe_rx_common.c +++ b/drivers/net/sxe/base/sxe_rx_common.c @@ -39,23 +39,23 @@ static inline void sxe_rx_resource_prefetch(u16 next_id= x, rte_sxe_prefetch(&buf_ring[next_idx]); } =20 - return; } =20 -void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev, bool rx_bat= ch_alloc_allowed, bool *rx_vec_allowed) +void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev, + bool rx_batch_alloc_allowed, bool *rx_vec_allowed) { =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD u16 i, is_using_sse; =20 if (sxe_rx_vec_condition_check(dev) || - !rx_batch_alloc_allowed=20 + !rx_batch_alloc_allowed #ifndef DPDK_19_11_6 || rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128 #endif ) { PMD_LOG_DEBUG(INIT, "Port[%d] doesn't meet Vector Rx " - "preconditions", dev->data->port_id); + "preconditions", dev->data->port_id); *rx_vec_allowed =3D false; } #else @@ -76,24 +76,31 @@ void __rte_cold __sxe_rx_function_set(struct rte_eth_de= v *dev, bool rx_batch_all #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD if (*rx_vec_allowed) { PMD_LOG_DEBUG(INIT, "Using Vector Scattered Rx " - "callback (port=3D%d).", - dev->data->port_id); + "callback (port=3D%d).", + dev->data->port_id); =20 dev->rx_pkt_burst =3D sxe_scattered_pkts_vec_recv; - } else + #endif + +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD + + } else if (rx_batch_alloc_allowed) { +#else if (rx_batch_alloc_allowed) { +#endif + PMD_LOG_DEBUG(INIT, "Using a Scattered with bulk " "allocation callback (port=3D%d).", - dev->data->port_id); + dev->data->port_id); =20 dev->rx_pkt_burst =3D sxe_batch_alloc_lro_pkts_recv; } else { PMD_LOG_DEBUG(INIT, "Using Regular (non-vector, " - "single allocation) " - "Scattered Rx callback " - "(port=3D%d).", - dev->data->port_id); + "single allocation) " + "Scattered Rx callback " + "(port=3D%d).", + dev->data->port_id); =20 dev->rx_pkt_burst =3D sxe_single_alloc_lro_pkts_recv; } @@ -101,17 +108,17 @@ void __rte_cold __sxe_rx_function_set(struct rte_eth_= dev *dev, bool rx_batch_all #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD else if (*rx_vec_allowed) { PMD_LOG_DEBUG(INIT, "Vector rx enabled, please make sure RX " - "burst size no less than %d (port=3D%d).", - SXE_DESCS_PER_LOOP, - dev->data->port_id); + "burst size no less than %d (port=3D%d).", + SXE_DESCS_PER_LOOP, + dev->data->port_id); =20 dev->rx_pkt_burst =3D sxe_pkts_vec_recv; } #endif else if (rx_batch_alloc_allowed) { PMD_LOG_DEBUG(INIT, "Rx Burst Bulk Alloc Preconditions are " - "satisfied. Rx Burst Bulk Alloc function " - "will be used on port=3D%d.", + "satisfied. Rx Burst Bulk Alloc function " + "will be used on port=3D%d.", dev->data->port_id); =20 dev->rx_pkt_burst =3D sxe_batch_alloc_pkts_recv; @@ -136,7 +143,6 @@ void __rte_cold __sxe_rx_function_set(struct rte_eth_de= v *dev, bool rx_batch_all } #endif =20 - return; } =20 #if defined DPDK_20_11_5 || defined DPDK_19_11_6 @@ -156,9 +162,8 @@ s32 __sxe_rx_descriptor_done(void *rx_queue, u16 offset) } =20 index =3D rxq->processing_idx + offset; - if (index >=3D rxq->ring_depth) { + if (index >=3D rxq->ring_depth) index -=3D rxq->ring_depth; - } =20 desc =3D &rxq->desc_ring[index]; is_done =3D !!(desc->wb.upper.status_error & @@ -198,17 +203,15 @@ s32 __sxe_rx_descriptor_status(void *rx_queue, u16 of= fset) } =20 desc =3D rxq->processing_idx + offset; - if (desc >=3D rxq->ring_depth) { + if (desc >=3D rxq->ring_depth) desc -=3D rxq->ring_depth; - } =20 status =3D &rxq->desc_ring[desc].wb.upper.status_error; - if (*status & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD)) { + if (*status & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD)) ret =3D RTE_ETH_RX_DESC_DONE; - } =20 l_end: - LOG_DEBUG("rx queue[%u] get desc status=3D%d\n",rxq->queue_id, ret); + LOG_DEBUG("rx queue[%u] get desc status=3D%d\n", rxq->queue_id, ret); return ret; } =20 @@ -234,23 +237,22 @@ u16 __sxe_pkts_recv(void *rx_queue, struct rte_mbuf *= *rx_pkts, while (done_num < pkts_num) { cur_desc =3D &desc_ring[processing_idx]; staterr =3D cur_desc->wb.upper.status_error; - if (!(staterr & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD))) { + if (!(staterr & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD))) break; - } =20 rxd =3D *cur_desc; =20 LOG_DEBUG("port_id=3D%u queue_id=3D%u processing_idx=3D%u " "staterr=3D0x%08x pkt_len=3D%u", - (unsigned) rxq->port_id, (unsigned) rxq->queue_id, - (unsigned) processing_idx, (unsigned) staterr, - (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length)); + (unsigned int)rxq->port_id, (unsigned int) rxq->queue_id, + (unsigned int)processing_idx, (unsigned int) staterr, + (unsigned int)rte_le_to_cpu_16(rxd.wb.upper.length)); =20 new_mb =3D rte_mbuf_raw_alloc(rxq->mb_pool); if (new_mb =3D=3D NULL) { LOG_ERROR("RX mbuf alloc failed port_id=3D%u " - "queue_id=3D%u", (unsigned) rxq->port_id, - (unsigned) rxq->queue_id); + "queue_id=3D%u", (unsigned int) rxq->port_id, + (unsigned int) rxq->queue_id); rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++; break; } @@ -258,9 +260,8 @@ u16 __sxe_pkts_recv(void *rx_queue, struct rte_mbuf **r= x_pkts, hold_num++; cur_buf =3D &buff_ring[processing_idx]; processing_idx++; - if (processing_idx =3D=3D rxq->ring_depth) { + if (processing_idx =3D=3D rxq->ring_depth) processing_idx =3D 0; - } =20 sxe_rx_resource_prefetch(processing_idx, buff_ring, desc_ring); =20 @@ -293,9 +294,9 @@ u16 __sxe_pkts_recv(void *rx_queue, struct rte_mbuf **r= x_pkts, if (hold_num > rxq->batch_alloc_size) { LOG_DEBUG("port_id=3D%u queue_id=3D%u rx_tail=3D%u " "num_hold=3D%u num_done=3D%u", - (unsigned) rxq->port_id, (unsigned) rxq->queue_id, - (unsigned) processing_idx, (unsigned) hold_num, - (unsigned) done_num); + (unsigned int)rxq->port_id, (unsigned int)rxq->queue_id, + (unsigned int)processing_idx, (unsigned int)hold_num, + (unsigned int)done_num); processing_idx =3D (u16)((processing_idx =3D=3D 0) ? (rxq->ring_depth - 1) : (processing_idx - 1)); SXE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, processing_idx); @@ -308,7 +309,7 @@ u16 __sxe_pkts_recv(void *rx_queue, struct rte_mbuf **r= x_pkts, =20 const u32 *__sxe_dev_supported_ptypes_get(struct rte_eth_dev *dev) { - const u32 * ptypes =3D NULL; + const u32 *ptypes =3D NULL; static const u32 ptypes_arr[] =3D { RTE_PTYPE_L2_ETHER, RTE_PTYPE_L3_IPV4, @@ -337,7 +338,7 @@ const u32 *__sxe_dev_supported_ptypes_get(struct rte_et= h_dev *dev) #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD #if defined(RTE_ARCH_X86) if (dev->rx_pkt_burst =3D=3D sxe_pkts_vec_recv || - dev->rx_pkt_burst =3D=3D sxe_scattered_pkts_vec_recv) { + dev->rx_pkt_burst =3D=3D sxe_scattered_pkts_vec_recv) { ptypes =3D ptypes_arr; } #endif diff --git a/drivers/net/sxe/base/sxe_rx_common.h b/drivers/net/sxe/base/sx= e_rx_common.h index b7eb37f54a..93d2314968 100644 --- a/drivers/net/sxe/base/sxe_rx_common.h +++ b/drivers/net/sxe/base/sxe_rx_common.h @@ -7,7 +7,8 @@ =20 #include "sxe_dpdk_version.h" =20 -void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev, bool rx_bat= ch_alloc_allowed, bool *rx_vec_allowed); +void __rte_cold __sxe_rx_function_set(struct rte_eth_dev *dev, + bool rx_batch_alloc_allowed, bool *rx_vec_allowed); =20 #if defined DPDK_20_11_5 || defined DPDK_19_11_6 s32 __sxe_rx_descriptor_done(void *rx_queue, u16 offset); diff --git a/drivers/net/sxe/base/sxe_tx_common.c b/drivers/net/sxe/base/sx= e_tx_common.c index a47f90109a..e74556866f 100644 --- a/drivers/net/sxe/base/sxe_tx_common.c +++ b/drivers/net/sxe/base/sxe_tx_common.c @@ -33,15 +33,13 @@ int __sxe_tx_descriptor_status(void *tx_queue, u16 offs= et) desc_idx =3D ((desc_idx + txq->rs_thresh - 1) / txq->rs_thresh) * txq->rs= _thresh; if (desc_idx >=3D txq->ring_depth) { desc_idx -=3D txq->ring_depth; - if (desc_idx >=3D txq->ring_depth) { + if (desc_idx >=3D txq->ring_depth) desc_idx -=3D txq->ring_depth; - } } =20 status =3D &txq->desc_ring[desc_idx].wb.status; - if (*status & rte_cpu_to_le_32(SXE_TX_DESC_STAT_DD)) { + if (*status & rte_cpu_to_le_32(SXE_TX_DESC_STAT_DD)) ret =3D RTE_ETH_TX_DESC_DONE; - } =20 l_end: return ret; diff --git a/drivers/net/sxe/base/sxe_types.h b/drivers/net/sxe/base/sxe_ty= pes.h index 966ee230b3..a36a3cfbf6 100644 --- a/drivers/net/sxe/base/sxe_types.h +++ b/drivers/net/sxe/base/sxe_types.h @@ -18,7 +18,7 @@ typedef uint8_t u8; typedef uint16_t u16; typedef uint32_t u32; -typedef uint64_t u64;=20 +typedef uint64_t u64; =20 typedef char s8; typedef int16_t s16; diff --git a/drivers/net/sxe/base/sxevf_hw.c b/drivers/net/sxe/base/sxevf_h= w.c index 75ac9dd25b..5786e28f92 100644 --- a/drivers/net/sxe/base/sxevf_hw.c +++ b/drivers/net/sxe/base/sxevf_hw.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright (C), 2022, Linkdata Technology Co., Ltd. */ -#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST)=20 +#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST) #include =20 #include "sxevf_hw.h" @@ -12,7 +12,7 @@ #include "sxevf_ring.h" #include "sxevf.h" #include "sxevf_rx_proc.h" -#else=20 +#else #include "sxe_errno.h" #include "sxe_logs.h" #include "sxe_dpdk_version.h" @@ -28,37 +28,33 @@ struct sxevf_adapter; #define DMA_BIT_MASK(n) (((n) =3D=3D 64) ? ~0ULL : ((1ULL<<(n))-1)) #define DMA_MASK_NONE 0x0ULL =20 -#define SXEVF_REG_READ_CNT 5 +#define SXEVF_REG_READ_CNT 5 =20 -#define SXE_REG_READ_FAIL 0xffffffffU +#define SXE_REG_READ_FAIL 0xffffffffU =20 -#define SXEVF_RING_WAIT_LOOP (100) -#define SXEVF_MAX_RX_DESC_POLL (10) +#define SXEVF_RING_WAIT_LOOP (100) +#define SXEVF_MAX_RX_DESC_POLL (10) =20 =20 -#define SXEVF_REG_READ(hw, addr) sxevf_reg_read(hw, addr) +#define SXEVF_REG_READ(hw, addr) sxevf_reg_read(hw, addr) #define SXEVF_REG_WRITE(hw, reg, value) sxevf_reg_write(hw, reg, value) #define SXEVF_WRITE_FLUSH(a) sxevf_reg_read(a, SXE_VFSTATUS) =20 -#ifndef SXE_DPDK=20 +#ifndef SXE_DPDK void sxevf_hw_fault_handle(struct sxevf_hw *hw) { struct sxevf_adapter *adapter =3D hw->adapter; =20 - if (test_bit(SXEVF_HW_FAULT, &hw->state)) { - goto l_ret; - } + if (test_bit(SXEVF_HW_FAULT, &hw->state)) + return; =20 set_bit(SXEVF_HW_FAULT, &hw->state); =20 LOG_DEV_ERR("sxe nic hw fault\n"); =20 - if ((hw->fault_handle !=3D NULL) && (hw->priv !=3D NULL) ) { + if ((hw->fault_handle !=3D NULL) && (hw->priv !=3D NULL)) hw->fault_handle(hw->priv); - } =20 -l_ret: - return; } =20 static void sxevf_hw_fault_check(struct sxevf_hw *hw, u32 reg) @@ -68,32 +64,27 @@ static void sxevf_hw_fault_check(struct sxevf_hw *hw, u= 32 reg) struct sxevf_adapter *adapter =3D hw->adapter; u8 i; =20 - if (reg =3D=3D SXE_VFSTATUS) { + if (reg =3D=3D SXE_VFSTATUS) sxevf_hw_fault_handle(hw); - return; - } =20 =20 for (i =3D 0; i < SXEVF_REG_READ_CNT; i++) { value =3D hw->reg_read(base_addr + SXE_VFSTATUS); =20 - if (value !=3D SXEVF_REG_READ_FAIL) { + if (value !=3D SXEVF_REG_READ_FAIL) break; - } =20 mdelay(20); } =20 LOG_INFO_BDF("retry done i:%d value:0x%x\n", i, value); =20 - if (value =3D=3D SXEVF_REG_READ_FAIL) { + if (value =3D=3D SXEVF_REG_READ_FAIL) sxevf_hw_fault_handle(hw); - } =20 - return; } =20 -STATIC u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg) +static u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg) { u32 value; u8 __iomem *base_addr =3D hw->reg_base_addr; @@ -105,7 +96,7 @@ STATIC u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg) } =20 value =3D hw->reg_read(base_addr + reg); - if (unlikely(SXEVF_REG_READ_FAIL =3D=3D value)) { + if (unlikely(value =3D=3D SXEVF_REG_READ_FAIL)) { LOG_ERROR_BDF("reg[0x%x] read failed, value=3D%#x\n", reg, value); sxevf_hw_fault_check(hw, reg); } @@ -114,29 +105,26 @@ STATIC u32 sxevf_reg_read(struct sxevf_hw *hw, u32 re= g) return value; } =20 -STATIC void sxevf_reg_write(struct sxevf_hw *hw, u32 reg, u32 value) +static void sxevf_reg_write(struct sxevf_hw *hw, u32 reg, u32 value) { u8 __iomem *base_addr =3D hw->reg_base_addr; =20 - if (sxevf_is_hw_fault(hw)) { - goto l_ret; - } + if (sxevf_is_hw_fault(hw)) + return; =20 hw->reg_write(value, base_addr + reg); =20 -l_ret: - return; } =20 -#else=20 +#else =20 -STATIC u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg) +static u32 sxevf_reg_read(struct sxevf_hw *hw, u32 reg) { u32 i, value; u8 __iomem *base_addr =3D hw->reg_base_addr; =20 value =3D rte_le_to_cpu_32(rte_read32(base_addr + reg)); - if (unlikely(SXEVF_REG_READ_FAIL =3D=3D value)) { + if (unlikely(value =3D=3D SXEVF_REG_READ_FAIL)) { for (i =3D 0; i < SXEVF_REG_READ_CNT; i++) { LOG_ERROR("reg[0x%x] read failed, value=3D%#x\n", reg, value); @@ -154,13 +142,12 @@ STATIC u32 sxevf_reg_read(struct sxevf_hw *hw, u32 re= g) return value; } =20 -STATIC void sxevf_reg_write(struct sxevf_hw *hw, u32 reg, u32 value) +static void sxevf_reg_write(struct sxevf_hw *hw, u32 reg, u32 value) { u8 __iomem *base_addr =3D hw->reg_base_addr; =20 rte_write32((rte_cpu_to_le_32(value)), (base_addr + reg)); =20 - return; } #endif =20 @@ -190,7 +177,6 @@ void sxevf_hw_stop(struct sxevf_hw *hw) } } =20 - return; } =20 void sxevf_msg_write(struct sxevf_hw *hw, u8 index, u32 msg) @@ -201,7 +187,6 @@ void sxevf_msg_write(struct sxevf_hw *hw, u8 index, u32= msg) =20 LOG_DEBUG_BDF("index:%u write mbx mem:0x%x.\n", index, msg); =20 - return; } =20 u32 sxevf_msg_read(struct sxevf_hw *hw, u8 index) @@ -222,21 +207,18 @@ u32 sxevf_mailbox_read(struct sxevf_hw *hw) void sxevf_mailbox_write(struct sxevf_hw *hw, u32 value) { SXEVF_REG_WRITE(hw, SXE_VFMAILBOX, value); - return; } =20 void sxevf_pf_req_irq_trigger(struct sxevf_hw *hw) { SXEVF_REG_WRITE(hw, SXE_VFMAILBOX, SXE_VFMAILBOX_REQ); =20 - return; } =20 void sxevf_pf_ack_irq_trigger(struct sxevf_hw *hw) { SXEVF_REG_WRITE(hw, SXE_VFMAILBOX, SXE_VFMAILBOX_ACK); =20 - return; } =20 void sxevf_event_irq_map(struct sxevf_hw *hw, u16 vector) @@ -252,14 +234,12 @@ void sxevf_event_irq_map(struct sxevf_hw *hw, u16 vec= tor) =20 SXEVF_REG_WRITE(hw, SXE_VFIVAR_MISC, ivar); =20 - return; } =20 void sxevf_specific_irq_enable(struct sxevf_hw *hw, u32 value) { SXEVF_REG_WRITE(hw, SXE_VFEIMS, value); =20 - return; } =20 void sxevf_irq_enable(struct sxevf_hw *hw, u32 mask) @@ -267,7 +247,6 @@ void sxevf_irq_enable(struct sxevf_hw *hw, u32 mask) SXEVF_REG_WRITE(hw, SXE_VFEIAM, mask); SXEVF_REG_WRITE(hw, SXE_VFEIMS, mask); =20 - return; } =20 void sxevf_irq_disable(struct sxevf_hw *hw) @@ -277,7 +256,6 @@ void sxevf_irq_disable(struct sxevf_hw *hw) =20 SXEVF_WRITE_FLUSH(hw); =20 - return; } =20 void sxevf_hw_ring_irq_map(struct sxevf_hw *hw, bool is_tx, u16 hw_ring_id= x, u16 vector) @@ -295,7 +273,6 @@ void sxevf_hw_ring_irq_map(struct sxevf_hw *hw, bool is= _tx, u16 hw_ring_idx, u16 =20 SXEVF_REG_WRITE(hw, SXE_VFIVAR(hw_ring_idx >> 1), ivar); =20 - return; } =20 void sxevf_ring_irq_interval_set(struct sxevf_hw *hw, u16 irq_idx, u32 int= erval) @@ -306,40 +283,36 @@ void sxevf_ring_irq_interval_set(struct sxevf_hw *hw,= u16 irq_idx, u32 interval) =20 SXEVF_REG_WRITE(hw, SXE_VFEITR(irq_idx), eitr); =20 - return; } =20 static void sxevf_event_irq_interval_set(struct sxevf_hw *hw, u16 irq_idx,= u32 value) { SXEVF_REG_WRITE(hw, SXE_VFEITR(irq_idx), value); =20 - return; } =20 static void sxevf_pending_irq_clear(struct sxevf_hw *hw) { SXEVF_REG_READ(hw, SXE_VFEICR); =20 - return; } =20 static void sxevf_ring_irq_trigger(struct sxevf_hw *hw, u64 eics) { SXEVF_REG_WRITE(hw, SXE_VFEICS, eics); =20 - return; } =20 static const struct sxevf_irq_operations sxevf_irq_ops =3D { .ring_irq_interval_set =3D sxevf_ring_irq_interval_set, .event_irq_interval_set =3D sxevf_event_irq_interval_set, - .ring_irq_map =3D sxevf_hw_ring_irq_map, - .event_irq_map =3D sxevf_event_irq_map, - .pending_irq_clear =3D sxevf_pending_irq_clear, - .ring_irq_trigger =3D sxevf_ring_irq_trigger, - .specific_irq_enable =3D sxevf_specific_irq_enable, - .irq_enable =3D sxevf_irq_enable, - .irq_disable =3D sxevf_irq_disable, + .ring_irq_map =3D sxevf_hw_ring_irq_map, + .event_irq_map =3D sxevf_event_irq_map, + .pending_irq_clear =3D sxevf_pending_irq_clear, + .ring_irq_trigger =3D sxevf_ring_irq_trigger, + .specific_irq_enable =3D sxevf_specific_irq_enable, + .irq_enable =3D sxevf_irq_enable, + .irq_disable =3D sxevf_irq_disable, }; =20 void sxevf_hw_reset(struct sxevf_hw *hw) @@ -347,10 +320,9 @@ void sxevf_hw_reset(struct sxevf_hw *hw) SXEVF_REG_WRITE(hw, SXE_VFCTRL, SXE_VFCTRL_RST); SXEVF_WRITE_FLUSH(hw); =20 - return; } =20 -STATIC bool sxevf_hw_rst_done(struct sxevf_hw *hw) +static bool sxevf_hw_rst_done(struct sxevf_hw *hw) { return !(SXEVF_REG_READ(hw, SXE_VFCTRL) & SXE_VFCTRL_RST); } @@ -374,9 +346,8 @@ static u32 sxevf_reg_dump(struct sxevf_hw *hw, u32 *reg= s_buff, u32 buf_size) u32 i; u32 regs_num =3D buf_size / sizeof(u32); =20 - for (i =3D 0; i < regs_num; i++) { + for (i =3D 0; i < regs_num; i++) regs_buff[i] =3D SXEVF_REG_READ(hw, dump_regs[i]); - } =20 return i; } @@ -476,7 +447,7 @@ static s32 sxevf_reg_set_and_check(struct sxevf_hw *hw,= int reg, return ret; } =20 -STATIC s32 sxevf_regs_test(struct sxevf_hw *hw) +static s32 sxevf_regs_test(struct sxevf_hw *hw) { u32 i; s32 ret =3D 0; @@ -521,9 +492,8 @@ STATIC s32 sxevf_regs_test(struct sxevf_hw *hw) break; } =20 - if (ret) { + if (ret) goto l_end; - } =20 } test++; @@ -545,14 +515,13 @@ static const struct sxevf_setup_operations sxevf_setu= p_ops =3D { static void sxevf_tx_ring_desc_configure(struct sxevf_hw *hw, u32 desc_mem= _len, u64 desc_dma_addr, u8 reg_idx) { - SXEVF_REG_WRITE(hw, SXEVF_TDBAL(reg_idx), (desc_dma_addr & \ + SXEVF_REG_WRITE(hw, SXEVF_TDBAL(reg_idx), (desc_dma_addr & DMA_BIT_MASK(32))); SXEVF_REG_WRITE(hw, SXEVF_TDBAH(reg_idx), (desc_dma_addr >> 32)); SXEVF_REG_WRITE(hw, SXEVF_TDLEN(reg_idx), desc_mem_len); SXEVF_REG_WRITE(hw, SXEVF_TDH(reg_idx), 0); SXEVF_REG_WRITE(hw, SXEVF_TDT(reg_idx), 0); =20 - return; } =20 static void sxevf_tx_writeback_off(struct sxevf_hw *hw, u8 reg_idx) @@ -560,7 +529,6 @@ static void sxevf_tx_writeback_off(struct sxevf_hw *hw,= u8 reg_idx) SXEVF_REG_WRITE(hw, SXEVF_TDWBAH(reg_idx), 0); SXEVF_REG_WRITE(hw, SXEVF_TDWBAL(reg_idx), 0); =20 - return; } =20 static void sxevf_tx_desc_thresh_set( @@ -578,7 +546,6 @@ static void sxevf_tx_desc_thresh_set( =20 SXEVF_REG_WRITE(hw, SXEVF_TXDCTL(reg_idx), txdctl); =20 - return; } =20 void sxevf_tx_ring_switch(struct sxevf_hw *hw, u8 reg_idx, bool is_on) @@ -610,7 +577,6 @@ void sxevf_tx_ring_switch(struct sxevf_hw *hw, u8 reg_i= dx, bool is_on) "the polling period\n", reg_idx, is_on); } =20 - return; } =20 static void sxevf_rx_disable(struct sxevf_hw *hw, u8 reg_idx) @@ -619,9 +585,8 @@ static void sxevf_rx_disable(struct sxevf_hw *hw, u8 re= g_idx) u32 wait_loop =3D SXEVF_RX_RING_POLL_MAX; struct sxevf_adapter *adapter =3D hw->adapter; =20 - if (!hw->reg_base_addr) { - goto l_end; - } + if (!hw->reg_base_addr) + return; =20 rxdctl =3D SXEVF_REG_READ(hw, SXE_VFRXDCTL(reg_idx)); rxdctl &=3D ~SXE_VFRXDCTL_ENABLE; @@ -637,8 +602,6 @@ static void sxevf_rx_disable(struct sxevf_hw *hw, u8 re= g_idx) reg_idx); } =20 -l_end: - return; } =20 void sxevf_rx_ring_switch(struct sxevf_hw *hw, u8 reg_idx, bool is_on) @@ -673,7 +636,6 @@ void sxevf_rx_ring_switch(struct sxevf_hw *hw, u8 reg_i= dx, bool is_on) "the polling period\n", reg_idx, is_on); } =20 - return; } =20 void sxevf_rx_ring_desc_configure(struct sxevf_hw *hw, u32 desc_mem_len, @@ -689,7 +651,6 @@ void sxevf_rx_ring_desc_configure(struct sxevf_hw *hw, = u32 desc_mem_len, SXEVF_REG_WRITE(hw, SXE_VFRDH(reg_idx), 0); SXEVF_REG_WRITE(hw, SXE_VFRDT(reg_idx), 0); =20 - return; } =20 void sxevf_rx_rcv_ctl_configure(struct sxevf_hw *hw, u8 reg_idx, @@ -697,9 +658,8 @@ void sxevf_rx_rcv_ctl_configure(struct sxevf_hw *hw, u8= reg_idx, { u32 srrctl =3D 0; =20 - if (drop_en) { + if (drop_en) srrctl =3D SXEVF_SRRCTL_DROP_EN; - } =20 srrctl |=3D ((header_buf_len << SXEVF_SRRCTL_BSIZEHDRSIZE_SHIFT) & SXEVF_SRRCTL_BSIZEHDR_MASK); @@ -708,7 +668,6 @@ void sxevf_rx_rcv_ctl_configure(struct sxevf_hw *hw, u8= reg_idx, =20 SXEVF_REG_WRITE(hw, SXE_VFSRRCTL(reg_idx), srrctl); =20 - return; } =20 static void sxevf_tx_ring_info_get(struct sxevf_hw *hw, @@ -717,48 +676,47 @@ static void sxevf_tx_ring_info_get(struct sxevf_hw *h= w, *head =3D SXEVF_REG_READ(hw, SXE_VFTDH(idx)); *tail =3D SXEVF_REG_READ(hw, SXE_VFTDT(idx)); =20 - return; } =20 static const struct sxevf_dma_operations sxevf_dma_ops =3D { .tx_ring_desc_configure =3D sxevf_tx_ring_desc_configure, - .tx_writeback_off =3D sxevf_tx_writeback_off, - .tx_desc_thresh_set =3D sxevf_tx_desc_thresh_set, - .tx_ring_switch =3D sxevf_tx_ring_switch, - .tx_ring_info_get =3D sxevf_tx_ring_info_get, - - .rx_disable =3D sxevf_rx_disable, - .rx_ring_switch =3D sxevf_rx_ring_switch, - .rx_ring_desc_configure=3D sxevf_rx_ring_desc_configure, + .tx_writeback_off =3D sxevf_tx_writeback_off, + .tx_desc_thresh_set =3D sxevf_tx_desc_thresh_set, + .tx_ring_switch =3D sxevf_tx_ring_switch, + .tx_ring_info_get =3D sxevf_tx_ring_info_get, + + .rx_disable =3D sxevf_rx_disable, + .rx_ring_switch =3D sxevf_rx_ring_switch, + .rx_ring_desc_configure =3D sxevf_rx_ring_desc_configure, .rx_rcv_ctl_configure =3D sxevf_rx_rcv_ctl_configure, }; =20 #ifdef SXE_DPDK -#define SXEVF_32BIT_COUNTER_UPDATE(reg, last, cur) = \ - { \ - u32 latest =3D SXEVF_REG_READ(hw, reg); \ - cur +=3D (latest - last) & UINT_MAX; \ - last =3D latest; \ - } -=09 -#define SXEVF_36BIT_COUNTER_UPDATE(lsb, msb, last, cur) \ - { \ - u64 new_lsb =3D SXEVF_REG_READ(hw, lsb); \ - u64 new_msb =3D SXEVF_REG_READ(hw, msb); \ - u64 latest =3D ((new_msb << 32) | new_lsb); \ +#define SXEVF_32BIT_COUNTER_UPDATE(reg, last, cur) \ + { \ + u32 latest =3D SXEVF_REG_READ(hw, reg); \ + cur +=3D (latest - last) & UINT_MAX; \ + last =3D latest; \ + } + +#define SXEVF_36BIT_COUNTER_UPDATE(lsb, msb, last, cur) \ + { \ + u64 new_lsb =3D SXEVF_REG_READ(hw, lsb); \ + u64 new_msb =3D SXEVF_REG_READ(hw, msb); \ + u64 latest =3D ((new_msb << 32) | new_lsb); \ cur +=3D (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ - last =3D latest; \ + last =3D latest; \ } =20 #else #define SXEVF_32BIT_COUNTER_UPDATE(reg, last_counter, counter) \ - { \ - u32 current_counter =3D SXEVF_REG_READ(hw, reg); \ - if (current_counter < last_counter) \ - counter +=3D 0x100000000LL; \ - last_counter =3D current_counter; \ - counter &=3D 0xFFFFFFFF00000000LL; \ - counter |=3D current_counter; \ + { \ + u32 current_counter =3D SXEVF_REG_READ(hw, reg); \ + if (current_counter < last_counter) \ + counter +=3D 0x100000000LL; \ + last_counter =3D current_counter; \ + counter &=3D 0xFFFFFFFF00000000LL; \ + counter |=3D current_counter; \ } =20 #define SXEVF_36BIT_COUNTER_UPDATE(reg_lsb, reg_msb, last_counter, counter= ) \ @@ -791,7 +749,6 @@ void sxevf_packet_stats_get(struct sxevf_hw *hw, SXEVF_32BIT_COUNTER_UPDATE(SXEVF_VFMPRC, stats->last_vfmprc, stats->vfmprc); =20 - return; } =20 void sxevf_stats_init_value_get(struct sxevf_hw *hw, @@ -805,7 +762,6 @@ void sxevf_stats_init_value_get(struct sxevf_hw *hw, stats->last_vfgotc |=3D (((u64)(SXEVF_REG_READ(hw, SXE_VFGOTC_MSB))) << 3= 2); stats->last_vfmprc =3D SXEVF_REG_READ(hw, SXE_VFMPRC); =20 - return; } static const struct sxevf_stat_operations sxevf_stat_ops =3D { .packet_stats_get =3D sxevf_packet_stats_get, @@ -816,13 +772,11 @@ static void sxevf_rx_max_used_ring_set(struct sxevf_h= w *hw, u16 max_rx_ring) { u32 rqpl =3D 0; =20 - if (max_rx_ring > 1) { + if (max_rx_ring > 1) rqpl |=3D BIT(29); - } =20 SXEVF_REG_WRITE(hw, SXE_VFPSRTYPE, rqpl); =20 - return; } =20 static const struct sxevf_dbu_operations sxevf_dbu_ops =3D { @@ -844,23 +798,22 @@ static const struct sxevf_mbx_operations sxevf_mbx_op= s =3D { void sxevf_hw_ops_init(struct sxevf_hw *hw) { hw->setup.ops =3D &sxevf_setup_ops; - hw->irq.ops =3D &sxevf_irq_ops; - hw->mbx.ops =3D &sxevf_mbx_ops; - hw->dma.ops =3D &sxevf_dma_ops; - hw->stat.ops =3D &sxevf_stat_ops; - hw->dbu.ops =3D &sxevf_dbu_ops; + hw->irq.ops =3D &sxevf_irq_ops; + hw->mbx.ops =3D &sxevf_mbx_ops; + hw->dma.ops =3D &sxevf_dma_ops; + hw->stat.ops =3D &sxevf_stat_ops; + hw->dbu.ops =3D &sxevf_dbu_ops; =20 - return; } =20 -#ifdef SXE_DPDK=20 +#ifdef SXE_DPDK =20 -#define SXEVF_RSS_FIELD_MASK 0xffff0000 -#define SXEVF_MRQC_RSSEN 0x00000001=20 +#define SXEVF_RSS_FIELD_MASK 0xffff0000 +#define SXEVF_MRQC_RSSEN 0x00000001 =20 -#define SXEVF_RSS_KEY_SIZE (40)=20=20 -#define SXEVF_MAX_RSS_KEY_ENTRIES (10)=20=20 -#define SXEVF_MAX_RETA_ENTRIES (128)=20 +#define SXEVF_RSS_KEY_SIZE (40) +#define SXEVF_MAX_RSS_KEY_ENTRIES (10) +#define SXEVF_MAX_RETA_ENTRIES (128) =20 void sxevf_rxtx_reg_init(struct sxevf_hw *hw) { @@ -886,7 +839,6 @@ void sxevf_rxtx_reg_init(struct sxevf_hw *hw) =20 SXEVF_WRITE_FLUSH(hw); =20 - return; } =20 u32 sxevf_irq_cause_get(struct sxevf_hw *hw) @@ -898,21 +850,19 @@ void sxevf_tx_desc_configure(struct sxevf_hw *hw, u32= desc_mem_len, u64 desc_dma_addr, u8 reg_idx) { =20 - SXEVF_REG_WRITE(hw, SXEVF_TDBAL(reg_idx), (desc_dma_addr & \ + SXEVF_REG_WRITE(hw, SXEVF_TDBAL(reg_idx), (desc_dma_addr & DMA_BIT_MASK(32))); SXEVF_REG_WRITE(hw, SXEVF_TDBAH(reg_idx), (desc_dma_addr >> 32)); SXEVF_REG_WRITE(hw, SXEVF_TDLEN(reg_idx), desc_mem_len); SXEVF_REG_WRITE(hw, SXEVF_TDH(reg_idx), 0); SXEVF_REG_WRITE(hw, SXEVF_TDT(reg_idx), 0); =20 - return; } =20 void sxevf_rss_bit_num_set(struct sxevf_hw *hw, u32 value) { SXEVF_REG_WRITE(hw, SXE_VFPSRTYPE, value); =20 - return; } =20 void sxevf_hw_vlan_tag_strip_switch(struct sxevf_hw *hw, @@ -922,15 +872,13 @@ void sxevf_hw_vlan_tag_strip_switch(struct sxevf_hw *= hw, =20 vlnctrl =3D SXEVF_REG_READ(hw, SXE_VFRXDCTL(reg_index)); =20 - if (is_enable) { + if (is_enable) vlnctrl |=3D SXEVF_RXDCTL_VME; - } else { + else vlnctrl &=3D ~SXEVF_RXDCTL_VME; - } =20 SXEVF_REG_WRITE(hw, SXE_VFRXDCTL(reg_index), vlnctrl); =20 - return; } =20 void sxevf_tx_queue_thresh_set(struct sxevf_hw *hw, u8 reg_idx, @@ -944,14 +892,12 @@ void sxevf_tx_queue_thresh_set(struct sxevf_hw *hw, u= 8 reg_idx, =20 SXEVF_REG_WRITE(hw, SXEVF_TXDCTL(reg_idx), txdctl); =20 - return; } =20 void sxevf_rx_desc_tail_set(struct sxevf_hw *hw, u8 reg_idx, u32 value) { SXEVF_REG_WRITE(hw, SXE_VFRDT(reg_idx), value); =20 - return; } =20 u32 sxevf_hw_rss_redir_tbl_get(struct sxevf_hw *hw, u16 reg_idx) @@ -963,18 +909,16 @@ void sxevf_hw_rss_redir_tbl_set(struct sxevf_hw *hw, u16 reg_idx, u32 value) { SXEVF_REG_WRITE(hw, SXE_VFRETA(reg_idx >> 2), value); - return; } =20 u32 sxevf_hw_rss_key_get(struct sxevf_hw *hw, u8 reg_idx) { u32 rss_key; =20 - if (reg_idx >=3D SXEVF_MAX_RSS_KEY_ENTRIES) { + if (reg_idx >=3D SXEVF_MAX_RSS_KEY_ENTRIES) rss_key =3D 0; - } else { + else rss_key =3D SXEVF_REG_READ(hw, SXE_VFRSSRK(reg_idx)); - } =20 return rss_key; } @@ -989,9 +933,8 @@ bool sxevf_hw_is_rss_enabled(struct sxevf_hw *hw) { bool rss_enable =3D false; u32 mrqc =3D SXEVF_REG_READ(hw, SXE_VFMRQC); - if (mrqc & SXEVF_MRQC_RSSEN) { + if (mrqc & SXEVF_MRQC_RSSEN) rss_enable =3D true; - } =20 return rss_enable; } @@ -1000,25 +943,21 @@ void sxevf_hw_rss_key_set_all(struct sxevf_hw *hw, u= 32 *rss_key) { u32 i; =20 - for (i =3D 0; i < SXEVF_MAX_RSS_KEY_ENTRIES; i++) { + for (i =3D 0; i < SXEVF_MAX_RSS_KEY_ENTRIES; i++) SXEVF_REG_WRITE(hw, SXE_VFRSSRK(i), rss_key[i]); - } =20 - return; } =20 void sxevf_hw_rss_cap_switch(struct sxevf_hw *hw, bool is_on) { u32 mrqc =3D SXEVF_REG_READ(hw, SXE_VFMRQC); - if (is_on) { + if (is_on) mrqc |=3D SXEVF_MRQC_RSSEN; - } else { + else mrqc &=3D ~SXEVF_MRQC_RSSEN; - } =20 SXEVF_REG_WRITE(hw, SXE_VFMRQC, mrqc); =20 - return; } =20 void sxevf_hw_rss_field_set(struct sxevf_hw *hw, u32 rss_field) @@ -1029,7 +968,6 @@ void sxevf_hw_rss_field_set(struct sxevf_hw *hw, u32 r= ss_field) mrqc |=3D rss_field; SXEVF_REG_WRITE(hw, SXE_VFMRQC, mrqc); =20 - return; } =20 u32 sxevf_hw_regs_group_read(struct sxevf_hw *hw, @@ -1044,7 +982,7 @@ u32 sxevf_hw_regs_group_read(struct sxevf_hw *hw, reg_buf[count + j] =3D SXEVF_REG_READ(hw, regs[i].addr + j * regs[i].stride); LOG_INFO("regs=3D %s, regs_addr=3D%x, regs_value=3D%04x\n", - regs[i].name , regs[i].addr, reg_buf[count + j]); + regs[i].name, regs[i].addr, reg_buf[count + j]); } =20 i++; diff --git a/drivers/net/sxe/base/sxevf_hw.h b/drivers/net/sxe/base/sxevf_h= w.h index 67d711d5b8..1530a3949f 100644 --- a/drivers/net/sxe/base/sxevf_hw.h +++ b/drivers/net/sxe/base/sxevf_hw.h @@ -5,7 +5,7 @@ #ifndef __SXEVF_HW_H__ #define __SXEVF_HW_H__ =20 -#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST) +#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST) #include #include #include @@ -18,7 +18,7 @@ =20 #include "sxevf_regs.h" =20 -#if defined (__KERNEL__) || defined (SXE_KERNEL_TEST) +#if defined(__KERNEL__) || defined(SXE_KERNEL_TEST) #define SXE_PRIU64 "llu" #define SXE_PRIX64 "llx" #define SXE_PRID64 "lld" @@ -28,30 +28,30 @@ #define SXE_PRID64 PRId64 #endif =20 -#define SXEVF_TXRX_RING_NUM_MAX 8=20=20 -#define SXEVF_MAX_TXRX_DESC_POLL (10) +#define SXEVF_TXRX_RING_NUM_MAX 8 +#define SXEVF_MAX_TXRX_DESC_POLL (10) #define SXEVF_TX_DESC_PREFETCH_THRESH_32 (32) -#define SXEVF_TX_DESC_HOST_THRESH_1 (1) +#define SXEVF_TX_DESC_HOST_THRESH_1 (1) #define SXEVF_TX_DESC_WRITEBACK_THRESH_8 (8) -#define SXEVF_TXDCTL_HTHRESH_SHIFT (8) -#define SXEVF_TXDCTL_WTHRESH_SHIFT (16) +#define SXEVF_TXDCTL_HTHRESH_SHIFT (8) +#define SXEVF_TXDCTL_WTHRESH_SHIFT (16) =20 -#define SXEVF_TXDCTL_THRESH_MASK (0x7F) +#define SXEVF_TXDCTL_THRESH_MASK (0x7F) =20 -#define SXEVF_RX_RING_POLL_MAX (10) +#define SXEVF_RX_RING_POLL_MAX (10) =20 -#define SXEVF_MAC_HDR_LEN_MAX (127) -#define SXEVF_NETWORK_HDR_LEN_MAX (511) +#define SXEVF_MAC_HDR_LEN_MAX (127) +#define SXEVF_NETWORK_HDR_LEN_MAX (511) =20 -#define SXEVF_LINK_SPEED_UNKNOWN 0 +#define SXEVF_LINK_SPEED_UNKNOWN 0 #define SXEVF_LINK_SPEED_1GB_FULL 0x0020 #define SXEVF_LINK_SPEED_10GB_FULL 0x0080 #define SXEVF_LINK_SPEED_100_FULL 0x0008 =20 -#define SXEVF_VFT_TBL_SIZE (128)=20=20=20 -#define SXEVF_HW_TXRX_RING_NUM_MAX (128)=20=20=20 +#define SXEVF_VFT_TBL_SIZE (128) +#define SXEVF_HW_TXRX_RING_NUM_MAX (128) =20 -#define SXEVF_VLAN_TAG_SIZE (4) +#define SXEVF_VLAN_TAG_SIZE (4) =20 #define SXEVF_HW_UC_ENTRY_NUM_MAX 128 =20 @@ -65,7 +65,7 @@ enum { SXEVF_DIAG_TEST_PASSED =3D 0, SXEVF_DIAG_TEST_BLOCKED =3D 1, SXEVF_DIAG_REG_PATTERN_TEST_ERR =3D 2, - SXEVF_DIAG_CHECK_REG_TEST_ERR =3D 3, + SXEVF_DIAG_CHECK_REG_TEST_ERR =3D 3, }; =20 struct sxevf_hw; @@ -83,11 +83,11 @@ struct sxevf_hw_stats { u64 last_vfgotc; u64 last_vfmprc; =20 - u64 vfgprc;=20=20=20=20=20=20 - u64 vfgptc;=20=20=20=20=20=20 - u64 vfgorc;=20=20=20=20=20=20 - u64 vfgotc;=20=20=20=20=20=20 - u64 vfmprc;=20=20=20=20=20=20 + u64 vfgprc; + u64 vfgptc; + u64 vfgorc; + u64 vfgotc; + u64 vfmprc; =20 u64 saved_reset_vfgprc; u64 saved_reset_vfgptc; @@ -100,12 +100,12 @@ void sxevf_hw_ops_init(struct sxevf_hw *hw); =20 =20 struct sxevf_setup_operations { - void (*reset)(struct sxevf_hw *); + void (*reset)(struct sxevf_hw *hw); void (*hw_stop)(struct sxevf_hw *hw); s32 (*regs_test)(struct sxevf_hw *hw); u32 (*link_state_get)(struct sxevf_hw *hw); u32 (*regs_dump)(struct sxevf_hw *hw, u32 *regs_buff, u32 buf_size); - bool (*reset_done)(struct sxevf_hw *); + bool (*reset_done)(struct sxevf_hw *hw); }; =20 struct sxevf_hw_setup { @@ -115,12 +115,12 @@ struct sxevf_hw_setup { struct sxevf_irq_operations { void (*pending_irq_clear)(struct sxevf_hw *hw); void (*ring_irq_interval_set)(struct sxevf_hw *hw, u16 irq_idx, u32 inter= val); - void (*event_irq_interval_set)(struct sxevf_hw * hw, u16 irq_idx, u32 val= ue); + void (*event_irq_interval_set)(struct sxevf_hw *hw, u16 irq_idx, u32 valu= e); void (*ring_irq_map)(struct sxevf_hw *hw, bool is_tx, u16 hw_ring_idx, u1= 6 irq_idx); void (*event_irq_map)(struct sxevf_hw *hw, u16 irq_idx); void (*ring_irq_trigger)(struct sxevf_hw *hw, u64 eics); - void (*irq_enable)(struct sxevf_hw * hw, u32 mask); - void (*specific_irq_enable)(struct sxevf_hw * hw, u32 value); + void (*irq_enable)(struct sxevf_hw *hw, u32 mask); + void (*specific_irq_enable)(struct sxevf_hw *hw, u32 value); void (*irq_disable)(struct sxevf_hw *hw); void (*irq_off)(struct sxevf_hw *hw); }; @@ -142,37 +142,40 @@ struct sxevf_mbx_operations { }; =20 struct sxevf_mbx_stats { - u32 send_msgs;=20 - u32 rcv_msgs;=20=20 + u32 send_msgs; + u32 rcv_msgs; =20 - u32 reqs;=20=20=20=20=20=20 - u32 acks;=20=20=20=20=20=20 - u32 rsts;=20=20=20=20=20=20 + u32 reqs; + u32 acks; + u32 rsts; }; =20 struct sxevf_mbx_info { - const struct sxevf_mbx_operations *ops;=20 - - struct sxevf_mbx_stats stats;=20 - u32 msg_len;=20=20 - u32 retry;=20=20=20=20 - u32 interval;=20 - u32 reg_value;=20 - u32 api_version;=20 + const struct sxevf_mbx_operations *ops; + + struct sxevf_mbx_stats stats; + u32 msg_len; + u32 retry; + u32 interval; + u32 reg_value; + u32 api_version; }; =20 struct sxevf_dma_operations { - void (* tx_ring_desc_configure)(struct sxevf_hw *, u32, u64, u8); - void (* tx_writeback_off)(struct sxevf_hw *, u8); - void (* tx_desc_thresh_set)(struct sxevf_hw *, u8, u32, u32, u32); - void (* tx_ring_switch)(struct sxevf_hw *, u8, bool); - void (* tx_desc_wb_flush)(struct sxevf_hw *, u8); - void (* tx_ring_info_get)(struct sxevf_hw *hw, u8 reg_idx, + void (*tx_ring_desc_configure)(struct sxevf_hw *hw, u32 desc_mem_len, + u64 desc_dma_addr, u8 reg_idx); + void (*tx_writeback_off)(struct sxevf_hw *hw, u8 reg_idx); + void (*tx_desc_thresh_set)(struct sxevf_hw *hw, u8 reg_idx, + u32 wb_thresh, u32 host_thresh, u32 prefech_thresh); + void (*tx_ring_switch)(struct sxevf_hw *hw, u8 reg_idx, bool is_on); + void (*tx_desc_wb_flush)(struct sxevf_hw *hw, u8 val); + void (*tx_ring_info_get)(struct sxevf_hw *hw, u8 reg_idx, u32 *head, u32 *tail); - void (* rx_disable)(struct sxevf_hw *, u8); - void (* rx_ring_switch)(struct sxevf_hw *, u8, bool); - void (* rx_ring_desc_configure)(struct sxevf_hw *, u32, u64, u8); - void (* rx_rcv_ctl_configure)(struct sxevf_hw *hw, u8 reg_idx, + void (*rx_disable)(struct sxevf_hw *hw, u8 reg_idx); + void (*rx_ring_switch)(struct sxevf_hw *hw, u8 reg_idx, bool is_on); + void (*rx_ring_desc_configure)(struct sxevf_hw *hw, u32 desc_mem_len, + u64 desc_dma_addr, u8 reg_idx); + void (*rx_rcv_ctl_configure)(struct sxevf_hw *hw, u8 reg_idx, u32 header_buf_len, u32 pkg_buf_len, bool drop_en); }; =20 @@ -181,8 +184,8 @@ struct sxevf_dma_info { }; =20 struct sxevf_stat_operations { - void (*packet_stats_get)(struct sxevf_hw *, - struct sxevf_hw_stats *); + void (*packet_stats_get)(struct sxevf_hw *hw, + struct sxevf_hw_stats *stats); void (*stats_init_value_get)(struct sxevf_hw *hw, struct sxevf_hw_stats *stats); }; @@ -192,7 +195,7 @@ struct sxevf_stat_info { }; =20 struct sxevf_dbu_operations { - void (*rx_max_used_ring_set)(struct sxevf_hw *, u16); + void (*rx_max_used_ring_set)(struct sxevf_hw *hw, u16 max_rx_ring); =20 }; =20 @@ -206,30 +209,30 @@ enum sxevf_hw_state { }; =20 struct sxevf_hw { - u8 __iomem *reg_base_addr;=20=20=20=20=20=20 + u8 __iomem *reg_base_addr; void *adapter; =20 void *priv; - unsigned long state;=20=20=20 + unsigned long state; void (*fault_handle)(void *priv); u32 (*reg_read)(const volatile void *reg); void (*reg_write)(u32 value, volatile void *reg); - s32 board_type;=09=09 + s32 board_type; =20 - struct sxevf_hw_setup setup;=20=20=20 - struct sxevf_irq_info irq;=20=20=20=20=20 - struct sxevf_mbx_info mbx;=20=20=20=20=20 + struct sxevf_hw_setup setup; + struct sxevf_irq_info irq; + struct sxevf_mbx_info mbx; =20 - struct sxevf_dma_info dma;=20=20=20=20 - struct sxevf_stat_info stat;=20=20=20 - struct sxevf_dbu_info dbu; + struct sxevf_dma_info dma; + struct sxevf_stat_info stat; + struct sxevf_dbu_info dbu; }; =20 struct sxevf_reg_info { - u32 addr;=20=20=20=20=20=20=20=20 - u32 count;=20=20=20=20=20=20=20 - u32 stride;=20=20=20=20=20=20 - const s8 *name;=20=20 + u32 addr; + u32 count; + u32 stride; + const s8 *name; }; =20 u16 sxevf_reg_dump_num_get(void); @@ -247,7 +250,6 @@ static inline void sxevf_hw_fault_handle_init(struct sx= evf_hw *hw, hw->priv =3D priv; hw->fault_handle =3D handle; =20 - return; } =20 static inline void sxevf_hw_reg_handle_init(struct sxevf_hw *hw, @@ -257,10 +259,9 @@ static inline void sxevf_hw_reg_handle_init(struct sxe= vf_hw *hw, hw->reg_read =3D read; hw->reg_write =3D write; =20 - return; } =20 -#ifdef SXE_DPDK=20 +#ifdef SXE_DPDK =20 void sxevf_irq_disable(struct sxevf_hw *hw); =20 @@ -347,5 +348,5 @@ u32 sxevf_hw_regs_group_read(struct sxevf_hw *hw, const struct sxevf_reg_info *regs, u32 *reg_buf); =20 -#endif=20 +#endif #endif diff --git a/drivers/net/sxe/base/sxevf_regs.h b/drivers/net/sxe/base/sxevf= _regs.h index 43486db526..50a22f559c 100644 --- a/drivers/net/sxe/base/sxevf_regs.h +++ b/drivers/net/sxe/base/sxevf_regs.h @@ -14,106 +14,106 @@ #define SXE_VFLINKS_SPEED_1G 0x00000004 #define SXE_VFLINKS_SPEED_100 0x00000002 =20 -#define SXE_VFCTRL 0x00000 -#define SXE_VFSTATUS 0x00008 -#define SXE_VFLINKS 0x00018 -#define SXE_VFFRTIMER 0x00048 +#define SXE_VFCTRL 0x00000 +#define SXE_VFSTATUS 0x00008 +#define SXE_VFLINKS 0x00018 +#define SXE_VFFRTIMER 0x00048 #define SXE_VFRXMEMWRAP 0x03190 -#define SXE_VFEICR 0x00100 -#define SXE_VFEICS 0x00104 -#define SXE_VFEIMS 0x00108 -#define SXE_VFEIMC 0x0010C -#define SXE_VFEIAM 0x00114 -#define SXE_VFEITR(x) (0x00820 + (4 * (x))) -#define SXE_VFIVAR(x) (0x00120 + (4 * (x))) -#define SXE_VFIVAR_MISC 0x00140 -#define SXE_VFRDBAL(x) (0x01000 + (0x40 * (x))) -#define SXE_VFRDBAH(x) (0x01004 + (0x40 * (x))) -#define SXE_VFRDLEN(x) (0x01008 + (0x40 * (x))) -#define SXE_VFRDH(x) (0x01010 + (0x40 * (x))) -#define SXE_VFRDT(x) (0x01018 + (0x40 * (x))) +#define SXE_VFEICR 0x00100 +#define SXE_VFEICS 0x00104 +#define SXE_VFEIMS 0x00108 +#define SXE_VFEIMC 0x0010C +#define SXE_VFEIAM 0x00114 +#define SXE_VFEITR(x) (0x00820 + (4 * (x))) +#define SXE_VFIVAR(x) (0x00120 + (4 * (x))) +#define SXE_VFIVAR_MISC 0x00140 +#define SXE_VFRDBAL(x) (0x01000 + (0x40 * (x))) +#define SXE_VFRDBAH(x) (0x01004 + (0x40 * (x))) +#define SXE_VFRDLEN(x) (0x01008 + (0x40 * (x))) +#define SXE_VFRDH(x) (0x01010 + (0x40 * (x))) +#define SXE_VFRDT(x) (0x01018 + (0x40 * (x))) #define SXE_VFRXDCTL(x) (0x01028 + (0x40 * (x))) #define SXE_VFSRRCTL(x) (0x01014 + (0x40 * (x))) #define SXE_VFLROCTL(x) (0x0102C + (0x40 * (x))) -#define SXE_VFPSRTYPE 0x00300 -#define SXE_VFTDBAL(x) (0x02000 + (0x40 * (x))) -#define SXE_VFTDBAH(x) (0x02004 + (0x40 * (x))) -#define SXE_VFTDLEN(x) (0x02008 + (0x40 * (x))) -#define SXE_VFTDH(x) (0x02010 + (0x40 * (x))) -#define SXE_VFTDT(x) (0x02018 + (0x40 * (x))) +#define SXE_VFPSRTYPE 0x00300 +#define SXE_VFTDBAL(x) (0x02000 + (0x40 * (x))) +#define SXE_VFTDBAH(x) (0x02004 + (0x40 * (x))) +#define SXE_VFTDLEN(x) (0x02008 + (0x40 * (x))) +#define SXE_VFTDH(x) (0x02010 + (0x40 * (x))) +#define SXE_VFTDT(x) (0x02018 + (0x40 * (x))) #define SXE_VFTXDCTL(x) (0x02028 + (0x40 * (x))) #define SXE_VFTDWBAL(x) (0x02038 + (0x40 * (x))) #define SXE_VFTDWBAH(x) (0x0203C + (0x40 * (x))) -#define SXE_VFDCA_RXCTRL(x) (0x0100C + (0x40 * (x))) -#define SXE_VFDCA_TXCTRL(x) (0x0200c + (0x40 * (x))) -#define SXE_VFGPRC 0x0101C -#define SXE_VFGPTC 0x0201C -#define SXE_VFGORC_LSB 0x01020 -#define SXE_VFGORC_MSB 0x01024 -#define SXE_VFGOTC_LSB 0x02020 -#define SXE_VFGOTC_MSB 0x02024 -#define SXE_VFMPRC 0x01034 -#define SXE_VFMRQC 0x3000 -#define SXE_VFRSSRK(x) (0x3100 + ((x) * 4)) -#define SXE_VFRETA(x) (0x3200 + ((x) * 4)) - -#define SXEVF_VFEIMC_IRQ_MASK (7) -#define SXEVF_IVAR_ALLOC_VALID (0x80) - -#define SXEVF_EITR_CNT_WDIS (0x80000000) -#define SXEVF_EITR_ITR_MASK (0x00000FF8) -#define SXEVF_EITR_ITR_SHIFT (2) -#define SXEVF_EITR_ITR_MAX (SXEVF_EITR_ITR_MASK >> SXEVF_EITR_ITR_S= HIFT) +#define SXE_VFDCA_RXCTRL(x) (0x0100C + (0x40 * (x))) +#define SXE_VFDCA_TXCTRL(x) (0x0200c + (0x40 * (x))) +#define SXE_VFGPRC 0x0101C +#define SXE_VFGPTC 0x0201C +#define SXE_VFGORC_LSB 0x01020 +#define SXE_VFGORC_MSB 0x01024 +#define SXE_VFGOTC_LSB 0x02020 +#define SXE_VFGOTC_MSB 0x02024 +#define SXE_VFMPRC 0x01034 +#define SXE_VFMRQC 0x3000 +#define SXE_VFRSSRK(x) (0x3100 + ((x) * 4)) +#define SXE_VFRETA(x) (0x3200 + ((x) * 4)) + +#define SXEVF_VFEIMC_IRQ_MASK (7) +#define SXEVF_IVAR_ALLOC_VALID (0x80) + +#define SXEVF_EITR_CNT_WDIS (0x80000000) +#define SXEVF_EITR_ITR_MASK (0x00000FF8) +#define SXEVF_EITR_ITR_SHIFT (2) +#define SXEVF_EITR_ITR_MAX (SXEVF_EITR_ITR_MASK >> SXEVF_EITR_ITR_SHIFT) =20 #define SXE_VFRXDCTL_ENABLE 0x02000000 #define SXE_VFTXDCTL_ENABLE 0x02000000 -#define SXE_VFCTRL_RST 0x04000000 - -#define SXEVF_RXDCTL_ENABLE 0x02000000=20=20 -#define SXEVF_RXDCTL_VME 0x40000000=20=20 - -#define SXEVF_PSRTYPE_RQPL_SHIFT 29=20 - -#define SXEVF_SRRCTL_DROP_EN 0x10000000 -#define SXEVF_SRRCTL_DESCTYPE_DATA_ONEBUF 0x02000000 -#define SXEVF_SRRCTL_BSIZEPKT_SHIFT (10) -#define SXEVF_SRRCTL_BSIZEHDRSIZE_SHIFT (2) -#define SXEVF_SRRCTL_BSIZEPKT_MASK 0x0000007F -#define SXEVF_SRRCTL_BSIZEHDR_MASK 0x00003F00 - -#define SXE_VFMAILBOX 0x002FC -#define SXE_VFMBMEM 0x00200 - -#define SXE_VFMAILBOX_REQ 0x00000001=20 -#define SXE_VFMAILBOX_ACK 0x00000002=20 -#define SXE_VFMAILBOX_VFU 0x00000004=20 -#define SXE_VFMAILBOX_PFU 0x00000008=20 -#define SXE_VFMAILBOX_PFSTS 0x00000010=20 -#define SXE_VFMAILBOX_PFACK 0x00000020=20 -#define SXE_VFMAILBOX_RSTI 0x00000040=20 -#define SXE_VFMAILBOX_RSTD 0x00000080=20 -#define SXE_VFMAILBOX_RC_BIT 0x000000B0=20=20 - -#define SXEVF_TDBAL(_i) (0x02000 + ((_i) * 0x40)) -#define SXEVF_TDBAH(_i) (0x02004 + ((_i) * 0x40)) -#define SXEVF_TDLEN(_i) (0x02008 + ((_i) * 0x40)) -#define SXEVF_TDH(_i) (0x02010 + ((_i) * 0x40)) -#define SXEVF_TDT(_i) (0x02018 + ((_i) * 0x40)) -#define SXEVF_TXDCTL(_i) (0x02028 + ((_i) * 0x40)) -#define SXEVF_TDWBAL(_i) (0x02038 + ((_i) * 0x40)) -#define SXEVF_TDWBAH(_i) (0x0203C + ((_i) * 0x40)) - -#define SXEVF_TXDCTL_SWFLSH (0x02000000)=20=20 -#define SXEVF_TXDCTL_ENABLE (0x02000000)=20 - -#define SXEVF_VFGPRC 0x0101C -#define SXEVF_VFGPTC 0x0201C -#define SXEVF_VFGORC_LSB 0x01020 -#define SXEVF_VFGORC_MSB 0x01024 -#define SXEVF_VFGOTC_LSB 0x02020 -#define SXEVF_VFGOTC_MSB 0x02024 -#define SXEVF_VFMPRC 0x01034 - -#define SXEVF_EICR_MASK 0x07 +#define SXE_VFCTRL_RST 0x04000000 + +#define SXEVF_RXDCTL_ENABLE 0x02000000 +#define SXEVF_RXDCTL_VME 0x40000000 + +#define SXEVF_PSRTYPE_RQPL_SHIFT 29 + +#define SXEVF_SRRCTL_DROP_EN 0x10000000 +#define SXEVF_SRRCTL_DESCTYPE_DATA_ONEBUF 0x02000000 +#define SXEVF_SRRCTL_BSIZEPKT_SHIFT (10) +#define SXEVF_SRRCTL_BSIZEHDRSIZE_SHIFT (2) +#define SXEVF_SRRCTL_BSIZEPKT_MASK 0x0000007F +#define SXEVF_SRRCTL_BSIZEHDR_MASK 0x00003F00 + +#define SXE_VFMAILBOX 0x002FC +#define SXE_VFMBMEM 0x00200 + +#define SXE_VFMAILBOX_REQ 0x00000001 +#define SXE_VFMAILBOX_ACK 0x00000002 +#define SXE_VFMAILBOX_VFU 0x00000004 +#define SXE_VFMAILBOX_PFU 0x00000008 +#define SXE_VFMAILBOX_PFSTS 0x00000010 +#define SXE_VFMAILBOX_PFACK 0x00000020 +#define SXE_VFMAILBOX_RSTI 0x00000040 +#define SXE_VFMAILBOX_RSTD 0x00000080 +#define SXE_VFMAILBOX_RC_BIT 0x000000B0 + +#define SXEVF_TDBAL(_i) (0x02000 + ((_i) * 0x40)) +#define SXEVF_TDBAH(_i) (0x02004 + ((_i) * 0x40)) +#define SXEVF_TDLEN(_i) (0x02008 + ((_i) * 0x40)) +#define SXEVF_TDH(_i) (0x02010 + ((_i) * 0x40)) +#define SXEVF_TDT(_i) (0x02018 + ((_i) * 0x40)) +#define SXEVF_TXDCTL(_i) (0x02028 + ((_i) * 0x40)) +#define SXEVF_TDWBAL(_i) (0x02038 + ((_i) * 0x40)) +#define SXEVF_TDWBAH(_i) (0x0203C + ((_i) * 0x40)) + +#define SXEVF_TXDCTL_SWFLSH (0x02000000) +#define SXEVF_TXDCTL_ENABLE (0x02000000) + +#define SXEVF_VFGPRC 0x0101C +#define SXEVF_VFGPTC 0x0201C +#define SXEVF_VFGORC_LSB 0x01020 +#define SXEVF_VFGORC_MSB 0x01024 +#define SXEVF_VFGOTC_LSB 0x02020 +#define SXEVF_VFGOTC_MSB 0x02024 +#define SXEVF_VFMPRC 0x01034 + +#define SXEVF_EICR_MASK 0x07 =20 #endif diff --git a/drivers/net/sxe/include/drv_msg.h b/drivers/net/sxe/include/dr= v_msg.h index 9f06624cc3..e441f9d371 100644 --- a/drivers/net/sxe/include/drv_msg.h +++ b/drivers/net/sxe/include/drv_msg.h @@ -16,7 +16,7 @@ =20 =20 typedef struct sxe_version_resp { - U8 fw_version[SXE_VERSION_LEN]; -}sxe_version_resp_s; + U8 fw_version[SXE_VERSION_LEN]; +} sxe_version_resp_s; =20 -#endif=20 +#endif diff --git a/drivers/net/sxe/include/sxe/mgl/sxe_port.h b/drivers/net/sxe/i= nclude/sxe/mgl/sxe_port.h index e41cb9e87b..642b9eb045 100644 --- a/drivers/net/sxe/include/sxe/mgl/sxe_port.h +++ b/drivers/net/sxe/include/sxe/mgl/sxe_port.h @@ -11,26 +11,27 @@ extern "C" { #include "mgc_types.h" #include "ps3_types.h" =20 -typedef enum MglPortCmdSetCode{ - MGL_CMD_PORT_SET_BASE =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_SET, 0), - MGL_CMD_PORT_SET_REG =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_SET, 1), - MGL_CMD_PORT_SET_LED =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_SET, 2), - MGL_CMD_SXE_SOC_HTHRESHOLD =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_SET, 3), - MGL_CMD_SXE_SFP_HTHRESHOLD =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_SET, 4), - MGL_CMD_SXE_SOC_RST =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_SET, 5), - MGL_CMD_SXE_SET_MFGINFO =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_SET, 6), - MGL_CMD_SXE_SET_INSIGHT =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_SET, 7), - MGL_CMD_SXE_OPT_INSIGHT =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_SET, 8), +typedef enum MglPortCmdSetCode { + MGL_CMD_PORT_SET_BASE =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL= _CMD_SET, 0), + MGL_CMD_PORT_SET_REG =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL= _CMD_SET, 1), + MGL_CMD_PORT_SET_LED =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL= _CMD_SET, 2), + MGL_CMD_SXE_SOC_HTHRESHOLD =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, = MGL_CMD_SET, 3), + MGL_CMD_SXE_SFP_HTHRESHOLD =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, = MGL_CMD_SET, 4), + MGL_CMD_SXE_SOC_RST =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CM= D_SET, 5), + MGL_CMD_SXE_SET_MFGINFO =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL= _CMD_SET, 6), + MGL_CMD_SXE_SET_INSIGHT =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL= _CMD_SET, 7), + MGL_CMD_SXE_OPT_INSIGHT =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL= _CMD_SET, 8), + MGL_CMD_SXE_SET_LLDPSTATE =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, = MGL_CMD_SET, 9), } MglPortCmdSetCode_e; =20 -typedef enum MglPortCmdGetCode{ - MGL_CMD_SXE_GET_REG =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_GET, 0), - MGL_CMD_SXE_GET_SOC_INFO =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_GET, 1), - MGL_CMD_SXE_LOG_EXPORT =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_GET, 2), - MGL_CMD_SXE_REGS_DUMP =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_GET, 3), - MGL_CMD_SXE_GET_MFGINFO =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_GET, 4), - MGL_CMD_SXE_MAC_ADDR_GET =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_GET, 5), - MGL_CMD_SXE_GET_INSIGHT =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_POR= T, MGL_CMD_GET, 6), +typedef enum MglPortCmdGetCode { + MGL_CMD_SXE_GET_REG =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL_CM= D_GET, 0), + MGL_CMD_SXE_GET_SOC_INFO =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, = MGL_CMD_GET, 1), + MGL_CMD_SXE_LOG_EXPORT =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL= _CMD_GET, 2), + MGL_CMD_SXE_REGS_DUMP =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL= _CMD_GET, 3), + MGL_CMD_SXE_GET_MFGINFO =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL= _CMD_GET, 4), + MGL_CMD_SXE_MAC_ADDR_GET =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, = MGL_CMD_GET, 5), + MGL_CMD_SXE_GET_INSIGHT =3D MGL_MK_LIMIT(MGL_All_LIMIT, MGL_CMD_PORT, MGL= _CMD_GET, 6), } MglPortCmdGetCode_e; =20 #if defined(__cplusplus) diff --git a/drivers/net/sxe/include/sxe/sxe_cli.h b/drivers/net/sxe/includ= e/sxe/sxe_cli.h index 206cc48542..a03e51b08e 100644 --- a/drivers/net/sxe/include/sxe/sxe_cli.h +++ b/drivers/net/sxe/include/sxe/sxe_cli.h @@ -9,160 +9,165 @@ #include "sxe_drv_type.h" #endif =20 -#define SXE_VERION_LEN (32) -#define SXE_MAC_NUM (128) -#define SXE_PORT_TRANSCEIVER_LEN (32) -#define SXE_PORT_VENDOR_LEN (32) -#define SXE_CHIP_TYPE_LEN (32) -#define SXE_VPD_SN_LEN (16) -#define SXE_SOC_RST_TIME (0x93A80)=20=20 -#define SXE_SFP_TEMP_THRESHOLD_INTERVAL (3)=20=20=20=20=20=20=20=20 -#define MGC_TERMLOG_INFO_MAX_LEN (12 * 1024) -#define SXE_REGS_DUMP_MAX_LEN (12 * 1024) -#define SXE_PRODUCT_NAME_LEN (32)=20=20=20=20=20=20=20 +#define SXE_VERION_LEN (32) +#define SXE_MAC_NUM (128) +#define SXE_PORT_TRANSCEIVER_LEN (32) +#define SXE_PORT_VENDOR_LEN (32) +#define SXE_CHIP_TYPE_LEN (32) +#define SXE_VPD_SN_LEN (16) +#define SXE_SOC_RST_TIME (0x93A80) +#define SXE_SFP_TEMP_THRESHOLD_INTERVAL (3) +#define MGC_TERMLOG_INFO_MAX_LEN (12 * 1024) +#define SXE_REGS_DUMP_MAX_LEN (12 * 1024) +#define SXE_PRODUCT_NAME_LEN (32) =20 typedef enum sxe_led_mode { - SXE_IDENTIFY_LED_BLINK_ON =3D 0,=20=20=20=20 - SXE_IDENTIFY_LED_BLINK_OFF,=20=20=20=20=20=20=20=20=20 - SXE_IDENTIFY_LED_ON,=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - SXE_IDENTIFY_LED_OFF,=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - SXE_IDENTIFY_LED_RESET,=20=20=20=20=20=20=20=20=20=20=20=20=20 + SXE_IDENTIFY_LED_BLINK_ON =3D 0, + SXE_IDENTIFY_LED_BLINK_OFF, + SXE_IDENTIFY_LED_ON, + SXE_IDENTIFY_LED_OFF, + SXE_IDENTIFY_LED_RESET, } sxe_led_mode_s; =20 typedef struct sxe_led_ctrl { - U32 mode;=20=20=20=20=20=20 - U32 duration;=20=20 + U32 mode; + U32 duration; =20 } sxe_led_ctrl_s; =20 typedef struct sxe_led_ctrl_resp { - U32 ack;=20=20=20=20=20=20=20 + U32 ack; } sxe_led_ctrl_resp_s; =20 typedef enum PortLinkSpeed { - PORT_LINK_NO =3D 0,=20=20=20=20=20 - PORT_LINK_100M =3D 1,=20=20=20=20=20 - PORT_LINK_1G =3D 2,=20=20=20=20=20 - PORT_LINK_10G =3D 3,=20=20=20=20=20 + PORT_LINK_NO =3D 0, + PORT_LINK_100M =3D 1, + PORT_LINK_1G =3D 2, + PORT_LINK_10G =3D 3, } PortLinkSpeed_e; =20 typedef struct SysSocInfo { - S8 fwVer[SXE_VERION_LEN];=20=20=20=20=20=20=20=20 - S8 optVer[SXE_VERION_LEN];=20=20=20=20=20=20=20 - U8 socStatus;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20 - U8 pad[3]; - S32 socTemp;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20 - U64 chipId;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20 - S8 chipType[SXE_CHIP_TYPE_LEN];=20=20 - S8 pba[SXE_VPD_SN_LEN];=20=20=20=20=20=20=20=20=20=20 - S8 productName[SXE_PRODUCT_NAME_LEN];=20=20=20 + S8 fwVer[SXE_VERION_LEN]; + S8 optVer[SXE_VERION_LEN]; + U8 socStatus; + U8 pad[3]; + S32 socTemp; + U64 chipId; + S8 chipType[SXE_CHIP_TYPE_LEN]; + S8 pba[SXE_VPD_SN_LEN]; + S8 productName[SXE_PRODUCT_NAME_LEN]; } SysSocInfo_s; =20 typedef struct SysPortInfo { - U64 mac[SXE_MAC_NUM];=20=20=20=20=20=20=20=20=20 - U8 isPortAbs;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - U8 linkStat;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - U8 linkSpeed;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - - - U8 isSfp:1;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - U8 isGetInfo:1;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - U8 rvd:6;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - S8 opticalModTemp;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20 - U8 pad[3]; - S8 transceiverType[SXE_PORT_TRANSCEIVER_LEN];=20=20=20 - S8 vendorName[SXE_PORT_VENDOR_LEN];=20=20=20=20=20=20=20=20=20=20= =20=20=20 - S8 vendorPn[SXE_PORT_VENDOR_LEN];=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20 + U64 mac[SXE_MAC_NUM]; + U8 isPortAbs; + U8 linkStat; + U8 linkSpeed; + + + U8 isSfp:1; + U8 isGetInfo:1; + U8 rvd:6; + S8 opticalModTemp; + U8 pad[3]; + S8 transceiverType[SXE_PORT_TRANSCEIVER_LEN]; + S8 vendorName[SXE_PORT_VENDOR_LEN]; + S8 vendorPn[SXE_PORT_VENDOR_LEN]; } SysPortInfo_s; =20 typedef struct SysInfoResp { - SysSocInfo_s socInfo;=20=20=20=20=20=20=20=20 - SysPortInfo_s portInfo;=20=20=20=20=20=20=20 + SysSocInfo_s socInfo; + SysPortInfo_s portInfo; } SysInfoResp_s; =20 typedef enum SfpTempTdMode { - SFP_TEMP_THRESHOLD_MODE_ALARM =3D 0, - SFP_TEMP_THRESHOLD_MODE_WARN, + SFP_TEMP_THRESHOLD_MODE_ALARM =3D 0, + SFP_TEMP_THRESHOLD_MODE_WARN, } SfpTempTdMode_e; =20 -typedef struct SfpTempTdSet{ - U8 mode;=20=20=20=20=20=20=20=20=20=20=20=20=20 - U8 pad[3]; - S8 hthreshold;=20=20=20=20=20=20=20 - S8 lthreshold;=20=20=20=20=20=20=20 +typedef struct SfpTempTdSet { + U8 mode; + U8 pad[3]; + S8 hthreshold; + S8 lthreshold; } SfpTempTdSet_s; =20 typedef struct SxeLogExportResp { - U16 curLogLen;=20=20=20=20=20=20=20 - U8 isEnd; - U8 pad; - S32 sessionId;=20=20=20=20=20=20=20 - S8 data[0]; + U16 curLogLen; + U8 isEnd; + U8 pad; + S32 sessionId; + S8 data[0]; } SxeLogExportResp_s; =20 typedef enum SxeLogExportType { - SXE_LOG_EXPORT_REQ =3D 0,=20=20=20=20=20 - SXE_LOG_EXPORT_FIN,=20=20=20=20=20=20=20=20=20=20=20=20 - SXE_LOG_EXPORT_ABORT,=20=20=20=20=20=20=20=20=20=20 + SXE_LOG_EXPORT_REQ =3D 0, + SXE_LOG_EXPORT_FIN, + SXE_LOG_EXPORT_ABORT, } SxeLogExportType_e; =20 typedef struct SxeLogExportReq { - U8 isALLlog;=20=20=20=20=20=20=20 - U8 cmdtype;=20=20=20=20=20=20=20=20 - U8 isBegin;=20=20=20=20=20=20=20=20 - U8 pad; - S32 sessionId;=20=20=20=20=20=20 - U32 logLen;=20=20=20=20=20=20=20=20=20 + U8 isALLlog; + U8 cmdtype; + U8 isBegin; + U8 pad; + S32 sessionId; + U32 logLen; } SxeLogExportReq_s; =20 typedef struct SocRstReq { - U32 time;=20=20=20=20=20=20=20=20 + U32 time; } SocRstReq_s; =20 typedef struct RegsDumpResp { - U32 curdwLen;=20=20=20=20 - U8 data[0]; + U32 curdwLen; + U8 data[0]; } RegsDumpResp_s; =20 enum { - SXE_MFG_PART_NUMBER_LEN =3D 8, - SXE_MFG_SERIAL_NUMBER_LEN =3D 16, - SXE_MFG_REVISION_LEN =3D 4, - SXE_MFG_OEM_STR_LEN =3D 64, - SXE_MFG_SXE_BOARD_ASSEMBLY_LEN =3D 32, - SXE_MFG_SXE_BOARD_TRACE_NUM_LEN =3D 16, - SXE_MFG_SXE_MAC_ADDR_CNT =3D 2, + SXE_MFG_PART_NUMBER_LEN =3D 8, + SXE_MFG_SERIAL_NUMBER_LEN =3D 16, + SXE_MFG_REVISION_LEN =3D 4, + SXE_MFG_OEM_STR_LEN =3D 64, + SXE_MFG_SXE_BOARD_ASSEMBLY_LEN =3D 32, + SXE_MFG_SXE_BOARD_TRACE_NUM_LEN =3D 16, + SXE_MFG_SXE_MAC_ADDR_CNT =3D 2, }; =20 typedef struct sxeMfgInfo { - U8 partNumber[SXE_MFG_PART_NUMBER_LEN];=20=20=20=20=20=20 - U8 serialNumber [SXE_MFG_SERIAL_NUMBER_LEN];=20 - U32 mfgDate;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20 - U8 revision[SXE_MFG_REVISION_LEN];=20=20=20=20=20=20=20=20=20 - U32 reworkDate;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20 - U8 pad[4]; - U64 macAddr[SXE_MFG_SXE_MAC_ADDR_CNT];=20=20=20=20=20=20=20=20=20=20= =20=20=20 - U8 boardTraceNum[SXE_MFG_SXE_BOARD_TRACE_NUM_LEN];=20 - U8 boardAssembly[SXE_MFG_SXE_BOARD_ASSEMBLY_LEN];=20=20 - U8 extra1[SXE_MFG_OEM_STR_LEN];=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20 - U8 extra2[SXE_MFG_OEM_STR_LEN];=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20 + U8 partNumber[SXE_MFG_PART_NUMBER_LEN]; + U8 serialNumber[SXE_MFG_SERIAL_NUMBER_LEN]; + U32 mfgDate; + U8 revision[SXE_MFG_REVISION_LEN]; + U32 reworkDate; + U8 pad[4]; + U64 macAddr[SXE_MFG_SXE_MAC_ADDR_CNT]; + U8 boardTraceNum[SXE_MFG_SXE_BOARD_TRACE_NUM_LEN]; + U8 boardAssembly[SXE_MFG_SXE_BOARD_ASSEMBLY_LEN]; + U8 extra1[SXE_MFG_OEM_STR_LEN]; + U8 extra2[SXE_MFG_OEM_STR_LEN]; } sxeMfgInfo_t; =20 +typedef struct SxeLldpInfo { + U8 lldpState; + U8 pad[3]; +} SxeLldpInfo_t; + typedef struct RegsDumpReq { - U32 baseAddr;=20=20=20=20 - U32 dwLen;=20=20=20=20=20=20=20 + U32 baseAddr; + U32 dwLen; } RegsDumpReq_s; =20 typedef enum sxe_pcs_mode { - SXE_PCS_MODE_1000BASE_KX_WO =3D 0,=20 - SXE_PCS_MODE_1000BASE_KX_W,=20=20=20=20=20=20 - SXE_PCS_MODE_SGMII,=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - SXE_PCS_MODE_10GBASE_KR_WO,=20=20=20=20=20=20 - SXE_PCS_MODE_AUTO_NEGT_73,=20=20=20=20=20=20=20 - SXE_PCS_MODE_LPBK_PHY_TX2RX,=20=20=20=20=20 - SXE_PCS_MODE_LPBK_PHY_RX2TX,=20=20=20=20=20 - SXE_PCS_MODE_LPBK_PCS_RX2TX,=20=20=20=20=20 - SXE_PCS_MODE_BUTT,=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 + SXE_PCS_MODE_1000BASE_KX_WO =3D 0, + SXE_PCS_MODE_1000BASE_KX_W, + SXE_PCS_MODE_SGMII, + SXE_PCS_MODE_10GBASE_KR_WO, + SXE_PCS_MODE_AUTO_NEGT_73, + SXE_PCS_MODE_LPBK_PHY_TX2RX, + SXE_PCS_MODE_LPBK_PHY_RX2TX, + SXE_PCS_MODE_LPBK_PCS_RX2TX, + SXE_PCS_MODE_BUTT, } sxe_pcs_mode_e; =20 typedef enum sxe_remote_fault_mode { @@ -174,40 +179,40 @@ typedef enum sxe_remote_fault_mode { } sxe_remote_fault_e; =20 typedef struct sxe_phy_cfg { - sxe_pcs_mode_e mode;=20=20=20=20=20=20=20=20=20=20 - U32 mtu; + sxe_pcs_mode_e mode; + U32 mtu; } sxe_pcs_cfg_s; =20 typedef enum sxe_an_speed { - SXE_AN_SPEED_NO_LINK =3D 0, - SXE_AN_SPEED_100M, - SXE_AN_SPEED_1G,=20=20=20=20=20=20 - SXE_AN_SPEED_10G,=20=20=20=20=20 - SXE_AN_SPEED_UNKNOWN, + SXE_AN_SPEED_NO_LINK =3D 0, + SXE_AN_SPEED_100M, + SXE_AN_SPEED_1G, + SXE_AN_SPEED_10G, + SXE_AN_SPEED_UNKNOWN, } sxe_an_speed_e; =20 typedef enum sxe_phy_pause_cap { - SXE_PAUSE_CAP_NO_PAUSE =3D 0,=20=20=20 - SXE_PAUSE_CAP_ASYMMETRIC_PAUSE,=20=20 - SXE_PAUSE_CAP_SYMMETRIC_PAUSE,=20=20=20 - SXE_PAUSE_CAP_BOTH_PAUSE,=20=20=20=20=20=20=20=20 - SXE_PAUSE_CAP_UNKNOWN, + SXE_PAUSE_CAP_NO_PAUSE =3D 0, + SXE_PAUSE_CAP_ASYMMETRIC_PAUSE, + SXE_PAUSE_CAP_SYMMETRIC_PAUSE, + SXE_PAUSE_CAP_BOTH_PAUSE, + SXE_PAUSE_CAP_UNKNOWN, } sxe_phy_pause_cap_e; =20 typedef enum sxe_phy_duplex_type { - SXE_FULL_DUPLEX =3D 0,=09=20=20 - SXE_HALF_DUPLEX =3D 1,=09=20=20 - SXE_UNKNOWN_DUPLEX, + SXE_FULL_DUPLEX =3D 0, + SXE_HALF_DUPLEX =3D 1, + SXE_UNKNOWN_DUPLEX, } sxe_phy_duplex_type_e; =20 typedef struct sxe_phy_an_cap { - sxe_remote_fault_e remote_fault;=20 - sxe_phy_pause_cap_e pause_cap;=20=20=20=20 - sxe_phy_duplex_type_e duplex_cap;=20=20 + sxe_remote_fault_e remote_fault; + sxe_phy_pause_cap_e pause_cap; + sxe_phy_duplex_type_e duplex_cap; } sxe_phy_an_cap_s; =20 typedef struct sxe_an_cap { - sxe_phy_an_cap_s local;=20=20=20=20=20 - sxe_phy_an_cap_s peer;=20=20=20=20=20=20 + sxe_phy_an_cap_s local; + sxe_phy_an_cap_s peer; } sxe_an_cap_s; #endif diff --git a/drivers/net/sxe/include/sxe/sxe_hdc.h b/drivers/net/sxe/includ= e/sxe/sxe_hdc.h index bbdc273bf9..ee69d9afb0 100644 --- a/drivers/net/sxe/include/sxe/sxe_hdc.h +++ b/drivers/net/sxe/include/sxe/sxe_hdc.h @@ -9,35 +9,35 @@ #include "sxe_drv_type.h" #endif =20 -#define HDC_CACHE_TOTAL_LEN (16 *1024)=20=20=20=20 -#define ONE_PACKET_LEN_MAX (1024)=20=20=20=20=20=20=20=20 -#define DWORD_NUM (256)=20=20=20=20=20=20=20=20=20 -#define HDC_TRANS_RETRY_COUNT (3)=20=20=20=20=20=20=20=20=20=20=20 +#define HDC_CACHE_TOTAL_LEN (16 *1024) +#define ONE_PACKET_LEN_MAX (1024) +#define DWORD_NUM (256) +#define HDC_TRANS_RETRY_COUNT (3) =20 =20 typedef enum SxeHdcErrnoCode { - PKG_OK =3D 0,=20=20=20=20=20 - PKG_ERR_REQ_LEN,=20=20=20=20=20=20=20=20=20=20=20 - PKG_ERR_RESP_LEN,=20=20=20=20=20=20=20=20=20=20 - PKG_ERR_PKG_SKIP,=20=20=20=20=20=20=20=20=20=20 - PKG_ERR_NODATA,=20=20=20=20=20=20=20=20=20=20=20=20 - PKG_ERR_PF_LK,=20=20=20=20=20=20=20=20=20=20=20=20=20 - PKG_ERR_OTHER, + PKG_OK =3D 0, + PKG_ERR_REQ_LEN, + PKG_ERR_RESP_LEN, + PKG_ERR_PKG_SKIP, + PKG_ERR_NODATA, + PKG_ERR_PF_LK, + PKG_ERR_OTHER, } SxeHdcErrnoCode_e; =20 typedef union HdcHeader { - struct { - U8 pid:4;=20=20=20=20=20=20=20=20=20=20 - U8 errCode:4;=20=20=20=20=20=20 - U8 len;=20=20=20=20=20=20=20=20=20=20=20=20 - U16 startPkg:1;=20=20=20=20 - U16 endPkg:1;=20=20=20=20=20=20 - U16 isRd:1;=20=20=20=20=20=20=20=20 - U16 msi:1;=20=20=20=20=20=20=20=20=20 - U16 totalLen:12;=20=20=20 - } head; - U32 dw0; + struct { + U8 pid:4; + U8 errCode:4; + U8 len; + U16 startPkg:1; + U16 endPkg:1; + U16 isRd:1; + U16 msi:1; + U16 totalLen:12; + } head; + U32 dw0; } HdcHeader_u; =20 -#endif=20 +#endif =20 diff --git a/drivers/net/sxe/include/sxe/sxe_ioctl.h b/drivers/net/sxe/incl= ude/sxe/sxe_ioctl.h index 4f39b0f92c..0a796add40 100644 --- a/drivers/net/sxe/include/sxe/sxe_ioctl.h +++ b/drivers/net/sxe/include/sxe/sxe_ioctl.h @@ -9,11 +9,11 @@ #endif =20 struct SxeIoctlSyncCmd { - U64 traceid; - void *inData; - U32 inLen; - void *outData; - U32 outLen; + U64 traceid; + void *inData; + U32 inLen; + void *outData; + U32 outLen; }; =20 #define SXE_CMD_IOCTL_SYNC_CMD _IOWR('M', 1, struct SxeIoctlSyncCmd) diff --git a/drivers/net/sxe/include/sxe/sxe_msg.h b/drivers/net/sxe/includ= e/sxe/sxe_msg.h index 3db4e60ce5..cea8915aa6 100644 --- a/drivers/net/sxe/include/sxe/sxe_msg.h +++ b/drivers/net/sxe/include/sxe/sxe_msg.h @@ -15,125 +15,125 @@ #define SXE_HDC_MSG_HDR_SIZE sizeof(struct sxe_hdc_drv_cmd_msg) =20 enum sxe_cmd_type { - SXE_CMD_TYPE_CLI, - SXE_CMD_TYPE_DRV, - SXE_CMD_TYPE_UNKOWN, + SXE_CMD_TYPE_CLI, + SXE_CMD_TYPE_DRV, + SXE_CMD_TYPE_UNKNOWN, }; =20 typedef struct sxe_hdc_cmd_hdr { - U8 cmd_type;=20=20=20=20=20=20=20 - U8 cmd_sub_type;=20=20=20 - U8 reserve[6]; + U8 cmd_type; + U8 cmd_sub_type; + U8 reserve[6]; }sxe_hdc_cmd_hdr_s; =20 =20 =20 typedef enum SxeFWState { - SXE_FW_START_STATE_UNDEFINED =3D 0x00,=20=20=20 - SXE_FW_START_STATE_INIT_BASE =3D 0x10,=20=20=20 - SXE_FW_START_STATE_SCAN_DEVICE =3D 0x20,=20=20=20 - SXE_FW_START_STATE_FINISHED =3D 0x30,=20=20=20 - SXE_FW_START_STATE_UPGRADE =3D 0x31,=20=20=20 - SXE_FW_RUNNING_STATE_ABNOMAL =3D 0x40,=20=20=20 - SXE_FW_START_STATE_MASK =3D 0xF0, + SXE_FW_START_STATE_UNDEFINED =3D 0x00, + SXE_FW_START_STATE_INIT_BASE =3D 0x10, + SXE_FW_START_STATE_SCAN_DEVICE =3D 0x20, + SXE_FW_START_STATE_FINISHED =3D 0x30, + SXE_FW_START_STATE_UPGRADE =3D 0x31, + SXE_FW_RUNNING_STATE_ABNOMAL =3D 0x40, + SXE_FW_START_STATE_MASK =3D 0xF0, }SxeFWState_e; =20 typedef struct SxeFWStateInfo { - U8 socStatus;=20=20=20=20=20=20=20=20=20=20 - char statBuff[32];=20=20=20=20=20=20=20 + U8 socStatus; + char statBuff[32]; } SxeFWStateInfo_s; =20 =20 typedef enum MsiEvt { - MSI_EVT_SOC_STATUS =3D 0x1, - MSI_EVT_HDC_FWOV =3D 0x2, - MSI_EVT_HDC_TIME_SYNC =3D 0x4, + MSI_EVT_SOC_STATUS =3D 0x1, + MSI_EVT_HDC_FWOV =3D 0x2, + MSI_EVT_HDC_TIME_SYNC =3D 0x4, =20 - MSI_EVT_MAX =3D 0x80000000, + MSI_EVT_MAX =3D 0x80000000, } MsiEvt_u; =20 =20 typedef enum SxeFwHdcState { - SXE_FW_HDC_TRANSACTION_IDLE =3D 0x01, - SXE_FW_HDC_TRANSACTION_BUSY, + SXE_FW_HDC_TRANSACTION_IDLE =3D 0x01, + SXE_FW_HDC_TRANSACTION_BUSY, =20 - SXE_FW_HDC_TRANSACTION_ERR, + SXE_FW_HDC_TRANSACTION_ERR, } SxeFwHdcState_e; =20 enum sxe_hdc_cmd_opcode { - SXE_CMD_SET_WOL =3D 1, - SXE_CMD_LED_CTRL, - SXE_CMD_SFP_READ, - SXE_CMD_SFP_WRITE, - SXE_CMD_TX_DIS_CTRL =3D 5, - SXE_CMD_TINE_SYNC, - SXE_CMD_RATE_SELECT, - SXE_CMD_R0_MAC_GET, - SXE_CMD_LOG_EXPORT, - SXE_CMD_FW_VER_GET =3D 10, - SXE_CMD_PCS_SDS_INIT,=20=20=20=20=20=20=20=20=20 - SXE_CMD_AN_SPEED_GET,=20=20=20=20=20=20=20=20=20 - SXE_CMD_AN_CAP_GET,=20=20=20=20=20=20=20=20=20=20=20 - SXE_CMD_GET_SOC_INFO,=20=20=20=20=20=20=20=20=20 - SXE_CMD_MNG_RST =3D 15,=20=20=20=20=20=20=20=20=20 - - SXE_CMD_MAX, + SXE_CMD_SET_WOL =3D 1, + SXE_CMD_LED_CTRL, + SXE_CMD_SFP_READ, + SXE_CMD_SFP_WRITE, + SXE_CMD_TX_DIS_CTRL =3D 5, + SXE_CMD_TINE_SYNC, + SXE_CMD_RATE_SELECT, + SXE_CMD_R0_MAC_GET, + SXE_CMD_LOG_EXPORT, + SXE_CMD_FW_VER_GET =3D 10, + SXE_CMD_PCS_SDS_INIT, + SXE_CMD_AN_SPEED_GET, + SXE_CMD_AN_CAP_GET, + SXE_CMD_GET_SOC_INFO, + SXE_CMD_MNG_RST =3D 15, + + SXE_CMD_MAX, }; =20 enum sxe_hdc_cmd_errcode { - SXE_ERR_INVALID_PARAM =3D 1, + SXE_ERR_INVALID_PARAM =3D 1, }; =20 typedef struct sxe_hdc_drv_cmd_msg { =20 - U16 opcode; - U16 errcode; - union dataLength { - U16 req_len; - U16 ack_len; - } length; - U8 reserve[8]; - U64 traceid; - U8 body[0]; + U16 opcode; + U16 errcode; + union dataLength { + U16 req_len; + U16 ack_len; + } length; + U8 reserve[8]; + U64 traceid; + U8 body[0]; } sxe_hdc_drv_cmd_msg_s; =20 =20 typedef struct sxe_sfp_rw_req { - U16 offset;=20=20=20=20=20=20=20 - U16 len;=20=20=20=20=20=20=20=20=20=20 - U8 write_data[0]; + U16 offset; + U16 len; + U8 write_data[0]; } sxe_sfp_rw_req_s; =20 =20 typedef struct sxe_sfp_read_resp { - U16 len;=20=20=20=20=20 - U8 resp[0];=20 + U16 len; + U8 resp[0]; } sxe_sfp_read_resp_s; =20 -typedef enum sxe_sfp_rate{ - SXE_SFP_RATE_1G =3D 0, - SXE_SFP_RATE_10G =3D 1, +typedef enum sxe_sfp_rate { + SXE_SFP_RATE_1G =3D 0, + SXE_SFP_RATE_10G =3D 1, } sxe_sfp_rate_e; =20 =20 typedef struct sxe_sfp_rate_able { - sxe_sfp_rate_e rate;=20=20=20=20=20=20=20 + sxe_sfp_rate_e rate; } sxe_sfp_rate_able_s; =20 =20 typedef struct sxe_spp_tx_able { - BOOL isDisable;=20=20=20=20=20=20=20 + BOOL isDisable; } sxe_spp_tx_able_s; =20 =20 typedef struct sxe_default_mac_addr_resp { - U8 addr[SXE_MAC_ADDR_LEN];=20 + U8 addr[SXE_MAC_ADDR_LEN]; } sxe_default_mac_addr_resp_s; =20 =20 typedef struct sxe_mng_rst { - BOOL enable;=20=20=20=20=20=20=20 + BOOL enable; } sxe_mng_rst_s; =20 -#endif=20 +#endif =20 diff --git a/drivers/net/sxe/include/sxe/sxe_regs.h b/drivers/net/sxe/inclu= de/sxe/sxe_regs.h index 0652cd4906..aa41f5aa18 100644 --- a/drivers/net/sxe/include/sxe/sxe_regs.h +++ b/drivers/net/sxe/include/sxe/sxe_regs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright (C), 2022, Linkdata Technology Co., Ltd. */ -=20 + #ifndef __SXE_REGS_H__ #define __SXE_REGS_H__ =20 @@ -20,9 +20,9 @@ #endif =20 =20 -#define SXE_CTRL 0x00000=20 -#define SXE_STATUS 0x00008=20 -#define SXE_CTRL_EXT 0x00018=20 +#define SXE_CTRL 0x00000 +#define SXE_STATUS 0x00008 +#define SXE_CTRL_EXT 0x00018 =20 =20 #define SXE_CTRL_LNK_RST 0x00000008 @@ -57,7 +57,7 @@ #define SXE_FCCFG_TFCE_PRIORITY 0x00000010 =20 =20 -#define SXE_GCR_EXT 0x11050=20 +#define SXE_GCR_EXT 0x11050 =20 =20 #define SXE_GCR_CMPL_TMOUT_MASK 0x0000F000 @@ -117,7 +117,7 @@ #define SXE_EIMC_EX(i) (0x00AB0 + (i) * 4) #define SXE_EIAM_EX(i) (0x00AD0 + (i) * 4) #define SXE_EITR(i) (((i) <=3D 23) ? (0x00820 + ((i) * 4)) : \ - (0x012300 + (((i) - 24) * 4))) + (0x012300 + (((i) - 24) * 4))) =20 #define SXE_SPP_PROC 0x00AD8 #define SXE_SPP_STATE 0x00AF4 @@ -136,13 +136,13 @@ =20 =20 #define SXE_EICS_RTX_QUEUE SXE_EICR_RTX_QUEUE -#define SXE_EICS_FLOW_NAV SXE_EICR_FLOW_NAV=20 -#define SXE_EICS_MAILBOX SXE_EICR_MAILBOX=20=20 -#define SXE_EICS_LSC SXE_EICR_LSC=20=20=20=20=20=20 -#define SXE_EICS_ECC SXE_EICR_ECC=20=20=20=20=20=20 -#define SXE_EICS_HDC SXE_EICR_HDC=20=20=20=20=20=20 +#define SXE_EICS_FLOW_NAV SXE_EICR_FLOW_NAV +#define SXE_EICS_MAILBOX SXE_EICR_MAILBOX +#define SXE_EICS_LSC SXE_EICR_LSC +#define SXE_EICS_ECC SXE_EICR_ECC +#define SXE_EICS_HDC SXE_EICR_HDC #define SXE_EICS_TCP_TIMER SXE_EICR_TCP_TIMER -#define SXE_EICS_OTHER SXE_EICR_OTHER=20=20=20=20 +#define SXE_EICS_OTHER SXE_EICR_OTHER =20 =20 #define SXE_EIMS_RTX_QUEUE SXE_EICR_RTX_QUEUE @@ -156,9 +156,9 @@ #define SXE_EIMS_ENABLE_MASK (SXE_EIMS_RTX_QUEUE | SXE_EIMS_LSC | \ SXE_EIMS_TCP_TIMER | SXE_EIMS_OTHER) =20 -#define SXE_EIMC_FLOW_NAV SXE_EICR_FLOW_NAV=20 -#define SXE_EIMC_LSC SXE_EICR_LSC=20=20=20=20=20=20 -#define SXE_EIMC_HDC SXE_EICR_HDC=20=20=20=20=20=20 +#define SXE_EIMC_FLOW_NAV SXE_EICR_FLOW_NAV +#define SXE_EIMC_LSC SXE_EICR_LSC +#define SXE_EIMC_HDC SXE_EICR_HDC =20 =20 #define SXE_GPIE_SPP0_EN 0x00000001 @@ -204,7 +204,7 @@ #define SXE_RXCSUM 0x05000 #define SXE_RFCTL 0x05008 #define SXE_FCTRL 0x05080 -#define SXE_EXVET 0x05078 +#define SXE_EXVET 0x05078 #define SXE_VLNCTRL 0x05088 #define SXE_MCSTCTRL 0x05090 #define SXE_ETQF(_i) (0x05128 + ((_i) * 4)) @@ -218,8 +218,8 @@ #define SXE_MPSAR_LOW(_i) (0x0A600 + ((_i) * 8)) #define SXE_MPSAR_HIGH(_i) (0x0A604 + ((_i) * 8)) #define SXE_PSRTYPE(_i) (0x0EA00 + ((_i) * 4)) -#define SXE_RETA(_i) (0x0EB00 + ((_i) * 4))=20 -#define SXE_RSSRK(_i) (0x0EB80 + ((_i) * 4))=20 +#define SXE_RETA(_i) (0x0EB00 + ((_i) * 4)) +#define SXE_RSSRK(_i) (0x0EB80 + ((_i) * 4)) #define SXE_RQTC 0x0EC70 #define SXE_MRQC 0x0EC80 #define SXE_IEOI 0x0F654 @@ -242,8 +242,8 @@ #define SXE_LPL_DEFAULT 0x26000000 =20 =20 -#define SXE_RXCSUM_IPPCSE 0x00001000=20=20 -#define SXE_RXCSUM_PCSD 0x00002000=20=20 +#define SXE_RXCSUM_IPPCSE 0x00001000 +#define SXE_RXCSUM_PCSD 0x00002000 =20 =20 #define SXE_RFCTL_LRO_DIS 0x00000020 @@ -259,14 +259,14 @@ #define SXE_FCTRL_DPF 0x00002000 =20 =20 -#define SXE_VLNCTRL_VET 0x0000FFFF=20 -#define SXE_VLNCTRL_CFI 0x10000000=20 -#define SXE_VLNCTRL_CFIEN 0x20000000=20 -#define SXE_VLNCTRL_VFE 0x40000000=20 -#define SXE_VLNCTRL_VME 0x80000000=20 +#define SXE_VLNCTRL_VET 0x0000FFFF +#define SXE_VLNCTRL_CFI 0x10000000 +#define SXE_VLNCTRL_CFIEN 0x20000000 +#define SXE_VLNCTRL_VFE 0x40000000 +#define SXE_VLNCTRL_VME 0x80000000 =20 -#define SXE_EXVET_VET_EXT_SHIFT 16 -#define SXE_EXTENDED_VLAN (1 << 26) +#define SXE_EXVET_VET_EXT_SHIFT 16 +#define SXE_EXTENDED_VLAN (1 << 26) =20 =20 #define SXE_MCSTCTRL_MFE 4 @@ -290,10 +290,10 @@ #define SXE_ETQS_QUEUE_EN 0x80000000 =20 =20 -#define SXE_SYN_FILTER_ENABLE 0x00000001 -#define SXE_SYN_FILTER_QUEUE 0x000000FE -#define SXE_SYN_FILTER_QUEUE_SHIFT 1 -#define SXE_SYN_FILTER_SYNQFP 0x80000000 +#define SXE_SYN_FILTER_ENABLE 0x00000001 +#define SXE_SYN_FILTER_QUEUE 0x000000FE +#define SXE_SYN_FILTER_QUEUE_SHIFT 1 +#define SXE_SYN_FILTER_SYNQFP 0x80000000 =20 =20 #define SXE_RAH_VIND_MASK 0x003C0000 @@ -309,26 +309,26 @@ #define SXE_PSRTYPE_L2HDR 0x00001000 =20 =20 -#define SXE_MRQC_RSSEN 0x00000001=20 -#define SXE_MRQC_MRQE_MASK 0xF -#define SXE_MRQC_RT8TCEN 0x00000002 -#define SXE_MRQC_RT4TCEN 0x00000003 -#define SXE_MRQC_RTRSS8TCEN 0x00000004 -#define SXE_MRQC_RTRSS4TCEN 0x00000005 -#define SXE_MRQC_VMDQEN 0x00000008 -#define SXE_MRQC_VMDQRSS32EN 0x0000000A -#define SXE_MRQC_VMDQRSS64EN 0x0000000B -#define SXE_MRQC_VMDQRT8TCEN 0x0000000C -#define SXE_MRQC_VMDQRT4TCEN 0x0000000D -#define SXE_MRQC_RSS_FIELD_MASK 0xFFFF0000 -#define SXE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 -#define SXE_MRQC_RSS_FIELD_IPV4 0x00020000 +#define SXE_MRQC_RSSEN 0x00000001 +#define SXE_MRQC_MRQE_MASK 0xF +#define SXE_MRQC_RT8TCEN 0x00000002 +#define SXE_MRQC_RT4TCEN 0x00000003 +#define SXE_MRQC_RTRSS8TCEN 0x00000004 +#define SXE_MRQC_RTRSS4TCEN 0x00000005 +#define SXE_MRQC_VMDQEN 0x00000008 +#define SXE_MRQC_VMDQRSS32EN 0x0000000A +#define SXE_MRQC_VMDQRSS64EN 0x0000000B +#define SXE_MRQC_VMDQRT8TCEN 0x0000000C +#define SXE_MRQC_VMDQRT4TCEN 0x0000000D +#define SXE_MRQC_RSS_FIELD_MASK 0xFFFF0000 +#define SXE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 +#define SXE_MRQC_RSS_FIELD_IPV4 0x00020000 #define SXE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 -#define SXE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 -#define SXE_MRQC_RSS_FIELD_IPV6 0x00100000 -#define SXE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 -#define SXE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 -#define SXE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 +#define SXE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 +#define SXE_MRQC_RSS_FIELD_IPV6 0x00100000 +#define SXE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 +#define SXE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 +#define SXE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 #define SXE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 =20 =20 @@ -348,9 +348,9 @@ (0x0D028 + (((_i) - 64) * 0x40))) #define SXE_LROCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ (0x0D02C + (((_i) - 64) * 0x40))) -#define SXE_RDRXCTL 0x02F00=20=20 -#define SXE_RXCTRL 0x03000=20 -#define SXE_LRODBU 0x03028=20=20 +#define SXE_RDRXCTL 0x02F00 +#define SXE_RXCTRL 0x03000 +#define SXE_LRODBU 0x03028 #define SXE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) =20 #define SXE_DRXCFG (0x03C20) @@ -370,9 +370,9 @@ #define SXE_SRRCTL_BSIZEHDR_MASK 0x00003F00 =20 =20 -#define SXE_RXDCTL_ENABLE 0x02000000=20 -#define SXE_RXDCTL_SWFLSH 0x04000000=20 -#define SXE_RXDCTL_VME 0x40000000=20 +#define SXE_RXDCTL_ENABLE 0x02000000 +#define SXE_RXDCTL_SWFLSH 0x04000000 +#define SXE_RXDCTL_VME 0x40000000 #define SXE_RXDCTL_DESC_FIFO_AE_TH_SHIFT 8 #define SXE_RXDCTL_PREFETCH_NUM_CFG_SHIFT 16 =20 @@ -409,11 +409,11 @@ #define SXE_LRODBU_LROACKDIS 0x00000080 =20 =20 -#define SXE_DRXCFG_GSP_ZERO 0x00000002 +#define SXE_DRXCFG_GSP_ZERO 0x00000002 #define SXE_DRXCFG_DBURX_START 0x00000001 =20 =20 -#define SXE_DMATXCTL 0x04A80=20=20=20 +#define SXE_DMATXCTL 0x04A80 #define SXE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) #define SXE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) #define SXE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) @@ -424,25 +424,25 @@ #define SXE_PVFTDWBAH(p) (0x0603C + (0x40 * (p))) #define SXE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) #define SXE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) -#define SXE_MTQC 0x08120=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 -#define SXE_TXPBFCS 0x0CE00=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 -#define SXE_DTXCFG 0x0CE08=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 -#define SXE_DTMPCNT 0x0CE98=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 +#define SXE_MTQC 0x08120 +#define SXE_TXPBFCS 0x0CE00 +#define SXE_DTXCFG 0x0CE08 +#define SXE_DTMPCNT 0x0CE98 =20 =20 #define SXE_DMATXCTL_DEFAULT 0x81000000 =20 =20 -#define SXE_DMATXCTL_TE 0x1=20=20=20=20=20=20=20 -#define SXE_DMATXCTL_GDV 0x8=20=20=20=20=20=20=20 -#define SXE_DMATXCTL_VT_SHIFT 16=20=20=20=20=20=20=20=20 -#define SXE_DMATXCTL_VT_MASK 0xFFFF0000 +#define SXE_DMATXCTL_TE 0x1 +#define SXE_DMATXCTL_GDV 0x8 +#define SXE_DMATXCTL_VT_SHIFT 16 +#define SXE_DMATXCTL_VT_MASK 0xFFFF0000 =20 =20 #define SXE_TXDCTL_HTHRESH_SHIFT 8 #define SXE_TXDCTL_WTHRESH_SHIFT 16 -#define SXE_TXDCTL_ENABLE 0x02000000 -#define SXE_TXDCTL_SWFLSH 0x04000000 +#define SXE_TXDCTL_ENABLE 0x02000000 +#define SXE_TXDCTL_SWFLSH 0x04000000 =20 #define SXE_PVFTDWBAL_N(ring_per_pool, vf_idx, vf_ring_idx) \ SXE_PVFTDWBAL((ring_per_pool) * (vf_idx) + vf_ring_idx) @@ -470,7 +470,7 @@ #define SXE_TFCS_PB_MASK 0xff =20 =20 -#define SXE_DTXCFG_DBUTX_START 0x00000001=20=20=20 +#define SXE_DTXCFG_DBUTX_START 0x00000001 #define SXE_DTXCFG_DBUTX_BUF_ALFUL_CFG 0x20 =20 =20 @@ -494,7 +494,7 @@ =20 =20 #define SXE_RTRPT4C_MCL_SHIFT 12 -#define SXE_RTRPT4C_BWG_SHIFT 9=20 +#define SXE_RTRPT4C_BWG_SHIFT 9 #define SXE_RTRPT4C_GSP 0x40000000 #define SXE_RTRPT4C_LSP 0x80000000 =20 @@ -537,40 +537,40 @@ #define SXE_RTTPCS_ARBDIS 0x00000040 #define SXE_RTTPCS_TPRM 0x00000100 #define SXE_RTTPCS_ARBD_SHIFT 22 -#define SXE_RTTPCS_ARBD_DCB 0x4=20=20=20=20=20=20=20 +#define SXE_RTTPCS_ARBD_DCB 0x4 =20 =20 #define SXE_RTTPT2C_MCL_SHIFT 12 #define SXE_RTTPT2C_BWG_SHIFT 9 -#define SXE_RTTPT2C_GSP 0x40000000 -#define SXE_RTTPT2C_LSP 0x80000000 +#define SXE_RTTPT2C_GSP 0x40000000 +#define SXE_RTTPT2C_LSP 0x80000000 =20 =20 #define SXE_TPH_CTRL 0x11074 -#define SXE_TPH_TXCTRL(_i) (0x0600C + ((_i) * 0x40)) +#define SXE_TPH_TXCTRL(_i) (0x0600C + ((_i) * 0x40)) #define SXE_TPH_RXCTRL(_i) (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ (0x0D00C + (((_i) - 64) * 0x40))) =20 =20 #define SXE_TPH_CTRL_ENABLE 0x00000000 #define SXE_TPH_CTRL_DISABLE 0x00000001 -#define SXE_TPH_CTRL_MODE_CB1 0x00=20=20=20=20=20=20 -#define SXE_TPH_CTRL_MODE_CB2 0x02=20=20=20=20=20=20 +#define SXE_TPH_CTRL_MODE_CB1 0x00 +#define SXE_TPH_CTRL_MODE_CB2 0x02 =20 =20 -#define SXE_TPH_RXCTRL_DESC_TPH_EN BIT(5)=20 -#define SXE_TPH_RXCTRL_HEAD_TPH_EN BIT(6)=20 -#define SXE_TPH_RXCTRL_DATA_TPH_EN BIT(7)=20 -#define SXE_TPH_RXCTRL_DESC_RRO_EN BIT(9)=20 +#define SXE_TPH_RXCTRL_DESC_TPH_EN BIT(5) +#define SXE_TPH_RXCTRL_HEAD_TPH_EN BIT(6) +#define SXE_TPH_RXCTRL_DATA_TPH_EN BIT(7) +#define SXE_TPH_RXCTRL_DESC_RRO_EN BIT(9) #define SXE_TPH_RXCTRL_DATA_WRO_EN BIT(13) #define SXE_TPH_RXCTRL_HEAD_WRO_EN BIT(15) -#define SXE_TPH_RXCTRL_CPUID_SHIFT 24=20=20=20=20=20 +#define SXE_TPH_RXCTRL_CPUID_SHIFT 24 =20 -#define SXE_TPH_TXCTRL_DESC_TPH_EN BIT(5)=20 -#define SXE_TPH_TXCTRL_DESC_RRO_EN BIT(9)=20 +#define SXE_TPH_TXCTRL_DESC_TPH_EN BIT(5) +#define SXE_TPH_TXCTRL_DESC_RRO_EN BIT(9) #define SXE_TPH_TXCTRL_DESC_WRO_EN BIT(11) #define SXE_TPH_TXCTRL_DATA_RRO_EN BIT(13) -#define SXE_TPH_TXCTRL_CPUID_SHIFT 24=20=20=20=20=20 +#define SXE_TPH_TXCTRL_CPUID_SHIFT 24 =20 =20 #define SXE_SECTXCTRL 0x08800 @@ -579,18 +579,18 @@ #define SXE_SECTXMINIFG 0x08810 #define SXE_SECRXCTRL 0x08D00 #define SXE_SECRXSTAT 0x08D04 -#define SXE_LSECTXCTRL 0x08A04 -#define SXE_LSECTXSCL 0x08A08 -#define SXE_LSECTXSCH 0x08A0C -#define SXE_LSECTXSA 0x08A10 -#define SXE_LSECTXPN(_n) (0x08A14 + (4 * (_n))) -#define SXE_LSECTXKEY(_n, _m) (0x08A1C + ((0x10 * (_n)) + (4 * (_m)))) -#define SXE_LSECRXCTRL 0x08B04 -#define SXE_LSECRXSCL 0x08B08 -#define SXE_LSECRXSCH 0x08B0C -#define SXE_LSECRXSA(_i) (0x08B10 + (4 * (_i))) -#define SXE_LSECRXPN(_i) (0x08B18 + (4 * (_i))) -#define SXE_LSECRXKEY(_n, _m) (0x08B20 + ((0x10 * (_n)) + (4 * (_m))))= =20=20 +#define SXE_LSECTXCTRL 0x08A04 +#define SXE_LSECTXSCL 0x08A08 +#define SXE_LSECTXSCH 0x08A0C +#define SXE_LSECTXSA 0x08A10 +#define SXE_LSECTXPN(_n) (0x08A14 + (4 * (_n))) +#define SXE_LSECTXKEY(_n, _m) (0x08A1C + ((0x10 * (_n)) + (4 * (_m)))) +#define SXE_LSECRXCTRL 0x08B04 +#define SXE_LSECRXSCL 0x08B08 +#define SXE_LSECRXSCH 0x08B0C +#define SXE_LSECRXSA(_i) (0x08B10 + (4 * (_i))) +#define SXE_LSECRXPN(_i) (0x08B18 + (4 * (_i))) +#define SXE_LSECRXKEY(_n, _m) (0x08B20 + ((0x10 * (_n)) + (4 * (_m)))) =20 =20 #define SXE_SECTXCTRL_SECTX_DIS 0x00000001 @@ -605,7 +605,7 @@ =20 #define SXE_SECRXCTRL_SECRX_DIS 0x00000001 #define SXE_SECRXCTRL_RX_DIS 0x00000002 -#define SXE_SECRXCTRL_RP 0x00000080 +#define SXE_SECRXCTRL_RP 0x00000080 =20 =20 #define SXE_SECRXSTAT_SECRX_RDY 0x00000001 @@ -614,41 +614,41 @@ =20 #define SXE_SECTX_DCB_ENABLE_MASK 0x00001F00 =20 -#define SXE_LSECTXCTRL_EN_MASK 0x00000003 -#define SXE_LSECTXCTRL_EN_SHIFT 0 -#define SXE_LSECTXCTRL_ES 0x00000010 -#define SXE_LSECTXCTRL_AISCI 0x00000020 +#define SXE_LSECTXCTRL_EN_MASK 0x00000003 +#define SXE_LSECTXCTRL_EN_SHIFT 0 +#define SXE_LSECTXCTRL_ES 0x00000010 +#define SXE_LSECTXCTRL_AISCI 0x00000020 #define SXE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 #define SXE_LSECTXCTRL_PNTHRSH_SHIFT 8 -#define SXE_LSECTXCTRL_RSV_MASK 0x000000D8 +#define SXE_LSECTXCTRL_RSV_MASK 0x000000D8 =20 -#define SXE_LSECRXCTRL_EN_MASK 0x0000000C -#define SXE_LSECRXCTRL_EN_SHIFT 2 -#define SXE_LSECRXCTRL_DROP_EN 0x00000010 +#define SXE_LSECRXCTRL_EN_MASK 0x0000000C +#define SXE_LSECRXCTRL_EN_SHIFT 2 +#define SXE_LSECRXCTRL_DROP_EN 0x00000010 #define SXE_LSECRXCTRL_DROP_EN_SHIFT 4 -#define SXE_LSECRXCTRL_PLSH 0x00000040 -#define SXE_LSECRXCTRL_PLSH_SHIFT 6 -#define SXE_LSECRXCTRL_RP 0x00000080 -#define SXE_LSECRXCTRL_RP_SHIFT 7 -#define SXE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 - -#define SXE_LSECTXSA_AN0_MASK 0x00000003 -#define SXE_LSECTXSA_AN0_SHIFT 0 -#define SXE_LSECTXSA_AN1_MASK 0x0000000C -#define SXE_LSECTXSA_AN1_SHIFT 2 -#define SXE_LSECTXSA_SELSA 0x00000010 -#define SXE_LSECTXSA_SELSA_SHIFT 4 -#define SXE_LSECTXSA_ACTSA 0x00000020 - -#define SXE_LSECRXSA_AN_MASK 0x00000003 -#define SXE_LSECRXSA_AN_SHIFT 0 -#define SXE_LSECRXSA_SAV 0x00000004 -#define SXE_LSECRXSA_SAV_SHIFT 2 -#define SXE_LSECRXSA_RETIRED 0x00000010 -#define SXE_LSECRXSA_RETIRED_SHIFT 4 - -#define SXE_LSECRXSCH_PI_MASK 0xFFFF0000 -#define SXE_LSECRXSCH_PI_SHIFT 16 +#define SXE_LSECRXCTRL_PLSH 0x00000040 +#define SXE_LSECRXCTRL_PLSH_SHIFT 6 +#define SXE_LSECRXCTRL_RP 0x00000080 +#define SXE_LSECRXCTRL_RP_SHIFT 7 +#define SXE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 + +#define SXE_LSECTXSA_AN0_MASK 0x00000003 +#define SXE_LSECTXSA_AN0_SHIFT 0 +#define SXE_LSECTXSA_AN1_MASK 0x0000000C +#define SXE_LSECTXSA_AN1_SHIFT 2 +#define SXE_LSECTXSA_SELSA 0x00000010 +#define SXE_LSECTXSA_SELSA_SHIFT 4 +#define SXE_LSECTXSA_ACTSA 0x00000020 + +#define SXE_LSECRXSA_AN_MASK 0x00000003 +#define SXE_LSECRXSA_AN_SHIFT 0 +#define SXE_LSECRXSA_SAV 0x00000004 +#define SXE_LSECRXSA_SAV_SHIFT 2 +#define SXE_LSECRXSA_RETIRED 0x00000010 +#define SXE_LSECRXSA_RETIRED_SHIFT 4 + +#define SXE_LSECRXSCH_PI_MASK 0xFFFF0000 +#define SXE_LSECRXSCH_PI_SHIFT 16 =20 #define SXE_LSECTXCTRL_DISABLE 0x0 #define SXE_LSECTXCTRL_AUTH 0x1 @@ -658,7 +658,7 @@ #define SXE_LSECRXCTRL_CHECK 0x1 #define SXE_LSECRXCTRL_STRICT 0x2 #define SXE_LSECRXCTRL_DROP 0x3 -#define SXE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 +#define SXE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 =20 =20 =20 @@ -757,34 +757,34 @@ #define SXE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) =20 #define SXE_EPC_GPRC 0x050E0 -#define SXE_RXDGPC 0x02F50 -#define SXE_RXDGBCL 0x02F54 -#define SXE_RXDGBCH 0x02F58 -#define SXE_RXDDGPC 0x02F5C -#define SXE_RXDDGBCL 0x02F60 -#define SXE_RXDDGBCH 0x02F64 -#define SXE_RXLPBKGPC 0x02F68 -#define SXE_RXLPBKGBCL 0x02F6C -#define SXE_RXLPBKGBCH 0x02F70 -#define SXE_RXDLPBKGPC 0x02F74 -#define SXE_RXDLPBKGBCL 0x02F78 -#define SXE_RXDLPBKGBCH 0x02F7C - -#define SXE_RXTPCIN 0x02F88 -#define SXE_RXTPCOUT 0x02F8C -#define SXE_RXPRDDC 0x02F9C +#define SXE_RXDGPC 0x02F50 +#define SXE_RXDGBCL 0x02F54 +#define SXE_RXDGBCH 0x02F58 +#define SXE_RXDDGPC 0x02F5C +#define SXE_RXDDGBCL 0x02F60 +#define SXE_RXDDGBCH 0x02F64 +#define SXE_RXLPBKGPC 0x02F68 +#define SXE_RXLPBKGBCL 0x02F6C +#define SXE_RXLPBKGBCH 0x02F70 +#define SXE_RXDLPBKGPC 0x02F74 +#define SXE_RXDLPBKGBCL 0x02F78 +#define SXE_RXDLPBKGBCH 0x02F7C + +#define SXE_RXTPCIN 0x02F88 +#define SXE_RXTPCOUT 0x02F8C +#define SXE_RXPRDDC 0x02F9C =20 #define SXE_TXDGPC 0x087A0 -#define SXE_TXDGBCL 0x087A4 -#define SXE_TXDGBCH 0x087A8 -#define SXE_TXSWERR 0x087B0 -#define SXE_TXSWITCH 0x087B4 -#define SXE_TXREPEAT 0x087B8 -#define SXE_TXDESCERR 0x087BC +#define SXE_TXDGBCL 0x087A4 +#define SXE_TXDGBCH 0x087A8 +#define SXE_TXSWERR 0x087B0 +#define SXE_TXSWITCH 0x087B4 +#define SXE_TXREPEAT 0x087B8 +#define SXE_TXDESCERR 0x087BC #define SXE_MNGPRC 0x040B4 #define SXE_MNGPDC 0x040B8 -#define SXE_RQSMR(_i) (0x02300 + ((_i) * 4))=20=20=20 -#define SXE_TQSM(_i) (0x08600 + ((_i) * 4))=20=20=20 +#define SXE_RQSMR(_i) (0x02300 + ((_i) * 4)) +#define SXE_TQSM(_i) (0x08600 + ((_i) * 4)) #define SXE_QPRC(_i) (0x01030 + ((_i) * 0x40)) #define SXE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) #define SXE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) @@ -792,9 +792,9 @@ =20 #define SXE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) #define SXE_QPTC(_i) (0x08680 + ((_i) * 0x4)) -#define SXE_QBTC_L(_i) (0x08700 + ((_i) * 0x8))=20 -#define SXE_QBTC_H(_i) (0x08704 + ((_i) * 0x8))=20 -#define SXE_SSVPC 0x08780=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20 +#define SXE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) +#define SXE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) +#define SXE_SSVPC 0x08780 #define SXE_MNGPTC 0x0CF90 #define SXE_MPC(_i) (0x03FA0 + ((_i) * 4)) =20 @@ -808,91 +808,91 @@ =20 =20 =20 -#define SXE_WUC 0x05800 -#define SXE_WUFC 0x05808 -#define SXE_WUS 0x05810 -#define SXE_IP6AT(_i) (0x05880 + ((_i) * 4))=20=20=20 +#define SXE_WUC 0x05800 +#define SXE_WUFC 0x05808 +#define SXE_WUS 0x05810 +#define SXE_IP6AT(_i) (0x05880 + ((_i) * 4)) =20 =20 -#define SXE_IP6AT_CNT 4 +#define SXE_IP6AT_CNT 4 =20 =20 -#define SXE_WUC_PME_EN 0x00000002 -#define SXE_WUC_PME_STATUS 0x00000004 -#define SXE_WUC_WKEN 0x00000010 -#define SXE_WUC_APME 0x00000020 +#define SXE_WUC_PME_EN 0x00000002 +#define SXE_WUC_PME_STATUS 0x00000004 +#define SXE_WUC_WKEN 0x00000010 +#define SXE_WUC_APME 0x00000020 =20 =20 -#define SXE_WUFC_LNKC 0x00000001 -#define SXE_WUFC_MAG 0x00000002 -#define SXE_WUFC_EX 0x00000004 -#define SXE_WUFC_MC 0x00000008 -#define SXE_WUFC_BC 0x00000010 -#define SXE_WUFC_ARP 0x00000020 -#define SXE_WUFC_IPV4 0x00000040 -#define SXE_WUFC_IPV6 0x00000080 -#define SXE_WUFC_MNG 0x00000100 +#define SXE_WUFC_LNKC 0x00000001 +#define SXE_WUFC_MAG 0x00000002 +#define SXE_WUFC_EX 0x00000004 +#define SXE_WUFC_MC 0x00000008 +#define SXE_WUFC_BC 0x00000010 +#define SXE_WUFC_ARP 0x00000020 +#define SXE_WUFC_IPV4 0x00000040 +#define SXE_WUFC_IPV6 0x00000080 +#define SXE_WUFC_MNG 0x00000100 =20 =20 =20 =20 -#define SXE_TSCTRL 0x14800 -#define SXE_TSES 0x14804 -#define SXE_TSYNCTXCTL 0x14810 -#define SXE_TSYNCRXCTL 0x14820 -#define SXE_RXSTMPL 0x14824 -#define SXE_RXSTMPH 0x14828 -#define SXE_SYSTIML 0x14840 -#define SXE_SYSTIMM 0x14844 -#define SXE_SYSTIMH 0x14848 -#define SXE_TIMADJL 0x14850 -#define SXE_TIMADJH 0x14854 -#define SXE_TIMINC 0x14860 +#define SXE_TSCTRL 0x14800 +#define SXE_TSES 0x14804 +#define SXE_TSYNCTXCTL 0x14810 +#define SXE_TSYNCRXCTL 0x14820 +#define SXE_RXSTMPL 0x14824 +#define SXE_RXSTMPH 0x14828 +#define SXE_SYSTIML 0x14840 +#define SXE_SYSTIMM 0x14844 +#define SXE_SYSTIMH 0x14848 +#define SXE_TIMADJL 0x14850 +#define SXE_TIMADJH 0x14854 +#define SXE_TIMINC 0x14860 =20 =20 -#define SXE_TSYNCTXCTL_TXTT 0x0001 -#define SXE_TSYNCTXCTL_TEN 0x0010 +#define SXE_TSYNCTXCTL_TXTT 0x0001 +#define SXE_TSYNCTXCTL_TEN 0x0010 =20 =20 -#define SXE_TSYNCRXCTL_RXTT 0x0001 -#define SXE_TSYNCRXCTL_REN 0x0010 +#define SXE_TSYNCRXCTL_RXTT 0x0001 +#define SXE_TSYNCRXCTL_REN 0x0010 =20 =20 -#define SXE_TSCTRL_TSSEL 0x00001 -#define SXE_TSCTRL_TSEN 0x00002 -#define SXE_TSCTRL_VER_2 0x00010 -#define SXE_TSCTRL_ONESTEP 0x00100 -#define SXE_TSCTRL_CSEN 0x01000 -#define SXE_TSCTRL_PTYP_ALL 0x00C00 +#define SXE_TSCTRL_TSSEL 0x00001 +#define SXE_TSCTRL_TSEN 0x00002 +#define SXE_TSCTRL_VER_2 0x00010 +#define SXE_TSCTRL_ONESTEP 0x00100 +#define SXE_TSCTRL_CSEN 0x01000 +#define SXE_TSCTRL_PTYP_ALL 0x00C00 #define SXE_TSCTRL_L4_UNICAST 0x08000 =20 =20 -#define SXE_TSES_TXES 0x00200 -#define SXE_TSES_RXES 0x00800 -#define SXE_TSES_TXES_V1_SYNC 0x00000 -#define SXE_TSES_TXES_V1_DELAY_REQ 0x00100 -#define SXE_TSES_TXES_V1_ALL 0x00200 -#define SXE_TSES_RXES_V1_SYNC 0x00000 -#define SXE_TSES_RXES_V1_DELAY_REQ 0x00400 -#define SXE_TSES_RXES_V1_ALL 0x00800 -#define SXE_TSES_TXES_V2_ALL 0x00200 -#define SXE_TSES_RXES_V2_ALL 0x00800 +#define SXE_TSES_TXES 0x00200 +#define SXE_TSES_RXES 0x00800 +#define SXE_TSES_TXES_V1_SYNC 0x00000 +#define SXE_TSES_TXES_V1_DELAY_REQ 0x00100 +#define SXE_TSES_TXES_V1_ALL 0x00200 +#define SXE_TSES_RXES_V1_SYNC 0x00000 +#define SXE_TSES_RXES_V1_DELAY_REQ 0x00400 +#define SXE_TSES_RXES_V1_ALL 0x00800 +#define SXE_TSES_TXES_V2_ALL 0x00200 +#define SXE_TSES_RXES_V2_ALL 0x00800 =20 -#define SXE_IV_SNS 0 -#define SXE_IV_NS 8 -#define SXE_INCPD 0 -#define SXE_BASE_INCVAL 8 +#define SXE_IV_SNS 0 +#define SXE_IV_NS 8 +#define SXE_INCPD 0 +#define SXE_BASE_INCVAL 8 =20 =20 #define SXE_VT_CTL 0x051B0 #define SXE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) =20 #define SXE_PFMBICR(_i) (0x00710 + (4 * (_i))) -#define SXE_VFLRE(i) ((i & 1)? 0x001C0 : 0x00600) +#define SXE_VFLRE(i) ((i & 1) ? 0x001C0 : 0x00600) #define SXE_VFLREC(i) (0x00700 + (i * 4)) #define SXE_VFRE(_i) (0x051E0 + ((_i) * 4)) #define SXE_VFTE(_i) (0x08110 + ((_i) * 4)) -#define SXE_QDE (0x02F04)=20=20=20=20=20=20=20=20=20=20=20=20=20 +#define SXE_QDE (0x02F04) #define SXE_SPOOF(_i) (0x08200 + (_i) * 4) #define SXE_PFDTXGSWC 0x08220 #define SXE_VMVIR(_i) (0x08000 + ((_i) * 4)) @@ -900,7 +900,7 @@ #define SXE_VLVF(_i) (0x0F100 + ((_i) * 4)) #define SXE_VLVFB(_i) (0x0F200 + ((_i) * 4)) #define SXE_MRCTL(_i) (0x0F600 + ((_i) * 4)) -#define SXE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) +#define SXE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) #define SXE_VMRVM(_i) (0x0F630 + ((_i) * 4)) #define SXE_VMECM(_i) (0x08790 + ((_i) * 4)) #define SXE_PFMBMEM(_i) (0x13000 + (64 * (_i))) @@ -932,23 +932,23 @@ =20 =20 #define SXE_VT_CTL_DIS_DEFPL 0x20000000 -#define SXE_VT_CTL_REPLEN 0x40000000 -#define SXE_VT_CTL_VT_ENABLE 0x00000001=20 +#define SXE_VT_CTL_REPLEN 0x40000000 +#define SXE_VT_CTL_VT_ENABLE 0x00000001 #define SXE_VT_CTL_POOL_SHIFT 7 #define SXE_VT_CTL_POOL_MASK (0x3F << SXE_VT_CTL_POOL_SHIFT) =20 =20 -#define SXE_PFMAILBOX_STS 0x00000001 -#define SXE_PFMAILBOX_ACK 0x00000002 -#define SXE_PFMAILBOX_VFU 0x00000004 -#define SXE_PFMAILBOX_PFU 0x00000008 -#define SXE_PFMAILBOX_RVFU 0x00000010 +#define SXE_PFMAILBOX_STS 0x00000001 +#define SXE_PFMAILBOX_ACK 0x00000002 +#define SXE_PFMAILBOX_VFU 0x00000004 +#define SXE_PFMAILBOX_PFU 0x00000008 +#define SXE_PFMAILBOX_RVFU 0x00000010 =20 =20 -#define SXE_PFMBICR_VFREQ 0x00000001 -#define SXE_PFMBICR_VFACK 0x00010000 -#define SXE_PFMBICR_VFREQ_MASK 0x0000FFFF -#define SXE_PFMBICR_VFACK_MASK 0xFFFF0000 +#define SXE_PFMBICR_VFREQ 0x00000001 +#define SXE_PFMBICR_VFACK 0x00010000 +#define SXE_PFMBICR_VFREQ_MASK 0x0000FFFF +#define SXE_PFMBICR_VFACK_MASK 0xFFFF0000 =20 =20 #define SXE_QDE_ENABLE (0x00000001) @@ -962,7 +962,7 @@ #define SXE_SPOOF_VLAN_SHIFT (8) =20 =20 -#define SXE_PFDTXGSWC_VT_LBEN 0x1=20 +#define SXE_PFDTXGSWC_VT_LBEN 0x1 =20 =20 #define SXE_VMVIR_VLANA_DEFAULT 0x40000000 @@ -978,51 +978,51 @@ #define SXE_VMOLR_MPE 0x10000000 =20 =20 -#define SXE_VLVF_VIEN 0x80000000=20 -#define SXE_VLVF_ENTRIES 64 +#define SXE_VLVF_VIEN 0x80000000 +#define SXE_VLVF_ENTRIES 64 #define SXE_VLVF_VLANID_MASK 0x00000FFF =20 =20 -#define SXE_HDC_HOST_BASE 0x16000 -#define SXE_HDC_SW_LK (SXE_HDC_HOST_BASE + 0x00) -#define SXE_HDC_PF_LK (SXE_HDC_HOST_BASE + 0x04) -#define SXE_HDC_SW_OV (SXE_HDC_HOST_BASE + 0x08) -#define SXE_HDC_FW_OV (SXE_HDC_HOST_BASE + 0x0C) -#define SXE_HDC_PACKET_HEAD0 (SXE_HDC_HOST_BASE + 0x10) +#define SXE_HDC_HOST_BASE 0x16000 +#define SXE_HDC_SW_LK (SXE_HDC_HOST_BASE + 0x00) +#define SXE_HDC_PF_LK (SXE_HDC_HOST_BASE + 0x04) +#define SXE_HDC_SW_OV (SXE_HDC_HOST_BASE + 0x08) +#define SXE_HDC_FW_OV (SXE_HDC_HOST_BASE + 0x0C) +#define SXE_HDC_PACKET_HEAD0 (SXE_HDC_HOST_BASE + 0x10) =20 -#define SXE_HDC_PACKET_DATA0 (SXE_HDC_HOST_BASE + 0x20) +#define SXE_HDC_PACKET_DATA0 (SXE_HDC_HOST_BASE + 0x20) =20 =20 #define SXE_HDC_MSI_STATUS_REG 0x17000 -#define SXE_FW_STATUS_REG 0x17004 -#define SXE_DRV_STATUS_REG 0x17008 -#define SXE_FW_HDC_STATE_REG 0x1700C -#define SXE_R0_MAC_ADDR_RAL 0x17010 -#define SXE_R0_MAC_ADDR_RAH 0x17014 +#define SXE_FW_STATUS_REG 0x17004 +#define SXE_DRV_STATUS_REG 0x17008 +#define SXE_FW_HDC_STATE_REG 0x1700C +#define SXE_R0_MAC_ADDR_RAL 0x17010 +#define SXE_R0_MAC_ADDR_RAH 0x17014 #define SXE_CRC_STRIP_REG 0x17018 =20 =20 -#define SXE_HDC_SW_LK_BIT 0x0001 -#define SXE_HDC_PF_LK_BIT 0x0003 -#define SXE_HDC_SW_OV_BIT 0x0001 -#define SXE_HDC_FW_OV_BIT 0x0001 +#define SXE_HDC_SW_LK_BIT 0x0001 +#define SXE_HDC_PF_LK_BIT 0x0003 +#define SXE_HDC_SW_OV_BIT 0x0001 +#define SXE_HDC_FW_OV_BIT 0x0001 #define SXE_HDC_RELEASE_SW_LK 0x0000 =20 -#define SXE_HDC_LEN_TO_REG(n) (n - 1) -#define SXE_HDC_LEN_FROM_REG(n) (n + 1) +#define SXE_HDC_LEN_TO_REG(n) (n - 1) +#define SXE_HDC_LEN_FROM_REG(n) (n + 1) =20 =20 -#define SXE_RX_PKT_BUF_SIZE_SHIFT 10 -#define SXE_TX_PKT_BUF_SIZE_SHIFT 10 +#define SXE_RX_PKT_BUF_SIZE_SHIFT 10 +#define SXE_TX_PKT_BUF_SIZE_SHIFT 10 =20 -#define SXE_RXIDX_TBL_SHIFT 1 -#define SXE_RXTXIDX_IPS_EN 0x00000001 -#define SXE_RXTXIDX_IDX_SHIFT 3 -#define SXE_RXTXIDX_READ 0x40000000 -#define SXE_RXTXIDX_WRITE 0x80000000 +#define SXE_RXIDX_TBL_SHIFT 1 +#define SXE_RXTXIDX_IPS_EN 0x00000001 +#define SXE_RXTXIDX_IDX_SHIFT 3 +#define SXE_RXTXIDX_READ 0x40000000 +#define SXE_RXTXIDX_WRITE 0x80000000 =20 =20 -#define SXE_KEEP_CRC_EN 0x00000001 +#define SXE_KEEP_CRC_EN 0x00000001 =20 =20 #define SXE_VMD_CTL 0x0581C @@ -1032,208 +1032,208 @@ #define SXE_VMD_CTL_POOL_FILTER 0x00000002 =20 =20 -#define SXE_FLCTRL 0x14300 -#define SXE_PFCTOP 0x14304 -#define SXE_FCTTV0 0x14310 -#define SXE_FCTTV(_i) (SXE_FCTTV0 + ((_i) * 4)) -#define SXE_FCRTV 0x14320 -#define SXE_TFCS 0x14324 +#define SXE_FLCTRL 0x14300 +#define SXE_PFCTOP 0x14304 +#define SXE_FCTTV0 0x14310 +#define SXE_FCTTV(_i) (SXE_FCTTV0 + ((_i) * 4)) +#define SXE_FCRTV 0x14320 +#define SXE_TFCS 0x14324 =20 =20 -#define SXE_FCTRL_TFCE_MASK 0x0018 -#define SXE_FCTRL_TFCE_LFC_EN 0x0008 -#define SXE_FCTRL_TFCE_PFC_EN 0x0010 -#define SXE_FCTRL_TFCE_DPF_EN 0x0020 -#define SXE_FCTRL_RFCE_MASK 0x0300 -#define SXE_FCTRL_RFCE_LFC_EN 0x0100 -#define SXE_FCTRL_RFCE_PFC_EN 0x0200 +#define SXE_FCTRL_TFCE_MASK 0x0018 +#define SXE_FCTRL_TFCE_LFC_EN 0x0008 +#define SXE_FCTRL_TFCE_PFC_EN 0x0010 +#define SXE_FCTRL_TFCE_DPF_EN 0x0020 +#define SXE_FCTRL_RFCE_MASK 0x0300 +#define SXE_FCTRL_RFCE_LFC_EN 0x0100 +#define SXE_FCTRL_RFCE_PFC_EN 0x0200 =20 -#define SXE_FCTRL_TFCE_FCEN_MASK 0x00FF0000 -#define SXE_FCTRL_TFCE_XONE_MASK 0xFF000000 +#define SXE_FCTRL_TFCE_FCEN_MASK 0x00FF0000 +#define SXE_FCTRL_TFCE_XONE_MASK 0xFF000000 =20 =20 -#define SXE_PFCTOP_FCT 0x8808 -#define SXE_PFCTOP_FCOP_MASK 0xFFFF0000 -#define SXE_PFCTOP_FCOP_PFC 0x01010000 -#define SXE_PFCTOP_FCOP_LFC 0x00010000 +#define SXE_PFCTOP_FCT 0x8808 +#define SXE_PFCTOP_FCOP_MASK 0xFFFF0000 +#define SXE_PFCTOP_FCOP_PFC 0x01010000 +#define SXE_PFCTOP_FCOP_LFC 0x00010000 =20 =20 -#define SXE_COMCTRL 0x14400 -#define SXE_PCCTRL 0x14404 -#define SXE_LPBKCTRL 0x1440C -#define SXE_MAXFS 0x14410 -#define SXE_SACONH 0x14420 -#define SXE_SACONL 0x14424 -#define SXE_VLANCTRL 0x14430 -#define SXE_VLANID 0x14434 -#define SXE_LINKS 0x14454 -#define SXE_FPGA_SDS_STS 0x14704 -#define SXE_MSCA 0x14500 -#define SXE_MSCD 0x14504 +#define SXE_COMCTRL 0x14400 +#define SXE_PCCTRL 0x14404 +#define SXE_LPBKCTRL 0x1440C +#define SXE_MAXFS 0x14410 +#define SXE_SACONH 0x14420 +#define SXE_SACONL 0x14424 +#define SXE_VLANCTRL 0x14430 +#define SXE_VLANID 0x14434 +#define SXE_LINKS 0x14454 +#define SXE_FPGA_SDS_STS 0x14704 +#define SXE_MSCA 0x14500 +#define SXE_MSCD 0x14504 =20 -#define SXE_HLREG0 0x04240 -#define SXE_MFLCN 0x04294 -#define SXE_MACC 0x04330 +#define SXE_HLREG0 0x04240 +#define SXE_MFLCN 0x04294 +#define SXE_MACC 0x04330 =20 -#define SXE_PCS1GLSTA 0x0420C -#define SXE_MFLCN 0x04294 -#define SXE_PCS1GANA 0x04850 -#define SXE_PCS1GANLP 0x04854 +#define SXE_PCS1GLSTA 0x0420C +#define SXE_MFLCN 0x04294 +#define SXE_PCS1GANA 0x04850 +#define SXE_PCS1GANLP 0x04854 =20 =20 -#define SXE_LPBKCTRL_EN 0x00000001 +#define SXE_LPBKCTRL_EN 0x00000001 =20 =20 -#define SXE_MAC_ADDR_SACONH_SHIFT 32 -#define SXE_MAC_ADDR_SACONL_MASK 0xFFFFFFFF +#define SXE_MAC_ADDR_SACONH_SHIFT 32 +#define SXE_MAC_ADDR_SACONL_MASK 0xFFFFFFFF =20 =20 -#define SXE_PCS1GLSTA_AN_COMPLETE 0x10000 -#define SXE_PCS1GLSTA_AN_PAGE_RX 0x20000 -#define SXE_PCS1GLSTA_AN_TIMED_OUT 0x40000 +#define SXE_PCS1GLSTA_AN_COMPLETE 0x10000 +#define SXE_PCS1GLSTA_AN_PAGE_RX 0x20000 +#define SXE_PCS1GLSTA_AN_TIMED_OUT 0x40000 #define SXE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 -#define SXE_PCS1GLSTA_AN_ERROR_RWS 0x100000 - -#define SXE_PCS1GANA_SYM_PAUSE 0x100 -#define SXE_PCS1GANA_ASM_PAUSE 0x80=20 - - -#define SXE_LKSTS_PCS_LKSTS_UP 0x00000001 -#define SXE_LINK_UP_TIME 90 -#define SXE_AUTO_NEG_TIME 45 - - -#define SXE_MSCA_NP_ADDR_MASK 0x0000FFFF -#define SXE_MSCA_NP_ADDR_SHIFT 0 -#define SXE_MSCA_DEV_TYPE_MASK 0x001F0000 -#define SXE_MSCA_DEV_TYPE_SHIFT 16=20=20=20=20=20=20=20=20 -#define SXE_MSCA_PHY_ADDR_MASK 0x03E00000 -#define SXE_MSCA_PHY_ADDR_SHIFT 21=20=20=20=20=20=20=20=20 -#define SXE_MSCA_OP_CODE_MASK 0x0C000000 -#define SXE_MSCA_OP_CODE_SHIFT 26=20=20=20=20=20=20=20=20 -#define SXE_MSCA_ADDR_CYCLE 0x00000000 -#define SXE_MSCA_WRITE 0x04000000 -#define SXE_MSCA_READ 0x0C000000 -#define SXE_MSCA_READ_AUTOINC 0x08000000 -#define SXE_MSCA_ST_CODE_MASK 0x30000000 -#define SXE_MSCA_ST_CODE_SHIFT 28=20=20=20=20=20=20=20=20 -#define SXE_MSCA_NEW_PROTOCOL 0x00000000 -#define SXE_MSCA_OLD_PROTOCOL 0x10000000 -#define SXE_MSCA_BYPASSRA_C45 0x40000000 +#define SXE_PCS1GLSTA_AN_ERROR_RWS 0x100000 + +#define SXE_PCS1GANA_SYM_PAUSE 0x100 +#define SXE_PCS1GANA_ASM_PAUSE 0x80 + + +#define SXE_LKSTS_PCS_LKSTS_UP 0x00000001 +#define SXE_LINK_UP_TIME 90 +#define SXE_AUTO_NEG_TIME 45 + + +#define SXE_MSCA_NP_ADDR_MASK 0x0000FFFF +#define SXE_MSCA_NP_ADDR_SHIFT 0 +#define SXE_MSCA_DEV_TYPE_MASK 0x001F0000 +#define SXE_MSCA_DEV_TYPE_SHIFT 16 +#define SXE_MSCA_PHY_ADDR_MASK 0x03E00000 +#define SXE_MSCA_PHY_ADDR_SHIFT 21 +#define SXE_MSCA_OP_CODE_MASK 0x0C000000 +#define SXE_MSCA_OP_CODE_SHIFT 26 +#define SXE_MSCA_ADDR_CYCLE 0x00000000 +#define SXE_MSCA_WRITE 0x04000000 +#define SXE_MSCA_READ 0x0C000000 +#define SXE_MSCA_READ_AUTOINC 0x08000000 +#define SXE_MSCA_ST_CODE_MASK 0x30000000 +#define SXE_MSCA_ST_CODE_SHIFT 28 +#define SXE_MSCA_NEW_PROTOCOL 0x00000000 +#define SXE_MSCA_OLD_PROTOCOL 0x10000000 +#define SXE_MSCA_BYPASSRA_C45 0x40000000 #define SXE_MSCA_MDI_CMD_ON_PROG 0x80000000 =20 =20 -#define MDIO_MSCD_RDATA_LEN 16 -#define MDIO_MSCD_RDATA_SHIFT 16 - - -#define SXE_CRCERRS 0x14A04 -#define SXE_ERRBC 0x14A10 -#define SXE_RLEC 0x14A14 -#define SXE_PRC64 0x14A18 -#define SXE_PRC127 0x14A1C -#define SXE_PRC255 0x14A20 -#define SXE_PRC511 0x14A24 -#define SXE_PRC1023 0x14A28 -#define SXE_PRC1522 0x14A2C -#define SXE_BPRC 0x14A30 -#define SXE_MPRC 0x14A34 -#define SXE_GPRC 0x14A38 -#define SXE_GORCL 0x14A3C -#define SXE_GORCH 0x14A40 -#define SXE_RUC 0x14A44 -#define SXE_RFC 0x14A48 -#define SXE_ROC 0x14A4C -#define SXE_RJC 0x14A50 -#define SXE_TORL 0x14A54 -#define SXE_TORH 0x14A58 -#define SXE_TPR 0x14A5C -#define SXE_PRCPF(_i) (0x14A60 + ((_i) * 4)) -#define SXE_GPTC 0x14B00 -#define SXE_GOTCL 0x14B04 -#define SXE_GOTCH 0x14B08 -#define SXE_TPT 0x14B0C -#define SXE_PTC64 0x14B10 -#define SXE_PTC127 0x14B14 -#define SXE_PTC255 0x14B18 -#define SXE_PTC511 0x14B1C -#define SXE_PTC1023 0x14B20 -#define SXE_PTC1522 0x14B24 -#define SXE_MPTC 0x14B28 -#define SXE_BPTC 0x14B2C -#define SXE_PFCT(_i) (0x14B30 + ((_i) * 4)) - -#define SXE_MACCFG 0x0CE04 -#define SXE_MACCFG_PAD_EN 0x00000001 - - -#define SXE_COMCTRL_TXEN 0x0001=20=20=20=20=20=20=20=20 -#define SXE_COMCTRL_RXEN 0x0002=20=20=20=20=20=20=20=20 -#define SXE_COMCTRL_EDSEL 0x0004=20=20=20=20=20=20=20=20 -#define SXE_COMCTRL_SPEED_1G 0x0200=20=20=20=20=20=20=20=20 -#define SXE_COMCTRL_SPEED_10G 0x0300=20=20=20=20=20=20=20=20 - - -#define SXE_PCCTRL_TXCE 0x0001=20=20=20=20=20=20=20=20 -#define SXE_PCCTRL_RXCE 0x0002=20=20=20=20=20=20=20=20 -#define SXE_PCCTRL_PEN 0x0100=20=20=20=20=20=20=20=20 -#define SXE_PCCTRL_PCSC_ALL 0x30000=20=20=20=20=20=20=20 - - -#define SXE_MAXFS_TFSEL 0x0001=20=20=20=20=20=20=20=20 -#define SXE_MAXFS_RFSEL 0x0002=20=20=20=20=20=20=20=20 -#define SXE_MAXFS_MFS_MASK 0xFFFF0000=20=20=20=20 -#define SXE_MAXFS_MFS 0x40000000=20=20=20=20 -#define SXE_MAXFS_MFS_SHIFT 16=20=20=20=20=20=20=20=20=20=20=20=20 - - -#define SXE_LINKS_UP 0x00000001=20=20=20=20 - -#define SXE_10G_LINKS_DOWN 0x00000006 - - -#define SXE_LINK_SPEED_UNKNOWN 0=20=20=20=20=20=20=20=20=20=20=20= =20=20 -#define SXE_LINK_SPEED_10_FULL 0x0002=20=20=20=20=20=20=20=20 -#define SXE_LINK_SPEED_100_FULL 0x0008=20=20=20=20=20=20=20=20 -#define SXE_LINK_SPEED_1GB_FULL 0x0020=20=20=20=20=20=20=20=20 -#define SXE_LINK_SPEED_10GB_FULL 0x0080=20=20=20=20=20=20=20=20 - - -#define SXE_HLREG0_TXCRCEN 0x00000001=20=20 -#define SXE_HLREG0_RXCRCSTRP 0x00000002=20=20 -#define SXE_HLREG0_JUMBOEN 0x00000004=20=20 -#define SXE_HLREG0_TXPADEN 0x00000400=20=20 -#define SXE_HLREG0_TXPAUSEEN 0x00001000=20=20 -#define SXE_HLREG0_RXPAUSEEN 0x00004000=20=20 -#define SXE_HLREG0_LPBK 0x00008000=20=20 -#define SXE_HLREG0_MDCSPD 0x00010000=20=20 -#define SXE_HLREG0_CONTMDC 0x00020000=20=20 -#define SXE_HLREG0_CTRLFLTR 0x00040000=20=20 -#define SXE_HLREG0_PREPEND 0x00F00000=20=20 -#define SXE_HLREG0_PRIPAUSEEN 0x01000000=20=20 -#define SXE_HLREG0_RXPAUSERECDA 0x06000000=20=20 -#define SXE_HLREG0_RXLNGTHERREN 0x08000000=20=20 -#define SXE_HLREG0_RXPADSTRIPEN 0x10000000=20=20 - -#define SXE_MFLCN_PMCF 0x00000001=20=20 -#define SXE_MFLCN_DPF 0x00000002=20=20 -#define SXE_MFLCN_RPFCE 0x00000004=20=20 -#define SXE_MFLCN_RFCE 0x00000008=20=20 -#define SXE_MFLCN_RPFCE_MASK 0x00000FF4=20=20 -#define SXE_MFLCN_RPFCE_SHIFT 4 - -#define SXE_MACC_FLU 0x00000001 -#define SXE_MACC_FSV_10G 0x00030000 -#define SXE_MACC_FS 0x00040000 - -#define SXE_DEFAULT_FCPAUSE 0xFFFF - - -#define SXE_SAQF(_i) (0x0E000 + ((_i) * 4))=20 -#define SXE_DAQF(_i) (0x0E200 + ((_i) * 4))=20 -#define SXE_SDPQF(_i) (0x0E400 + ((_i) * 4))=20 -#define SXE_FTQF(_i) (0x0E600 + ((_i) * 4))=20 -#define SXE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4))=20 +#define MDIO_MSCD_RDATA_LEN 16 +#define MDIO_MSCD_RDATA_SHIFT 16 + + +#define SXE_CRCERRS 0x14A04 +#define SXE_ERRBC 0x14A10 +#define SXE_RLEC 0x14A14 +#define SXE_PRC64 0x14A18 +#define SXE_PRC127 0x14A1C +#define SXE_PRC255 0x14A20 +#define SXE_PRC511 0x14A24 +#define SXE_PRC1023 0x14A28 +#define SXE_PRC1522 0x14A2C +#define SXE_BPRC 0x14A30 +#define SXE_MPRC 0x14A34 +#define SXE_GPRC 0x14A38 +#define SXE_GORCL 0x14A3C +#define SXE_GORCH 0x14A40 +#define SXE_RUC 0x14A44 +#define SXE_RFC 0x14A48 +#define SXE_ROC 0x14A4C +#define SXE_RJC 0x14A50 +#define SXE_TORL 0x14A54 +#define SXE_TORH 0x14A58 +#define SXE_TPR 0x14A5C +#define SXE_PRCPF(_i) (0x14A60 + ((_i) * 4)) +#define SXE_GPTC 0x14B00 +#define SXE_GOTCL 0x14B04 +#define SXE_GOTCH 0x14B08 +#define SXE_TPT 0x14B0C +#define SXE_PTC64 0x14B10 +#define SXE_PTC127 0x14B14 +#define SXE_PTC255 0x14B18 +#define SXE_PTC511 0x14B1C +#define SXE_PTC1023 0x14B20 +#define SXE_PTC1522 0x14B24 +#define SXE_MPTC 0x14B28 +#define SXE_BPTC 0x14B2C +#define SXE_PFCT(_i) (0x14B30 + ((_i) * 4)) + +#define SXE_MACCFG 0x0CE04 +#define SXE_MACCFG_PAD_EN 0x00000001 + + +#define SXE_COMCTRL_TXEN 0x0001 +#define SXE_COMCTRL_RXEN 0x0002 +#define SXE_COMCTRL_EDSEL 0x0004 +#define SXE_COMCTRL_SPEED_1G 0x0200 +#define SXE_COMCTRL_SPEED_10G 0x0300 + + +#define SXE_PCCTRL_TXCE 0x0001 +#define SXE_PCCTRL_RXCE 0x0002 +#define SXE_PCCTRL_PEN 0x0100 +#define SXE_PCCTRL_PCSC_ALL 0x30000 + + +#define SXE_MAXFS_TFSEL 0x0001 +#define SXE_MAXFS_RFSEL 0x0002 +#define SXE_MAXFS_MFS_MASK 0xFFFF0000 +#define SXE_MAXFS_MFS 0x40000000 +#define SXE_MAXFS_MFS_SHIFT 16 + + +#define SXE_LINKS_UP 0x00000001 + +#define SXE_10G_LINKS_DOWN 0x00000006 + + +#define SXE_LINK_SPEED_UNKNOWN 0 +#define SXE_LINK_SPEED_10_FULL 0x0002 +#define SXE_LINK_SPEED_100_FULL 0x0008 +#define SXE_LINK_SPEED_1GB_FULL 0x0020 +#define SXE_LINK_SPEED_10GB_FULL 0x0080 + + +#define SXE_HLREG0_TXCRCEN 0x00000001 +#define SXE_HLREG0_RXCRCSTRP 0x00000002 +#define SXE_HLREG0_JUMBOEN 0x00000004 +#define SXE_HLREG0_TXPADEN 0x00000400 +#define SXE_HLREG0_TXPAUSEEN 0x00001000 +#define SXE_HLREG0_RXPAUSEEN 0x00004000 +#define SXE_HLREG0_LPBK 0x00008000 +#define SXE_HLREG0_MDCSPD 0x00010000 +#define SXE_HLREG0_CONTMDC 0x00020000 +#define SXE_HLREG0_CTRLFLTR 0x00040000 +#define SXE_HLREG0_PREPEND 0x00F00000 +#define SXE_HLREG0_PRIPAUSEEN 0x01000000 +#define SXE_HLREG0_RXPAUSERECDA 0x06000000 +#define SXE_HLREG0_RXLNGTHERREN 0x08000000 +#define SXE_HLREG0_RXPADSTRIPEN 0x10000000 + +#define SXE_MFLCN_PMCF 0x00000001 +#define SXE_MFLCN_DPF 0x00000002 +#define SXE_MFLCN_RPFCE 0x00000004 +#define SXE_MFLCN_RFCE 0x00000008 +#define SXE_MFLCN_RPFCE_MASK 0x00000FF4 +#define SXE_MFLCN_RPFCE_SHIFT 4 + +#define SXE_MACC_FLU 0x00000001 +#define SXE_MACC_FSV_10G 0x00030000 +#define SXE_MACC_FS 0x00040000 + +#define SXE_DEFAULT_FCPAUSE 0xFFFF + + +#define SXE_SAQF(_i) (0x0E000 + ((_i) * 4)) +#define SXE_DAQF(_i) (0x0E200 + ((_i) * 4)) +#define SXE_SDPQF(_i) (0x0E400 + ((_i) * 4)) +#define SXE_FTQF(_i) (0x0E600 + ((_i) * 4)) +#define SXE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) =20 #define SXE_MAX_FTQF_FILTERS 128 #define SXE_FTQF_PROTOCOL_MASK 0x00000003 @@ -1264,11 +1264,11 @@ #define SXE_L34T_IMIR_QUEUE 0x0FE00000 #define SXE_L34T_IMIR_QUEUE_SHIFT 21 =20 -#define SXE_VMTXSW(_i) (0x05180 + ((_i) * 4))=20=20=20 -#define SXE_VMTXSW_REGISTER_COUNT 2 +#define SXE_VMTXSW(_i) (0x05180 + ((_i) * 4)) +#define SXE_VMTXSW_REGISTER_COUNT 2 =20 -#define SXE_TXSTMP_SEL 0x14510=20=20 -#define SXE_TXSTMP_VAL 0x1451c=20=20 +#define SXE_TXSTMP_SEL 0x14510 +#define SXE_TXSTMP_VAL 0x1451c =20 #define SXE_TXTS_MAGIC0 0x005a005900580057 #define SXE_TXTS_MAGIC1 0x005e005d005c005b diff --git a/drivers/net/sxe/include/sxe_type.h b/drivers/net/sxe/include/s= xe_type.h index 433385a0c9..d416632c3f 100644 --- a/drivers/net/sxe/include/sxe_type.h +++ b/drivers/net/sxe/include/sxe_type.h @@ -5,69 +5,69 @@ #ifndef __SXE_TYPE_H__ #define __SXE_TYPE_H__ =20 -#define SXE_TXD_CMD_EOP 0x01000000=20=20 -#define SXE_TXD_CMD_RS 0x08000000=20=20 -#define SXE_TXD_STAT_DD 0x00000001=20=20 +#define SXE_TXD_CMD_EOP 0x01000000 +#define SXE_TXD_CMD_RS 0x08000000 +#define SXE_TXD_STAT_DD 0x00000001 =20 -#define SXE_TXD_CMD (SXE_TXD_CMD_EOP | SXE_TXD_CMD_RS) +#define SXE_TXD_CMD (SXE_TXD_CMD_EOP | SXE_TXD_CMD_RS) =20 =20 typedef union sxe_adv_tx_desc { - struct { - U64 buffer_addr; - U32 cmd_type_len; - U32 olinfo_status; - } read; - struct { - U64 rsvd; - U32 nxtseq_seed; - U32 status; - } wb; -}sxe_adv_tx_desc_u; + struct { + U64 buffer_addr; + U32 cmd_type_len; + U32 olinfo_status; + } read; + struct { + U64 rsvd; + U32 nxtseq_seed; + U32 status; + } wb; +} sxe_adv_tx_desc_u; =20 typedef union sxe_adv_rx_desc { - struct { - U64 pkt_addr; - U64 hdr_addr; - } read; - struct { - struct { - union { - U32 data; - struct { - U16 pkt_info; - U16 hdr_info; - } hs_rss; - } lo_dword; - union { - U32 rss; - struct { - U16 ip_id; - U16 csum; - } csum_ip; - }hi_dword; - } lower; - struct { - U32 status_error; - U16 length; - U16 vlan; - } upper; - } wb; -}sxe_adv_rx_desc_u; - -#define SXE_RXD_STAT_DD 0x01=20=20 -#define SXE_RXD_STAT_EOP 0x02=20=20 + struct { + U64 pkt_addr; + U64 hdr_addr; + } read; + struct { + struct { + union { + U32 data; + struct { + U16 pkt_info; + U16 hdr_info; + } hs_rss; + } lo_dword; + union { + U32 rss; + struct { + U16 ip_id; + U16 csum; + } csum_ip; + } hi_dword; + } lower; + struct { + U32 status_error; + U16 length; + U16 vlan; + } upper; + } wb; +} sxe_adv_rx_desc_u; + +#define SXE_RXD_STAT_DD 0x01 +#define SXE_RXD_STAT_EOP 0x02 =20 =20 #define PCI_VENDOR_ID_STARS 0x1FF2 #define SXE_DEV_ID_FPGA 0x1160 =20 =20 -#define SXE_CTRL 0x00000 -#define SXE_STATUS 0x00008 +#define SXE_CTRL 0x00000 +#define SXE_STATUS 0x00008 #define SXE_CTRL_EXT 0x00018 -#define SXE_ESDP 0x00020 -#define SXE_EODSDP 0x00028 +#define SXE_ESDP 0x00020 +#define SXE_EODSDP 0x00028 =20 #define SXE_I2CCTL_8259X 0x00028 #define SXE_I2CCTL_X540 SXE_I2CCTL_8259X @@ -76,19 +76,19 @@ typedef union sxe_adv_rx_desc { #define SXE_I2CCTL_X550EM_a SXE_I2CCTL_X550 #define SXE_I2CCTL(_hw) SXE_BY_MAC((_hw), I2CCTL) =20 -#define SXE_LEDCTL 0x00200 +#define SXE_LEDCTL 0x00200 #define SXE_FRTIMER 0x00048 #define SXE_TCPTIMER 0x0004C #define SXE_CORESPARE 0x00600 -#define SXE_EXVET 0x05078 +#define SXE_EXVET 0x05078 =20 =20 -#define SXE_EICR 0x00800 -#define SXE_EICS 0x00808 -#define SXE_EIMS 0x00880 -#define SXE_EIMC 0x00888 -#define SXE_EIAC 0x00810 -#define SXE_EIAM 0x00890 +#define SXE_EICR 0x00800 +#define SXE_EICS 0x00808 +#define SXE_EIMS 0x00880 +#define SXE_EIMC 0x00888 +#define SXE_EIAC 0x00810 +#define SXE_EIAM 0x00890 #define SXE_EICR_EX(_i) (0x00A80 + (_i) * 4) #define SXE_EICS_EX(_i) (0x00A90 + (_i) * 4) #define SXE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) @@ -110,26 +110,28 @@ typedef union sxe_adv_rx_desc { (0x0D028 + (((_i) - 64) * 0x40))) #define SXE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ (0x0D02C + (((_i) - 64) * 0x40))) -#define SXE_RSCDBU 0x03028 -#define SXE_RDDCC 0x02F20 +#define SXE_RSCDBU 0x03028 +#define SXE_RDDCC 0x02F20 #define SXE_RXMEMWRAP 0x03190 #define SXE_STARCTRL 0x03024 =20 #define SXE_SRRCTL(_i) (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : (0x0D014= + (((_i) - 64) * 0x40))) =20 -#define SXE_DCA_RXCTRL(_i) (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : (= 0x0D00C + (((_i) - 64) * 0x40))) -#define SXE_RDRXCTL 0x02F00 -#define SXE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))=20=20=20=20 +#define SXE_DCA_RXCTRL(_i) (((_i) < 64) ? \ + (0x0100C + ((_i) * 0x40)) : \ + (0x0D00C + (((_i) - 64) * 0x40))) +#define SXE_RDRXCTL 0x02F00 +#define SXE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) #define SXE_DRXCFG 0x03C20 -#define SXE_RXCTRL 0x03000 -#define SXE_DROPEN 0x03D04 +#define SXE_RXCTRL 0x03000 +#define SXE_DROPEN 0x03D04 #define SXE_RXPBSIZE_SHIFT 10 -#define SXE_DRXCFG_GSP_ZERO 0x00000002 +#define SXE_DRXCFG_GSP_ZERO 0x00000002 #define SXE_DRXCFG_DBURX_START 0x00000001 =20 =20 -#define SXE_RXCSUM 0x05000 -#define SXE_RFCTL 0x05008 +#define SXE_RXCSUM 0x05000 +#define SXE_RFCTL 0x05008 #define SXE_DRECCCTL 0x02F08 #define SXE_DRECCCTL_DISABLE 0 =20 @@ -141,61 +143,61 @@ typedef union sxe_adv_rx_desc { #define SXE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) =20 =20 -#define SXE_PSRTYPE(_i) (0x0EA00 + ((_i) * 4)) +#define SXE_PSRTYPE(_i) (0x0EA00 + ((_i) * 4)) =20 =20 #define SXE_VFTA(_i) (0x0A000 + ((_i) * 4)) =20 =20 #define SXE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) -#define SXE_FCTRL 0x05080 +#define SXE_FCTRL 0x05080 #define SXE_VLNCTRL 0x05088 #define SXE_MCSTCTRL 0x05090 -#define SXE_MRQC 0x0EC80 -#define SXE_SAQF(_i) (0x0E000 + ((_i) * 4))=20 -#define SXE_DAQF(_i) (0x0E200 + ((_i) * 4))=20 -#define SXE_SDPQF(_i) (0x0E400 + ((_i) * 4))=20 -#define SXE_FTQF(_i) (0x0E600 + ((_i) * 4))=20 -#define SXE_ETQF(_i) (0x05128 + ((_i) * 4))=20 -#define SXE_ETQS(_i) (0x0EC00 + ((_i) * 4))=20 -#define SXE_SYNQF 0x0EC30=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20 -#define SXE_RQTC 0x0EC70 -#define SXE_MTQC 0x08120 -#define SXE_VLVF(_i) (0x0F100 + ((_i) * 4))=20 -#define SXE_VLVFB(_i) (0x0F200 + ((_i) * 4))=20 -#define SXE_VMVIR(_i) (0x08000 + ((_i) * 4))=20 -#define SXE_PFFLPL 0x050B0 -#define SXE_PFFLPH 0x050B4 -#define SXE_VT_CTL 0x051B0 -#define SXE_PFMAILBOX(_i) (0x04B00 + (4 * (_i)))=20=20=20 -#define SXE_PFMBMEM(_i) (0x13000 + (64 * (_i)))=20=20 -#define SXE_PFMBICR(_i) (0x00710 + (4 * (_i)))=20=20=20 -#define SXE_PFMBIMR(_i) (0x00720 + (4 * (_i)))=20=20=20 -#define SXE_VFRE(_i) (0x051E0 + ((_i) * 4)) -#define SXE_VFTE(_i) (0x08110 + ((_i) * 4)) -#define SXE_VMECM(_i) (0x08790 + ((_i) * 4)) -#define SXE_QDE 0x2F04 -#define SXE_VMTXSW(_i) (0x05180 + ((_i) * 4))=20=20=20 -#define SXE_VMOLR(_i) (0x0F000 + ((_i) * 4))=20=20=20=20 -#define SXE_UTA(_i) (0x0F400 + ((_i) * 4)) -#define SXE_MRCTL(_i) (0x0F600 + ((_i) * 4)) -#define SXE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) -#define SXE_VMRVM(_i) (0x0F630 + ((_i) * 4)) -#define SXE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4))=20=20=20=20 -#define SXE_WQBR_TX(_i) (0x8130 + ((_i) * 4))=20=20=20=20 -#define SXE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4))=20=20=20 -#define SXE_RXFECCERR0 0x051B8 +#define SXE_MRQC 0x0EC80 +#define SXE_SAQF(_i) (0x0E000 + ((_i) * 4)) +#define SXE_DAQF(_i) (0x0E200 + ((_i) * 4)) +#define SXE_SDPQF(_i) (0x0E400 + ((_i) * 4)) +#define SXE_FTQF(_i) (0x0E600 + ((_i) * 4)) +#define SXE_ETQF(_i) (0x05128 + ((_i) * 4)) +#define SXE_ETQS(_i) (0x0EC00 + ((_i) * 4)) +#define SXE_SYNQF 0x0EC30 +#define SXE_RQTC 0x0EC70 +#define SXE_MTQC 0x08120 +#define SXE_VLVF(_i) (0x0F100 + ((_i) * 4)) +#define SXE_VLVFB(_i) (0x0F200 + ((_i) * 4)) +#define SXE_VMVIR(_i) (0x08000 + ((_i) * 4)) +#define SXE_PFFLPL 0x050B0 +#define SXE_PFFLPH 0x050B4 +#define SXE_VT_CTL 0x051B0 +#define SXE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) +#define SXE_PFMBMEM(_i) (0x13000 + (64 * (_i))) +#define SXE_PFMBICR(_i) (0x00710 + (4 * (_i))) +#define SXE_PFMBIMR(_i) (0x00720 + (4 * (_i))) +#define SXE_VFRE(_i) (0x051E0 + ((_i) * 4)) +#define SXE_VFTE(_i) (0x08110 + ((_i) * 4)) +#define SXE_VMECM(_i) (0x08790 + ((_i) * 4)) +#define SXE_QDE 0x2F04 +#define SXE_VMTXSW(_i) (0x05180 + ((_i) * 4)) +#define SXE_VMOLR(_i) (0x0F000 + ((_i) * 4)) +#define SXE_UTA(_i) (0x0F400 + ((_i) * 4)) +#define SXE_MRCTL(_i) (0x0F600 + ((_i) * 4)) +#define SXE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) +#define SXE_VMRVM(_i) (0x0F630 + ((_i) * 4)) +#define SXE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4)) +#define SXE_WQBR_TX(_i) (0x8130 + ((_i) * 4)) +#define SXE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) +#define SXE_RXFECCERR0 0x051B8 #define SXE_LLITHRESH 0x0EC90 -#define SXE_IMIR(_i) (0x05A80 + ((_i) * 4))=20=20=20=20=20=20=20=20=20 -#define SXE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) -#define SXE_IMIRVP 0x0EC60 +#define SXE_IMIR(_i) (0x05A80 + ((_i) * 4)) +#define SXE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) +#define SXE_IMIRVP 0x0EC60 #define SXE_VMD_CTL 0x0581C -#define SXE_RETA(_i) (0x0EB00 + ((_i) * 4))=20=20=20=20=20=20=20=20 -#define SXE_ERETA(_i) (0x0EE80 + ((_i) * 4))=20=20=20=20=20 -#define SXE_RSSRK(_i) (0x0EB80 + ((_i) * 4))=20=20=20=20=20=20=20 +#define SXE_RETA(_i) (0x0EB00 + ((_i) * 4)) +#define SXE_ERETA(_i) (0x0EE80 + ((_i) * 4)) +#define SXE_RSSRK(_i) (0x0EB80 + ((_i) * 4)) =20 =20 -#define SXE_TDBAL(_i) (0x06000 + ((_i) * 0x40))=20=20 +#define SXE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) #define SXE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) #define SXE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) #define SXE_TDH(_i) (0x06010 + ((_i) * 0x40)) @@ -203,82 +205,82 @@ typedef union sxe_adv_rx_desc { #define SXE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) #define SXE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) #define SXE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) -#define SXE_DTXCTL 0x07E00 +#define SXE_DTXCTL 0x07E00 =20 -#define SXE_DMATXCTL 0x04A80 -#define SXE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4))=20=20 -#define SXE_PFDTXGSWC 0x08220 -#define SXE_DTXMXSZRQ 0x08100 -#define SXE_DTXTCPFLGL 0x04A88 -#define SXE_DTXTCPFLGH 0x04A8C -#define SXE_LBDRPEN 0x0CA00 -#define SXE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4))=20=20 +#define SXE_DMATXCTL 0x04A80 +#define SXE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) +#define SXE_PFDTXGSWC 0x08220 +#define SXE_DTXMXSZRQ 0x08100 +#define SXE_DTXTCPFLGL 0x04A88 +#define SXE_DTXTCPFLGH 0x04A8C +#define SXE_LBDRPEN 0x0CA00 +#define SXE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) =20 -#define SXE_DMATXCTL_TE 0x1=20=20=20 -#define SXE_DMATXCTL_NS 0x2=20=20=20 -#define SXE_DMATXCTL_GDV 0x8=20=20=20 -#define SXE_DMATXCTL_MDP_EN 0x20=20=20 -#define SXE_DMATXCTL_MBINTEN 0x40=20=20 -#define SXE_DMATXCTL_VT_SHIFT 16=20=20=20=20 +#define SXE_DMATXCTL_TE 0x1 +#define SXE_DMATXCTL_NS 0x2 +#define SXE_DMATXCTL_GDV 0x8 +#define SXE_DMATXCTL_MDP_EN 0x20 +#define SXE_DMATXCTL_MBINTEN 0x40 +#define SXE_DMATXCTL_VT_SHIFT 16 =20 -#define SXE_PFDTXGSWC_VT_LBEN 0x1=20=20=20 +#define SXE_PFDTXGSWC_VT_LBEN 0x1 =20 =20 #define SXE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) -#define SXE_TIPG 0x0CB00 -#define SXE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4))=20=20 +#define SXE_TIPG 0x0CB00 +#define SXE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) #define SXE_DTXCFG 0x0CE08 #define SXE_MNGTXMAP 0x0CD10 #define SXE_TIPG_FIBER_DEFAULT 3 -#define SXE_TXPBSIZE_SHIFT 10 +#define SXE_TXPBSIZE_SHIFT 10 #define SXE_DTXCFG_DBUTX_START 0x00000001 =20 =20 -#define SXE_RTRPCS 0x02430 -#define SXE_RTTDCS 0x04900 -#define SXE_RTTDCS_ARBDIS 0x00000040=20=20=20 -#define SXE_RTTPCS 0x0CD00 -#define SXE_RTRUP2TC 0x03020 -#define SXE_RTTUP2TC 0x0C800 -#define SXE_RTRPT4C(_i) (0x02140 + ((_i) * 4))=20=20 -#define SXE_TXLLQ(_i) (0x082E0 + ((_i) * 4))=20=20 -#define SXE_RTRPT4S(_i) (0x02160 + ((_i) * 4))=20=20 -#define SXE_RTTDT2C(_i) (0x04910 + ((_i) * 4))=20=20 -#define SXE_RTTDT2S(_i) (0x04930 + ((_i) * 4))=20=20 -#define SXE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4))=20=20 -#define SXE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4))=20=20 -#define SXE_RTTDQSEL 0x04904 -#define SXE_RTTDT1C 0x04908 -#define SXE_RTTDT1S 0x0490C - - -#define SXE_RTTQCNCR 0x08B00 -#define SXE_RTTQCNTG 0x04A90 -#define SXE_RTTBCNRD 0x0498C -#define SXE_RTTQCNRR 0x0498C -#define SXE_RTTDTECC 0x04990 -#define SXE_RTTDTECC_NO_BCN 0x00000100 -#define SXE_RTTBCNRC 0x04984 -#define SXE_RTTBCNRC_RS_ENA 0x80000000 -#define SXE_RTTBCNRC_RF_DEC_MASK 0x00003FFF +#define SXE_RTRPCS 0x02430 +#define SXE_RTTDCS 0x04900 +#define SXE_RTTDCS_ARBDIS 0x00000040 +#define SXE_RTTPCS 0x0CD00 +#define SXE_RTRUP2TC 0x03020 +#define SXE_RTTUP2TC 0x0C800 +#define SXE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) +#define SXE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) +#define SXE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) +#define SXE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) +#define SXE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) +#define SXE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) +#define SXE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) +#define SXE_RTTDQSEL 0x04904 +#define SXE_RTTDT1C 0x04908 +#define SXE_RTTDT1S 0x0490C + + +#define SXE_RTTQCNCR 0x08B00 +#define SXE_RTTQCNTG 0x04A90 +#define SXE_RTTBCNRD 0x0498C +#define SXE_RTTQCNRR 0x0498C +#define SXE_RTTDTECC 0x04990 +#define SXE_RTTDTECC_NO_BCN 0x00000100 +#define SXE_RTTBCNRC 0x04984 +#define SXE_RTTBCNRC_RS_ENA 0x80000000 +#define SXE_RTTBCNRC_RF_DEC_MASK 0x00003FFF #define SXE_RTTBCNRC_RF_INT_SHIFT 14 -#define SXE_RTTBCNRC_RF_INT_MASK (SXE_RTTBCNRC_RF_DEC_MASK << SXE_RTTBC= NRC_RF_INT_SHIFT) -#define SXE_RTTBCNRM 0x04980 -#define SXE_RTTQCNRM 0x04980 +#define SXE_RTTBCNRC_RF_INT_MASK (SXE_RTTBCNRC_RF_DEC_MASK << SXE_RTTBCNRC= _RF_INT_SHIFT) +#define SXE_RTTBCNRM 0x04980 +#define SXE_RTTQCNRM 0x04980 =20 =20 -#define SXE_MACCFG 0x0CE04 +#define SXE_MACCFG 0x0CE04 =20 =20 -#define SXE_GCR_EXT 0x11050 -#define SXE_GSCL_5_82599 0x11030 -#define SXE_GSCL_6_82599 0x11034 -#define SXE_GSCL_7_82599 0x11038 -#define SXE_GSCL_8_82599 0x1103C -#define SXE_PHYADR_82599 0x11040 -#define SXE_PHYDAT_82599 0x11044 -#define SXE_PHYCTL_82599 0x11048 -#define SXE_PBACLR_82599 0x11068 +#define SXE_GCR_EXT 0x11050 +#define SXE_GSCL_5_82599 0x11030 +#define SXE_GSCL_6_82599 0x11034 +#define SXE_GSCL_7_82599 0x11038 +#define SXE_GSCL_8_82599 0x1103C +#define SXE_PHYADR_82599 0x11040 +#define SXE_PHYDAT_82599 0x11044 +#define SXE_PHYCTL_82599 0x11048 +#define SXE_PBACLR_82599 0x11068 =20 #define SXE_CIAA_8259X 0x11088 =20 @@ -286,28 +288,28 @@ typedef union sxe_adv_rx_desc { #define SXE_CIAD_8259X 0x1108C =20 =20 -#define SXE_PICAUSE 0x110B0 -#define SXE_PIENA 0x110B8 -#define SXE_CDQ_MBR_82599 0x110B4 -#define SXE_PCIESPARE 0x110BC -#define SXE_MISC_REG_82599 0x110F0 +#define SXE_PICAUSE 0x110B0 +#define SXE_PIENA 0x110B8 +#define SXE_CDQ_MBR_82599 0x110B4 +#define SXE_PCIESPARE 0x110BC +#define SXE_MISC_REG_82599 0x110F0 #define SXE_ECC_CTRL_0_82599 0x11100 #define SXE_ECC_CTRL_1_82599 0x11104 #define SXE_ECC_STATUS_82599 0x110E0 -#define SXE_BAR_CTRL_82599 0x110F4 +#define SXE_BAR_CTRL_82599 0x110F4 =20 =20 -#define SXE_GCR_CMPL_TMOUT_MASK 0x0000F000 -#define SXE_GCR_CMPL_TMOUT_10ms 0x00001000 -#define SXE_GCR_CMPL_TMOUT_RESEND 0x00010000 -#define SXE_GCR_CAP_VER2 0x00040000 +#define SXE_GCR_CMPL_TMOUT_MASK 0x0000F000 +#define SXE_GCR_CMPL_TMOUT_10ms 0x00001000 +#define SXE_GCR_CMPL_TMOUT_RESEND 0x00010000 +#define SXE_GCR_CAP_VER2 0x00040000 =20 -#define SXE_GCR_EXT_MSIX_EN 0x80000000 -#define SXE_GCR_EXT_BUFFERS_CLEAR 0x40000000 -#define SXE_GCR_EXT_VT_MODE_16 0x00000001 -#define SXE_GCR_EXT_VT_MODE_32 0x00000002 -#define SXE_GCR_EXT_VT_MODE_64 0x00000003 -#define SXE_GCR_EXT_SRIOV (SXE_GCR_EXT_MSIX_EN | \ +#define SXE_GCR_EXT_MSIX_EN 0x80000000 +#define SXE_GCR_EXT_BUFFERS_CLEAR 0x40000000 +#define SXE_GCR_EXT_VT_MODE_16 0x00000001 +#define SXE_GCR_EXT_VT_MODE_32 0x00000002 +#define SXE_GCR_EXT_VT_MODE_64 0x00000003 +#define SXE_GCR_EXT_SRIOV (SXE_GCR_EXT_MSIX_EN | \ SXE_GCR_EXT_VT_MODE_64) =20 =20 @@ -320,108 +322,108 @@ typedef union sxe_adv_rx_desc { #define SXE_PCS1GANLP 0x0421C #define SXE_PCS1GANNP 0x04220 #define SXE_PCS1GANLPNP 0x04224 -#define SXE_HLREG0 0x04240 -#define SXE_HLREG1 0x04244 -#define SXE_PAP 0x04248 -#define SXE_MACA 0x0424C -#define SXE_APAE 0x04250 -#define SXE_ARD 0x04254 -#define SXE_AIS 0x04258 -#define SXE_MSCA 0x0425C -#define SXE_MSRWD 0x04260 -#define SXE_MLADD 0x04264 -#define SXE_MHADD 0x04268 -#define SXE_MAXFRS 0x04268 -#define SXE_TREG 0x0426C -#define SXE_PCSS1 0x04288 -#define SXE_PCSS2 0x0428C -#define SXE_XPCSS 0x04290 -#define SXE_MFLCN 0x04294 +#define SXE_HLREG0 0x04240 +#define SXE_HLREG1 0x04244 +#define SXE_PAP 0x04248 +#define SXE_MACA 0x0424C +#define SXE_APAE 0x04250 +#define SXE_ARD 0x04254 +#define SXE_AIS 0x04258 +#define SXE_MSCA 0x0425C +#define SXE_MSRWD 0x04260 +#define SXE_MLADD 0x04264 +#define SXE_MHADD 0x04268 +#define SXE_MAXFRS 0x04268 +#define SXE_TREG 0x0426C +#define SXE_PCSS1 0x04288 +#define SXE_PCSS2 0x0428C +#define SXE_XPCSS 0x04290 +#define SXE_MFLCN 0x04294 #define SXE_SERDESC 0x04298 #define SXE_MAC_SGMII_BUSY 0x04298 -#define SXE_MACS 0x0429C -#define SXE_AUTOC 0x042A0 -#define SXE_LINKS 0x042A4 -#define SXE_LINKS2 0x04324 -#define SXE_AUTOC2 0x042A8 -#define SXE_AUTOC3 0x042AC -#define SXE_ANLP1 0x042B0 -#define SXE_ANLP2 0x042B4 -#define SXE_MACC 0x04330 +#define SXE_MACS 0x0429C +#define SXE_AUTOC 0x042A0 +#define SXE_LINKS 0x042A4 +#define SXE_LINKS2 0x04324 +#define SXE_AUTOC2 0x042A8 +#define SXE_AUTOC3 0x042AC +#define SXE_ANLP1 0x042B0 +#define SXE_ANLP2 0x042B4 +#define SXE_MACC 0x04330 #define SXE_ATLASCTL 0x04800 -#define SXE_MMNGC 0x042D0 +#define SXE_MMNGC 0x042D0 #define SXE_ANLPNP1 0x042D4 #define SXE_ANLPNP2 0x042D8 #define SXE_KRPCSFC 0x042E0 -#define SXE_KRPCSS 0x042E4 -#define SXE_FECS1 0x042E8 -#define SXE_FECS2 0x042EC +#define SXE_KRPCSS 0x042E4 +#define SXE_FECS1 0x042E8 +#define SXE_FECS2 0x042EC #define SXE_SMADARCTL 0x14F10 -#define SXE_MPVC 0x04318 -#define SXE_SGMIIC 0x04314 +#define SXE_MPVC 0x04318 +#define SXE_SGMIIC 0x04314 =20 =20 -#define SXE_COMCTRL 0x14400 -#define SXE_PCCTRL 0x14404 -#define SXE_LPBKCTRL 0x1440C -#define SXE_MAXFS 0x14410 -#define SXE_SACONH 0x14420 -#define SXE_VLANCTRL 0x14430 -#define SXE_VLANID 0x14434 -#define SXE_VLANCTRL 0x14430 -#define SXE_FPAG_SDS_CON 0x14700 +#define SXE_COMCTRL 0x14400 +#define SXE_PCCTRL 0x14404 +#define SXE_LPBKCTRL 0x1440C +#define SXE_MAXFS 0x14410 +#define SXE_SACONH 0x14420 +#define SXE_VLANCTRL 0x14430 +#define SXE_VLANID 0x14434 +#define SXE_VLANCTRL 0x14430 +#define SXE_FPAG_SDS_CON 0x14700 =20 =20 -#define SXE_COMCTRL_TXEN 0x0001 -#define SXE_COMCTRL_RXEN 0x0002 -#define SXE_COMCTRL_EDSEL 0x0004 -#define SXE_COMCTRL_SPEED_1G 0x0200 +#define SXE_COMCTRL_TXEN 0x0001 +#define SXE_COMCTRL_RXEN 0x0002 +#define SXE_COMCTRL_EDSEL 0x0004 +#define SXE_COMCTRL_SPEED_1G 0x0200 #define SXE_COMCTRL_SPEED_10G 0x0300 =20 =20 -#define SXE_PCCTRL_TXCE 0x0001 -#define SXE_PCCTRL_RXCE 0x0002 -#define SXE_PCCTRL_PEN 0x0100 -#define SXE_PCCTRL_PCSC_ALL 0x30000 +#define SXE_PCCTRL_TXCE 0x0001 +#define SXE_PCCTRL_RXCE 0x0002 +#define SXE_PCCTRL_PEN 0x0100 +#define SXE_PCCTRL_PCSC_ALL 0x30000 =20 =20 -#define SXE_MAXFS_TFSEL 0x0001 -#define SXE_MAXFS_RFSEL 0x0002 -#define SXE_MAXFS_MFS_MASK 0xFFFF0000 -#define SXE_MAXFS_MFS 0x40000000 -#define SXE_MAXFS_MFS_SHIFT 16 +#define SXE_MAXFS_TFSEL 0x0001 +#define SXE_MAXFS_RFSEL 0x0002 +#define SXE_MAXFS_MFS_MASK 0xFFFF0000 +#define SXE_MAXFS_MFS 0x40000000 +#define SXE_MAXFS_MFS_SHIFT 16 =20 =20 -#define SXE_FPGA_SDS_CON_FULL_DUPLEX_MODE 0x00200000 -#define SXE_FPGA_SDS_CON_ANRESTART 0x00008000 -#define SXE_FPGA_SDS_CON_AN_ENABLE 0x00001000 +#define SXE_FPGA_SDS_CON_FULL_DUPLEX_MODE 0x00200000 +#define SXE_FPGA_SDS_CON_ANRESTART 0x00008000 +#define SXE_FPGA_SDS_CON_AN_ENABLE 0x00001000 =20 =20 -#define SXE_RSCDBU_RSCSMALDIS_MASK 0x0000007F -#define SXE_RSCDBU_RSCACKDIS 0x00000080 +#define SXE_RSCDBU_RSCSMALDIS_MASK 0x0000007F +#define SXE_RSCDBU_RSCACKDIS 0x00000080 =20 =20 -#define SXE_RDRXCTL_RDMTS_1_2 0x00000000=20=20 -#define SXE_RDRXCTL_CRCSTRIP 0x00000002=20=20 -#define SXE_RDRXCTL_PSP 0x00000004=20=20 -#define SXE_RDRXCTL_MVMEN 0x00000020 -#define SXE_RDRXCTL_DMAIDONE 0x00000008=20=20 -#define SXE_RDRXCTL_AGGDIS 0x00010000=20=20 -#define SXE_RDRXCTL_RSCFRSTSIZE 0x003E0000=20=20 -#define SXE_RDRXCTL_RSCLLIDIS 0x00800000=20=20 -#define SXE_RDRXCTL_RSCACKC 0x02000000=20=20 -#define SXE_RDRXCTL_FCOE_WRFIX 0x04000000=20=20 -#define SXE_RDRXCTL_MBINTEN 0x10000000 -#define SXE_RDRXCTL_MDP_EN 0x20000000 +#define SXE_RDRXCTL_RDMTS_1_2 0x00000000 +#define SXE_RDRXCTL_CRCSTRIP 0x00000002 +#define SXE_RDRXCTL_PSP 0x00000004 +#define SXE_RDRXCTL_MVMEN 0x00000020 +#define SXE_RDRXCTL_DMAIDONE 0x00000008 +#define SXE_RDRXCTL_AGGDIS 0x00010000 +#define SXE_RDRXCTL_RSCFRSTSIZE 0x003E0000 +#define SXE_RDRXCTL_RSCLLIDIS 0x00800000 +#define SXE_RDRXCTL_RSCACKC 0x02000000 +#define SXE_RDRXCTL_FCOE_WRFIX 0x04000000 +#define SXE_RDRXCTL_MBINTEN 0x10000000 +#define SXE_RDRXCTL_MDP_EN 0x20000000 =20 =20 -#define SXE_CTRL_GIO_DIS 0x00000004 -#define SXE_CTRL_LNK_RST 0x00000008 -#define SXE_CTRL_RST 0x04000000 -#define SXE_CTRL_RST_MASK (SXE_CTRL_LNK_RST | SXE_CTRL_RST) +#define SXE_CTRL_GIO_DIS 0x00000004 +#define SXE_CTRL_LNK_RST 0x00000008 +#define SXE_CTRL_RST 0x04000000 +#define SXE_CTRL_RST_MASK (SXE_CTRL_LNK_RST | SXE_CTRL_RST) =20 =20 -#define SXE_MHADD_MFS_MASK 0xFFFF0000 +#define SXE_MHADD_MFS_MASK 0xFFFF0000 #define SXE_MHADD_MFS_SHIFT 16 =20 =20 @@ -431,92 +433,92 @@ typedef union sxe_adv_rx_desc { #define SXE_CTRL_EXT_DRV_LOAD 0x10000000 =20 =20 -#define SXE_TXPBSIZE_20KB 0x00005000=20=20 -#define SXE_TXPBSIZE_40KB 0x0000A000=20=20 -#define SXE_RXPBSIZE_48KB 0x0000C000=20=20 -#define SXE_RXPBSIZE_64KB 0x00010000=20=20 -#define SXE_RXPBSIZE_80KB 0x00014000=20=20 -#define SXE_RXPBSIZE_128KB 0x00020000=20=20 -#define SXE_RXPBSIZE_MAX 0x00080000=20=20 -#define SXE_TXPBSIZE_MAX 0x00028000=20=20 +#define SXE_TXPBSIZE_20KB 0x00005000 +#define SXE_TXPBSIZE_40KB 0x0000A000 +#define SXE_RXPBSIZE_48KB 0x0000C000 +#define SXE_RXPBSIZE_64KB 0x00010000 +#define SXE_RXPBSIZE_80KB 0x00014000 +#define SXE_RXPBSIZE_128KB 0x00020000 +#define SXE_RXPBSIZE_MAX 0x00080000 +#define SXE_TXPBSIZE_MAX 0x00028000 =20 -#define SXE_TXPKT_SIZE_MAX 0xA=20=20=20=20=20=20=20=20=20 +#define SXE_TXPKT_SIZE_MAX 0xA #define SXE_MAX_PB 8 =20 =20 -#define SXE_HLREG0_TXCRCEN 0x00000001=20=20 -#define SXE_HLREG0_RXCRCSTRP 0x00000002=20=20 -#define SXE_HLREG0_JUMBOEN 0x00000004=20=20 -#define SXE_HLREG0_TXPADEN 0x00000400=20=20 -#define SXE_HLREG0_TXPAUSEEN 0x00001000=20=20 -#define SXE_HLREG0_RXPAUSEEN 0x00004000=20=20 -#define SXE_HLREG0_LPBK 0x00008000=20=20 -#define SXE_HLREG0_MDCSPD 0x00010000=20=20 -#define SXE_HLREG0_CONTMDC 0x00020000=20=20 -#define SXE_HLREG0_CTRLFLTR 0x00040000=20=20 -#define SXE_HLREG0_PREPEND 0x00F00000=20=20 -#define SXE_HLREG0_PRIPAUSEEN 0x01000000=20=20 -#define SXE_HLREG0_RXPAUSERECDA 0x06000000=20=20 -#define SXE_HLREG0_RXLNGTHERREN 0x08000000=20=20 -#define SXE_HLREG0_RXPADSTRIPEN 0x10000000=20=20 +#define SXE_HLREG0_TXCRCEN 0x00000001 +#define SXE_HLREG0_RXCRCSTRP 0x00000002 +#define SXE_HLREG0_JUMBOEN 0x00000004 +#define SXE_HLREG0_TXPADEN 0x00000400 +#define SXE_HLREG0_TXPAUSEEN 0x00001000 +#define SXE_HLREG0_RXPAUSEEN 0x00004000 +#define SXE_HLREG0_LPBK 0x00008000 +#define SXE_HLREG0_MDCSPD 0x00010000 +#define SXE_HLREG0_CONTMDC 0x00020000 +#define SXE_HLREG0_CTRLFLTR 0x00040000 +#define SXE_HLREG0_PREPEND 0x00F00000 +#define SXE_HLREG0_PRIPAUSEEN 0x01000000 +#define SXE_HLREG0_RXPAUSERECDA 0x06000000 +#define SXE_HLREG0_RXLNGTHERREN 0x08000000 +#define SXE_HLREG0_RXPADSTRIPEN 0x10000000 =20 =20 #define SXE_VMOLR_UPE 0x00400000 #define SXE_VMOLR_VPE 0x00800000 -#define SXE_VMOLR_AUPE 0x01000000 -#define SXE_VMOLR_ROMPE 0x02000000 -#define SXE_VMOLR_ROPE 0x04000000 -#define SXE_VMOLR_BAM 0x08000000 -#define SXE_VMOLR_MPE 0x10000000 +#define SXE_VMOLR_AUPE 0x01000000 +#define SXE_VMOLR_ROMPE 0x02000000 +#define SXE_VMOLR_ROPE 0x04000000 +#define SXE_VMOLR_BAM 0x08000000 +#define SXE_VMOLR_MPE 0x10000000 =20 =20 -#define SXE_RXCSUM_IPPCSE 0x00001000=20=20 -#define SXE_RXCSUM_PCSD 0x00002000=20=20 +#define SXE_RXCSUM_IPPCSE 0x00001000 +#define SXE_RXCSUM_PCSD 0x00002000 =20 =20 -#define SXE_VMD_CTL_VMDQ_EN 0x00000001 +#define SXE_VMD_CTL_VMDQ_EN 0x00000001 #define SXE_VMD_CTL_VMDQ_FILTER 0x00000002 =20 =20 -#define SXE_MACCFG_PAD_EN 0x00000001 +#define SXE_MACCFG_PAD_EN 0x00000001 =20 =20 -#define SXE_IRQ_CLEAR_MASK 0xFFFFFFFF +#define SXE_IRQ_CLEAR_MASK 0xFFFFFFFF =20 =20 -#define SXE_STATUS_LAN_ID 0x0000000C -#define SXE_STATUS_LAN_ID_SHIFT 2=20=20=20=20=20=20=20=20=20 -#define SXE_STATUS_GIO 0x00080000 +#define SXE_STATUS_LAN_ID 0x0000000C +#define SXE_STATUS_LAN_ID_SHIFT 2 +#define SXE_STATUS_GIO 0x00080000 =20 =20 #define SXE_LINKS_KX_AN_COMP 0x80000000 -#define SXE_LINKS_UP 0x40000000 -#define SXE_LINKS_SPEED 0x20000000 -#define SXE_LINKS_MODE 0x18000000 -#define SXE_LINKS_RX_MODE 0x06000000 -#define SXE_LINKS_TX_MODE 0x01800000 -#define SXE_LINKS_XGXS_EN 0x00400000 -#define SXE_LINKS_SGMII_EN 0x02000000 +#define SXE_LINKS_UP 0x40000000 +#define SXE_LINKS_SPEED 0x20000000 +#define SXE_LINKS_MODE 0x18000000 +#define SXE_LINKS_RX_MODE 0x06000000 +#define SXE_LINKS_TX_MODE 0x01800000 +#define SXE_LINKS_XGXS_EN 0x00400000 +#define SXE_LINKS_SGMII_EN 0x02000000 #define SXE_LINKS_PCS_1G_EN 0x00200000 -#define SXE_LINKS_1G_AN_EN 0x00100000 +#define SXE_LINKS_1G_AN_EN 0x00100000 #define SXE_LINKS_KX_AN_IDLE 0x00080000 -#define SXE_LINKS_1G_SYNC 0x00040000 +#define SXE_LINKS_1G_SYNC 0x00040000 #define SXE_LINKS_10G_ALIGN 0x00020000 #define SXE_LINKS_10G_LANE_SYNC 0x00017000 -#define SXE_LINKS_TL_FAULT 0x00001000 -#define SXE_LINKS_SIGNAL 0x00000F00 +#define SXE_LINKS_TL_FAULT 0x00001000 +#define SXE_LINKS_SIGNAL 0x00000F00 =20 =20 -#define SXE_PCI_DEVICE_STATUS 0x7A=20 +#define SXE_PCI_DEVICE_STATUS 0x7A #define SXE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 -#define SXE_PCI_LINK_STATUS 0x82=20 -#define SXE_PCI_DEVICE_CONTROL2 0x98=20 -#define SXE_PCI_LINK_WIDTH 0x3F0 -#define SXE_PCI_LINK_WIDTH_1 0x10 -#define SXE_PCI_LINK_WIDTH_2 0x20 -#define SXE_PCI_LINK_WIDTH_4 0x40 -#define SXE_PCI_LINK_WIDTH_8 0x80 -#define SXE_PCI_LINK_SPEED 0xF +#define SXE_PCI_LINK_STATUS 0x82 +#define SXE_PCI_DEVICE_CONTROL2 0x98 +#define SXE_PCI_LINK_WIDTH 0x3F0 +#define SXE_PCI_LINK_WIDTH_1 0x10 +#define SXE_PCI_LINK_WIDTH_2 0x20 +#define SXE_PCI_LINK_WIDTH_4 0x40 +#define SXE_PCI_LINK_WIDTH_8 0x80 +#define SXE_PCI_LINK_SPEED 0xF #define SXE_PCI_LINK_SPEED_2500 0x1 #define SXE_PCI_LINK_SPEED_5000 0x2 #define SXE_PCI_LINK_SPEED_8000 0x3 @@ -539,39 +541,39 @@ typedef union sxe_adv_rx_desc { #define SXE_PCI_MASTER_DISABLE_TIMEOUT 800 =20 =20 -#define SXE_RAH_VIND_MASK 0x003C0000 -#define SXE_RAH_VIND_SHIFT 18 -#define SXE_RAH_AV 0x80000000 -#define SXE_CLEAR_VMDQ_ALL 0xFFFFFFFF +#define SXE_RAH_VIND_MASK 0x003C0000 +#define SXE_RAH_VIND_SHIFT 18 +#define SXE_RAH_AV 0x80000000 +#define SXE_CLEAR_VMDQ_ALL 0xFFFFFFFF =20 =20 -#define SXE_RFCTL_ISCSI_DIS 0x00000001 +#define SXE_RFCTL_ISCSI_DIS 0x00000001 #define SXE_RFCTL_ISCSI_DWC_MASK 0x0000003E #define SXE_RFCTL_ISCSI_DWC_SHIFT 1 #define SXE_RFCTL_RSC_DIS 0x00000020 -#define SXE_RFCTL_NFSW_DIS 0x00000040 -#define SXE_RFCTL_NFSR_DIS 0x00000080 -#define SXE_RFCTL_NFS_VER_MASK 0x00000300 +#define SXE_RFCTL_NFSW_DIS 0x00000040 +#define SXE_RFCTL_NFSR_DIS 0x00000080 +#define SXE_RFCTL_NFS_VER_MASK 0x00000300 #define SXE_RFCTL_NFS_VER_SHIFT 8 -#define SXE_RFCTL_NFS_VER_2 0 -#define SXE_RFCTL_NFS_VER_3 1 -#define SXE_RFCTL_NFS_VER_4 2 -#define SXE_RFCTL_IPV6_DIS 0x00000400 +#define SXE_RFCTL_NFS_VER_2 0 +#define SXE_RFCTL_NFS_VER_3 1 +#define SXE_RFCTL_NFS_VER_4 2 +#define SXE_RFCTL_IPV6_DIS 0x00000400 #define SXE_RFCTL_IPV6_XSUM_DIS 0x00000800 -#define SXE_RFCTL_IPFRSP_DIS 0x00004000 -#define SXE_RFCTL_IPV6_EX_DIS 0x00010000 +#define SXE_RFCTL_IPFRSP_DIS 0x00004000 +#define SXE_RFCTL_IPV6_EX_DIS 0x00010000 #define SXE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 =20 =20 -#define SXE_TXDCTL_ENABLE 0x02000000=20=20=20 -#define SXE_TXDCTL_SWFLSH 0x04000000=20=20=20 -#define SXE_TXDCTL_WTHRESH_SHIFT 16=20=20=20 +#define SXE_TXDCTL_ENABLE 0x02000000 +#define SXE_TXDCTL_SWFLSH 0x04000000 +#define SXE_TXDCTL_WTHRESH_SHIFT 16 =20 =20 -#define SXE_RXCTRL_RXEN 0x00000001=20 -#define SXE_RXCTRL_DMBYPS 0x00000002=20 -#define SXE_RXDCTL_ENABLE 0x02000000=20 -#define SXE_RXDCTL_SWFLSH 0x04000000=20 +#define SXE_RXCTRL_RXEN 0x00000001 +#define SXE_RXCTRL_DMBYPS 0x00000002 +#define SXE_RXDCTL_ENABLE 0x02000000 +#define SXE_RXDCTL_SWFLSH 0x04000000 =20 =20 #define SXE_RXDCTL_DESC_FIFO_AFUL_TH_MASK 0x0000001F @@ -585,12 +587,12 @@ typedef union sxe_adv_rx_desc { #define SXE_PCI_MASTER_DISABLE_TIMEOUT 800 =20 =20 -#define SXE_FCTRL_SBP 0x00000002=20=20 -#define SXE_FCTRL_MPE 0x00000100=20=20 -#define SXE_FCTRL_UPE 0x00000200=20=20 -#define SXE_FCTRL_BAM 0x00000400=20=20 -#define SXE_FCTRL_PMCF 0x00001000=20 -#define SXE_FCTRL_DPF 0x00002000=20=20 +#define SXE_FCTRL_SBP 0x00000002 +#define SXE_FCTRL_MPE 0x00000100 +#define SXE_FCTRL_UPE 0x00000200 +#define SXE_FCTRL_BAM 0x00000400 +#define SXE_FCTRL_PMCF 0x00001000 +#define SXE_FCTRL_DPF 0x00002000 =20 =20 #define SXE_QDE_ENABLE 0x00000001 @@ -599,89 +601,89 @@ typedef union sxe_adv_rx_desc { #define SXE_QDE_IDX_SHIFT 8 #define SXE_QDE_WRITE 0x00010000 =20 -#define SXE_TXD_POPTS_IXSM 0x01=20=20=20=20=20=20 -#define SXE_TXD_POPTS_TXSM 0x02=20=20=20=20=20=20 -#define SXE_TXD_CMD_EOP 0x01000000 +#define SXE_TXD_POPTS_IXSM 0x01 +#define SXE_TXD_POPTS_TXSM 0x02 +#define SXE_TXD_CMD_EOP 0x01000000 #define SXE_TXD_CMD_IFCS 0x02000000 -#define SXE_TXD_CMD_IC 0x04000000 -#define SXE_TXD_CMD_RS 0x08000000 +#define SXE_TXD_CMD_IC 0x04000000 +#define SXE_TXD_CMD_RS 0x08000000 #define SXE_TXD_CMD_DEXT 0x20000000 -#define SXE_TXD_CMD_VLE 0x40000000 -#define SXE_TXD_STAT_DD 0x00000001 +#define SXE_TXD_CMD_VLE 0x40000000 +#define SXE_TXD_STAT_DD 0x00000001 =20 =20 -#define SXE_SRRCTL_BSIZEPKT_SHIFT 10=20=20=20=20=20=20=20=20=20=20 -#define SXE_SRRCTL_RDMTS_SHIFT 22 -#define SXE_SRRCTL_RDMTS_MASK 0x01C00000 -#define SXE_SRRCTL_DROP_EN 0x10000000 -#define SXE_SRRCTL_BSIZEPKT_MASK 0x0000007F -#define SXE_SRRCTL_BSIZEHDR_MASK 0x00003F00 -#define SXE_SRRCTL_DESCTYPE_LEGACY 0x00000000 +#define SXE_SRRCTL_BSIZEPKT_SHIFT 10 +#define SXE_SRRCTL_RDMTS_SHIFT 22 +#define SXE_SRRCTL_RDMTS_MASK 0x01C00000 +#define SXE_SRRCTL_DROP_EN 0x10000000 +#define SXE_SRRCTL_BSIZEPKT_MASK 0x0000007F +#define SXE_SRRCTL_BSIZEHDR_MASK 0x00003F00 +#define SXE_SRRCTL_DESCTYPE_LEGACY 0x00000000 #define SXE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 #define SXE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 #define SXE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 #define SXE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 -#define SXE_SRRCTL_DESCTYPE_MASK 0x0E000000 +#define SXE_SRRCTL_DESCTYPE_MASK 0x0E000000 =20 -#define SXE_RXDPS_HDRSTAT_HDRSP 0x00008000 +#define SXE_RXDPS_HDRSTAT_HDRSP 0x00008000 #define SXE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF =20 -#define SXE_RXDADV_RSSTYPE_MASK 0x0000000F -#define SXE_RXDADV_PKTTYPE_MASK 0x0000FFF0 -#define SXE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 -#define SXE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 -#define SXE_RXDADV_RSCCNT_MASK 0x001E0000 -#define SXE_RXDADV_RSCCNT_SHIFT 17 -#define SXE_RXDADV_HDRBUFLEN_SHIFT 5 -#define SXE_RXDADV_SPLITHEADER_EN 0x00001000 -#define SXE_RXDADV_SPH 0x8000 +#define SXE_RXDADV_RSSTYPE_MASK 0x0000000F +#define SXE_RXDADV_PKTTYPE_MASK 0x0000FFF0 +#define SXE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 +#define SXE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 +#define SXE_RXDADV_RSCCNT_MASK 0x001E0000 +#define SXE_RXDADV_RSCCNT_SHIFT 17 +#define SXE_RXDADV_HDRBUFLEN_SHIFT 5 +#define SXE_RXDADV_SPLITHEADER_EN 0x00001000 +#define SXE_RXDADV_SPH 0x8000 =20 =20 -#define SXE_ADVTXD_DTYP_DATA 0x00300000=20=20=20=20=20=20=20=20 -#define SXE_ADVTXD_DCMD_IFCS SXE_TXD_CMD_IFCS=20=20 -#define SXE_ADVTXD_DCMD_DEXT SXE_TXD_CMD_DEXT=20=20 -#define SXE_ADVTXD_PAYLEN_SHIFT 14=20=20=20=20=20=20=20=20=20=20=20 +#define SXE_ADVTXD_DTYP_DATA 0x00300000 +#define SXE_ADVTXD_DCMD_IFCS SXE_TXD_CMD_IFCS +#define SXE_ADVTXD_DCMD_DEXT SXE_TXD_CMD_DEXT +#define SXE_ADVTXD_PAYLEN_SHIFT 14 =20 =20 #define SXE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 =20 =20 -#define SXE_ERR_EEPROM -1 -#define SXE_ERR_EEPROM_CHECKSUM -2 -#define SXE_ERR_PHY -3 -#define SXE_ERR_CONFIG -4 -#define SXE_ERR_PARAM -5 -#define SXE_ERR_MAC_TYPE -6 -#define SXE_ERR_UNKNOWN_PHY -7 -#define SXE_ERR_LINK_SETUP -8 -#define SXE_ERR_ADAPTER_STOPPED -9 -#define SXE_ERR_INVALID_MAC_ADDR -10 -#define SXE_ERR_DEVICE_NOT_SUPPORTED -11 -#define SXE_ERR_MASTER_REQUESTS_PENDING -12 -#define SXE_ERR_INVALID_LINK_SETTINGS -13 -#define SXE_ERR_AUTONEG_NOT_COMPLETE -14 -#define SXE_ERR_RESET_FAILED -15 -#define SXE_ERR_SWFW_SYNC -16 -#define SXE_ERR_PHY_ADDR_INVALID -17 -#define SXE_ERR_I2C -18 -#define SXE_ERR_SFP_NOT_SUPPORTED -19 -#define SXE_ERR_SFP_NOT_PRESENT -20 -#define SXE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 -#define SXE_ERR_NO_SAN_ADDR_PTR -22 -#define SXE_ERR_FDIR_REINIT_FAILED -23 -#define SXE_ERR_EEPROM_VERSION -24 -#define SXE_ERR_NO_SPACE -25 -#define SXE_ERR_OVERTEMP -26 -#define SXE_ERR_FC_NOT_NEGOTIATED -27 -#define SXE_ERR_FC_NOT_SUPPORTED -28 -#define SXE_ERR_SFP_SETUP_NOT_COMPLETE -30 -#define SXE_ERR_PBA_SECTION -31 -#define SXE_ERR_INVALID_ARGUMENT -32 -#define SXE_ERR_HOST_INTERFACE_COMMAND -33 +#define SXE_ERR_EEPROM -1 +#define SXE_ERR_EEPROM_CHECKSUM -2 +#define SXE_ERR_PHY -3 +#define SXE_ERR_CONFIG -4 +#define SXE_ERR_PARAM -5 +#define SXE_ERR_MAC_TYPE -6 +#define SXE_ERR_UNKNOWN_PHY -7 +#define SXE_ERR_LINK_SETUP -8 +#define SXE_ERR_ADAPTER_STOPPED -9 +#define SXE_ERR_INVALID_MAC_ADDR -10 +#define SXE_ERR_DEVICE_NOT_SUPPORTED -11 +#define SXE_ERR_MASTER_REQUESTS_PENDING -12 +#define SXE_ERR_INVALID_LINK_SETTINGS -13 +#define SXE_ERR_AUTONEG_NOT_COMPLETE -14 +#define SXE_ERR_RESET_FAILED -15 +#define SXE_ERR_SWFW_SYNC -16 +#define SXE_ERR_PHY_ADDR_INVALID -17 +#define SXE_ERR_I2C -18 +#define SXE_ERR_SFP_NOT_SUPPORTED -19 +#define SXE_ERR_SFP_NOT_PRESENT -20 +#define SXE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 +#define SXE_ERR_NO_SAN_ADDR_PTR -22 +#define SXE_ERR_FDIR_REINIT_FAILED -23 +#define SXE_ERR_EEPROM_VERSION -24 +#define SXE_ERR_NO_SPACE -25 +#define SXE_ERR_OVERTEMP -26 +#define SXE_ERR_FC_NOT_NEGOTIATED -27 +#define SXE_ERR_FC_NOT_SUPPORTED -28 +#define SXE_ERR_SFP_SETUP_NOT_COMPLETE -30 +#define SXE_ERR_PBA_SECTION -31 +#define SXE_ERR_INVALID_ARGUMENT -32 +#define SXE_ERR_HOST_INTERFACE_COMMAND -33 #define SXE_ERR_FDIR_CMD_INCOMPLETE -38 #define SXE_ERR_FW_RESP_INVALID -39 #define SXE_ERR_TOKEN_RETRY -40 -#define SXE_NOT_IMPLEMENTED 0x7FFFFFFF +#define SXE_NOT_IMPLEMENTED 0x7FFFFFFF =20 #define SXE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) #define SXE_FUSES0_300MHZ BIT(5) @@ -790,5 +792,5 @@ typedef union sxe_adv_rx_desc { #define SXE_NW_MNG_IF_SEL_MDIO_PHY_ADD \ (0x1F << SXE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT) =20 -#endif=20 +#endif =20 diff --git a/drivers/net/sxe/include/sxe_version.h b/drivers/net/sxe/includ= e/sxe_version.h index 50afd69a63..6b5e4caef1 100644 --- a/drivers/net/sxe/include/sxe_version.h +++ b/drivers/net/sxe/include/sxe_version.h @@ -4,29 +4,28 @@ #ifndef __SXE_VER_H__ #define __SXE_VER_H__ =20 -#define SXE_VERSION "0.0.0.0" -#define SXE_COMMIT_ID "13cf402" -#define SXE_BRANCH "feature/sagitta-1.3.0-P3-dpdk_patch_rw= y" -#define SXE_BUILD_TIME "2024-08-24 11:02:12" +#define SXE_VERSION "0.0.0.0" +#define SXE_COMMIT_ID "51935d6" +#define SXE_BRANCH "feature/sagitta-1.3.0-P3-dpdk_patch_rwy" +#define SXE_BUILD_TIME "2024-09-05 21:49:55" =20 =20 -#define SXE_DRV_NAME "sxe" -#define SXEVF_DRV_NAME "sxevf" -#define SXE_DRV_LICENSE "GPL v2" -#define SXE_DRV_COPYRIGHT "Copyright (C), 2022, Linkdata Tech= nology Co., Ltd." -#define SXE_DRV_AUTHOR "Linkdata Technology Corporation" -#define SXE_DRV_DESCRIPTION "LD 1160-2X 2-port 10G SFP+ NIC" -#define SXEVF_DRV_DESCRIPTION "LD 1160-2X Virtual Function" -#define SXE_DRV_CONNECTION "Linkdata Technology 10G Network Co= nnection" +#define SXE_DRV_NAME "sxe" +#define SXEVF_DRV_NAME "sxevf" +#define SXE_DRV_LICENSE "GPL v2" +#define SXE_DRV_AUTHOR "sxe" +#define SXEVF_DRV_AUTHOR "sxevf" +#define SXE_DRV_DESCRIPTION "sxe driver" +#define SXEVF_DRV_DESCRIPTION "sxevf driver" =20 =20 -#define SXE_FW_NAME "soc" -#define SXE_FW_ARCH "arm32" +#define SXE_FW_NAME "soc" +#define SXE_FW_ARCH "arm32" =20 #ifndef PS3_CFG_RELEASE -#define PS3_SXE_FW_BUILD_MODE "debug" +#define PS3_SXE_FW_BUILD_MODE "debug" #else -#define PS3_SXE_FW_BUILD_MODE "release" +#define PS3_SXE_FW_BUILD_MODE "release" #endif =20 #endif diff --git a/drivers/net/sxe/meson.build b/drivers/net/sxe/meson.build index 5e7b49dcf6..50611c27fe 100644 --- a/drivers/net/sxe/meson.build +++ b/drivers/net/sxe/meson.build @@ -5,6 +5,10 @@ cflags +=3D ['-DSXE_DPDK'] cflags +=3D ['-DSXE_HOST_DRIVER'] cflags +=3D ['-DSXE_DPDK_L4_FEATURES'] cflags +=3D ['-DSXE_DPDK_SRIOV'] +cflags +=3D ['-DSXE_DPDK_FILTER_CTRL'] +cflags +=3D ['-DSXE_DPDK_MACSEC'] +cflags +=3D ['-DSXE_DPDK_TM'] +cflags +=3D ['-DSXE_DPDK_SIMD'] =20 #subdir('base') #objs =3D [base_objs] @@ -26,6 +30,10 @@ sources =3D files( 'pf/sxe_ptp.c', 'pf/sxe_vf.c', 'pf/sxe_dcb.c', + 'pf/sxe_filter_ctrl.c', + 'pf/sxe_fnav.c', + 'pf/sxe_tm.c', + 'pf/sxe_macsec.c', 'vf/sxevf_main.c', 'vf/sxevf_filter.c', 'vf/sxevf_irq.c', @@ -47,6 +55,12 @@ sources =3D files( =20 testpmd_sources =3D files('sxe_testpmd.c') =20 +if arch_subdir =3D=3D 'x86' + sources +=3D files('pf/sxe_vec_sse.c') +elif arch_subdir =3D=3D 'arm' + sources +=3D files('pf/sxe_vec_neon.c') +endif + includes +=3D include_directories('base') includes +=3D include_directories('pf') includes +=3D include_directories('vf') diff --git a/drivers/net/sxe/pf/sxe.h b/drivers/net/sxe/pf/sxe.h index 139480e90d..4d7e03adee 100644 --- a/drivers/net/sxe/pf/sxe.h +++ b/drivers/net/sxe/pf/sxe.h @@ -28,21 +28,23 @@ struct sxe_hw; struct sxe_vlan_context; =20 -#define SXE_LPBK_DISABLED 0x0=20 -#define SXE_LPBK_ENABLED 0x1=20 +#define SXE_LPBK_DISABLED 0x0 +#define SXE_LPBK_ENABLED 0x1 =20 -#define PCI_VENDOR_ID_STARS 0x1FF2 -#define SXE_DEV_ID_ASIC 0x10a1 +#define PCI_VENDOR_ID_STARS 0x1FF2 +#define SXE_DEV_ID_ASIC 0x10a1 =20 #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ADDR(x) ((u8*)(x))[0],((u8*)(x))[1], \ - ((u8*)(x))[2],((u8*)(x))[3], \ - ((u8*)(x))[4],((u8*)(x))[5] +#define MAC_ADDR(x) ((u8 *)(x))[0], ((u8 *)(x))[1], \ + ((u8 *)(x))[2], ((u8 *)(x))[3], \ + ((u8 *)(x))[4], ((u8 *)(x))[5] =20 #ifdef RTE_PMD_PACKET_PREFETCH #define rte_packet_prefetch(p) rte_prefetch1(p) #else -#define rte_packet_prefetch(p) do {} while(0) +#define rte_packet_prefetch(p) \ + do { \ + } while (0) #endif =20 #if 1 @@ -56,9 +58,9 @@ struct sxe_vlan_context; #endif =20 struct sxe_ptp_context { - struct rte_timecounter systime_tc; - struct rte_timecounter rx_tstamp_tc; - struct rte_timecounter tx_tstamp_tc; + struct rte_timecounter systime_tc; + struct rte_timecounter rx_tstamp_tc; + struct rte_timecounter tx_tstamp_tc; u32 tx_hwtstamp_sec; u32 tx_hwtstamp_nsec; }; @@ -75,7 +77,7 @@ struct sxe_adapter { #endif struct sxe_ptp_context ptp_ctxt; struct sxe_phy_context phy_ctxt; - struct sxe_virtual_context vt_ctxt;=20 + struct sxe_virtual_context vt_ctxt; =20 struct sxe_stats_info stats_info; struct sxe_dcb_context dcb_ctxt; @@ -97,7 +99,7 @@ struct sxe_adapter { #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD bool rx_vec_allowed; #endif - s8 name[PCI_PRI_STR_SIZE+1];=20 + s8 name[PCI_PRI_STR_SIZE+1]; =20 u32 mtu; =20 @@ -114,4 +116,4 @@ void sxe_hw_start(struct sxe_hw *hw); =20 bool is_sxe_supported(struct rte_eth_dev *dev); =20 -#endif=20 +#endif diff --git a/drivers/net/sxe/pf/sxe_dcb.c b/drivers/net/sxe/pf/sxe_dcb.c index 5217cc655f..dad5b29e23 100644 --- a/drivers/net/sxe/pf/sxe_dcb.c +++ b/drivers/net/sxe/pf/sxe_dcb.c @@ -15,9 +15,9 @@ #define DCB_RX_CONFIG 1 #define DCB_TX_CONFIG 1 =20 -#define DCB_CREDIT_QUANTUM 64=20=20=20 -#define MAX_CREDIT_REFILL 511=20=20 -#define MAX_CREDIT 4095=20 +#define DCB_CREDIT_QUANTUM 64 +#define MAX_CREDIT_REFILL 511 +#define MAX_CREDIT 4095 =20 void sxe_dcb_init(struct rte_eth_dev *dev) { @@ -54,7 +54,6 @@ void sxe_dcb_init(struct rte_eth_dev *dev) cfg->vmdq_active =3D true; cfg->round_robin_enable =3D false; =20 - return; } =20 static u8 sxe_dcb_get_tc_from_up(struct sxe_dcb_config *cfg, @@ -64,14 +63,12 @@ static u8 sxe_dcb_get_tc_from_up(struct sxe_dcb_config = *cfg, u8 prio_mask =3D BIT(up); u8 tc =3D cfg->num_tcs.pg_tcs; =20 - if (!tc) { + if (!tc) goto l_ret; - } =20 for (tc--; tc; tc--) { - if (prio_mask & tc_config[tc].channel[direction].up_to_tc_bitmap) { + if (prio_mask & tc_config[tc].channel[direction].up_to_tc_bitmap) break; - } } =20 l_ret: @@ -89,7 +86,6 @@ static void sxe_dcb_up2tc_map_parse(struct sxe_dcb_config= *cfg, LOG_DEBUG("up[%u] --- up2tc_map[%u]\n", up, map[up]); } =20 - return; } =20 s32 sxe_priority_flow_ctrl_set(struct rte_eth_dev *dev, @@ -122,10 +118,10 @@ s32 sxe_priority_flow_ctrl_set(struct rte_eth_dev *de= v, max_high_water =3D (rx_buf_size - RTE_ETHER_MAX_LEN) >> SXE_RX_PKT_BUF_SIZE_SHIFT; if ((pfc_conf->fc.high_water > max_high_water) || - (pfc_conf->fc.high_water <=3D pfc_conf->fc.low_water)) { + (pfc_conf->fc.high_water <=3D pfc_conf->fc.low_water)) { PMD_LOG_ERR(INIT, "Invalid high/low water setup value in KB, " - "high water=3D0x%x, low water=3D0x%x", - pfc_conf->fc.high_water, pfc_conf->fc.low_water); + "high water=3D0x%x, low water=3D0x%x", + pfc_conf->fc.high_water, pfc_conf->fc.low_water); PMD_LOG_ERR(INIT, "High_water must <=3D 0x%x", max_high_water); ret =3D -EINVAL; goto l_end; @@ -162,21 +158,19 @@ s32 sxe_get_dcb_info(struct rte_eth_dev *dev, u8 tcs_num; u8 i, j; =20 - if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) { + if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) dcb_info->nb_tcs =3D dcb_config->num_tcs.pg_tcs; - } else { + else dcb_info->nb_tcs =3D 1; - } =20 tc_queue =3D &dcb_info->tc_queue; tcs_num =3D dcb_info->nb_tcs; =20 - if (dcb_config->vmdq_active) {=20 + if (dcb_config->vmdq_active) { struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =3D &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; - for (i =3D 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) { + for (i =3D 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) dcb_info->prio_tc[i] =3D vmdq_rx_conf->dcb_tc[i]; - } =20 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { for (j =3D 0; j < tcs_num; j++) { @@ -197,12 +191,11 @@ s32 sxe_get_dcb_info(struct rte_eth_dev *dev, } } } - } else {=20 + } else { struct rte_eth_dcb_rx_conf *rx_conf =3D &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; - for (i =3D 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) { + for (i =3D 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) dcb_info->prio_tc[i] =3D rx_conf->dcb_tc[i]; - } =20 if (dcb_info->nb_tcs =3D=3D RTE_ETH_4_TCS) { for (i =3D 0; i < dcb_info->nb_tcs; i++) { @@ -279,7 +272,6 @@ static void sxe_dcb_vmdq_rx_param_get(struct rte_eth_de= v *dev, (u8)(1 << i); } =20 - return; } =20 void sxe_dcb_vmdq_rx_hw_configure(struct rte_eth_dev *dev) @@ -315,7 +307,6 @@ void sxe_dcb_vmdq_rx_hw_configure(struct rte_eth_dev *d= ev) cfg->pool_map[i].pools); } =20 - return; } =20 static void sxe_dcb_rx_param_get(struct rte_eth_dev *dev, @@ -341,11 +332,10 @@ static void sxe_dcb_rx_param_get(struct rte_eth_dev *= dev, (u8)(1 << i); } =20 - return; } =20 static void sxe_dcb_rx_hw_configure(struct rte_eth_dev *dev, - struct sxe_dcb_config *dcb_config) + struct sxe_dcb_config *dcb_config) { struct sxe_adapter *adapter =3D dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; @@ -354,7 +344,6 @@ static void sxe_dcb_rx_hw_configure(struct rte_eth_dev = *dev, sxe_hw_dcb_rx_configure(hw, dcb_config->vmdq_active, RTE_ETH_DEV_SRIOV(dev).active, dcb_config->num_tcs.pg_tcs); - return; } =20 static void sxe_dcb_vmdq_tx_param_get(struct rte_eth_dev *dev, @@ -385,7 +374,6 @@ static void sxe_dcb_vmdq_tx_param_get(struct rte_eth_de= v *dev, (u8)(1 << i); } =20 - return; } =20 static void sxe_dcb_vmdq_tx_hw_configure(struct rte_eth_dev *dev, @@ -402,7 +390,6 @@ static void sxe_dcb_vmdq_tx_hw_configure(struct rte_eth= _dev *dev, =20 sxe_hw_dcb_tx_configure(hw, dcb_config->vmdq_active, dcb_config->num_tcs.pg_tcs); - return; } =20 static void sxe_dcb_tx_param_get(struct rte_eth_dev *dev, @@ -428,7 +415,6 @@ static void sxe_dcb_tx_param_get(struct rte_eth_dev *de= v, (u8)(1 << i); } =20 - return; } =20 static u32 sxe_dcb_min_credit_get(u32 max_frame) @@ -468,9 +454,8 @@ static u32 sxe_dcb_cee_min_link_percent_get( link_percentage =3D sxe_dcb_cee_tc_link_percent_get( cee_config, direction, tc_index); =20 - if (link_percentage && link_percentage < min_link_percent) { + if (link_percentage && link_percentage < min_link_percent) min_link_percent =3D link_percentage; - } } =20 return min_link_percent; @@ -513,18 +498,16 @@ static s32 sxe_dcb_cee_tc_credits_calculate(struct sx= e_hw *hw, LOG_DEBUG_BDF("tc[%u] bwg_percent=3D%u, link_percentage=3D%u\n", tc_index, tc_info->bwg_percent, link_percentage); =20 - if (tc_info->bwg_percent > 0 && link_percentage =3D=3D 0) { + if (tc_info->bwg_percent > 0 && link_percentage =3D=3D 0) link_percentage =3D 1; - } =20 tc_info->link_percent =3D (u8)link_percentage; =20 credit_refill =3D min(link_percentage * total_credit, - (u32)MAX_CREDIT_REFILL); + (u32)MAX_CREDIT_REFILL); =20 - if (credit_refill < min_credit) { + if (credit_refill < min_credit) credit_refill =3D min_credit; - } =20 tc_info->data_credits_refill =3D (u16)credit_refill; LOG_DEBUG_BDF("tc[%u] credit_refill=3D%u\n", @@ -532,16 +515,14 @@ static s32 sxe_dcb_cee_tc_credits_calculate(struct sx= e_hw *hw, =20 credit_max =3D (link_percentage * MAX_CREDIT) / 100; =20 - if (credit_max < min_credit) { + if (credit_max < min_credit) credit_max =3D min_credit; - } LOG_DEBUG_BDF("tc[%u] credit_max=3D%u\n", tc_index, credit_max); =20 - if (direction =3D=3D DCB_PATH_TX) { + if (direction =3D=3D DCB_PATH_TX) cee_config->tc_config[tc_index].desc_credits_max =3D (u16)credit_max; - } =20 tc_info->data_credits_max =3D (u16)credit_max; } @@ -556,12 +537,10 @@ static void sxe_dcb_cee_refill_parse(struct sxe_dcb_c= onfig *cfg, struct sxe_tc_config *tc_config =3D &cfg->tc_config[0]; =20 for (tc =3D 0; tc < MAX_TRAFFIC_CLASS; tc++) { - refill[tc] =3D tc_config[tc]. \ - channel[direction].data_credits_refill; + refill[tc] =3D tc_config[tc].channel[direction].data_credits_refill; LOG_DEBUG("tc[%u] --- refill[%u]\n", tc, refill[tc]); } =20 - return; } =20 static void sxe_dcb_cee_max_credits_parse(struct sxe_dcb_config *cfg, @@ -575,7 +554,6 @@ static void sxe_dcb_cee_max_credits_parse(struct sxe_dc= b_config *cfg, LOG_DEBUG("tc[%u] --- max_credits[%u]\n", tc, max_credits[tc]); } =20 - return; } =20 static void sxe_dcb_cee_bwgid_parse(struct sxe_dcb_config *cfg, @@ -589,7 +567,6 @@ static void sxe_dcb_cee_bwgid_parse(struct sxe_dcb_conf= ig *cfg, LOG_DEBUG("tc[%u] --- bwgid[%u]\n", tc, bwgid[tc]); } =20 - return; } =20 static void sxe_dcb_cee_prio_parse(struct sxe_dcb_config *cfg, @@ -603,7 +580,6 @@ static void sxe_dcb_cee_prio_parse(struct sxe_dcb_confi= g *cfg, LOG_DEBUG("tc[%u] --- ptype[%u]\n", tc, ptype[tc]); } =20 - return; } =20 static void sxe_dcb_cee_pfc_parse(struct sxe_dcb_config *cfg, @@ -613,13 +589,11 @@ static void sxe_dcb_cee_pfc_parse(struct sxe_dcb_conf= ig *cfg, struct sxe_tc_config *tc_config =3D &cfg->tc_config[0]; =20 for (*pfc_en =3D 0, up =3D 0; up < MAX_TRAFFIC_CLASS; up++) { - if (tc_config[map[up]].pfc_type !=3D pfc_disabled) { + if (tc_config[map[up]].pfc_type !=3D pfc_disabled) *pfc_en |=3D BIT(up); - } } LOG_DEBUG("cfg[%p] pfc_en[0x%x]\n", cfg, *pfc_en); =20 - return; } =20 static s32 sxe_dcb_tc_stats_configure(struct sxe_hw *hw, @@ -673,7 +647,6 @@ static void sxe_dcb_rx_mq_mode_configure(struct rte_eth= _dev *dev, break; } =20 - return; } =20 static void sxe_dcb_tx_mq_mode_configure(struct rte_eth_dev *dev, @@ -705,7 +678,6 @@ static void sxe_dcb_tx_mq_mode_configure(struct rte_eth= _dev *dev, break; } =20 - return; } =20 static void sxe_dcb_bwg_percentage_alloc(struct rte_eth_dev *dev, @@ -719,25 +691,22 @@ static void sxe_dcb_bwg_percentage_alloc(struct rte_e= th_dev *dev, u8 nb_tcs =3D dcb_config->num_tcs.pfc_tcs; =20 if (nb_tcs =3D=3D RTE_ETH_4_TCS) { - - - for (i =3D 0; i < MAX_TRAFFIC_CLASS; i++) { - if (map[i] >=3D nb_tcs) { - PMD_LOG_INFO(DRV, "map[up-%u] to tc[%u] not exist, " - "change to tc 0", i, map[i]); - map[i] =3D 0; + for (i =3D 0; i < MAX_TRAFFIC_CLASS; i++) { + if (map[i] >=3D nb_tcs) { + PMD_LOG_INFO(DRV, "map[up-%u] to tc[%u] not exist, " + "change to tc 0", i, map[i]); + map[i] =3D 0; + } } - } =20 for (i =3D 0; i < nb_tcs; i++) { tc =3D &dcb_config->tc_config[i]; if (bw_conf->tc_num !=3D nb_tcs) { tc->channel[DCB_PATH_TX].bwg_percent =3D + (u8)(100 / nb_tcs); + } + tc->channel[DCB_PATH_RX].bwg_percent =3D (u8)(100 / nb_tcs); - } - - tc->channel[DCB_PATH_RX].bwg_percent =3D - (u8)(100 / nb_tcs); } for (; i < MAX_TRAFFIC_CLASS; i++) { tc =3D &dcb_config->tc_config[i]; @@ -757,7 +726,6 @@ static void sxe_dcb_bwg_percentage_alloc(struct rte_eth= _dev *dev, } } =20 - return; } =20 static void sxe_dcb_rx_pkt_buf_configure(struct sxe_hw *hw, @@ -768,15 +736,12 @@ static void sxe_dcb_rx_pkt_buf_configure(struct sxe_h= w *hw, =20 pbsize =3D (u16)(rx_buffer_size / tcs_num); =20 - for (i =3D 0; i < tcs_num; i++) { + for (i =3D 0; i < tcs_num; i++) sxe_hw_rx_pkt_buf_size_set(hw, i, pbsize); - } =20 - for (; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) { + for (; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++) sxe_hw_rx_pkt_buf_size_set(hw, i, 0); - } =20 - return; } =20 static void sxe_dcb_tx_pkt_buf_configure(struct sxe_hw *hw, u8 tcs_num) @@ -787,7 +752,6 @@ static void sxe_dcb_tx_pkt_buf_configure(struct sxe_hw = *hw, u8 tcs_num) sxe_hw_tx_pkt_buf_thresh_configure(hw, tcs_num, true); =20 sxe_hw_tx_pkt_buf_switch(hw, true); - return; } =20 static void sxe_dcb_rx_configure(struct rte_eth_dev *dev, @@ -795,10 +759,10 @@ static void sxe_dcb_rx_configure(struct rte_eth_dev *= dev, { struct sxe_adapter *adapter =3D dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; - u8 tsa[MAX_TRAFFIC_CLASS] =3D {0}; + u8 tsa[MAX_TRAFFIC_CLASS] =3D {0}; u8 bwgid[MAX_TRAFFIC_CLASS] =3D {0}; u16 refill[MAX_TRAFFIC_CLASS] =3D {0}; - u16 max[MAX_TRAFFIC_CLASS] =3D {0}; + u16 max[MAX_TRAFFIC_CLASS] =3D {0}; =20 sxe_dcb_rx_pkt_buf_configure(hw, SXE_RX_PKT_BUF_SIZE, dcb_config->num_tcs= .pg_tcs); =20 @@ -809,7 +773,6 @@ static void sxe_dcb_rx_configure(struct rte_eth_dev *de= v, =20 sxe_hw_dcb_rx_bw_alloc_configure(hw, refill, max, bwgid, tsa, map, MAX_USER_PRIORITY); - return; } =20 static void sxe_dcb_tx_configure(struct rte_eth_dev *dev, @@ -817,10 +780,10 @@ static void sxe_dcb_tx_configure(struct rte_eth_dev *= dev, { struct sxe_adapter *adapter =3D dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; - u8 tsa[MAX_TRAFFIC_CLASS] =3D {0}; + u8 tsa[MAX_TRAFFIC_CLASS] =3D {0}; u8 bwgid[MAX_TRAFFIC_CLASS] =3D {0}; u16 refill[MAX_TRAFFIC_CLASS] =3D {0}; - u16 max[MAX_TRAFFIC_CLASS] =3D {0}; + u16 max[MAX_TRAFFIC_CLASS] =3D {0}; =20 sxe_dcb_tx_pkt_buf_configure(hw, dcb_config->num_tcs.pg_tcs); =20 @@ -833,7 +796,6 @@ static void sxe_dcb_tx_configure(struct rte_eth_dev *de= v, sxe_hw_dcb_tx_data_bw_alloc_configure(hw, refill, max, bwgid, tsa, map, MAX_USER_PRIORITY); =20 - return; } =20 static void sxe_dcb_pfc_configure(struct sxe_hw *hw, @@ -855,13 +817,11 @@ static void sxe_dcb_pfc_configure(struct sxe_hw *hw, } =20 sxe_dcb_cee_pfc_parse(dcb_config, map, &pfc_en); - if (dcb_config->num_tcs.pfc_tcs =3D=3D RTE_ETH_4_TCS) { + if (dcb_config->num_tcs.pfc_tcs =3D=3D RTE_ETH_4_TCS) pfc_en &=3D 0x0F; - } =20 sxe_hw_dcb_pfc_configure(hw, pfc_en, map, MAX_USER_PRIORITY); =20 - return; } =20 static void sxe_dcb_hw_configure(struct rte_eth_dev *dev, @@ -884,21 +844,17 @@ static void sxe_dcb_hw_configure(struct rte_eth_dev *= dev, sxe_dcb_cee_tc_credits_calculate(hw, dcb_config, max_frame, DCB_PATH_TX); sxe_dcb_cee_tc_credits_calculate(hw, dcb_config, max_frame, DCB_PATH_RX); =20 - if (rx_configed) { + if (rx_configed) sxe_dcb_rx_configure(dev, dcb_config, map); - } =20 - if (tx_configed) { + if (tx_configed) sxe_dcb_tx_configure(dev, dcb_config, map); - } =20 sxe_dcb_tc_stats_configure(hw, dcb_config); =20 - if (dev->data->dev_conf.dcb_capability_en & RTE_ETH_DCB_PFC_SUPPORT) { + if (dev->data->dev_conf.dcb_capability_en & RTE_ETH_DCB_PFC_SUPPORT) sxe_dcb_pfc_configure(hw, dcb_config, map); - } =20 - return; } =20 void sxe_dcb_configure(struct rte_eth_dev *dev) @@ -913,21 +869,19 @@ void sxe_dcb_configure(struct rte_eth_dev *dev) if ((dev_conf->rxmode.mq_mode !=3D RTE_ETH_MQ_RX_VMDQ_DCB) && (dev_conf->rxmode.mq_mode !=3D RTE_ETH_MQ_RX_DCB) && (dev_conf->rxmode.mq_mode !=3D RTE_ETH_MQ_RX_DCB_RSS)) { - PMD_LOG_INFO(INIT, "dcb config failed, cause mq_mode=3D0x%x",=20 + PMD_LOG_INFO(INIT, "dcb config failed, cause mq_mode=3D0x%x", (u8)dev_conf->rxmode.mq_mode); - goto l_end; + return; } =20 if (dev->data->nb_rx_queues > RTE_ETH_DCB_NUM_QUEUES) { - PMD_LOG_INFO(INIT, "dcb config failed, cause nb_rx_queues=3D%u > %u",=20 + PMD_LOG_INFO(INIT, "dcb config failed, cause nb_rx_queues=3D%u > %u", dev->data->nb_rx_queues, RTE_ETH_DCB_NUM_QUEUES); - goto l_end; + return; } =20 sxe_dcb_hw_configure(dev, dcb_cfg); =20 -l_end: - return; } =20 s32 rte_pmd_sxe_tc_bw_set(u8 port, @@ -979,20 +933,19 @@ s32 rte_pmd_sxe_tc_bw_set(u8 port, =20 if (nb_tcs !=3D tc_num) { PMD_LOG_ERR(DRV, - "Weight should be set for all %d enabled TCs.", - nb_tcs); + "Weight should be set for all %d enabled TCs.", + nb_tcs); ret =3D -EINVAL; goto l_end; } =20 sum =3D 0; - for (i =3D 0; i < nb_tcs; i++) { + for (i =3D 0; i < nb_tcs; i++) sum +=3D bw_weight[i]; - } =20 if (sum !=3D 100) { PMD_LOG_ERR(DRV, - "The summary of the TC weight should be 100."); + "The summary of the TC weight should be 100."); ret =3D -EINVAL; goto l_end; } diff --git a/drivers/net/sxe/pf/sxe_dcb.h b/drivers/net/sxe/pf/sxe_dcb.h index accfc930af..2330febb2e 100644 --- a/drivers/net/sxe/pf/sxe_dcb.h +++ b/drivers/net/sxe/pf/sxe_dcb.h @@ -1,21 +1,21 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright (C), 2022, Linkdata Technology Co., Ltd. */ -=20 + #ifndef __SXE_DCB_H__ #define __SXE_DCB_H__ #include =20 -#define PBA_STRATEGY_EQUAL (0)=20=20=20=20 -#define PBA_STRATEGY_WEIGHTED (1)=09 -#define MAX_BW_GROUP 8 -#define MAX_USER_PRIORITY 8 -#define SXE_DCB_MAX_TRAFFIC_CLASS 8 +#define PBA_STRATEGY_EQUAL (0) +#define PBA_STRATEGY_WEIGHTED (1) +#define MAX_BW_GROUP 8 +#define MAX_USER_PRIORITY 8 +#define SXE_DCB_MAX_TRAFFIC_CLASS 8 =20 enum sxe_dcb_strict_prio_type { - DCB_PRIO_NONE =3D 0,=20 - DCB_PRIO_GROUP,=20=20=20=20 - DCB_PRIO_LINK=20=20=20=20=20=20 + DCB_PRIO_NONE =3D 0, + DCB_PRIO_GROUP, + DCB_PRIO_LINK }; enum { DCB_PATH_TX =3D 0, @@ -35,18 +35,18 @@ enum sxe_dcb_pba_config { }; =20 struct sxe_dcb_num_tcs { - u8 pg_tcs;=09 + u8 pg_tcs; u8 pfc_tcs; }; =20 struct sxe_tc_bw_alloc { - u8 bwg_id;=09=09=20=20 - u8 bwg_percent;=09=09=20=20 - u8 link_percent;=09=20=20 - u8 up_to_tc_bitmap;=09=20=20 - u16 data_credits_refill;=20=20 - u16 data_credits_max;=09=20=20 - enum sxe_dcb_strict_prio_type prio_type;=20 + u8 bwg_id; + u8 bwg_percent; + u8 link_percent; + u8 up_to_tc_bitmap; + u16 data_credits_refill; + u16 data_credits_max; + enum sxe_dcb_strict_prio_type prio_type; }; =20 enum sxe_dcb_pfc_type { @@ -57,17 +57,17 @@ enum sxe_dcb_pfc_type { }; =20 struct sxe_tc_config { - struct sxe_tc_bw_alloc channel[DCB_PATH_NUM];=20 - enum sxe_dcb_pfc_type pfc_type;=20 + struct sxe_tc_bw_alloc channel[DCB_PATH_NUM]; + enum sxe_dcb_pfc_type pfc_type; =20 - u16 desc_credits_max;=20 - u8 tc;=20 + u16 desc_credits_max; + u8 tc; }; =20 struct sxe_dcb_config { struct sxe_tc_config tc_config[SXE_DCB_MAX_TRAFFIC_CLASS]; struct sxe_dcb_num_tcs num_tcs; - u8 bwg_link_percent[DCB_PATH_NUM][MAX_BW_GROUP];=20 + u8 bwg_link_percent[DCB_PATH_NUM][MAX_BW_GROUP]; bool pfc_mode_enable; bool round_robin_enable; =20 @@ -76,7 +76,7 @@ struct sxe_dcb_config { }; =20 struct sxe_bw_config { - u8 tc_num;=20 + u8 tc_num; }; =20 struct sxe_dcb_context { @@ -86,7 +86,7 @@ struct sxe_dcb_context { =20 void sxe_dcb_init(struct rte_eth_dev *dev); =20 -s32 sxe_priority_flow_ctrl_set(struct rte_eth_dev *dev,=20 +s32 sxe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf); =20 s32 sxe_get_dcb_info(struct rte_eth_dev *dev, diff --git a/drivers/net/sxe/pf/sxe_ethdev.c b/drivers/net/sxe/pf/sxe_ethde= v.c index 00c6674f75..136469cb72 100644 --- a/drivers/net/sxe/pf/sxe_ethdev.c +++ b/drivers/net/sxe/pf/sxe_ethdev.c @@ -53,20 +53,20 @@ #include "sxe_tm.h" #endif =20 -#define SXE_DEFAULT_MTU 1500 -#define SXE_ETH_HLEN 14 -#define SXE_ETH_FCS_LEN 4 -#define SXE_ETH_FRAME_LEN 1514 +#define SXE_DEFAULT_MTU 1500 +#define SXE_ETH_HLEN 14 +#define SXE_ETH_FCS_LEN 4 +#define SXE_ETH_FRAME_LEN 1514 =20 -#define SXE_ETH_MAX_LEN (RTE_ETHER_MTU + SXE_ETH_OVERHEAD)=20 +#define SXE_ETH_MAX_LEN (RTE_ETHER_MTU + SXE_ETH_OVERHEAD) =20 -STATIC const struct rte_eth_desc_lim sxe_rx_desc_lim =3D { +static const struct rte_eth_desc_lim sxe_rx_desc_lim =3D { .nb_max =3D SXE_MAX_RING_DESC, .nb_min =3D SXE_MIN_RING_DESC, .nb_align =3D SXE_RX_DESC_RING_ALIGN, }; =20 -STATIC const struct rte_eth_desc_lim sxe_tx_desc_lim =3D { +static const struct rte_eth_desc_lim sxe_tx_desc_lim =3D { .nb_max =3D SXE_MAX_RING_DESC, .nb_min =3D SXE_MIN_RING_DESC, .nb_align =3D SXE_TX_DESC_RING_ALIGN, @@ -74,9 +74,9 @@ STATIC const struct rte_eth_desc_lim sxe_tx_desc_lim =3D { .nb_mtu_seg_max =3D SXE_TX_MAX_SEG, }; =20 -s32 sxe_dev_reset(struct rte_eth_dev *eth_dev); +static s32 sxe_dev_reset(struct rte_eth_dev *eth_dev); =20 -STATIC s32 sxe_dev_configure(struct rte_eth_dev *dev) +static s32 sxe_dev_configure(struct rte_eth_dev *dev) { s32 ret; struct sxe_adapter *adapter =3D dev->data->dev_private; @@ -94,7 +94,7 @@ STATIC s32 sxe_dev_configure(struct rte_eth_dev *dev) ret =3D sxe_mq_mode_check(dev); if (ret !=3D 0) { PMD_LOG_ERR(INIT, "sxe mq mode check fails with %d.", - ret); + ret); goto l_end; } =20 @@ -114,13 +114,12 @@ STATIC s32 sxe_dev_configure(struct rte_eth_dev *dev) static void sxe_txrx_start(struct rte_eth_dev *dev) { struct sxe_adapter *adapter =3D dev->data->dev_private; - struct sxe_hw *hw =3D &adapter->hw; + struct sxe_hw *hw =3D &adapter->hw; =20 sxe_hw_rx_cap_switch_on(hw); =20 sxe_hw_mac_txrx_enable(hw); =20 - return; } =20 static s32 sxe_link_configure(struct rte_eth_dev *dev) @@ -145,11 +144,11 @@ static s32 sxe_link_configure(struct rte_eth_dev *dev) goto l_end; } =20 - if (adapter->phy_ctxt.sfp_info.multispeed_fiber) { + if (adapter->phy_ctxt.sfp_info.multispeed_fiber) ret =3D sxe_multispeed_sfp_link_configure(dev, conf_speeds, false); - } else { + else ret =3D sxe_sfp_link_configure(dev); - } + if (ret) { PMD_LOG_ERR(INIT, "link config failed, speed=3D%x", conf_speeds); @@ -184,7 +183,7 @@ static s32 sxe_loopback_pcs_init(struct sxe_adapter *ad= apter, sxe_fc_mac_addr_set(adapter); =20 LOG_INFO_BDF("mode:%u max_frame:0x%x loopback pcs init done.\n", - mode, max_frame); + mode, max_frame); l_end: return ret; } @@ -300,12 +299,12 @@ static s32 sxe_dev_start(struct rte_eth_dev *dev) =20 if (dev->data->dev_conf.lpbk_mode =3D=3D SXE_LPBK_DISABLED) { sxe_link_configure(dev); - } else if (dev->data->dev_conf.lpbk_mode =3D=3D SXE_LPBK_ENABLED){ - sxe_loopback_configure(adapter); + } else if (dev->data->dev_conf.lpbk_mode =3D=3D SXE_LPBK_ENABLED) { + sxe_loopback_configure(adapter); } else { ret =3D -ENOTSUP; PMD_LOG_ERR(INIT, "unsupport loopback mode:%u.", - dev->data->dev_conf.lpbk_mode); + dev->data->dev_conf.lpbk_mode); goto l_end; } =20 @@ -320,9 +319,8 @@ static s32 sxe_dev_start(struct rte_eth_dev *dev) sxe_dcb_configure(dev); =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_MACSEC - if (macsec_ctxt->offload_en) { + if (macsec_ctxt->offload_en) sxe_macsec_enable(dev, macsec_ctxt); - } #endif =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL @@ -389,15 +387,14 @@ static s32 sxe_dev_stop(struct rte_eth_dev *dev) adapter->is_stopped =3D true; =20 num =3D rte_eal_alarm_cancel(sxe_event_irq_delayed_handler, dev); - if (num > 0) { + if (num > 0) sxe_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); - } =20 LOG_DEBUG_BDF("dev stop success."); =20 l_end: #ifdef DPDK_19_11_6 - return; + LOG_DEBUG_BDF("at end of dev stop."); #else return ret; #endif @@ -417,7 +414,7 @@ static s32 sxe_dev_close(struct rte_eth_dev *dev) =20 if (rte_eal_process_type() !=3D RTE_PROC_PRIMARY) { PMD_LOG_INFO(INIT, "not primary, do nothing"); - goto l_end; + goto l_end; } =20 sxe_hw_hdc_drv_status_set(hw, (u32)false); @@ -436,9 +433,8 @@ static s32 sxe_dev_close(struct rte_eth_dev *dev) sxe_dev_stop(dev); #else ret =3D sxe_dev_stop(dev); - if (ret) { + if (ret) PMD_LOG_ERR(INIT, "dev stop fail.(err:%d)", ret); - } #endif =20 sxe_queues_free(dev); @@ -461,7 +457,7 @@ static s32 sxe_dev_close(struct rte_eth_dev *dev) =20 l_end: #ifdef DPDK_19_11_6 - return; + LOG_DEBUG_BDF("at end of dev close."); #else return ret; #endif @@ -476,13 +472,12 @@ static s32 sxe_dev_infos_get(struct rte_eth_dev *dev, dev_info->max_rx_queues =3D SXE_HW_TXRX_RING_NUM_MAX; dev_info->max_tx_queues =3D SXE_HW_TXRX_RING_NUM_MAX; if (RTE_ETH_DEV_SRIOV(dev).active =3D=3D 0) { - if (dev_conf->txmode.mq_mode =3D=3D RTE_ETH_MQ_TX_NONE) { + if (dev_conf->txmode.mq_mode =3D=3D RTE_ETH_MQ_TX_NONE) dev_info->max_tx_queues =3D SXE_HW_TX_NONE_MODE_Q_NUM; - } } =20 dev_info->min_rx_bufsize =3D 1024; - dev_info->max_rx_pktlen =3D 15872;=20 + dev_info->max_rx_pktlen =3D 15872; dev_info->max_mac_addrs =3D SXE_UC_ENTRY_NUM_MAX; dev_info->max_hash_mac_addrs =3D SXE_HASH_UC_NUM_MAX; dev_info->max_vfs =3D pci_dev->max_vfs; @@ -493,7 +488,7 @@ static s32 sxe_dev_infos_get(struct rte_eth_dev *dev, =20 dev_info->rx_queue_offload_capa =3D sxe_rx_queue_offload_capa_get(dev); dev_info->rx_offload_capa =3D (sxe_rx_port_offload_capa_get(dev) | - dev_info->rx_queue_offload_capa); + dev_info->rx_queue_offload_capa); dev_info->tx_queue_offload_capa =3D sxe_tx_queue_offload_capa_get(dev); dev_info->tx_offload_capa =3D sxe_tx_port_offload_capa_get(dev); =20 @@ -548,7 +543,7 @@ static s32 sxe_mtu_set(struct rte_eth_dev *dev, u16 mtu) =20 ret =3D sxe_dev_infos_get(dev, &dev_info); if (ret !=3D 0) { - PMD_LOG_ERR(INIT, "get dev info fails with ret=3D%d",ret); + PMD_LOG_ERR(INIT, "get dev info fails with ret=3D%d", ret); goto l_end; } =20 @@ -586,7 +581,7 @@ static s32 sxe_mtu_set(struct rte_eth_dev *dev, u16 mtu) } =20 static int sxe_get_regs(struct rte_eth_dev *dev, - struct rte_dev_reg_info *regs) + struct rte_dev_reg_info *regs) { s32 ret =3D 0; u32 *data =3D regs->data; @@ -625,7 +620,7 @@ static s32 sxe_led_reset(struct rte_eth_dev *dev) struct sxe_adapter *adapter =3D (struct sxe_adapter *)(dev->data->dev_pri= vate); struct sxe_hw *hw =3D &adapter->hw; =20 - ctrl.mode =3D SXE_IDENTIFY_LED_RESET;=20 + ctrl.mode =3D SXE_IDENTIFY_LED_RESET; ctrl.duration =3D 0; =20 ret =3D sxe_driver_cmd_trans(hw, SXE_CMD_LED_CTRL, @@ -635,7 +630,7 @@ static s32 sxe_led_reset(struct rte_eth_dev *dev) LOG_ERROR_BDF("hdc trans failed ret=3D%d, cmd:led reset", ret); ret =3D -EIO; } else { - LOG_DEBUG_BDF("led reset sucess"); + LOG_DEBUG_BDF("led reset success"); } =20 return ret; @@ -648,8 +643,7 @@ static s32 sxe_led_ctrl(struct sxe_adapter *adapter, bo= ol is_on) struct sxe_led_ctrl ctrl; struct sxe_hw *hw =3D &adapter->hw; =20 - ctrl.mode =3D (true =3D=3D is_on) ? SXE_IDENTIFY_LED_ON : \ - SXE_IDENTIFY_LED_OFF; + ctrl.mode =3D (true =3D=3D is_on) ? SXE_IDENTIFY_LED_ON : SXE_IDENTIFY_LE= D_OFF; ctrl.duration =3D 0; =20 ret =3D sxe_driver_cmd_trans(hw, SXE_CMD_LED_CTRL, @@ -708,11 +702,10 @@ static int sxe_fw_version_get(struct rte_eth_dev *dev= , char *fw_version, goto l_end; } =20 - ret +=3D 1;=20 + ret +=3D 1; =20 - if (fw_size >=3D (size_t)ret) { + if (fw_size >=3D (size_t)ret) ret =3D 0; - } =20 l_end: return ret; @@ -787,9 +780,9 @@ static const struct eth_dev_ops sxe_eth_dev_ops =3D { .timesync_read_time =3D sxe_timesync_read_time, .timesync_write_time =3D sxe_timesync_write_time, =20 - .vlan_filter_set =3D sxe_vlan_filter_set, - .vlan_tpid_set =3D sxe_vlan_tpid_set, - .vlan_offload_set =3D sxe_vlan_offload_set, + .vlan_filter_set =3D sxe_vlan_filter_set, + .vlan_tpid_set =3D sxe_vlan_tpid_set, + .vlan_offload_set =3D sxe_vlan_offload_set, .vlan_strip_queue_set =3D sxe_vlan_strip_queue_set, =20 .get_reg =3D sxe_get_regs, @@ -809,8 +802,8 @@ static const struct eth_dev_ops sxe_eth_dev_ops =3D { =20 #ifdef ETH_DEV_MIRROR_RULE #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SRIOV - .mirror_rule_set =3D sxe_mirror_rule_set, - .mirror_rule_reset =3D sxe_mirror_rule_reset, + .mirror_rule_set =3D sxe_mirror_rule_set, + .mirror_rule_reset =3D sxe_mirror_rule_reset, #endif #endif =20 @@ -885,20 +878,20 @@ static s32 sxe_hw_base_init(struct rte_eth_dev *eth_d= ev) #endif =20 l_out: - if (ret) { + if (ret) sxe_hw_hdc_drv_status_set(hw, (u32)false); - } + return ret; } =20 -void sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, bool rx_batch_al= loc_allowed, bool *rx_vec_allowed) +void sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, + bool rx_batch_alloc_allowed, bool *rx_vec_allowed) { __sxe_secondary_proc_init(eth_dev, rx_batch_alloc_allowed, rx_vec_allowed= ); =20 - return; } =20 -STATIC void sxe_ethdev_mac_mem_free(struct rte_eth_dev *eth_dev) +static void sxe_ethdev_mac_mem_free(struct rte_eth_dev *eth_dev) { struct sxe_adapter *adapter =3D eth_dev->data->dev_private; =20 @@ -917,14 +910,13 @@ STATIC void sxe_ethdev_mac_mem_free(struct rte_eth_de= v *eth_dev) adapter->mac_filter_ctxt.uc_addr_table =3D NULL; } =20 - return; } =20 -#ifdef DPDK_19_11_6 +#ifdef DPDK_19_11_6 static void sxe_pf_init(struct sxe_adapter *adapter) { memset(&adapter->vlan_ctxt, 0, sizeof(adapter->vlan_ctxt)); - memset(&adapter->mac_filter_ctxt.uta_hash_table, 0, \ + memset(&adapter->mac_filter_ctxt.uta_hash_table, 0, sizeof(adapter->mac_filter_ctxt.uta_hash_table)); memset(&adapter->dcb_ctxt.config, 0, sizeof(adapter->dcb_ctxt.config)); =20 @@ -932,7 +924,6 @@ static void sxe_pf_init(struct sxe_adapter *adapter) memset(&adapter->filter_ctxt, 0, sizeof(adapter->filter_ctxt)); #endif =20 - return; } #endif =20 @@ -948,7 +939,7 @@ s32 sxe_ethdev_init(struct rte_eth_dev *eth_dev, void *= param __rte_unused) eth_dev->dev_ops =3D &sxe_eth_dev_ops; =20 #ifndef ETH_DEV_OPS_HAS_DESC_RELATE - eth_dev->rx_queue_count =3D sxe_rx_queue_count; + eth_dev->rx_queue_count =3D sxe_rx_queue_count; eth_dev->rx_descriptor_status =3D sxe_rx_descriptor_status; eth_dev->tx_descriptor_status =3D sxe_tx_descriptor_status; #ifdef ETH_DEV_RX_DESC_DONE @@ -962,10 +953,12 @@ s32 sxe_ethdev_init(struct rte_eth_dev *eth_dev, void= *param __rte_unused) =20 if (rte_eal_process_type() !=3D RTE_PROC_PRIMARY) { #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD - sxe_secondary_proc_init(eth_dev, adapter->rx_batch_alloc_allowed, &adapt= er->rx_vec_allowed); + sxe_secondary_proc_init(eth_dev, adapter->rx_batch_alloc_allowed, + &adapter->rx_vec_allowed); #else bool rx_vec_allowed =3D 0; - sxe_secondary_proc_init(eth_dev, adapter->rx_batch_alloc_allowed, &rx_ve= c_allowed); + sxe_secondary_proc_init(eth_dev, adapter->rx_batch_alloc_allowed, + &rx_vec_allowed); #endif goto l_out; } @@ -973,7 +966,7 @@ s32 sxe_ethdev_init(struct rte_eth_dev *eth_dev, void *= param __rte_unused) rte_atomic32_clear(&adapter->link_thread_running); rte_eth_copy_pci_info(eth_dev, pci_dev); =20 -#ifdef DPDK_19_11_6 +#ifdef DPDK_19_11_6 eth_dev->data->dev_flags |=3D RTE_ETH_DEV_CLOSE_REMOVE; sxe_pf_init(adapter); #endif @@ -1045,13 +1038,13 @@ s32 sxe_ethdev_uninit(struct rte_eth_dev *eth_dev) return 0; } =20 -s32 sxe_dev_reset(struct rte_eth_dev *eth_dev) +static s32 sxe_dev_reset(struct rte_eth_dev *eth_dev) { s32 ret; =20 if (eth_dev->data->sriov.active) { ret =3D -ENOTSUP; - PMD_LOG_ERR(INIT, "sriov actived, not support reset pf port[%u]", + PMD_LOG_ERR(INIT, "sriov activated, not support reset pf port[%u]", eth_dev->data->port_id); goto l_end; } @@ -1092,7 +1085,7 @@ s32 rte_pmd_sxe_tx_loopback_set(u16 port, u8 on) if (on > 1) { ret =3D -EINVAL; PMD_LOG_ERR(DRV, "port:%u invalid user configure value:%u.", - port, on); + port, on); goto l_out; } =20 diff --git a/drivers/net/sxe/pf/sxe_ethdev.h b/drivers/net/sxe/pf/sxe_ethde= v.h index f1165e0413..66034343ea 100644 --- a/drivers/net/sxe/pf/sxe_ethdev.h +++ b/drivers/net/sxe/pf/sxe_ethdev.h @@ -7,11 +7,11 @@ =20 #include "sxe.h" =20 -#define SXE_MMW_SIZE_DEFAULT 0x4 -#define SXE_MMW_SIZE_JUMBO_FRAME 0x14 -#define SXE_MAX_JUMBO_FRAME_SIZE 0x2600=20 +#define SXE_MMW_SIZE_DEFAULT 0x4 +#define SXE_MMW_SIZE_JUMBO_FRAME 0x14 +#define SXE_MAX_JUMBO_FRAME_SIZE 0x2600 =20 -#define SXE_ETH_MAX_LEN (RTE_ETHER_MTU + SXE_ETH_OVERHEAD)=20 +#define SXE_ETH_MAX_LEN (RTE_ETHER_MTU + SXE_ETH_OVERHEAD) =20 #define SXE_HKEY_MAX_INDEX 10 #define SXE_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN) @@ -22,6 +22,7 @@ s32 sxe_ethdev_init(struct rte_eth_dev *eth_dev, void *pa= ram __rte_unused); =20 s32 sxe_ethdev_uninit(struct rte_eth_dev *eth_dev); =20 -void sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, bool rx_batch_al= loc_allowed, bool *rx_vec_allowed); +void sxe_secondary_proc_init(struct rte_eth_dev *eth_dev, + bool rx_batch_alloc_allowed, bool *rx_vec_allowed); =20 #endif diff --git a/drivers/net/sxe/pf/sxe_filter.c b/drivers/net/sxe/pf/sxe_filte= r.c index e323af94f8..1d1d78b516 100644 --- a/drivers/net/sxe/pf/sxe_filter.c +++ b/drivers/net/sxe/pf/sxe_filter.c @@ -25,7 +25,7 @@ #include "sxe_cli.h" #include "sxe_compat_version.h" =20 -#define PF_POOL_INDEX(p) (p) +#define PF_POOL_INDEX(p) (p) =20 #define SXE_STRIP_BITMAP_SET(h, q) \ do { \ @@ -76,16 +76,14 @@ static void sxe_default_mac_addr_get(struct sxe_adapter= *adapter) ret =3D sxe_get_mac_addr_from_fw(adapter, mac_addr.addr_bytes); if (ret || !rte_is_valid_assigned_ether_addr(&mac_addr)) { LOG_DEBUG("invalid default mac addr:"MAC_FMT" result:%d\n", - MAC_ADDR(mac_addr.addr_bytes), ret); - goto l_out; + MAC_ADDR(mac_addr.addr_bytes), ret); + return; } =20 LOG_DEBUG("default mac addr =3D "MAC_FMT"\n", MAC_ADDR(mac_addr.addr_byte= s)); rte_ether_addr_copy(&mac_addr, &adapter->mac_filter_ctxt.def_mac_addr); rte_ether_addr_copy(&mac_addr, &adapter->mac_filter_ctxt.fc_mac_addr); =20 -l_out: - return; } =20 static u8 sxe_sw_uc_entry_add(struct sxe_adapter *adapter, u8 index, @@ -114,9 +112,8 @@ static u8 sxe_sw_uc_entry_del(struct sxe_adapter *adapt= er, u8 index) struct sxe_uc_addr_table *uc_table =3D adapter->mac_filter_ctxt.uc_addr_t= able; =20 for (i =3D 0; i < SXE_UC_ENTRY_NUM_MAX; i++) { - if (!uc_table[i].used || (uc_table[i].type !=3D SXE_PF)) { + if (!uc_table[i].used || (uc_table[i].type !=3D SXE_PF)) continue; - } =20 if (uc_table[i].original_index =3D=3D index) { uc_table[i].used =3D false; @@ -154,16 +151,14 @@ s32 sxe_sw_uc_entry_vf_del(struct sxe_adapter *adapte= r, u8 vf_idx, struct sxe_uc_addr_table *uc_table =3D adapter->mac_filter_ctxt.uc_addr_t= able; =20 for (i =3D 0; i < SXE_UC_ENTRY_NUM_MAX; i++) { - if (!uc_table[i].used || (uc_table[i].type =3D=3D SXE_PF)) { + if (!uc_table[i].used || (uc_table[i].type =3D=3D SXE_PF)) continue; - } =20 if (uc_table[i].vf_idx =3D=3D vf_idx) { uc_table[i].used =3D false; sxe_hw_uc_addr_del(&adapter->hw, i); - if (!macvlan) { + if (!macvlan) break; - } } } =20 @@ -244,11 +239,11 @@ s32 sxe_promiscuous_enable(struct rte_eth_dev *dev) u32 flt_ctrl; =20 flt_ctrl =3D sxe_hw_rx_mode_get(hw); - PMD_LOG_DEBUG(DRV,"read flt_ctrl=3D0x%x\n", flt_ctrl); + PMD_LOG_DEBUG(DRV, "read flt_ctrl=3D0x%x\n", flt_ctrl); =20 flt_ctrl |=3D (SXE_FCTRL_UPE | SXE_FCTRL_MPE); =20 - PMD_LOG_DEBUG(DRV,"write flt_ctrl=3D0x%x\n", flt_ctrl); + PMD_LOG_DEBUG(DRV, "write flt_ctrl=3D0x%x\n", flt_ctrl); sxe_hw_rx_mode_set(hw, flt_ctrl); =20 return 0; @@ -261,16 +256,15 @@ s32 sxe_promiscuous_disable(struct rte_eth_dev *dev) u32 flt_ctrl; =20 flt_ctrl =3D sxe_hw_rx_mode_get(hw); - PMD_LOG_DEBUG(DRV,"read flt_ctrl=3D0x%x\n", flt_ctrl); + PMD_LOG_DEBUG(DRV, "read flt_ctrl=3D0x%x\n", flt_ctrl); =20 flt_ctrl &=3D (~SXE_FCTRL_UPE); - if (dev->data->all_multicast =3D=3D 1) { + if (dev->data->all_multicast =3D=3D 1) flt_ctrl |=3D SXE_FCTRL_MPE; - } else { + else flt_ctrl &=3D (~SXE_FCTRL_MPE); - } =20 - PMD_LOG_DEBUG(DRV,"write flt_ctrl=3D0x%x\n", flt_ctrl); + PMD_LOG_DEBUG(DRV, "write flt_ctrl=3D0x%x\n", flt_ctrl); sxe_hw_rx_mode_set(hw, flt_ctrl); =20 return 0; @@ -283,11 +277,11 @@ s32 sxe_allmulticast_enable(struct rte_eth_dev *dev) u32 flt_ctrl; =20 flt_ctrl =3D sxe_hw_rx_mode_get(hw); - PMD_LOG_DEBUG(DRV,"read flt_ctrl=3D0x%x\n", flt_ctrl); + PMD_LOG_DEBUG(DRV, "read flt_ctrl=3D0x%x\n", flt_ctrl); =20 flt_ctrl |=3D SXE_FCTRL_MPE; =20 - PMD_LOG_DEBUG(DRV,"write flt_ctrl=3D0x%x\n", flt_ctrl); + PMD_LOG_DEBUG(DRV, "write flt_ctrl=3D0x%x\n", flt_ctrl); sxe_hw_rx_mode_set(hw, flt_ctrl); =20 return 0; @@ -300,16 +294,16 @@ s32 sxe_allmulticast_disable(struct rte_eth_dev *dev) u32 flt_ctrl; =20 if (dev->data->promiscuous =3D=3D 1) { - PMD_LOG_DEBUG(DRV,"promiscuous is enable, allmulticast must be enabled.\= n"); + PMD_LOG_DEBUG(DRV, "promiscuous is enable, allmulticast must be enabled.= \n"); goto l_out; } =20 flt_ctrl =3D sxe_hw_rx_mode_get(hw); - PMD_LOG_DEBUG(DRV,"read flt_ctrl=3D0x%x\n", flt_ctrl); + PMD_LOG_DEBUG(DRV, "read flt_ctrl=3D0x%x\n", flt_ctrl); =20 flt_ctrl &=3D (~SXE_FCTRL_MPE); =20 - PMD_LOG_DEBUG(DRV,"write flt_ctrl=3D0x%x\n", flt_ctrl); + PMD_LOG_DEBUG(DRV, "write flt_ctrl=3D0x%x\n", flt_ctrl); sxe_hw_rx_mode_set(hw, flt_ctrl); =20 l_out: @@ -317,8 +311,8 @@ s32 sxe_allmulticast_disable(struct rte_eth_dev *dev) } =20 s32 sxe_mac_addr_add(struct rte_eth_dev *dev, - struct rte_ether_addr *mac_addr, - u32 index, u32 pool) + struct rte_ether_addr *mac_addr, + u32 index, u32 pool) { struct sxe_adapter *adapter =3D dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; @@ -359,15 +353,13 @@ void sxe_mac_addr_remove(struct rte_eth_dev *dev, u32= index) if (ret) { PMD_LOG_ERR(DRV, "rar_idx:%u remove fail.(err:%d)", rar_idx, ret); - goto l_out; + return; } =20 PMD_LOG_INFO(DRV, "rar_idx:%u mac_addr:"MAC_FMT" remove done", rar_idx, MAC_ADDR(&dev->data->mac_addrs[rar_idx])); =20 -l_out: - return; } =20 void sxe_fc_mac_addr_set(struct sxe_adapter *adapter) @@ -377,11 +369,10 @@ void sxe_fc_mac_addr_set(struct sxe_adapter *adapter) sxe_hw_fc_mac_addr_set(hw, adapter->mac_filter_ctxt.fc_mac_addr.addr_bytes); =20 - return; } =20 s32 sxe_mac_addr_set(struct rte_eth_dev *dev, - struct rte_ether_addr *mac_addr) + struct rte_ether_addr *mac_addr) { u8 pool_idx; struct sxe_adapter *adapter =3D dev->data->dev_private; @@ -425,7 +416,6 @@ static void sxe_hash_mac_addr_parse(u8 *mac_addr, u16 *= reg_idx, PMD_LOG_DEBUG(DRV, "mac_addr:"MAC_FMT" hash reg_idx:%u bit_idx:%u", MAC_ADDR(mac_addr), *reg_idx, *bit_idx); =20 - return; } =20 s32 sxe_uc_hash_table_set(struct rte_eth_dev *dev, @@ -442,16 +432,15 @@ s32 sxe_uc_hash_table_set(struct rte_eth_dev *dev, sxe_hash_mac_addr_parse(mac_addr->addr_bytes, ®_idx, &bit_idx); =20 value =3D (mac_filter->uta_hash_table[reg_idx] >> bit_idx) & 0x1; - if (value =3D=3D on) { + if (value =3D=3D on) goto l_out; - } =20 value =3D sxe_hw_uta_hash_table_get(hw, reg_idx); if (on) { mac_filter->uta_used_count++; value |=3D (0x1 << bit_idx); mac_filter->uta_hash_table[reg_idx] |=3D (0x1 << bit_idx); - } else {=20 + } else { mac_filter->uta_used_count--; value &=3D ~(0x1 << bit_idx); mac_filter->uta_hash_table[reg_idx] &=3D ~(0x1 << bit_idx); @@ -509,13 +498,11 @@ s32 sxe_set_mc_addr_list(struct rte_eth_dev *dev, mac_filter->mta_hash_table[reg_idx] |=3D (0x1 << bit_idx); } =20 - for (i =3D 0; i < SXE_MTA_ENTRY_NUM_MAX; i++) { + for (i =3D 0; i < SXE_MTA_ENTRY_NUM_MAX; i++) sxe_hw_mta_hash_table_set(hw, i, mac_filter->mta_hash_table[i]); - } =20 - if (nb_mc_addr) { + if (nb_mc_addr) sxe_hw_mc_filter_enable(hw); - } =20 PMD_LOG_INFO(DRV, "mc addr list cnt:%u set to mta done.", nb_mc_addr); =20 @@ -535,11 +522,10 @@ s32 sxe_vlan_filter_set(struct rte_eth_dev *eth_dev, = u16 vlan_id, s32 on) bit_idx =3D (vlan_id & SXE_VLAN_ID_BIT_MASK); =20 value =3D sxe_hw_vlan_filter_array_read(hw, reg_idx); - if (on) { + if (on) value |=3D (1 << bit_idx); - } else { + else value &=3D ~(1 << bit_idx); - } =20 sxe_hw_vlan_filter_array_write(hw, reg_idx, value); =20 @@ -563,11 +549,10 @@ static void sxe_vlan_tpid_write(struct sxe_hw *hw, u1= 6 tpid) (tpid << SXE_DMATXCTL_VT_SHIFT); sxe_hw_txctl_vlan_type_set(hw, value); =20 - return; } =20 s32 sxe_vlan_tpid_set(struct rte_eth_dev *eth_dev, - enum rte_vlan_type vlan_type, u16 tpid) + enum rte_vlan_type vlan_type, u16 tpid) { struct sxe_adapter *adapter =3D eth_dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; @@ -585,7 +570,7 @@ s32 sxe_vlan_tpid_set(struct rte_eth_dev *eth_dev, } else { ret =3D -ENOTSUP; PMD_LOG_ERR(DRV, "unsupport inner vlan without " - "global double vlan."); + "global double vlan."); } break; case RTE_ETH_VLAN_TYPE_OUTER: @@ -615,19 +600,18 @@ static void sxe_vlan_strip_bitmap_set(struct rte_eth_= dev *dev, u16 queue_idx, bo sxe_rx_queue_s *rxq; =20 if ((queue_idx >=3D SXE_HW_TXRX_RING_NUM_MAX) || - (queue_idx >=3D dev->data->nb_rx_queues)) { + (queue_idx >=3D dev->data->nb_rx_queues)) { PMD_LOG_ERR(DRV, "invalid queue idx:%u exceed max" " queue number:%u or nb_rx_queues:%u.", queue_idx, SXE_HW_TXRX_RING_NUM_MAX, dev->data->nb_rx_queues); - goto l_out; + return; } =20 - if (on) { + if (on) SXE_STRIP_BITMAP_SET(vlan_ctxt, queue_idx); - } else { + else SXE_STRIP_BITMAP_CLEAR(vlan_ctxt, queue_idx); - } =20 rxq =3D dev->data->rx_queues[queue_idx]; =20 @@ -640,10 +624,8 @@ static void sxe_vlan_strip_bitmap_set(struct rte_eth_d= ev *dev, u16 queue_idx, bo } =20 PMD_LOG_INFO(DRV, "queue idx:%u vlan strip on:%d set bitmap and offload d= one.", - queue_idx, on); + queue_idx, on); =20 -l_out: - return; } =20 void sxe_vlan_strip_switch_set(struct rte_eth_dev *dev) @@ -659,17 +641,15 @@ void sxe_vlan_strip_switch_set(struct rte_eth_dev *de= v) for (i =3D 0; i < dev->data->nb_rx_queues; i++) { rxq =3D dev->data->rx_queues[i]; =20 - if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { + if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) on =3D true; - } else { + else on =3D false; - } sxe_hw_vlan_tag_strip_switch(hw, i, on); =20 sxe_vlan_strip_bitmap_set(dev, i, on); } =20 - return; } =20 static void sxe_vlan_filter_disable(struct rte_eth_dev *dev) @@ -681,7 +661,6 @@ static void sxe_vlan_filter_disable(struct rte_eth_dev = *dev) =20 sxe_hw_vlan_filter_switch(hw, 0); =20 - return; } =20 static void sxe_vlan_filter_enable(struct rte_eth_dev *dev) @@ -699,11 +678,9 @@ static void sxe_vlan_filter_enable(struct rte_eth_dev = *dev) vlan_ctl |=3D SXE_VLNCTRL_VFE; sxe_hw_vlan_type_set(hw, vlan_ctl); =20 - for (i =3D 0; i < SXE_VFT_TBL_SIZE; i++) { + for (i =3D 0; i < SXE_VFT_TBL_SIZE; i++) sxe_hw_vlan_filter_array_write(hw, i, vlan_ctxt->vlan_hash_table[i]); - } =20 - return; } =20 static void sxe_vlan_extend_disable(struct rte_eth_dev *dev) @@ -722,7 +699,6 @@ static void sxe_vlan_extend_disable(struct rte_eth_dev = *dev) ctrl &=3D ~SXE_EXTENDED_VLAN; sxe_hw_ext_vlan_set(hw, ctrl); =20 - return; } =20 static void sxe_vlan_extend_enable(struct rte_eth_dev *dev) @@ -741,35 +717,31 @@ static void sxe_vlan_extend_enable(struct rte_eth_dev= *dev) ctrl |=3D SXE_EXTENDED_VLAN; sxe_hw_ext_vlan_set(hw, ctrl); =20 - return; } =20 static s32 sxe_vlan_offload_configure(struct rte_eth_dev *dev, s32 mask) { struct rte_eth_rxmode *rxmode =3D &dev->data->dev_conf.rxmode; =20 - if (mask & RTE_ETH_VLAN_STRIP_MASK) { + if (mask & RTE_ETH_VLAN_STRIP_MASK) sxe_vlan_strip_switch_set(dev); - } =20 if (mask & RTE_ETH_VLAN_FILTER_MASK) { - if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { + if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) sxe_vlan_filter_enable(dev); - } else { + else sxe_vlan_filter_disable(dev); - } } =20 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { - if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) { + if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) sxe_vlan_extend_enable(dev); - } else { + else sxe_vlan_extend_disable(dev); - } } =20 PMD_LOG_INFO(DRV, "mask:0x%x rx mode offload:0x%"SXE_PRIX64 - " vlan offload set done", mask, rxmode->offloads); + " vlan offload set done", mask, rxmode->offloads); =20 return 0; } @@ -780,7 +752,7 @@ s32 sxe_vlan_offload_set(struct rte_eth_dev *dev, s32 v= lan_mask) s32 ret =3D 0; =20 if (vlan_mask & RTE_ETH_VLAN_STRIP_MASK) { - PMD_LOG_WARN(DRV, "vlan strip has been on, not support to set."); + PMD_LOG_WARN(DRV, "please set vlan strip before device start, not at thi= s stage."); ret =3D -1; goto l_out; } @@ -788,7 +760,7 @@ s32 sxe_vlan_offload_set(struct rte_eth_dev *dev, s32 v= lan_mask) =20 sxe_vlan_offload_configure(dev, mask); =20 - PMD_LOG_INFO(DRV, "vlan offload mask:0x%d set done.", vlan_mask); + PMD_LOG_INFO(DRV, "vlan offload mask:0x%x set done.", vlan_mask); =20 l_out: return ret; @@ -797,10 +769,10 @@ s32 sxe_vlan_offload_set(struct rte_eth_dev *dev, s32= vlan_mask) void sxe_vlan_strip_queue_set(struct rte_eth_dev *dev, u16 queue, s32 on) { UNUSED(dev); + UNUSED(queue); UNUSED(on); - PMD_LOG_WARN(DRV, "queue:%u vlan strip has been on, not support to set.",= queue); + PMD_LOG_WARN(DRV, "please set vlan strip before device start, not at this= stage."); =20 - return; } =20 void sxe_vlan_filter_configure(struct rte_eth_dev *dev) @@ -811,7 +783,7 @@ void sxe_vlan_filter_configure(struct rte_eth_dev *dev) u32 vlan_ctl; =20 vlan_mask =3D RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | - RTE_ETH_VLAN_EXTEND_MASK; + RTE_ETH_VLAN_EXTEND_MASK; sxe_vlan_offload_configure(dev, vlan_mask); =20 if (dev->data->dev_conf.rxmode.mq_mode =3D=3D RTE_ETH_MQ_RX_VMDQ_ONLY) { @@ -821,6 +793,5 @@ void sxe_vlan_filter_configure(struct rte_eth_dev *dev) LOG_DEBUG_BDF("vmdq mode enable vlan filter done."); } =20 - return; } =20 diff --git a/drivers/net/sxe/pf/sxe_filter.h b/drivers/net/sxe/pf/sxe_filte= r.h index a541dce586..f7d147e492 100644 --- a/drivers/net/sxe/pf/sxe_filter.h +++ b/drivers/net/sxe/pf/sxe_filter.h @@ -19,14 +19,14 @@ struct sxe_adapter; =20 #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ADDR(x) ((u8*)(x))[0],((u8*)(x))[1], \ - ((u8*)(x))[2],((u8*)(x))[3], \ - ((u8*)(x))[4],((u8*)(x))[5] +#define MAC_ADDR(x) ((u8 *)(x))[0], ((u8 *)(x))[1], \ + ((u8 *)(x))[2], ((u8 *)(x))[3], \ + ((u8 *)(x))[4], ((u8 *)(x))[5] =20 #define BYTE_BIT_NUM 8 =20 -#define SXE_VLAN_STRIP_BITMAP_SIZE \ - RTE_ALIGN((SXE_HW_TXRX_RING_NUM_MAX / (sizeof(u32) * BYTE_BIT_NUM)= ), \ +#define SXE_VLAN_STRIP_BITMAP_SIZE \ + RTE_ALIGN((SXE_HW_TXRX_RING_NUM_MAX / (sizeof(u32) * BYTE_BIT_NUM)), \ sizeof(u32)) =20 struct sxe_vlan_context { @@ -42,24 +42,24 @@ enum sxe_uc_addr_src_type { }; =20 struct sxe_uc_addr_table { - u8 rar_idx;=20=20=20=20=20=20=20=20=20 - u8 vf_idx;=20=20=20=20=20=20=20=20=20=20 - u8 type;=20=20=20=20=20=20=20=20=20=20=20=20 - u8 original_index;=20=20 - bool used;=20=20=20=20=20=20=20=20=20=20 - u8 addr[SXE_MAC_ADDR_LEN];=20=20 + u8 rar_idx; + u8 vf_idx; + u8 type; + u8 original_index; + bool used; + u8 addr[SXE_MAC_ADDR_LEN]; }; =20 struct sxe_mac_filter_context { - struct rte_ether_addr def_mac_addr;=20 - struct rte_ether_addr cur_mac_addr;=20 + struct rte_ether_addr def_mac_addr; + struct rte_ether_addr cur_mac_addr; =20 struct rte_ether_addr fc_mac_addr; =20 - u32 uta_used_count;=20=20=20=20=20=20=20=20=20=20=20=20 - u32 uta_hash_table[SXE_UTA_ENTRY_NUM_MAX];=20 + u32 uta_used_count; + u32 uta_hash_table[SXE_UTA_ENTRY_NUM_MAX]; =20 - u32 mta_hash_table[SXE_MTA_ENTRY_NUM_MAX];=20 + u32 mta_hash_table[SXE_MTA_ENTRY_NUM_MAX]; struct sxe_uc_addr_table *uc_addr_table; }; =20 @@ -74,13 +74,13 @@ s32 sxe_allmulticast_enable(struct rte_eth_dev *dev); s32 sxe_allmulticast_disable(struct rte_eth_dev *dev); =20 s32 sxe_mac_addr_add(struct rte_eth_dev *dev, - struct rte_ether_addr *mac_addr, - u32 rar_idx, u32 pool); + struct rte_ether_addr *mac_addr, + u32 rar_idx, u32 pool); =20 void sxe_mac_addr_remove(struct rte_eth_dev *dev, u32 rar_idx); =20 s32 sxe_mac_addr_set(struct rte_eth_dev *dev, - struct rte_ether_addr *mac_addr); + struct rte_ether_addr *mac_addr); =20 s32 sxe_uc_hash_table_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, u8 on); @@ -94,7 +94,7 @@ s32 sxe_set_mc_addr_list(struct rte_eth_dev *dev, s32 sxe_vlan_filter_set(struct rte_eth_dev *eth_dev, u16 vlan_id, s32 on); =20 s32 sxe_vlan_tpid_set(struct rte_eth_dev *eth_dev, - enum rte_vlan_type vlan_type, u16 tpid); + enum rte_vlan_type vlan_type, u16 tpid); =20 s32 sxe_vlan_offload_set(struct rte_eth_dev *dev, s32 vlan_mask); =20 diff --git a/drivers/net/sxe/pf/sxe_filter_ctrl.c b/drivers/net/sxe/pf/sxe_= filter_ctrl.c new file mode 100644 index 0000000000..3bf2453f70 --- /dev/null +++ b/drivers/net/sxe/pf/sxe_filter_ctrl.c @@ -0,0 +1,2951 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL +#include +#include +#include +#include + +#include "sxe.h" +#include "sxe_logs.h" +#include "sxe_hw.h" +#include "sxe_fnav.h" +#include "sxe_filter_ctrl.h" +#include "sxe_offload.h" + +#define SXE_MIN_FIVETUPLE_PRIORITY 1 +#define SXE_MAX_FIVETUPLE_PRIORITY 7 + +struct sxe_ntuple_filter_ele { + TAILQ_ENTRY(sxe_ntuple_filter_ele) entries; + struct rte_eth_ntuple_filter filter_info; +}; + +struct sxe_ethertype_filter_ele { + TAILQ_ENTRY(sxe_ethertype_filter_ele) entries; + struct rte_eth_ethertype_filter filter_info; +}; + +struct sxe_eth_syn_filter_ele { + TAILQ_ENTRY(sxe_eth_syn_filter_ele) entries; + struct rte_eth_syn_filter filter_info; +}; + +struct sxe_fnav_rule_ele { + TAILQ_ENTRY(sxe_fnav_rule_ele) entries; + struct sxe_fnav_rule filter_info; +}; + +struct sxe_rss_filter_ele { + TAILQ_ENTRY(sxe_rss_filter_ele) entries; + struct sxe_rss_filter filter_info; +}; + +struct sxe_fivetuple_filter { + TAILQ_ENTRY(sxe_fivetuple_filter) entries; + u16 index; + struct sxe_fivetuple_filter_info filter_info; + u16 queue; +}; + +static inline +bool sxe_is_user_param_null(const struct rte_flow_item *pattern, + const struct rte_flow_action *actions, + const struct rte_flow_attr *attr, + struct rte_flow_error *error) +{ + bool ret =3D true; + + if (!pattern) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM_NUM, + NULL, "NULL pattern."); + PMD_LOG_ERR(DRV, "pattern is null, validate failed."); + goto l_out; + } + + if (!actions) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION_NUM, + NULL, "NULL action."); + PMD_LOG_ERR(DRV, "action is null, validate failed."); + goto l_out; + } + + if (!attr) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR, + NULL, "NULL attribute."); + PMD_LOG_ERR(DRV, "attribute is null, validate failed."); + goto l_out; + } + + ret =3D false; + +l_out: + return ret; +} + +static inline +bool sxe_is_attribute_wrong(const struct rte_flow_attr *attr, + struct rte_flow_error *error) +{ + bool ret =3D true; + + if (!attr->ingress) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, + attr, "Only support ingress."); + PMD_LOG_ERR(DRV, "only sopport ingrass, validate failed."); + goto l_out; + } + + if (attr->egress) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, + attr, "Not support egress."); + PMD_LOG_ERR(DRV, "not support egress, validate failed."); + goto l_out; + } + + if (attr->transfer) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, + attr, "Not support transfer."); + PMD_LOG_ERR(DRV, "not support transfer, validate failed."); + goto l_out; + } + + if (attr->group) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_GROUP, + attr, "Not support group."); + PMD_LOG_ERR(DRV, "not support group, validate failed."); + goto l_out; + } + + ret =3D false; + +l_out: + return ret; +} + +static inline +bool sxe_is_port_mask_wrong(u16 src_port_mask, u16 dst_port_mask, + const struct rte_flow_item *item, + struct rte_flow_error *error) +{ + bool ret =3D true; + + if ((src_port_mask !=3D 0 && src_port_mask !=3D UINT16_MAX) || + (dst_port_mask !=3D 0 && dst_port_mask !=3D UINT16_MAX)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "mask--src_port[0x%x], dst_port[0x%x], validate failed= .", + src_port_mask, dst_port_mask); + goto l_out; + } + + ret =3D false; + +l_out: + return ret; +} + +static inline +const struct rte_flow_item *sxe_next_no_void_pattern( + const struct rte_flow_item pattern[], + const struct rte_flow_item *current) +{ + const struct rte_flow_item *next =3D + current ? current + 1 : &pattern[0]; + while (1) { + if (next->type !=3D RTE_FLOW_ITEM_TYPE_VOID) + return next; + next++; + } +} + +static inline +const struct rte_flow_action *sxe_next_no_void_action( + const struct rte_flow_action actions[], + const struct rte_flow_action *current) +{ + const struct rte_flow_action *next =3D + current ? current + 1 : &actions[0]; + while (1) { + if (next->type !=3D RTE_FLOW_ACTION_TYPE_VOID) + return next; + next++; + } +} + +static inline +const struct rte_flow_item *sxe_next_no_fuzzy_pattern( + const struct rte_flow_item pattern[], + const struct rte_flow_item *current) +{ + const struct rte_flow_item *next =3D + sxe_next_no_void_pattern(pattern, current); + while (1) { + if (next->type !=3D RTE_FLOW_ITEM_TYPE_FUZZY) + return next; + next =3D sxe_next_no_void_pattern(pattern, next); + } +} + +static u8 +sxe_flow_l4type_convert(enum rte_flow_item_type protocol) +{ + U8 proto =3D 0; + + switch (protocol) { + case RTE_FLOW_ITEM_TYPE_TCP: + proto =3D IPPROTO_TCP; + break; + case RTE_FLOW_ITEM_TYPE_UDP: + proto =3D IPPROTO_UDP; + break; + case RTE_FLOW_ITEM_TYPE_SCTP: + proto =3D IPPROTO_SCTP; + break; + default: + PMD_LOG_WARN(DRV, "flow l4type convert failed."); + } + + return proto; +} + +static s32 sxe_filter_action_parse(struct rte_eth_dev *dev, + const struct rte_flow_action actions[], + struct rte_flow_error *error, + u16 *queue_index) +{ + const struct rte_flow_action *act; + + act =3D sxe_next_no_void_action(actions, NULL); + if (act->type !=3D RTE_FLOW_ACTION_TYPE_QUEUE) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto l_out; + } + + *queue_index =3D + ((const struct rte_flow_action_queue *)act->conf)->index; + + if (*queue_index >=3D dev->data->nb_rx_queues) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + act, "queue index much too big"); + PMD_LOG_ERR(DRV, "queue index check wrong, validate failed."); + goto l_out; + } + + act =3D sxe_next_no_void_action(actions, act); + if (act->type !=3D RTE_FLOW_ACTION_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto l_out; + } + + PMD_LOG_DEBUG(DRV, "filter action parse success."); + rte_errno =3D 0; + +l_out: + return -rte_errno; +} + +static s32 sxe_fivetuple_filter_pattern_parse(const struct rte_flow_item p= attern[], + struct rte_eth_ntuple_filter *filter, + struct rte_flow_error *error) +{ + const struct rte_flow_item *item; + const struct rte_flow_item_ipv4 *ipv4_spec; + const struct rte_flow_item_ipv4 *ipv4_mask; + const struct rte_flow_item_tcp *tcp_spec; + const struct rte_flow_item_tcp *tcp_mask; + const struct rte_flow_item_udp *udp_spec; + const struct rte_flow_item_udp *udp_mask; + const struct rte_flow_item_sctp *sctp_spec; + const struct rte_flow_item_sctp *sctp_mask; + const struct rte_flow_item_eth *eth_spec; + const struct rte_flow_item_eth *eth_mask; + const struct rte_flow_item_vlan *vlan_spec; + const struct rte_flow_item_vlan *vlan_mask; + struct rte_flow_item_eth eth_null; + struct rte_flow_item_vlan vlan_null; + + memset(ð_null, 0, sizeof(struct rte_flow_item_eth)); + memset(&vlan_null, 0, sizeof(struct rte_flow_item_vlan)); + + item =3D sxe_next_no_void_pattern(pattern, NULL); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_ETH && + item->type !=3D RTE_FLOW_ITEM_TYPE_IPV4) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->type= ); + goto l_out; + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_ETH) { + eth_spec =3D item->spec; + eth_mask =3D item->mask; + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + if ((item->spec || item->mask) && + ((item->spec && memcmp(eth_spec, ð_null, + sizeof(struct rte_flow_item_eth))) || + (item->mask && memcmp(eth_mask, ð_null, + sizeof(struct rte_flow_item_eth))))) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "item spec[%p], item mask[%p], validate failed.", + item->spec, item->mask); + goto l_out; + } + + item =3D sxe_next_no_void_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_IPV4 && + item->type !=3D RTE_FLOW_ITEM_TYPE_VLAN) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_VLAN) { + vlan_spec =3D item->spec; + vlan_mask =3D item->mask; + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + if ((item->spec || item->mask) && + ((item->spec && memcmp(vlan_spec, &vlan_null, + sizeof(struct rte_flow_item_vlan))) || + (item->mask && memcmp(vlan_mask, &vlan_null, + sizeof(struct rte_flow_item_vlan))))) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "item spec[%p], item mask[%p], validate failed.", + item->spec, item->mask); + goto l_out; + } + + item =3D sxe_next_no_void_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_IPV4) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (item->mask) { + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + if (!item->spec || !item->mask) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid ntuple spec"); + PMD_LOG_WARN(DRV, "item spec is null, validate failed."); + goto l_out; + } + + ipv4_mask =3D item->mask; + if (SXE_5TUPLE_IPV4_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "not support other mask set, validate failed."); + goto l_out; + } + if ((ipv4_mask->hdr.src_addr !=3D 0 && + ipv4_mask->hdr.src_addr !=3D UINT32_MAX) || + (ipv4_mask->hdr.dst_addr !=3D 0 && + ipv4_mask->hdr.dst_addr !=3D UINT32_MAX) || + (ipv4_mask->hdr.next_proto_id !=3D UINT8_MAX && + ipv4_mask->hdr.next_proto_id !=3D 0)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "mask--src_addr[0x%x], dst_addr[0x%x], next_proto_id[= 0x%x], validate failed.", + ipv4_mask->hdr.src_addr, ipv4_mask->hdr.dst_addr, + ipv4_mask->hdr.next_proto_id); + goto l_out; + } + + filter->dst_ip_mask =3D ipv4_mask->hdr.dst_addr; + filter->src_ip_mask =3D ipv4_mask->hdr.src_addr; + filter->proto_mask =3D ipv4_mask->hdr.next_proto_id; + + ipv4_spec =3D item->spec; + filter->dst_ip =3D ipv4_spec->hdr.dst_addr; + filter->src_ip =3D ipv4_spec->hdr.src_addr; + filter->proto =3D ipv4_spec->hdr.next_proto_id; + } + + item =3D sxe_next_no_void_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_TCP && + item->type !=3D RTE_FLOW_ITEM_TYPE_UDP && + item->type !=3D RTE_FLOW_ITEM_TYPE_SCTP && + item->type !=3D RTE_FLOW_ITEM_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->type= ); + goto l_out; + } + + if ((item->type !=3D RTE_FLOW_ITEM_TYPE_END) && + (!item->spec && !item->mask)) { + if (!filter->proto_mask) { + filter->proto_mask =3D UINT8_MAX; + filter->proto =3D sxe_flow_l4type_convert(item->type); + } + PMD_LOG_DEBUG(DRV, "TCP/UDP/SCTP item spec and mask is null, to check ac= tion."); + rte_errno =3D 0; + goto l_out; + } + + if (item->type !=3D RTE_FLOW_ITEM_TYPE_END && + (!item->spec || !item->mask)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid ntuple mask"); + PMD_LOG_WARN(DRV, "spec or mask is null, validate failed."); + goto l_out; + } + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_TCP) { + if (filter->proto !=3D IPPROTO_TCP && + filter->proto_mask !=3D 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "protocal id is not TCP, please check."); + goto l_out; + } + + tcp_mask =3D item->mask; + if (SXE_5TUPLE_TCP_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "not support other mask set, validate failed."); + goto l_out; + } + + if (sxe_is_port_mask_wrong(tcp_mask->hdr.src_port, + tcp_mask->hdr.dst_port, item, error)) { + PMD_LOG_WARN(DRV, "port mask set wrong, validate failed."); + goto l_out; + } + + filter->dst_port_mask =3D tcp_mask->hdr.dst_port; + filter->src_port_mask =3D tcp_mask->hdr.src_port; + + tcp_spec =3D item->spec; + filter->dst_port =3D tcp_spec->hdr.dst_port; + filter->src_port =3D tcp_spec->hdr.src_port; + } else if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_UDP) { + if (filter->proto !=3D IPPROTO_UDP && + filter->proto_mask !=3D 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "protocal id is not UDP, please check."); + goto l_out; + } + + udp_mask =3D item->mask; + if (SXE_5TUPLE_UDP_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "not support other mask set, validate failed."); + goto l_out; + } + + if (sxe_is_port_mask_wrong(udp_mask->hdr.src_port, + udp_mask->hdr.dst_port, item, error)) { + PMD_LOG_WARN(DRV, "port mask set wrong, validate failed."); + goto l_out; + } + + filter->dst_port_mask =3D udp_mask->hdr.dst_port; + filter->src_port_mask =3D udp_mask->hdr.src_port; + + udp_spec =3D item->spec; + filter->dst_port =3D udp_spec->hdr.dst_port; + filter->src_port =3D udp_spec->hdr.src_port; + } else if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_SCTP) { + if (filter->proto !=3D IPPROTO_SCTP && + filter->proto_mask !=3D 0) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "protocal id is not SCTP, please check."); + goto l_out; + } + + sctp_mask =3D item->mask; + if (SXE_5TUPLE_SCTP_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "not support other mask set, validate failed."); + goto l_out; + } + + if (sxe_is_port_mask_wrong(sctp_mask->hdr.src_port, + sctp_mask->hdr.dst_port, item, error)) { + PMD_LOG_WARN(DRV, "port mask set wrong, validate failed."); + goto l_out; + } + + filter->dst_port_mask =3D sctp_mask->hdr.dst_port; + filter->src_port_mask =3D sctp_mask->hdr.src_port; + + sctp_spec =3D item->spec; + filter->dst_port =3D sctp_spec->hdr.dst_port; + filter->src_port =3D sctp_spec->hdr.src_port; + } else { + rte_errno =3D 0; + goto l_out; + } + + item =3D sxe_next_no_void_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ntuple filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->type= ); + goto l_out; + } + + PMD_LOG_DEBUG(DRV, "fivetuple filter pattern parse success."); + rte_errno =3D 0; + +l_out: + return -rte_errno; + +} + +static s32 sxe_fivetuple_filter_parse(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_eth_ntuple_filter *filter, + struct rte_flow_error *error) +{ + s32 ret =3D 0; + u16 queue_index =3D 0; + + if (sxe_is_user_param_null(pattern, actions, attr, error)) { + PMD_LOG_ERR(DRV, "user param is null, validate failed."); + goto parse_failed; + } + + ret =3D sxe_fivetuple_filter_pattern_parse(pattern, filter, error); + if (ret !=3D 0) { + PMD_LOG_WARN(DRV, "pattern check wrong, validate failed."); + goto parse_failed; + } + + ret =3D sxe_filter_action_parse(dev, actions, error, &queue_index); + if (ret !=3D 0) { + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto parse_failed; + } else { + filter->queue =3D queue_index; + } + + if (sxe_is_attribute_wrong(attr, error)) { + PMD_LOG_ERR(DRV, "attribute check wrong, validate failed."); + goto parse_failed; + } + + if (attr->priority > 0xFFFF) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, + attr, "Error priority."); + PMD_LOG_ERR(DRV, "priority check wrong, validate failed."); + goto parse_failed; + } + + filter->priority =3D (u16)attr->priority; + if (attr->priority < SXE_MIN_FIVETUPLE_PRIORITY || + attr->priority > SXE_MAX_FIVETUPLE_PRIORITY) { + PMD_LOG_WARN(DRV, "priority[%d] is out of 1~7, set to 1.", attr->priorit= y); + filter->priority =3D SXE_MIN_FIVETUPLE_PRIORITY; + } + + PMD_LOG_DEBUG(DRV, "five tuple filter fit, validate success!!"); + rte_errno =3D 0; + goto l_out; + +parse_failed: + memset(filter, 0, sizeof(struct rte_eth_ntuple_filter)); + PMD_LOG_WARN(DRV, "five tuple filter, validate failed."); +l_out: + return -rte_errno; +} + +static enum sxe_fivetuple_protocol +sxe_protocol_type_convert(u8 protocol_value) +{ + enum sxe_fivetuple_protocol protocol; + + switch (protocol_value) { + case IPPROTO_TCP: + protocol =3D SXE_FILTER_PROTOCOL_TCP; + break; + case IPPROTO_UDP: + protocol =3D SXE_FILTER_PROTOCOL_UDP; + break; + case IPPROTO_SCTP: + protocol =3D SXE_FILTER_PROTOCOL_SCTP; + break; + default: + protocol =3D SXE_FILTER_PROTOCOL_NONE; + } + + return protocol; +} + +static s32 +sxe_ntuple_filter_to_fivetuple(struct rte_eth_ntuple_filter *ntuple_filter, + struct sxe_fivetuple_filter_info *filter_info) +{ + s32 ret =3D -EINVAL; + + switch (ntuple_filter->dst_ip_mask) { + case UINT32_MAX: + filter_info->dst_ip_mask =3D 0; + filter_info->dst_ip =3D ntuple_filter->dst_ip; + break; + case 0: + filter_info->dst_ip_mask =3D 1; + break; + default: + PMD_LOG_ERR(DRV, "invalid dst_ip mask."); + goto l_out; + } + + switch (ntuple_filter->src_ip_mask) { + case UINT32_MAX: + filter_info->src_ip_mask =3D 0; + filter_info->src_ip =3D ntuple_filter->src_ip; + break; + case 0: + filter_info->src_ip_mask =3D 1; + break; + default: + PMD_LOG_ERR(DRV, "invalid src_ip mask."); + goto l_out; + } + + switch (ntuple_filter->dst_port_mask) { + case UINT16_MAX: + filter_info->dst_port_mask =3D 0; + filter_info->dst_port =3D ntuple_filter->dst_port; + break; + case 0: + filter_info->dst_port_mask =3D 1; + break; + default: + PMD_LOG_ERR(DRV, "invalid dst_port mask."); + goto l_out; + } + + switch (ntuple_filter->src_port_mask) { + case UINT16_MAX: + filter_info->src_port_mask =3D 0; + filter_info->src_port =3D ntuple_filter->src_port; + break; + case 0: + filter_info->src_port_mask =3D 1; + break; + default: + PMD_LOG_ERR(DRV, "invalid src_port mask."); + goto l_out; + } + + switch (ntuple_filter->proto_mask) { + case UINT8_MAX: + filter_info->proto_mask =3D 0; + filter_info->protocol =3D + sxe_protocol_type_convert(ntuple_filter->proto); + break; + case 0: + filter_info->proto_mask =3D 1; + break; + default: + PMD_LOG_ERR(DRV, "invalid protocol mask."); + goto l_out; + } + + filter_info->priority =3D (u8)ntuple_filter->priority; + ret =3D 0; + +l_out: + return ret; +} + +static struct sxe_fivetuple_filter * +sxe_fivetuple_filter_lookup(struct sxe_fivetuple_filter_list *filter_list, + struct sxe_fivetuple_filter_info *filter_info) +{ + struct sxe_fivetuple_filter *filter; + + TAILQ_FOREACH(filter, filter_list, entries) { + if (memcmp(filter_info, &filter->filter_info, + sizeof(struct sxe_fivetuple_filter_info)) =3D=3D 0) { + goto l_out; + } + } + filter =3D NULL; + +l_out: + return filter; +} + +static s32 +sxe_fivetuple_filter_add(struct rte_eth_dev *dev, + struct sxe_fivetuple_filter *filter) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + struct sxe_fivetuple_node_info filter_node_info; + s32 i, index, shift; + s32 ret =3D 0; + + for (i =3D 0; i < SXE_MAX_FTQF_FILTERS; i++) { + index =3D i / (sizeof(u32) * BYTE_BIT_NUM); + shift =3D i % (sizeof(u32) * BYTE_BIT_NUM); + if (!(filter_ctxt->fivetuple_mask[index] & (1 << shift))) { + filter_ctxt->fivetuple_mask[index] |=3D 1 << shift; + filter->index =3D i; + TAILQ_INSERT_TAIL(&filter_ctxt->fivetuple_list, filter, entries); + break; + } + } + if (i >=3D SXE_MAX_FTQF_FILTERS) { + PMD_LOG_ERR(DRV, "fivetuple filters are full."); + ret =3D -ENOSYS; + goto l_out; + } + + filter_node_info.index =3D filter->index; + filter_node_info.queue =3D filter->queue; + memcpy(&filter_node_info.filter_info, &filter->filter_info, + sizeof(struct sxe_fivetuple_filter_info)); + sxe_hw_fivetuple_filter_add(dev, &filter_node_info); + +l_out: + return ret; +} + +static void +sxe_fivetuple_filter_delete(struct rte_eth_dev *dev, + struct sxe_fivetuple_filter *filter) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + u16 index =3D filter->index; + + filter_ctxt->fivetuple_mask[index / (sizeof(u32) * BYTE_BIT_NUM)] &=3D + ~(1 << (index % (sizeof(u32) * BYTE_BIT_NUM))); + TAILQ_REMOVE(&filter_ctxt->fivetuple_list, filter, entries); + rte_free(filter); + + sxe_hw_fivetuple_filter_del(hw, index); + +} + +static s32 sxe_fivetuple_filter_configure(struct rte_eth_dev *dev, + struct rte_eth_ntuple_filter *ntuple_filter, + bool add) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + struct sxe_fivetuple_filter_info filter_fivetuple_info; + struct sxe_fivetuple_filter *filter; + s32 ret =3D 0; + + memset(&filter_fivetuple_info, 0, sizeof(struct sxe_fivetuple_filter_info= )); + ret =3D sxe_ntuple_filter_to_fivetuple(ntuple_filter, &filter_fivetuple_i= nfo); + if (ret < 0) + goto l_out; + + filter =3D sxe_fivetuple_filter_lookup(&filter_ctxt->fivetuple_list, + &filter_fivetuple_info); + if (filter !=3D NULL && add) { + PMD_LOG_ERR(DRV, "filter exists, not support add."); + ret =3D -EEXIST; + goto l_out; + } + if (filter =3D=3D NULL && !add) { + PMD_LOG_ERR(DRV, "filter doesn't exist, not support delete."); + ret =3D -ENOENT; + goto l_out; + } + + if (add) { + filter =3D rte_zmalloc("sxe_fivetuple_filter", + sizeof(struct sxe_fivetuple_filter), 0); + if (filter =3D=3D NULL) { + PMD_LOG_ERR(DRV, "fivetuple filter malloc failed."); + ret =3D -ENOMEM; + goto l_out; + } + rte_memcpy(&filter->filter_info, + &filter_fivetuple_info, + sizeof(struct sxe_fivetuple_filter_info)); + filter->queue =3D ntuple_filter->queue; + + ret =3D sxe_fivetuple_filter_add(dev, filter); + if (ret < 0) { + PMD_LOG_ERR(DRV, "fivetuple filter add failed."); + rte_free(filter); + goto l_out; + } + } else { + sxe_fivetuple_filter_delete(dev, filter); + } + +l_out: + return ret; +} + +void sxe_fivetuple_filter_uninit(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + struct sxe_fivetuple_filter *filter; + + while ((filter =3D TAILQ_FIRST(&filter_ctxt->fivetuple_list))) { + TAILQ_REMOVE(&filter_ctxt->fivetuple_list, + filter, + entries); + rte_free(filter); + } + memset(filter_ctxt->fivetuple_mask, 0, + sizeof(u32) * SXE_5TUPLE_ARRAY_SIZE); + +} + +static s32 +sxe_ethertype_filter_pattern_parse(const struct rte_flow_item pattern[], + struct rte_eth_ethertype_filter *filter, + struct rte_flow_error *error) +{ + const struct rte_flow_item *item; + const struct rte_flow_item_eth *eth_spec; + const struct rte_flow_item_eth *eth_mask; + + item =3D sxe_next_no_void_pattern(pattern, NULL); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_ETH) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ethertype filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->type= ); + goto l_out; + } + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + if (!item->spec || !item->mask) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ethertype filter"); + PMD_LOG_WARN(DRV, "spec[%p] or mask[%p] is null.", item->spec, item->mas= k); + goto l_out; + } + + eth_spec =3D item->spec; + eth_mask =3D item->mask; + + if (!rte_is_zero_ether_addr(ð_mask->src) || + !rte_is_zero_ether_addr(ð_mask->dst)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid ether address mask"); + PMD_LOG_WARN(DRV, "mac src or dst mask is not zero."); + goto l_out; + } + + if ((eth_mask->type & UINT16_MAX) !=3D UINT16_MAX) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid ethertype mask"); + PMD_LOG_WARN(DRV, "ethertype mask[0x%x] is wrong.", eth_mask->type); + goto l_out; + } + filter->ether_type =3D rte_be_to_cpu_16(eth_spec->type); + + if (filter->ether_type =3D=3D RTE_ETHER_TYPE_IPV4 || + filter->ether_type =3D=3D RTE_ETHER_TYPE_IPV6) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + NULL, "IPv4/IPv6 not supported by ethertype filter"); + PMD_LOG_WARN(DRV, "not support IPv4 and IPv6 ethertype, validate failed.= "); + goto l_out; + } + + item =3D sxe_next_no_void_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by ethertype filter."); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->type= ); + goto l_out; + } + + PMD_LOG_DEBUG(DRV, "ethertype filter pattern parse success."); + rte_errno =3D 0; + +l_out: + return -rte_errno; +} + +static s32 +sxe_ethertype_filter_parse(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_eth_ethertype_filter *filter, + struct rte_flow_error *error) +{ + s32 ret; + u16 queue; + + if (sxe_is_user_param_null(pattern, actions, attr, error)) { + PMD_LOG_ERR(DRV, "user param is null, validate failed.\n"); + goto parse_failed; + } + + ret =3D sxe_ethertype_filter_pattern_parse(pattern, filter, error); + if (ret !=3D 0) { + PMD_LOG_WARN(DRV, "pattern check wrong, validate failed."); + goto parse_failed; + } + + ret =3D sxe_filter_action_parse(dev, actions, error, &queue); + if (ret !=3D 0) { + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto parse_failed; + } else { + filter->queue =3D queue; + } + + if (sxe_is_attribute_wrong(attr, error)) { + PMD_LOG_ERR(DRV, "user attribute is wrong, validate failed.\n"); + goto parse_failed; + } + if (attr->priority) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, + attr, "Not support priority."); + PMD_LOG_ERR(DRV, "not support priority, validate failed.\n"); + goto parse_failed; + } + + PMD_LOG_DEBUG(DRV, "ethertype filter fit, validate success!!"); + rte_errno =3D 0; + goto l_out; + +parse_failed: + memset(filter, 0, sizeof(struct rte_eth_ethertype_filter)); + PMD_LOG_WARN(DRV, "ethertype filter, validate failed."); +l_out: + return -rte_errno; + +} + +static s32 +sxe_ethertype_filter_lookup(struct sxe_filter_context *filter_ctxt, + u16 ethertype) +{ + s32 i; + + for (i =3D 0; i < SXE_MAX_ETQF_FILTERS; i++) { + if (filter_ctxt->ethertype_filters[i].ethertype =3D=3D ethertype && + (filter_ctxt->ethertype_mask & (1 << i))) { + goto l_out; + } + } + i =3D -1; + +l_out: + return i; +} + +static s32 +sxe_ethertype_filter_insert(struct sxe_filter_context *filter_ctxt, + struct sxe_ethertype_filter *ethertype_filter) +{ + s32 i; + + for (i =3D 0; i < SXE_MAX_ETQF_FILTERS; i++) { + if (!(filter_ctxt->ethertype_mask & (1 << i))) { + filter_ctxt->ethertype_mask |=3D 1 << i; + filter_ctxt->ethertype_filters[i].ethertype =3D + ethertype_filter->ethertype; + filter_ctxt->ethertype_filters[i].queue =3D + ethertype_filter->queue; + filter_ctxt->ethertype_filters[i].conf =3D + ethertype_filter->conf; + goto l_out; + } + } + i =3D -1; + +l_out: + return i; +} + +static s32 +sxe_ethertype_filter_remove(struct sxe_filter_context *filter_ctxt, + u8 index) +{ + if (index >=3D SXE_MAX_ETQF_FILTERS) { + index =3D -1; + goto l_out; + } + filter_ctxt->ethertype_mask &=3D ~(1 << index); + filter_ctxt->ethertype_filters[index].ethertype =3D 0; + filter_ctxt->ethertype_filters[index].queue =3D 0; + filter_ctxt->ethertype_filters[index].conf =3D false; + +l_out: + return index; +} + +static s32 +sxe_ethertype_filter_configure(struct rte_eth_dev *dev, + struct rte_eth_ethertype_filter *filter, + bool add) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + s32 ret; + s32 result =3D 0; + struct sxe_ethertype_filter ethertype_filter; + + ret =3D sxe_ethertype_filter_lookup(filter_ctxt, filter->ether_type); + if (ret >=3D 0 && add) { + PMD_LOG_ERR(DRV, "ethertype (0x%04x) filter exists.", + filter->ether_type); + result =3D -EEXIST; + goto l_out; + } + if (ret < 0 && !add) { + PMD_LOG_ERR(DRV, "ethertype (0x%04x) filter doesn't exist.", + filter->ether_type); + result =3D -ENOENT; + goto l_out; + } + + if (add) { + ethertype_filter.ethertype =3D filter->ether_type; + ethertype_filter.queue =3D filter->queue; + ethertype_filter.conf =3D false; + + ret =3D sxe_ethertype_filter_insert(filter_ctxt, + ðertype_filter); + if (ret < 0) { + PMD_LOG_ERR(DRV, "ethertype filters are full."); + result =3D -ENOSPC; + goto l_out; + } + + sxe_hw_ethertype_filter_add(hw, ret, filter->ether_type, filter->queue); + } else { + ret =3D sxe_ethertype_filter_remove(filter_ctxt, (u8)ret); + if (ret < 0) { + PMD_LOG_ERR(DRV, "ethertype filters remove failed."); + result =3D -ENOSYS; + goto l_out; + } + + sxe_hw_ethertype_filter_del(hw, ret); + } + +l_out: + return result; +} + +static s32 +sxe_syn_filter_pattern_parse(const struct rte_flow_item pattern[], + struct rte_flow_error *error) +{ + const struct rte_flow_item *item; + const struct rte_flow_item_tcp *tcp_spec; + const struct rte_flow_item_tcp *tcp_mask; + + item =3D sxe_next_no_void_pattern(pattern, NULL); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_ETH && + item->type !=3D RTE_FLOW_ITEM_TYPE_IPV4 && + item->type !=3D RTE_FLOW_ITEM_TYPE_IPV6 && + item->type !=3D RTE_FLOW_ITEM_TYPE_TCP) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by syn filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->type= ); + goto l_out; + } + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_ETH) { + if (item->spec || item->mask) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid SYN address mask"); + PMD_LOG_WARN(DRV, "eth spec and mask should be NULL, validate failed."); + goto l_out; + } + + item =3D sxe_next_no_void_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_IPV4 && + item->type !=3D RTE_FLOW_ITEM_TYPE_IPV6) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by syn filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_IPV4 || + item->type =3D=3D RTE_FLOW_ITEM_TYPE_IPV6) { + if (item->spec || item->mask) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid SYN mask"); + PMD_LOG_WARN(DRV, "ip spec and mask should be null, validate failed."); + goto l_out; + } + + item =3D sxe_next_no_void_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_TCP) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by syn filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (!item->spec || !item->mask) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Invalid SYN mask"); + PMD_LOG_WARN(DRV, "tcp spec or mask is null, validate failed."); + goto l_out; + } + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + tcp_spec =3D item->spec; + tcp_mask =3D item->mask; + if (!(tcp_spec->hdr.tcp_flags & RTE_TCP_SYN_FLAG) || + tcp_mask->hdr.tcp_flags !=3D RTE_TCP_SYN_FLAG || + SXE_SYN_TCP_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by syn filter"); + PMD_LOG_WARN(DRV, "not support other mask set, validate failed."); + goto l_out; + } + + item =3D sxe_next_no_void_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by syn filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->type= ); + goto l_out; + } + + PMD_LOG_DEBUG(DRV, "syn filter pattern parse success."); + rte_errno =3D 0; + +l_out: + return -rte_errno; +} + +static s32 +sxe_syn_filter_parse(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_eth_syn_filter *filter, + struct rte_flow_error *error) +{ + s32 ret; + u16 queue; + + if (sxe_is_user_param_null(pattern, actions, attr, error)) { + PMD_LOG_ERR(DRV, "user param is null, validate failed.\n"); + goto parse_failed; + } + + ret =3D sxe_syn_filter_pattern_parse(pattern, error); + if (ret !=3D 0) { + PMD_LOG_WARN(DRV, "pattern check wrong, validate failed."); + goto parse_failed; + } + + ret =3D sxe_filter_action_parse(dev, actions, error, &queue); + if (ret !=3D 0) { + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto parse_failed; + } else { + filter->queue =3D queue; + } + + if (sxe_is_attribute_wrong(attr, error)) { + PMD_LOG_ERR(DRV, "user attribute is wrong, validate failed.\n"); + goto parse_failed; + } + if (!attr->priority) { + filter->hig_pri =3D 0; + } else if (attr->priority =3D=3D (u32)~0U) { + filter->hig_pri =3D 1; + } else { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, + attr, "Not support priority."); + PMD_LOG_ERR(DRV, "priority check wrong, validate failed."); + goto parse_failed; + } + + PMD_LOG_DEBUG(DRV, "syn filter fit, validate success!!"); + rte_errno =3D 0; + goto l_out; + +parse_failed: + memset(filter, 0, sizeof(struct rte_eth_syn_filter)); + PMD_LOG_WARN(DRV, "sys filter, validate failed."); +l_out: + return -rte_errno; +} + +static s32 +sxe_syn_filter_configure(struct rte_eth_dev *dev, + struct rte_eth_syn_filter *filter, + bool add) +{ + s32 ret =3D 0; + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + struct sxe_syn_filter *syn_filter =3D &filter_ctxt->syn_filter; + bool is_syn_enable =3D syn_filter->is_syn_enable; + + if (add) { + if (is_syn_enable) { + PMD_LOG_WARN(DRV, "syn filter is on, no need to reopen."); + ret =3D -EINVAL; + goto l_out; + } + + sxe_hw_syn_filter_add(hw, filter->queue, filter->hig_pri); + syn_filter->is_syn_enable =3D true; + syn_filter->queue =3D filter->queue; + syn_filter->priority =3D filter->hig_pri; + } else { + if (!is_syn_enable) { + PMD_LOG_WARN(DRV, "syn filter is off, not support to reclose."); + ret =3D -ENOENT; + goto l_out; + } + + sxe_hw_syn_filter_del(hw); + syn_filter->is_syn_enable =3D false; + } + +l_out: + return ret; +} + +static void +sxe_syn_filter_delete(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + struct sxe_syn_filter *syn_filter =3D &filter_ctxt->syn_filter; + bool is_syn_enable =3D syn_filter->is_syn_enable; + + if (is_syn_enable) { + sxe_hw_syn_filter_del(hw); + syn_filter->is_syn_enable =3D false; + } + +} + +static bool +sxe_is_fnav_signature_mode(const struct rte_flow_item pattern[]) +{ + const struct rte_flow_item_fuzzy *spec, *last, *mask; + const struct rte_flow_item *item; + u32 sh, lh, mh; + s32 i =3D 0; + bool ismatch =3D false; + + while (1) { + item =3D pattern + i; + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_END) + break; + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_FUZZY) { + spec =3D item->spec; + last =3D item->last; + mask =3D item->mask; + + if (!spec || !mask) { + ismatch =3D false; + goto l_out; + } + + sh =3D spec->thresh; + + if (!last) + lh =3D sh; + else + lh =3D last->thresh; + + mh =3D mask->thresh; + sh =3D sh & mh; + lh =3D lh & mh; + + if (!sh || sh > lh) { + ismatch =3D false; + goto l_out; + } + + ismatch =3D true; + goto l_out; + } + + i++; + } + +l_out: + return ismatch; +} + +static s32 +sxe_fnav_filter_pattern_parse(struct rte_eth_dev *dev, + const struct rte_flow_item pattern[], + struct sxe_fnav_rule *rule, + struct rte_flow_error *error) +{ + enum rte_fdir_mode fnav_mode =3D + SXE_DEV_FNAV_CONF(dev)->mode; + const struct rte_flow_item *item; + const struct rte_flow_item_ipv4 *ipv4_spec; + const struct rte_flow_item_ipv4 *ipv4_mask; + const struct rte_flow_item_ipv6 *ipv6_spec; + const struct rte_flow_item_ipv6 *ipv6_mask; + const struct rte_flow_item_tcp *tcp_spec; + const struct rte_flow_item_tcp *tcp_mask; + const struct rte_flow_item_udp *udp_spec; + const struct rte_flow_item_udp *udp_mask; + const struct rte_flow_item_sctp *sctp_mask; + const struct rte_flow_item_vlan *vlan_spec; + const struct rte_flow_item_vlan *vlan_mask; + const struct rte_flow_item_raw *raw_mask; + const struct rte_flow_item_raw *raw_spec; + u8 j; + + memset(rule, 0, sizeof(struct sxe_fnav_rule)); + memset(&rule->mask, 0xFF, sizeof(struct sxe_hw_fnav_mask)); + rule->mask.vlan_tci_mask =3D 0; + rule->mask.flex_bytes_mask =3D 0; + + item =3D sxe_next_no_fuzzy_pattern(pattern, NULL); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_ETH && + item->type !=3D RTE_FLOW_ITEM_TYPE_IPV4 && + item->type !=3D RTE_FLOW_ITEM_TYPE_IPV6 && + item->type !=3D RTE_FLOW_ITEM_TYPE_TCP && + item->type !=3D RTE_FLOW_ITEM_TYPE_UDP && + item->type !=3D RTE_FLOW_ITEM_TYPE_SCTP) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->type= ); + goto l_out; + } + + if (sxe_is_fnav_signature_mode(pattern)) + rule->mode =3D RTE_FDIR_MODE_SIGNATURE; + else + rule->mode =3D RTE_FDIR_MODE_PERFECT; + +#ifdef DPDK_22_11_3 + s32 ret; + if (fnav_mode =3D=3D RTE_FDIR_MODE_NONE) { + SXE_DEV_FNAV_CONF(dev)->mode =3D rule->mode; + ret =3D sxe_fnav_filter_configure(dev); + if (ret) { + SXE_DEV_FNAV_CONF(dev)->mode =3D RTE_FDIR_MODE_NONE; + PMD_LOG_ERR(DRV, "fnav config fail."); + rte_errno =3D -ret; + goto l_out; + } + } else if (fnav_mode !=3D rule->mode) { +#else + if (fnav_mode =3D=3D RTE_FDIR_MODE_NONE || + fnav_mode !=3D rule->mode) { +#endif + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Fnav mode is not correct"); + PMD_LOG_WARN(DRV, "fnav mode is wrong, validate failed."); + goto l_out; + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_ETH) { + if (item->spec || item->mask) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "mac spec or mask is not NULL, validate failed."); + goto l_out; + } + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + item =3D sxe_next_no_fuzzy_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_IPV4 && + item->type !=3D RTE_FLOW_ITEM_TYPE_VLAN) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_VLAN) { + if (!(item->spec && item->mask)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "vlan spec or mask is null, validate failed."); + goto l_out; + } + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + vlan_spec =3D item->spec; + vlan_mask =3D item->mask; + + rule->sxe_fnav.ntuple.vlan_id =3D vlan_spec->tci; + rule->mask.vlan_tci_mask =3D vlan_mask->tci; + rule->mask.vlan_tci_mask &=3D rte_cpu_to_be_16(0xEFFF); + + item =3D sxe_next_no_fuzzy_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_IPV4) { + rule->sxe_fnav.ntuple.flow_type =3D SXE_SAMPLE_FLOW_TYPE_IPV4; + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + if (!item->mask) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "ipv4 mask is null, validate failed."); + goto l_out; + } + rule->b_mask =3D true; + ipv4_mask =3D item->mask; + if (SXE_FNAV_IPV4_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "not support other mask set, validate failed."); + goto l_out; + } + rule->mask.dst_ipv4_mask =3D ipv4_mask->hdr.dst_addr; + rule->mask.src_ipv4_mask =3D ipv4_mask->hdr.src_addr; + + if (item->spec) { + rule->b_spec =3D true; + ipv4_spec =3D item->spec; + rule->sxe_fnav.ntuple.dst_ip[0] =3D + ipv4_spec->hdr.dst_addr; + rule->sxe_fnav.ntuple.src_ip[0] =3D + ipv4_spec->hdr.src_addr; + } + + item =3D sxe_next_no_fuzzy_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_TCP && + item->type !=3D RTE_FLOW_ITEM_TYPE_UDP && + item->type !=3D RTE_FLOW_ITEM_TYPE_SCTP && + item->type !=3D RTE_FLOW_ITEM_TYPE_END && + item->type !=3D RTE_FLOW_ITEM_TYPE_RAW) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_IPV6) { + rule->sxe_fnav.ntuple.flow_type =3D SXE_SAMPLE_FLOW_TYPE_IPV6; + + if (rule->mode !=3D RTE_FDIR_MODE_SIGNATURE || + item->last || + !item->mask) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "error in ipv6, validate failed."); + goto l_out; + } + + rule->b_mask =3D true; + ipv6_mask =3D item->mask; + if (SXE_FNAV_IPV6_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "not support other mask set, validate failed."); + goto l_out; + } + + for (j =3D 0; j < 16; j++) { + if (ipv6_mask->hdr.src_addr[j] =3D=3D 0) { + rule->mask.src_ipv6_mask &=3D ~(1 << j); + } else if (ipv6_mask->hdr.src_addr[j] !=3D UINT8_MAX) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "src addr mask is wrong, validate failed."); + goto l_out; + } + } + + for (j =3D 0; j < 16; j++) { + if (ipv6_mask->hdr.dst_addr[j] =3D=3D 0) { + rule->mask.dst_ipv6_mask &=3D ~(1 << j); + } else if (ipv6_mask->hdr.dst_addr[j] !=3D UINT8_MAX) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "dst addr mask is wrong, validate failed."); + goto l_out; + } + } + + if (item->spec) { + rule->b_spec =3D true; + ipv6_spec =3D item->spec; + rte_memcpy(rule->sxe_fnav.ntuple.src_ip, + ipv6_spec->hdr.src_addr, 16); + rte_memcpy(rule->sxe_fnav.ntuple.dst_ip, + ipv6_spec->hdr.dst_addr, 16); + } + + item =3D sxe_next_no_fuzzy_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_TCP && + item->type !=3D RTE_FLOW_ITEM_TYPE_UDP && + item->type !=3D RTE_FLOW_ITEM_TYPE_SCTP && + item->type !=3D RTE_FLOW_ITEM_TYPE_END && + item->type !=3D RTE_FLOW_ITEM_TYPE_RAW) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_TCP) { + rule->sxe_fnav.ntuple.flow_type |=3D SXE_SAMPLE_L4TYPE_TCP; + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + if (!item->mask) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "tcp mask is null, validate failed."); + goto l_out; + } + rule->b_mask =3D true; + tcp_mask =3D item->mask; + if (SXE_FNAV_TCP_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "not support other mask set, validate failed."); + goto l_out; + } + rule->mask.src_port_mask =3D tcp_mask->hdr.src_port; + rule->mask.dst_port_mask =3D tcp_mask->hdr.dst_port; + + if (item->spec) { + rule->b_spec =3D true; + tcp_spec =3D item->spec; + rule->sxe_fnav.ntuple.src_port =3D + tcp_spec->hdr.src_port; + rule->sxe_fnav.ntuple.dst_port =3D + tcp_spec->hdr.dst_port; + } + + item =3D sxe_next_no_fuzzy_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_RAW && + item->type !=3D RTE_FLOW_ITEM_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_UDP) { + rule->sxe_fnav.ntuple.flow_type |=3D SXE_SAMPLE_L4TYPE_UDP; + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + if (!item->mask) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "udp mask is null, validate failed."); + goto l_out; + } + rule->b_mask =3D true; + udp_mask =3D item->mask; + if (SXE_FNAV_UDP_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "not support other mask set, validate failed."); + goto l_out; + } + rule->mask.src_port_mask =3D udp_mask->hdr.src_port; + rule->mask.dst_port_mask =3D udp_mask->hdr.dst_port; + + if (item->spec) { + rule->b_spec =3D true; + udp_spec =3D item->spec; + rule->sxe_fnav.ntuple.src_port =3D + udp_spec->hdr.src_port; + rule->sxe_fnav.ntuple.dst_port =3D + udp_spec->hdr.dst_port; + } + + item =3D sxe_next_no_fuzzy_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_RAW && + item->type !=3D RTE_FLOW_ITEM_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_SCTP) { + rule->sxe_fnav.ntuple.flow_type |=3D SXE_SAMPLE_L4TYPE_SCTP; + + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + sctp_mask =3D item->mask; + if (sctp_mask && SXE_FNAV_SCTP_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "not support other mask set, validate failed."); + goto l_out; + } + + item =3D sxe_next_no_fuzzy_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_RAW && + item->type !=3D RTE_FLOW_ITEM_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_RAW) { + if (item->last) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + item, "Not supported last point for range"); + PMD_LOG_WARN(DRV, "not support last set, validate failed."); + goto l_out; + } + + if (!item->mask || !item->spec) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "raw mask or spec is null, validate failed."); + goto l_out; + } + + raw_mask =3D item->mask; + if (SXE_FNAV_RAW_MASK) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "raw mask is wrong, validate failed."); + goto l_out; + } + + raw_spec =3D item->spec; + if (SXE_FNAV_RAW_SPEC) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "raw spec is wrong, validate failed."); + goto l_out; + } + + rule->mask.flex_bytes_mask =3D 0xffff; + rule->sxe_fnav.ntuple.flex_bytes =3D + (((u16)raw_spec->pattern[1]) << 8) | raw_spec->pattern[0]; + rule->flex_bytes_offset =3D raw_spec->offset; + } + + if (item->type !=3D RTE_FLOW_ITEM_TYPE_END) { + item =3D sxe_next_no_fuzzy_pattern(pattern, item); + if (item->type !=3D RTE_FLOW_ITEM_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + item, "Not supported by fnav filter"); + PMD_LOG_WARN(DRV, "item type[%d] is wrong, validate failed.", item->typ= e); + goto l_out; + } + } + + PMD_LOG_DEBUG(DRV, "fnav filter pattern parse success."); + rte_errno =3D 0; + +l_out: + return -rte_errno; +} + +static s32 +sxe_fnav_filter_action_parse(struct rte_eth_dev *dev, + const struct rte_flow_action actions[], + struct sxe_fnav_rule *rule, + struct rte_flow_error *error) +{ + const struct rte_flow_action *act; + const struct rte_flow_action_queue *act_queue; + const struct rte_flow_action_mark *mark; + + act =3D sxe_next_no_void_action(actions, NULL); + if (act->type !=3D RTE_FLOW_ACTION_TYPE_QUEUE && + act->type !=3D RTE_FLOW_ACTION_TYPE_DROP) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto l_out; + } + + if (act->type =3D=3D RTE_FLOW_ACTION_TYPE_QUEUE) { + act_queue =3D (const struct rte_flow_action_queue *)act->conf; + rule->queue =3D act_queue->index; + if (rule->queue >=3D dev->data->nb_rx_queues) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + PMD_LOG_ERR(DRV, "queue index check wrong, validate failed."); + goto l_out; + } + } else { + if (rule->mode =3D=3D RTE_FDIR_MODE_SIGNATURE) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + PMD_LOG_ERR(DRV, "signature not supprot drop, validate failed."); + goto l_out; + } + if (rule->sxe_fnav.ntuple.src_port !=3D 0 || + rule->sxe_fnav.ntuple.dst_port !=3D 0) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + PMD_LOG_ERR(DRV, "not supported action, validate failed."); + goto l_out; + } + rule->fnavflags =3D SXE_FNAVCMD_DROP; + } + + act =3D sxe_next_no_void_action(actions, act); + if ((act->type !=3D RTE_FLOW_ACTION_TYPE_MARK) && + (act->type !=3D RTE_FLOW_ACTION_TYPE_END)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto l_out; + } + + rule->soft_id =3D 0; + + if (act->type =3D=3D RTE_FLOW_ACTION_TYPE_MARK) { + mark =3D (const struct rte_flow_action_mark *)act->conf; + rule->soft_id =3D mark->id; + act =3D sxe_next_no_void_action(actions, act); + } + + if (act->type !=3D RTE_FLOW_ACTION_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto l_out; + } + + PMD_LOG_DEBUG(DRV, "fnav filter action parse success."); + rte_errno =3D 0; + +l_out: + return -rte_errno; +} + +static s32 +sxe_fnav_filter_parse(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct sxe_fnav_rule *rule, + struct rte_flow_error *error) +{ + s32 ret; + + if (sxe_is_user_param_null(pattern, actions, attr, error)) { + PMD_LOG_ERR(DRV, "user param is null, validate failed.\n"); + goto parse_failed; + } + + ret =3D sxe_fnav_filter_pattern_parse(dev, pattern, rule, error); + if (ret !=3D 0) { + PMD_LOG_WARN(DRV, "pattern check wrong, validate failed."); + goto parse_failed; + } + + ret =3D sxe_fnav_filter_action_parse(dev, actions, rule, error); + if (ret !=3D 0) { + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto parse_failed; + } + + if (sxe_is_attribute_wrong(attr, error)) { + PMD_LOG_ERR(DRV, "user attribute is wrong, validate failed.\n"); + goto parse_failed; + } + if (attr->priority) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, + attr, "Not support priority."); + PMD_LOG_ERR(DRV, "priority check wrong, validate failed."); + goto parse_failed; + } + + PMD_LOG_DEBUG(DRV, "fnav filter fit, validate success!!"); + rte_errno =3D 0; + goto l_out; + +parse_failed: + memset(rule, 0, sizeof(struct sxe_fnav_rule)); + PMD_LOG_WARN(DRV, "fnav filter, validate failed."); +l_out: + return -rte_errno; +} + +static s32 +sxe_fnav_filter_program(struct rte_eth_dev *dev, + struct sxe_fnav_rule *rule, + bool del) +{ + u32 fnavcmd_flags; + u32 fnavhash; + u8 queue; + s32 ret; + u32 soft_id =3D 0; + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_fnav_context *fnav_ctxt =3D &adapter->fnav_ctxt; + enum rte_fdir_mode fnav_mode =3D SXE_DEV_FNAV_CONF(dev)->mode; + struct sxe_fnav_filter *node; + bool add_node =3D false; + + if (fnav_mode =3D=3D RTE_FDIR_MODE_NONE || + fnav_mode !=3D rule->mode) { + PMD_LOG_ERR(DRV, "fnav mode is wrong."); + ret =3D -ENOTSUP; + goto l_out; + } + + rule->sxe_fnav.ntuple.bkt_hash =3D 0; + if (fnav_mode =3D=3D RTE_FDIR_MODE_PERFECT) { + if (rule->sxe_fnav.ntuple.flow_type & SXE_SAMPLE_L4TYPE_IPV6_MASK) { + PMD_LOG_ERR(DRV, "ipv6 is not supported in perfect mode!"); + ret =3D -ENOTSUP; + goto l_out; + } + fnavhash =3D sxe_fnav_perfect_hash_compute(&rule->sxe_fnav, + SXE_DEV_FNAV_CONF(dev)->pballoc); + soft_id =3D rule->soft_id; + } else { + fnavhash =3D sxe_fnav_signature_hash_compute(&rule->sxe_fnav, + SXE_DEV_FNAV_CONF(dev)->pballoc); + } + rule->sxe_fnav.ntuple.bkt_hash =3D fnavhash; + + if (del) { + ret =3D sxe_fnav_filter_remove(fnav_ctxt, &rule->sxe_fnav); + if (ret < 0) { + PMD_LOG_ERR(DRV, "fnav filter remove failed."); + goto l_out; + } + + ret =3D sxe_hw_fnav_specific_rule_del(hw, &rule->sxe_fnav, soft_id); + if (ret < 0) + PMD_LOG_ERR(DRV, "fail to delete fnav filter!"); + else + PMD_LOG_DEBUG(DRV, "success to delete fnav filter!"); + goto l_out; + } + + fnavcmd_flags =3D 0; + if (rule->fnavflags & SXE_FNAVCMD_DROP) { + if (fnav_mode =3D=3D RTE_FDIR_MODE_PERFECT) { + queue =3D SXE_DEV_FNAV_CONF(dev)->drop_queue; + fnavcmd_flags |=3D SXE_FNAVCMD_DROP; + } else { + PMD_LOG_ERR(DRV, "drop option is not supported in" + " signature mode."); + ret =3D -EINVAL; + goto l_out; + } + } else if (rule->queue < SXE_HW_TXRX_RING_NUM_MAX) { + queue =3D rule->queue; + } else { + PMD_LOG_ERR(DRV, "not support action."); + ret =3D -EINVAL; + goto l_out; + } + + node =3D sxe_fnav_filter_lookup(fnav_ctxt, &rule->sxe_fnav); + if (node) { + PMD_LOG_ERR(DRV, "conflict with existing fnav filter!"); + ret =3D -EINVAL; + goto l_out; + } else { + add_node =3D true; + node =3D rte_zmalloc("sxe_fnav", + sizeof(struct sxe_fnav_filter), 0); + if (!node) { + PMD_LOG_ERR(DRV, "fnav node malloc failed."); + ret =3D -ENOMEM; + goto l_out; + } + rte_memcpy(&node->sxe_fnav, &rule->sxe_fnav, + sizeof(union sxe_fnav_rule_info)); + node->fnavflags =3D fnavcmd_flags; + node->fnavhash =3D fnavhash; + node->soft_id =3D soft_id; + node->queue =3D queue; + + ret =3D sxe_fnav_filter_insert(fnav_ctxt, node); + if (ret < 0) { + rte_free(node); + goto l_out; + } + } + + if (fnav_mode =3D=3D RTE_FDIR_MODE_PERFECT) { + ret =3D sxe_hw_fnav_specific_rule_add(hw, &rule->sxe_fnav, + soft_id, queue); + } else { + sxe_hw_fnav_sample_rule_configure(hw, + rule->sxe_fnav.ntuple.flow_type, + fnavhash, queue); + } + if (ret < 0) { + PMD_LOG_ERR(DRV, "fail to add fnav filter!"); + if (add_node) + (void)sxe_fnav_filter_remove(fnav_ctxt, &rule->sxe_fnav); + + } else { + ret =3D 0; + PMD_LOG_DEBUG(DRV, "success to add fnav filter"); + } + +l_out: + return ret; +} + +s32 sxe_fnav_filter_init(struct rte_eth_dev *dev) +{ + s32 ret =3D 0; + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_fnav_context *fnav_info =3D &adapter->fnav_ctxt; + char fnav_hash_name[RTE_HASH_NAMESIZE]; + struct rte_hash_parameters fnav_hash_params =3D { + .name =3D fnav_hash_name, + .entries =3D SXE_MAX_FNAV_FILTER_NUM, + .key_len =3D sizeof(union sxe_fnav_rule_info), + .hash_func =3D rte_hash_crc, + .hash_func_init_val =3D 0, + .socket_id =3D rte_socket_id(), + }; + + TAILQ_INIT(&fnav_info->fnav_list); + snprintf(fnav_hash_name, RTE_HASH_NAMESIZE, + "fnav_%s", dev->device->name); + + fnav_info->hash_handle =3D rte_hash_create(&fnav_hash_params); + if (!fnav_info->hash_handle) { + PMD_LOG_ERR(INIT, "failed to create fnav hash table!"); + ret =3D -EINVAL; + goto l_out; + } + + fnav_info->hash_map =3D rte_zmalloc("sxe", + sizeof(struct sxe_fnav_filter *) * + SXE_MAX_FNAV_FILTER_NUM, + 0); + if (!fnav_info->hash_map) { + PMD_LOG_ERR(INIT, + "failed to allocate memory for fnav hash map!"); + rte_hash_free(fnav_info->hash_handle); + ret =3D -ENOMEM; + goto l_out; + } + fnav_info->mask_added =3D false; + +l_out: + return ret; +} + +void sxe_fnav_filter_uninit(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_fnav_context *fnav_info =3D &adapter->fnav_ctxt; + struct sxe_fnav_filter *fnav_filter; + + if (fnav_info->hash_map) { + rte_free(fnav_info->hash_map); + fnav_info->hash_map =3D NULL; + } + if (fnav_info->hash_handle) + rte_hash_free(fnav_info->hash_handle); + + while ((fnav_filter =3D TAILQ_FIRST(&fnav_info->fnav_list))) { + TAILQ_REMOVE(&fnav_info->fnav_list, + fnav_filter, + entries); + rte_free(fnav_filter); + } + +} + +static s32 +sxe_rss_filter_conf_copy(struct sxe_rss_filter *out, + const struct rte_flow_action_rss *in) +{ + s32 ret =3D 0; + + if (in->key_len > RTE_DIM(out->key) || + in->queue_num > RTE_DIM(out->queue)) { + ret =3D -EINVAL; + goto l_out; + } + + out->conf =3D (struct rte_flow_action_rss){ + .func =3D in->func, + .level =3D in->level, + .types =3D in->types, + .key_len =3D in->key_len, + .queue_num =3D in->queue_num, + .key =3D memcpy(out->key, in->key, in->key_len), + .queue =3D memcpy(out->queue, in->queue, + sizeof(*in->queue) * in->queue_num), + }; + +l_out: + return ret; +} + +static s32 sxe_rss_filter_action_parse(struct rte_eth_dev *dev, + const struct rte_flow_action actions[], + struct sxe_rss_filter *rss_filter, + struct rte_flow_error *error) +{ + const struct rte_flow_action *act; + const struct rte_flow_action_rss *rss; + u16 n; + + if (!actions) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION_NUM, + NULL, "NULL action."); + PMD_LOG_ERR(DRV, "action is null, validate failed."); + goto l_out; + } + + act =3D sxe_next_no_void_action(actions, NULL); + if (act->type !=3D RTE_FLOW_ACTION_TYPE_RSS) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto l_out; + } + + rss =3D (const struct rte_flow_action_rss *)act->conf; + + if (!rss || !rss->queue_num) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "no valid queues"); + PMD_LOG_WARN(DRV, "rss queue is invalid, validate failed."); + goto l_out; + } + + if (rss->queue_num > dev->data->nb_rx_queues) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, act, + "too many queues for RSS context"); + PMD_LOG_WARN(DRV, "too many queues for rss context, validate failed."); + goto l_out; + } + + for (n =3D 0; n < rss->queue_num; n++) { + if (rss->queue[n] >=3D dev->data->nb_rx_queues) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "queue id > max number of queues"); + PMD_LOG_WARN(DRV, "queue id > max number of queues, validate failed."); + goto l_out; + } + } + + if (rss->func !=3D RTE_ETH_HASH_FUNCTION_DEFAULT) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, act, + "non-default RSS hash functions are not supported"); + PMD_LOG_WARN(DRV, "non-default rss hash functions are not supported."); + goto l_out; + } + + if (rss->level) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, act, + "a nonzero RSS encapsulation level is not supported"); + PMD_LOG_WARN(DRV, "a nonzero rss encapsulation level is not supported."); + goto l_out; + } + + if (rss->key_len && rss->key_len !=3D RTE_DIM(rss_filter->key)) { + rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, act, + "RSS hash key must be exactly 40 bytes"); + PMD_LOG_WARN(DRV, "rss hash key must be exactly 40 bytes."); + goto l_out; + } + + if (sxe_rss_filter_conf_copy(rss_filter, rss)) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, act, + "RSS context initialization failure"); + PMD_LOG_WARN(DRV, "rss context initialization failure, validate failed."= ); + goto l_out; + } + + act =3D sxe_next_no_void_action(actions, act); + if (act->type !=3D RTE_FLOW_ACTION_TYPE_END) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, + act, "Not supported action."); + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto l_out; + } + + PMD_LOG_DEBUG(DRV, "rss filter action parse success."); + rte_errno =3D 0; + +l_out: + return -rte_errno; +} + +static s32 +sxe_rss_filter_parse(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_action actions[], + struct sxe_rss_filter *rss_filter, + struct rte_flow_error *error) +{ + s32 ret =3D 0; + + ret =3D sxe_rss_filter_action_parse(dev, actions, rss_filter, error); + if (ret !=3D 0) { + PMD_LOG_WARN(DRV, "action check wrong, validate failed."); + goto parse_failed; + } + + if (sxe_is_attribute_wrong(attr, error)) { + PMD_LOG_ERR(DRV, "user attribute is wrong, validate failed.\n"); + goto parse_failed; + } + if (attr->priority) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, + attr, "Error priority."); + PMD_LOG_ERR(DRV, "priority check wrong, validate failed."); + goto parse_failed; + } + + PMD_LOG_DEBUG(DRV, "rss filter fit, validate success!!"); + rte_errno =3D 0; + goto l_out; + +parse_failed: + memset(rss_filter, 0, sizeof(struct sxe_rss_filter)); + PMD_LOG_WARN(DRV, "rss filter, validate failed."); +l_out: + return -rte_errno; +} + +bool sxe_is_rss_filter_same(const struct rte_flow_action_rss *cur_rss, + const struct rte_flow_action_rss *user_rss) +{ + return (cur_rss->func =3D=3D user_rss->func && + cur_rss->level =3D=3D user_rss->level && + cur_rss->types =3D=3D user_rss->types && + cur_rss->key_len =3D=3D user_rss->key_len && + cur_rss->queue_num =3D=3D user_rss->queue_num && + !memcmp(cur_rss->key, user_rss->key, user_rss->key_len) && + !memcmp(cur_rss->queue, user_rss->queue, + sizeof(*user_rss->queue) * user_rss->queue_num)); +} + +static s32 +sxe_rss_filter_configure(struct rte_eth_dev *dev, + struct sxe_rss_filter *rss_filter, bool add) +{ + u16 i, j; + s32 ret =3D 0; + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + u8 rss_indir_tbl[SXE_MAX_RETA_ENTRIES]; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + struct rte_eth_rss_conf rss_conf =3D { + .rss_key =3D rss_filter->conf.key_len ? + (void *)(uintptr_t)rss_filter->conf.key : NULL, + .rss_key_len =3D rss_filter->conf.key_len, + .rss_hf =3D rss_filter->conf.types, + }; + + if (!add) { + if (sxe_is_rss_filter_same(&filter_ctxt->rss_filter.conf, + &rss_filter->conf)) { + sxe_rss_disable(dev); + memset(&filter_ctxt->rss_filter, 0, + sizeof(struct sxe_rss_filter)); + PMD_LOG_DEBUG(DRV, "rss filter delete success."); + goto l_out; + } + PMD_LOG_ERR(DRV, "rss filter delete failed."); + ret =3D -EINVAL; + goto l_out; + } + + if (filter_ctxt->rss_filter.conf.queue_num) { + PMD_LOG_ERR(DRV, "rss filter has been create, not support recreate."); + ret =3D -EINVAL; + goto l_out; + } + + for (i =3D 0, j =3D 0; i < SXE_MAX_RETA_ENTRIES; i++, j++) { + if (j =3D=3D rss_filter->conf.queue_num) + j =3D 0; + + rss_indir_tbl[i] =3D rss_filter->conf.queue[j]; + } + sxe_hw_rss_redir_tbl_set_all(hw, rss_indir_tbl); + + if ((rss_conf.rss_hf & SXE_RSS_OFFLOAD_ALL) =3D=3D 0) { + sxe_rss_disable(dev); + PMD_LOG_DEBUG(DRV, "hash function is null, rss filter delete success."); + goto l_out; + } + + if (rss_conf.rss_key =3D=3D NULL) + rss_conf.rss_key =3D sxe_rss_hash_key_get(); + + sxe_rss_hash_set(hw, &rss_conf); + if (sxe_rss_filter_conf_copy(&filter_ctxt->rss_filter, &rss_filter->conf)= ) { + PMD_LOG_ERR(DRV, "copy rss filter info to private data failed."); + ret =3D -EINVAL; + goto l_out; + } + +l_out: + return ret; +} + +static void +sxe_rss_filter_delete(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + + if (filter_ctxt->rss_filter.conf.queue_num) + sxe_rss_filter_configure(dev, &filter_ctxt->rss_filter, false); + +} + +static void +sxe_fivetuple_filter_restore(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + struct sxe_fivetuple_filter *filter; + struct sxe_fivetuple_node_info filter_node_info; + + TAILQ_FOREACH(filter, &filter_ctxt->fivetuple_list, entries) { + filter_node_info.index =3D filter->index; + filter_node_info.queue =3D filter->queue; + memcpy(&filter_node_info.filter_info, &filter->filter_info, + sizeof(struct sxe_fivetuple_filter_info)); + sxe_hw_fivetuple_filter_add(dev, &filter_node_info); + } + +} + +static void +sxe_ethertype_filter_restore(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + s32 i; + u16 ethertype, queue; + + for (i =3D 0; i < SXE_MAX_ETQF_FILTERS; i++) { + if (filter_ctxt->ethertype_mask & (1 << i)) { + ethertype =3D filter_ctxt->ethertype_filters[i].ethertype; + queue =3D filter_ctxt->ethertype_filters[i].queue; + sxe_hw_ethertype_filter_add(hw, i, ethertype, queue); + } + } + +} + +static void +sxe_syn_filter_restore(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + struct sxe_syn_filter *syn_filter =3D &filter_ctxt->syn_filter; + bool is_syn_enable =3D syn_filter->is_syn_enable; + u16 queue =3D syn_filter->queue; + u8 priority =3D syn_filter->priority; + + if (is_syn_enable) + sxe_hw_syn_filter_add(hw, queue, priority); + +} + +static void +sxe_rss_filter_restore(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + + if (filter_ctxt->rss_filter.conf.queue_num) { + sxe_rss_filter_configure(dev, + &filter_ctxt->rss_filter, true); + } + +} + +void sxe_filter_restore(struct rte_eth_dev *dev) +{ + sxe_fivetuple_filter_restore(dev); + sxe_ethertype_filter_restore(dev); + sxe_syn_filter_restore(dev); + sxe_fnav_filter_restore(dev); + sxe_rss_filter_restore(dev); + +} + +static s32 sxe_flow_validate(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow_error *error) +{ + struct rte_eth_ntuple_filter ntuple_filter; + struct rte_eth_ethertype_filter ethertype_filter; + struct rte_eth_syn_filter syn_filter; + struct sxe_fnav_rule fnav_rule; + struct sxe_rss_filter rss_filter; + s32 ret =3D 0; + + /* Five tuple filter */ + memset(&ntuple_filter, 0, sizeof(struct rte_eth_ntuple_filter)); + ret =3D sxe_fivetuple_filter_parse(dev, attr, pattern, + actions, &ntuple_filter, error); + if (!ret) + goto l_out; + + /* Ethertype filter */ + memset(ðertype_filter, 0, sizeof(struct rte_eth_ethertype_filter)); + ret =3D sxe_ethertype_filter_parse(dev, attr, pattern, + actions, ðertype_filter, error); + if (!ret) + goto l_out; + + /* Syn filter:export */ + memset(&syn_filter, 0, sizeof(struct rte_eth_syn_filter)); + ret =3D sxe_syn_filter_parse(dev, attr, pattern, + actions, &syn_filter, error); + if (!ret) + goto l_out; + + /* Fnav filter:export */ + memset(&fnav_rule, 0, sizeof(struct sxe_fnav_rule)); + ret =3D sxe_fnav_filter_parse(dev, attr, pattern, + actions, &fnav_rule, error); + if (!ret) + goto l_out; + + /* RSS filter:export */ + memset(&rss_filter, 0, sizeof(struct sxe_rss_filter)); + ret =3D sxe_rss_filter_parse(dev, attr, + actions, &rss_filter, error); + +l_out: + return ret; +} + +static struct rte_flow * +sxe_flow_create(struct rte_eth_dev *dev, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action actions[], + struct rte_flow_error *error) +{ + s32 ret; + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct rte_eth_ntuple_filter ntuple_filter; + struct rte_eth_ethertype_filter ethertype_filter; + struct rte_eth_syn_filter syn_filter; + struct sxe_fnav_rule fnav_rule; + struct sxe_fnav_context *fnav_info =3D &adapter->fnav_ctxt; + struct sxe_rss_filter rss_filter; + struct rte_flow *flow =3D NULL; + struct sxe_ntuple_filter_ele *ntuple_filter_ele; + struct sxe_ethertype_filter_ele *ethertype_filter_ele; + struct sxe_eth_syn_filter_ele *syn_filter_ele; + struct sxe_fnav_rule_ele *fnav_rule_ele; + struct sxe_rss_filter_ele *rss_filter_ele; + u8 first_mask =3D false; + + flow =3D rte_zmalloc("sxe_rte_flow", sizeof(struct rte_flow), 0); + if (!flow) { + PMD_LOG_ERR(DRV, "failed to allocate memory"); + ret =3D -ENOMEM; + goto l_out; + } + + memset(&ntuple_filter, 0, sizeof(struct rte_eth_ntuple_filter)); + ret =3D sxe_fivetuple_filter_parse(dev, attr, pattern, + actions, &ntuple_filter, error); + if (!ret) { + ret =3D sxe_fivetuple_filter_configure(dev, &ntuple_filter, 1); + if (!ret) { + ntuple_filter_ele =3D rte_zmalloc("sxe_ntuple_filter", + sizeof(struct sxe_ntuple_filter_ele), 0); + if (!ntuple_filter_ele) { + PMD_LOG_ERR(DRV, "failed to allocate memory"); + ret =3D -ENOMEM; + goto fail; + } + rte_memcpy(&ntuple_filter_ele->filter_info, + &ntuple_filter, + sizeof(struct rte_eth_ntuple_filter)); + flow->rule =3D ntuple_filter_ele; + flow->filter_type =3D RTE_ETH_FILTER_NTUPLE; + PMD_LOG_DEBUG(DRV, "create fivetuple_filter success!"); + goto l_out; + } + PMD_LOG_ERR(DRV, "create fivetuple_filter failed!"); + goto fail; + } + + memset(ðertype_filter, 0, sizeof(struct rte_eth_ethertype_filter)); + ret =3D sxe_ethertype_filter_parse(dev, attr, pattern, + actions, ðertype_filter, error); + if (!ret) { + ret =3D sxe_ethertype_filter_configure(dev, + ðertype_filter, true); + if (!ret) { + ethertype_filter_ele =3D rte_zmalloc( + "sxe_ethertype_filter", + sizeof(struct sxe_ethertype_filter_ele), 0); + if (!ethertype_filter_ele) { + PMD_LOG_ERR(DRV, "failed to allocate memory"); + ret =3D -ENOMEM; + goto fail; + } + rte_memcpy(ðertype_filter_ele->filter_info, + ðertype_filter, + sizeof(struct rte_eth_ethertype_filter)); + flow->rule =3D ethertype_filter_ele; + flow->filter_type =3D RTE_ETH_FILTER_ETHERTYPE; + PMD_LOG_DEBUG(DRV, "create ethertype_filter success!"); + goto l_out; + } + PMD_LOG_ERR(DRV, "create ethertype_filter failed!"); + goto fail; + } + + memset(&syn_filter, 0, sizeof(struct rte_eth_syn_filter)); + ret =3D sxe_syn_filter_parse(dev, attr, pattern, + actions, &syn_filter, error); + if (!ret) { + ret =3D sxe_syn_filter_configure(dev, &syn_filter, true); + if (!ret) { + syn_filter_ele =3D rte_zmalloc("sxe_syn_filter", + sizeof(struct sxe_eth_syn_filter_ele), 0); + if (!syn_filter_ele) { + PMD_LOG_ERR(DRV, "failed to allocate memory"); + ret =3D -ENOMEM; + goto fail; + } + rte_memcpy(&syn_filter_ele->filter_info, + &syn_filter, + sizeof(struct rte_eth_syn_filter)); + flow->rule =3D syn_filter_ele; + flow->filter_type =3D RTE_ETH_FILTER_SYN; + PMD_LOG_DEBUG(DRV, "create syn_filter success!"); + goto l_out; + } + PMD_LOG_ERR(DRV, "create syn_filter failed!"); + goto fail; + } + + memset(&fnav_rule, 0, sizeof(struct sxe_fnav_rule)); + ret =3D sxe_fnav_filter_parse(dev, attr, pattern, + actions, &fnav_rule, error); + if (!ret) { + if (fnav_rule.b_mask) { + if (!fnav_info->mask_added) { + rte_memcpy(&fnav_info->mask, &fnav_rule.mask, + sizeof(struct sxe_hw_fnav_mask)); + + if (fnav_rule.mask.flex_bytes_mask && + fnav_info->flex_bytes_offset !=3D + fnav_rule.flex_bytes_offset) { + ret =3D sxe_hw_fnav_flex_offset_set(hw, + fnav_rule.flex_bytes_offset); + if (ret) { + PMD_LOG_ERR(DRV, "flex_byte_offset set failed."); + goto fail; + } else { + fnav_info->flex_bytes_offset =3D + fnav_rule.flex_bytes_offset; + } + } + + ret =3D sxe_fnav_mask_set(dev); + if (ret) { + PMD_LOG_ERR(DRV, "fnav filter create---fnav mask set failed."); + goto fail; + } + + fnav_info->mask_added =3D true; + first_mask =3D true; + } else { + /* All fnav filter use one mask */ + ret =3D memcmp(&fnav_info->mask, + &fnav_rule.mask, + sizeof(struct sxe_hw_fnav_mask)); + if (ret) { + ret =3D -EINVAL; + PMD_LOG_ERR(DRV, "don't support to set different mask."); + goto fail; + } + + if (fnav_rule.mask.flex_bytes_mask && + fnav_info->flex_bytes_offset !=3D + fnav_rule.flex_bytes_offset) { + PMD_LOG_ERR(DRV, "don't support to set different flex_byte_offset."); + ret =3D -EINVAL; + goto fail; + } + } + } + + if (fnav_rule.b_spec) { + ret =3D sxe_fnav_filter_program(dev, &fnav_rule, false); + if (!ret) { + fnav_rule_ele =3D rte_zmalloc("sxe_fnav_filter", + sizeof(struct sxe_fnav_rule_ele), 0); + if (!fnav_rule_ele) { + PMD_LOG_ERR(DRV, "failed to allocate memory"); + ret =3D -ENOMEM; + goto fail; + } + rte_memcpy(&fnav_rule_ele->filter_info, + &fnav_rule, + sizeof(struct sxe_fnav_rule)); + flow->rule =3D fnav_rule_ele; + flow->filter_type =3D RTE_ETH_FILTER_FDIR; + PMD_LOG_DEBUG(DRV, "create fnav_filter success!"); + goto l_out; + } + + if (ret) { + if (first_mask) + fnav_info->mask_added =3D false; + PMD_LOG_ERR(DRV, "fnav_rule_spec set failed!"); + goto fail; + } + } + + ret =3D -EINVAL; + PMD_LOG_ERR(DRV, "create fnav_filter failed!"); + goto fail; + } + + memset(&rss_filter, 0, sizeof(struct sxe_rss_filter)); + ret =3D sxe_rss_filter_parse(dev, attr, + actions, &rss_filter, error); + if (!ret) { + ret =3D sxe_rss_filter_configure(dev, &rss_filter, true); + if (!ret) { + rss_filter_ele =3D rte_zmalloc("sxe_rss_filter", + sizeof(struct sxe_rss_filter_ele), 0); + if (!rss_filter_ele) { + PMD_LOG_ERR(DRV, "failed to allocate memory"); + ret =3D -ENOMEM; + goto fail; + } + + sxe_rss_filter_conf_copy(&rss_filter_ele->filter_info, + &rss_filter.conf); + flow->rule =3D rss_filter_ele; + flow->filter_type =3D RTE_ETH_FILTER_HASH; + PMD_LOG_DEBUG(DRV, "create rss_filter success!"); + goto l_out; + } + } +fail: + rte_flow_error_set(error, -ret, + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, + "Failed to create flow."); + rte_free(flow); + flow =3D NULL; +l_out: + return flow; + +} + +static s32 sxe_flow_destroy(struct rte_eth_dev *dev, + struct rte_flow *flow, + struct rte_flow_error *error) +{ + s32 ret; + struct rte_flow *pmd_flow =3D flow; + enum rte_filter_type filter_type =3D pmd_flow->filter_type; + struct sxe_fnav_rule fnav_rule; + struct rte_eth_ntuple_filter ntuple_filter; + struct rte_eth_ethertype_filter ethertype_filter; + struct rte_eth_syn_filter syn_filter; + struct sxe_ntuple_filter_ele *ntuple_filter_ele; + struct sxe_ethertype_filter_ele *ethertype_filter_ele; + struct sxe_eth_syn_filter_ele *syn_filter_ele; + struct sxe_fnav_rule_ele *fnav_rule_ele; + struct sxe_rss_filter_ele *rss_filter_ele; + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_fnav_context *fnav_info =3D &adapter->fnav_ctxt; + + switch (filter_type) { + case RTE_ETH_FILTER_NTUPLE: + ntuple_filter_ele =3D (struct sxe_ntuple_filter_ele *) + pmd_flow->rule; + rte_memcpy(&ntuple_filter, + &ntuple_filter_ele->filter_info, + sizeof(struct rte_eth_ntuple_filter)); + ret =3D sxe_fivetuple_filter_configure(dev, &ntuple_filter, 0); + if (!ret) { + PMD_LOG_DEBUG(DRV, "destroy fivetuple filter success."); + rte_free(ntuple_filter_ele); + } + break; + case RTE_ETH_FILTER_ETHERTYPE: + ethertype_filter_ele =3D (struct sxe_ethertype_filter_ele *) + pmd_flow->rule; + rte_memcpy(ðertype_filter, + ðertype_filter_ele->filter_info, + sizeof(struct rte_eth_ethertype_filter)); + ret =3D sxe_ethertype_filter_configure(dev, + ðertype_filter, false); + if (!ret) { + PMD_LOG_DEBUG(DRV, "destroy ethertype filter success."); + rte_free(ethertype_filter_ele); + } + break; + case RTE_ETH_FILTER_SYN: + syn_filter_ele =3D (struct sxe_eth_syn_filter_ele *) + pmd_flow->rule; + rte_memcpy(&syn_filter, + &syn_filter_ele->filter_info, + sizeof(struct rte_eth_syn_filter)); + ret =3D sxe_syn_filter_configure(dev, &syn_filter, false); + if (!ret) { + PMD_LOG_DEBUG(DRV, "destroy syn filter success."); + rte_free(syn_filter_ele); + } + break; + case RTE_ETH_FILTER_FDIR: + fnav_rule_ele =3D (struct sxe_fnav_rule_ele *)pmd_flow->rule; + rte_memcpy(&fnav_rule, + &fnav_rule_ele->filter_info, + sizeof(struct sxe_fnav_rule)); + ret =3D sxe_fnav_filter_program(dev, &fnav_rule, true); + if (!ret) { + PMD_LOG_DEBUG(DRV, "destroy fnav filter success."); + rte_free(fnav_rule_ele); + if (TAILQ_EMPTY(&fnav_info->fnav_list)) + fnav_info->mask_added =3D false; + } + break; + case RTE_ETH_FILTER_HASH: + rss_filter_ele =3D (struct sxe_rss_filter_ele *) + pmd_flow->rule; + ret =3D sxe_rss_filter_configure(dev, + &rss_filter_ele->filter_info, false); + if (!ret) { + PMD_LOG_DEBUG(DRV, "destroy rss filter success."); + rte_free(rss_filter_ele); + } + break; + default: + PMD_LOG_WARN(DRV, "filter type (%d) not supported", filter_type); + ret =3D -EINVAL; + break; + } + + if (ret) { + rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_HANDLE, + NULL, "Failed to destroy flow"); + goto l_out; + } + + rte_free(flow); + +l_out: + return ret; +} + +static s32 sxe_flow_flush(struct rte_eth_dev *dev, + struct rte_flow_error *error) +{ + s32 ret =3D 0; + u8 i; + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_filter_context *filter_ctxt =3D &adapter->filter_ctxt; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_fivetuple_filter *filter; + + while ((filter =3D TAILQ_FIRST(&filter_ctxt->fivetuple_list))) + sxe_fivetuple_filter_delete(dev, filter); + + for (i =3D 0; i < SXE_MAX_ETQF_FILTERS; i++) { + if (filter_ctxt->ethertype_mask & (1 << i) && + !filter_ctxt->ethertype_filters[i].conf) { + (void)sxe_ethertype_filter_remove(filter_ctxt, (u8)i); + sxe_hw_ethertype_filter_del(hw, i); + } + } + + sxe_syn_filter_delete(dev); + + ret =3D sxe_fnav_filter_delete_all(dev); + if (ret < 0) { + rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, + NULL, "Failed to flush rule"); + PMD_LOG_ERR(DRV, "flush fnav filter failed, flush failed."); + goto l_out; + } + + sxe_rss_filter_delete(dev); + +l_out: + return ret; +} + +const struct rte_flow_ops sxe_flow_ops =3D { + .validate =3D sxe_flow_validate, + .create =3D sxe_flow_create, + .destroy =3D sxe_flow_destroy, + .flush =3D sxe_flow_flush, +}; + +#ifdef ETH_DEV_OPS_FILTER_CTRL +s32 sxe_filter_ctrl(__rte_unused struct rte_eth_dev *dev, + enum rte_filter_type filter_type, + enum rte_filter_op filter_op, + void *arg) +{ + s32 ret =3D 0; + + switch (filter_type) { + case RTE_ETH_FILTER_GENERIC: + if (filter_op !=3D RTE_ETH_FILTER_GET) { + ret =3D -EINVAL; + goto l_out; + } + *(const void **)arg =3D &sxe_flow_ops; + break; + default: + PMD_LOG_WARN(DRV, "filter type (%d) not supported", filter_type); + ret =3D -EINVAL; + break; + } + +l_out: + return ret; +} +#else +s32 sxe_flow_ops_get(__rte_unused struct rte_eth_dev *dev, + const struct rte_flow_ops **ops) +{ + *ops =3D &sxe_flow_ops; + return 0; +} +#endif +#endif diff --git a/drivers/net/sxe/pf/sxe_filter_ctrl.h b/drivers/net/sxe/pf/sxe_= filter_ctrl.h new file mode 100644 index 0000000000..4487caf3ad --- /dev/null +++ b/drivers/net/sxe/pf/sxe_filter_ctrl.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ +#ifndef __SXE_FILTER_CTRL_H__ +#define __SXE_FILTER_CTRL_H__ + +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL +#include "sxe_filter.h" +#include "sxe_regs.h" + +#define SXE_HKEY_MAX_INDEX 10 + +#define SXE_5TUPLE_ARRAY_SIZE \ + (RTE_ALIGN(SXE_MAX_FTQF_FILTERS, (sizeof(u32) * BYTE_BIT_NUM)) / \ + (sizeof(u32) * BYTE_BIT_NUM)) + +#define SXE_5TUPLE_IPV4_MASK (ipv4_mask->hdr.version_ihl || \ + ipv4_mask->hdr.type_of_service || \ + ipv4_mask->hdr.total_length || \ + ipv4_mask->hdr.packet_id || \ + ipv4_mask->hdr.fragment_offset || \ + ipv4_mask->hdr.time_to_live || \ + ipv4_mask->hdr.hdr_checksum) + +#define SXE_5TUPLE_TCP_MASK (tcp_mask->hdr.tcp_flags || \ + tcp_mask->hdr.sent_seq || \ + tcp_mask->hdr.recv_ack || \ + tcp_mask->hdr.data_off || \ + tcp_mask->hdr.rx_win || \ + tcp_mask->hdr.cksum || \ + tcp_mask->hdr.tcp_urp) + +#define SXE_5TUPLE_UDP_MASK (udp_mask->hdr.dgram_len || \ + udp_mask->hdr.dgram_cksum) + +#define SXE_5TUPLE_SCTP_MASK (sctp_mask->hdr.tag || \ + sctp_mask->hdr.cksum) + +#define SXE_SYN_TCP_MASK (tcp_mask->hdr.src_port || \ + tcp_mask->hdr.dst_port || \ + tcp_mask->hdr.sent_seq || \ + tcp_mask->hdr.recv_ack || \ + tcp_mask->hdr.data_off || \ + tcp_mask->hdr.rx_win || \ + tcp_mask->hdr.cksum || \ + tcp_mask->hdr.tcp_urp) + +#define SXE_FNAV_IPV4_MASK (ipv4_mask->hdr.version_ihl || \ + ipv4_mask->hdr.type_of_service || \ + ipv4_mask->hdr.total_length || \ + ipv4_mask->hdr.packet_id || \ + ipv4_mask->hdr.fragment_offset || \ + ipv4_mask->hdr.time_to_live || \ + ipv4_mask->hdr.next_proto_id || \ + ipv4_mask->hdr.hdr_checksum) + +#define SXE_FNAV_IPV6_MASK (ipv6_mask->hdr.vtc_flow || \ + ipv6_mask->hdr.payload_len || \ + ipv6_mask->hdr.proto || \ + ipv6_mask->hdr.hop_limits) + +#define SXE_FNAV_TCP_MASK (tcp_mask->hdr.sent_seq || \ + tcp_mask->hdr.recv_ack || \ + tcp_mask->hdr.data_off || \ + tcp_mask->hdr.tcp_flags || \ + tcp_mask->hdr.rx_win || \ + tcp_mask->hdr.cksum || \ + tcp_mask->hdr.tcp_urp) + +#define SXE_FNAV_UDP_MASK (udp_mask->hdr.dgram_len || \ + udp_mask->hdr.dgram_cksum) + +#define SXE_FNAV_SCTP_MASK (sctp_mask->hdr.src_port || \ + sctp_mask->hdr.dst_port || \ + sctp_mask->hdr.tag || \ + sctp_mask->hdr.cksum) + +#define SXE_FNAV_RAW_MASK (raw_mask->relative !=3D 0x1 || \ + raw_mask->search !=3D 0x1 || \ + raw_mask->reserved !=3D 0x0 || \ + (u32)raw_mask->offset !=3D 0xffffffff || \ + raw_mask->limit !=3D 0xffff || \ + raw_mask->length !=3D 0xffff || \ + raw_mask->pattern[0] !=3D 0xff || \ + raw_mask->pattern[1] !=3D 0xff) + +#define SXE_FNAV_RAW_SPEC (raw_spec->relative !=3D 0 || \ + raw_spec->search !=3D 0 || \ + raw_spec->reserved !=3D 0 || \ + raw_spec->offset > SXE_MAX_FLX_SOURCE_OFF || \ + raw_spec->offset % 2 || \ + raw_spec->limit !=3D 0 || \ + raw_spec->length !=3D 2 || \ + (raw_spec->pattern[0] =3D=3D 0xff && \ + raw_spec->pattern[1] =3D=3D 0xff)) + +struct rte_flow { + enum rte_filter_type filter_type; + void *rule; +}; + +TAILQ_HEAD(sxe_fivetuple_filter_list, sxe_fivetuple_filter); + +struct sxe_ethertype_filter { + u16 ethertype; + u16 queue; + bool conf; +}; + +struct sxe_syn_filter { + bool is_syn_enable; + u16 queue; + u8 priority; +}; + +struct sxe_rss_filter { + struct rte_flow_action_rss conf; + u8 key[SXE_HKEY_MAX_INDEX * sizeof(u32)]; + u16 queue[SXE_HW_TXRX_RING_NUM_MAX]; +}; + +struct sxe_filter_context { + u8 ethertype_mask; + struct sxe_ethertype_filter ethertype_filters[SXE_MAX_ETQF_FILTERS]; + u32 fivetuple_mask[SXE_5TUPLE_ARRAY_SIZE]; + struct sxe_fivetuple_filter_list fivetuple_list; + struct sxe_syn_filter syn_filter; + struct sxe_rss_filter rss_filter; +}; + +#ifdef ETH_DEV_OPS_FILTER_CTRL +s32 sxe_filter_ctrl(__rte_unused struct rte_eth_dev *dev, + enum rte_filter_type filter_type, + enum rte_filter_op filter_op, + void *arg); +#else +s32 sxe_flow_ops_get(__rte_unused struct rte_eth_dev *dev, + const struct rte_flow_ops **ops); +#endif + +s32 sxe_fnav_filter_init(struct rte_eth_dev *dev); + +void sxe_fnav_filter_uninit(struct rte_eth_dev *dev); + +void sxe_filter_restore(struct rte_eth_dev *dev); + +void sxe_fivetuple_filter_uninit(struct rte_eth_dev *dev); + +bool sxe_is_rss_filter_same(const struct rte_flow_action_rss *cur_rss, + const struct rte_flow_action_rss *user_rss); + +#endif +#endif diff --git a/drivers/net/sxe/pf/sxe_flow_ctrl.c b/drivers/net/sxe/pf/sxe_fl= ow_ctrl.c index 33c4ffeb9d..890c5e7df3 100644 --- a/drivers/net/sxe/pf/sxe_flow_ctrl.c +++ b/drivers/net/sxe/pf/sxe_flow_ctrl.c @@ -20,7 +20,7 @@ s32 sxe_flow_ctrl_enable(struct rte_eth_dev *dev) return ret; } =20 -s32 sxe_flow_ctrl_get(struct rte_eth_dev *dev,=20 +s32 sxe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) { struct sxe_adapter *adapter =3D dev->data->dev_private; @@ -38,20 +38,19 @@ s32 sxe_flow_ctrl_get(struct rte_eth_dev *dev, =20 sxe_hw_fc_status_get(hw, &rx_pause_on, &tx_pause_on); =20 - if (rx_pause_on && tx_pause_on) { + if (rx_pause_on && tx_pause_on) fc_conf->mode =3D RTE_ETH_FC_FULL; - } else if (rx_pause_on) { + else if (rx_pause_on) fc_conf->mode =3D RTE_ETH_FC_RX_PAUSE; - } else if (tx_pause_on) { + else if (tx_pause_on) fc_conf->mode =3D RTE_ETH_FC_TX_PAUSE; - } else { + else fc_conf->mode =3D RTE_ETH_FC_NONE; - } =20 return 0; } =20 -s32 sxe_flow_ctrl_set(struct rte_eth_dev *dev,=20 +s32 sxe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) { struct sxe_adapter *adapter =3D dev->data->dev_private; diff --git a/drivers/net/sxe/pf/sxe_flow_ctrl.h b/drivers/net/sxe/pf/sxe_fl= ow_ctrl.h index 0be5d1aaaf..fb124b11bd 100644 --- a/drivers/net/sxe/pf/sxe_flow_ctrl.h +++ b/drivers/net/sxe/pf/sxe_flow_ctrl.h @@ -1,16 +1,16 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright (C), 2022, Linkdata Technology Co., Ltd. */ -=20 + #ifndef __SXE_FLOW_CTRL_H__ #define __SXE_FLOW_CTRL_H__ =20 s32 sxe_flow_ctrl_enable(struct rte_eth_dev *dev); =20 -s32 sxe_flow_ctrl_get(struct rte_eth_dev *dev,=20 +s32 sxe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); =20 -s32 sxe_flow_ctrl_set(struct rte_eth_dev *dev,=20 +s32 sxe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); =20 #endif diff --git a/drivers/net/sxe/pf/sxe_fnav.c b/drivers/net/sxe/pf/sxe_fnav.c new file mode 100644 index 0000000000..c0b54bbefe --- /dev/null +++ b/drivers/net/sxe/pf/sxe_fnav.c @@ -0,0 +1,507 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL +#include +#include +#include +#include +#include +#include "sxe_dpdk_version.h" +#if defined DPDK_20_11_5 || defined DPDK_19_11_6 +#include +#else +#include +#endif +#include +#include + +#include "sxe.h" +#include "sxe_logs.h" +#include "sxe_hw.h" +#include "sxe_fnav.h" + +#define FNAVCTRL_PBALLOC_MASK 0x03 + +#define PBALLOC_SIZE_SHIFT 15 + +#define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF +#define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF +#define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF +#define SIG_BUCKET_64KB_HASH_MASK 0x1FFF +#define SIG_BUCKET_128KB_HASH_MASK 0x3FFF +#define SIG_BUCKET_256KB_HASH_MASK 0x7FFF + +#define SXE_DEFAULT_FLEXBYTES_OFFSET 12 + +static s32 sxe_ipv6_to_mask(const u32 *ipaddr, u16 *ipv6m) +{ + u8 ipv6_addr[16]; + u8 i; + + rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr)); + (*ipv6m) =3D 0; + for (i =3D 0; i < sizeof(ipv6_addr); i++) { + if (ipv6_addr[i] =3D=3D UINT8_MAX) + (*ipv6m) |=3D 1 << i; + else if (ipv6_addr[i] !=3D 0) { + PMD_LOG_ERR(DRV, " invalid ipv6 address mask."); + return -EINVAL; + } + } + + return 0; +} + +static s32 +sxe_fnav_ctrl_info_parse(const struct rte_eth_fdir_conf *conf, u32 *fnavct= rl) +{ + *fnavctrl =3D 0; + s32 ret =3D 0; + + switch (conf->pballoc) { + case RTE_ETH_FDIR_PBALLOC_64K: + *fnavctrl |=3D SXE_FNAVCTRL_PBALLOC_64K; + break; + case RTE_ETH_FDIR_PBALLOC_128K: + *fnavctrl |=3D SXE_FNAVCTRL_PBALLOC_128K; + break; + case RTE_ETH_FDIR_PBALLOC_256K: + *fnavctrl |=3D SXE_FNAVCTRL_PBALLOC_256K; + break; + default: + PMD_LOG_ERR(INIT, "invalid fnav_conf->pballoc value"); + ret =3D -EINVAL; + goto l_out; + }; + + switch (conf->status) { + case RTE_FDIR_NO_REPORT_STATUS: + break; + case RTE_FDIR_REPORT_STATUS: + *fnavctrl |=3D SXE_FNAVCTRL_REPORT_STATUS; + break; + case RTE_FDIR_REPORT_STATUS_ALWAYS: + *fnavctrl |=3D SXE_FNAVCTRL_REPORT_STATUS_ALWAYS; + break; + default: + PMD_LOG_ERR(INIT, "invalid fnav_conf->status value"); + ret =3D -EINVAL; + goto l_out; + }; + + *fnavctrl |=3D (SXE_DEFAULT_FLEXBYTES_OFFSET / sizeof(u16)) << + SXE_FNAVCTRL_FLEX_SHIFT; + + if (conf->mode =3D=3D RTE_FDIR_MODE_PERFECT) { + *fnavctrl |=3D SXE_FNAVCTRL_SPECIFIC_MATCH; + *fnavctrl |=3D (conf->drop_queue << SXE_FNAVCTRL_DROP_Q_SHIFT); + } + +l_out: + return ret; +} + +static s32 +sxe_fnav_mask_store(struct rte_eth_dev *dev, + const struct rte_eth_fdir_masks *mask) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_fnav_context *fnav_ctxt =3D &adapter->fnav_ctxt; + u16 dst_ipv6_mask =3D 0; + u16 src_ipv6_mask =3D 0; + int rtn =3D 0; + + memset(&fnav_ctxt->mask, 0, sizeof(struct sxe_hw_fnav_mask)); + fnav_ctxt->mask.vlan_tci_mask =3D mask->vlan_tci_mask; + fnav_ctxt->mask.src_port_mask =3D mask->src_port_mask; + fnav_ctxt->mask.dst_port_mask =3D mask->dst_port_mask; + fnav_ctxt->mask.src_ipv4_mask =3D mask->ipv4_mask.src_ip; + fnav_ctxt->mask.dst_ipv4_mask =3D mask->ipv4_mask.dst_ip; + + rtn =3D sxe_ipv6_to_mask(mask->ipv6_mask.src_ip, &src_ipv6_mask); + if (rtn =3D=3D -EINVAL) { + return rtn; + } + rtn =3D sxe_ipv6_to_mask(mask->ipv6_mask.dst_ip, &dst_ipv6_mask); + if (rtn =3D=3D -EINVAL) { + return rtn; + } + fnav_ctxt->mask.src_ipv6_mask =3D src_ipv6_mask; + fnav_ctxt->mask.dst_ipv6_mask =3D dst_ipv6_mask; + + return 0; +} + +s32 sxe_fnav_mask_set(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_fnav_context *fnav_ctxt =3D &adapter->fnav_ctxt; + union sxe_fnav_rule_info mask; + s32 ret =3D 0; + + PMD_INIT_FUNC_TRACE(); + memset(&mask, 0, sizeof(union sxe_fnav_rule_info)); + + if (fnav_ctxt->mask.dst_port_mask !=3D 0 || fnav_ctxt->mask.src_port_mask= !=3D 0) + mask.ntuple.flow_type |=3D SXE_SAMPLE_L4TYPE_MASK; + + mask.ntuple.vlan_id =3D fnav_ctxt->mask.vlan_tci_mask; + mask.ntuple.flex_bytes =3D fnav_ctxt->mask.flex_bytes_mask; + mask.ntuple.dst_port =3D fnav_ctxt->mask.dst_port_mask; + mask.ntuple.src_port =3D fnav_ctxt->mask.src_port_mask; + mask.ntuple.src_ip[0] =3D fnav_ctxt->mask.src_ipv4_mask; + mask.ntuple.dst_ip[0] =3D fnav_ctxt->mask.dst_ipv4_mask; + + ret =3D sxe_hw_fnav_specific_rule_mask_set(hw, &mask); + if (ret) { + PMD_LOG_ERR(DRV, "error on setting fnav mask"); + goto l_out; + } + + if (SXE_DEV_FNAV_CONF(dev)->mode =3D=3D RTE_FDIR_MODE_SIGNATURE) { + sxe_hw_fnav_ipv6_mask_set(hw, fnav_ctxt->mask.src_ipv6_mask, + fnav_ctxt->mask.dst_ipv6_mask); + } + +l_out: + return ret; +} + +static s32 +sxe_fnav_mask_configure(struct rte_eth_dev *dev, + const struct rte_eth_fdir_masks *mask) +{ + s32 ret; + + ret =3D sxe_fnav_mask_store(dev, mask); + if (ret) { + PMD_LOG_ERR(INIT, " error on storing fnav mask"); + goto l_out; + } + + ret =3D sxe_fnav_mask_set(dev); + if (ret) { + PMD_LOG_ERR(INIT, " error on setting fnav mask"); + goto l_out; + } + +l_out: + return ret; +} + +static s32 +sxe_fnav_flex_conf_set(struct rte_eth_dev *dev, + const struct rte_eth_fdir_flex_conf *conf, u32 *fnavctrl) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_fnav_context *fnav_ctxt =3D &adapter->fnav_ctxt; + const struct rte_eth_flex_payload_cfg *flex_cfg; + const struct rte_eth_fdir_flex_mask *flex_mask; + u16 flexbytes =3D 0; + u16 i; + s32 ret =3D -EINVAL; + + if (conf =3D=3D NULL) { + PMD_LOG_ERR(DRV, "null pointer."); + goto l_out; + } + + for (i =3D 0; i < conf->nb_payloads; i++) { + flex_cfg =3D &conf->flex_set[i]; + if (flex_cfg->type !=3D RTE_ETH_RAW_PAYLOAD) { + PMD_LOG_ERR(DRV, "unsupported payload type."); + goto l_out; + } + if (((flex_cfg->src_offset[0] & 0x1) =3D=3D 0) && + (flex_cfg->src_offset[1] =3D=3D flex_cfg->src_offset[0] + 1) && + (flex_cfg->src_offset[0] <=3D SXE_MAX_FLX_SOURCE_OFF)) { + *fnavctrl &=3D ~SXE_FNAVCTRL_FLEX_MASK; + *fnavctrl |=3D + (flex_cfg->src_offset[0] / sizeof(u16)) << + SXE_FNAVCTRL_FLEX_SHIFT; + } else { + PMD_LOG_ERR(DRV, "invalid flexbytes arguments."); + goto l_out; + } + } + + for (i =3D 0; i < conf->nb_flexmasks; i++) { + flex_mask =3D &conf->flex_mask[i]; + if (flex_mask->flow_type !=3D RTE_ETH_FLOW_UNKNOWN) { + PMD_LOG_ERR(DRV, "flexmask should be set globally."); + goto l_out; + } + flexbytes =3D (u16)(((flex_mask->mask[0] << 8) & 0xFF00) | + ((flex_mask->mask[1]) & 0xFF)); + if (flexbytes !=3D UINT16_MAX && flexbytes !=3D 0) { + PMD_LOG_ERR(DRV, "invalid flexbytes mask arguments."); + goto l_out; + } + } + + sxe_hw_fnav_flex_mask_set(hw, flexbytes); + + fnav_ctxt->mask.flex_bytes_mask =3D flexbytes ? UINT16_MAX : 0; + fnav_ctxt->flex_bytes_offset =3D (u8)((*fnavctrl & + SXE_FNAVCTRL_FLEX_MASK) >> + SXE_FNAVCTRL_FLEX_SHIFT); + ret =3D 0; + +l_out: + return ret; +} + +s32 sxe_fnav_filter_configure(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + s32 ret; + u32 fnavctrl, pbsize; + enum rte_fdir_mode mode =3D SXE_DEV_FNAV_CONF(dev)->mode; + + PMD_INIT_FUNC_TRACE(); + + if (mode !=3D RTE_FDIR_MODE_SIGNATURE && + mode !=3D RTE_FDIR_MODE_PERFECT) { + ret =3D -ENOSYS; + goto l_out; + } + + ret =3D sxe_fnav_ctrl_info_parse(SXE_DEV_FNAV_CONF(dev), &fnavctrl); + if (ret) { + PMD_LOG_ERR(INIT, "fnav flag config fail."); + goto l_out; + } + + pbsize =3D (1 << (PBALLOC_SIZE_SHIFT + (fnavctrl & FNAVCTRL_PBALLOC_MASK)= )); + sxe_hw_fnav_rx_pkt_buf_size_reset(hw, pbsize); + + ret =3D sxe_fnav_mask_configure(dev, &(SXE_DEV_FNAV_CONF(dev)->mask)); + if (ret < 0) { + PMD_LOG_ERR(INIT, " error on setting fnav mask"); + goto l_out; + } + + ret =3D sxe_fnav_flex_conf_set(dev, + &(SXE_DEV_FNAV_CONF(dev)->flex_conf), &fnavctrl); + if (ret < 0) { + PMD_LOG_ERR(INIT, "error on setting fnav flexible arguments."); + goto l_out; + } + + sxe_hw_fnav_enable(hw, fnavctrl); + +l_out: + return ret; +} + +static u32 +sxe_fnav_hash_compute(union sxe_fnav_rule_info *rule_info, u32 key) +{ + __be32 common_dword =3D 0; + u32 high_dword, low_dword, flow_vm_vlan; + u32 result =3D 0; + u8 i; + + flow_vm_vlan =3D rte_be_to_cpu_32(rule_info->fast_access[0]); + + for (i =3D 1; i <=3D 10; i++) + common_dword ^=3D rule_info->fast_access[i]; + + high_dword =3D rte_be_to_cpu_32(common_dword); + low_dword =3D (high_dword >> 16) | (high_dword << 16); + high_dword ^=3D flow_vm_vlan ^ (flow_vm_vlan >> 16); + + if (key & 0x0001) + result ^=3D low_dword; + + if (key & 0x00010000) + result ^=3D high_dword; + + low_dword ^=3D flow_vm_vlan ^ (flow_vm_vlan << 16); + + for (i =3D 15; i; i--) { + if (key & (0x0001 << i)) + result ^=3D low_dword >> i; + if (key & (0x00010000 << i)) + result ^=3D high_dword >> i; + } + + return result; +} + +u32 sxe_fnav_perfect_hash_compute(union sxe_fnav_rule_info *rule_info, + enum rte_eth_fdir_pballoc_type pballoc) +{ + u32 ret; + + if (pballoc =3D=3D RTE_ETH_FDIR_PBALLOC_256K) { + ret =3D sxe_fnav_hash_compute(rule_info, + SXE_FNAV_BUCKET_HASH_KEY) & + PERFECT_BUCKET_256KB_HASH_MASK; + goto l_out; + } else if (pballoc =3D=3D RTE_ETH_FDIR_PBALLOC_128K) { + ret =3D sxe_fnav_hash_compute(rule_info, + SXE_FNAV_BUCKET_HASH_KEY) & + PERFECT_BUCKET_128KB_HASH_MASK; + goto l_out; + } else { + ret =3D sxe_fnav_hash_compute(rule_info, + SXE_FNAV_BUCKET_HASH_KEY) & + PERFECT_BUCKET_64KB_HASH_MASK; + goto l_out; + } + +l_out: + return ret; +} + +u32 sxe_fnav_signature_hash_compute(union sxe_fnav_rule_info *rule_info, + enum rte_eth_fdir_pballoc_type pballoc) +{ + u32 bucket_hash, sig_hash; + + if (pballoc =3D=3D RTE_ETH_FDIR_PBALLOC_256K) { + bucket_hash =3D sxe_fnav_hash_compute(rule_info, + SXE_FNAV_BUCKET_HASH_KEY) & + SIG_BUCKET_256KB_HASH_MASK; + } else if (pballoc =3D=3D RTE_ETH_FDIR_PBALLOC_128K) { + bucket_hash =3D sxe_fnav_hash_compute(rule_info, + SXE_FNAV_BUCKET_HASH_KEY) & + SIG_BUCKET_128KB_HASH_MASK; + } else { + bucket_hash =3D sxe_fnav_hash_compute(rule_info, + SXE_FNAV_BUCKET_HASH_KEY) & + SIG_BUCKET_64KB_HASH_MASK; + } + + sig_hash =3D sxe_fnav_hash_compute(rule_info, SXE_FNAV_SAMPLE_HASH_KEY); + + return (sig_hash << SXE_FNAVHASH_SIG_SW_INDEX_SHIFT) | bucket_hash; +} + +s32 sxe_fnav_filter_insert(struct sxe_fnav_context *fnav_ctxt, + struct sxe_fnav_filter *fnav_filter) +{ + s32 ret; + + ret =3D rte_hash_add_key(fnav_ctxt->hash_handle, + &fnav_filter->sxe_fnav); + if (ret < 0) { + PMD_LOG_ERR(DRV, + "failed to insert fnav filter to hash table %d!", + ret); + goto l_out; + } + + fnav_ctxt->hash_map[ret] =3D fnav_filter; + + TAILQ_INSERT_TAIL(&fnav_ctxt->fnav_list, fnav_filter, entries); + +l_out: + return ret; +} + +s32 sxe_fnav_filter_remove(struct sxe_fnav_context *fnav_ctxt, + union sxe_fnav_rule_info *key) +{ + s32 ret; + struct sxe_fnav_filter *fnav_filter; + + ret =3D rte_hash_del_key(fnav_ctxt->hash_handle, key); + if (ret < 0) { + PMD_LOG_ERR(DRV, "no such fnav filter to delete %d!", ret); + goto l_out; + } + + fnav_filter =3D fnav_ctxt->hash_map[ret]; + fnav_ctxt->hash_map[ret] =3D NULL; + + TAILQ_REMOVE(&fnav_ctxt->fnav_list, fnav_filter, entries); + rte_free(fnav_filter); + +l_out: + return ret; +} + +struct sxe_fnav_filter * +sxe_fnav_filter_lookup(struct sxe_fnav_context *fnav_ctxt, + union sxe_fnav_rule_info *key) +{ + s32 ret; + struct sxe_fnav_filter *fnav_filter; + + ret =3D rte_hash_lookup(fnav_ctxt->hash_handle, (const void *)key); + if (ret < 0) { + fnav_filter =3D NULL; + goto l_out; + } + + fnav_filter =3D fnav_ctxt->hash_map[ret]; +l_out: + return fnav_filter; +} + +s32 sxe_fnav_filter_delete_all(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_fnav_context *fnav_ctxt =3D &adapter->fnav_ctxt; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_fnav_filter *fnav_filter; + struct sxe_fnav_filter *filter; + s32 ret =3D 0; + + rte_hash_reset(fnav_ctxt->hash_handle); + memset(fnav_ctxt->hash_map, 0, + sizeof(struct sxe_fnav_filter *) * SXE_MAX_FNAV_FILTER_NUM); + filter =3D TAILQ_FIRST(&fnav_ctxt->fnav_list); + + while ((fnav_filter =3D TAILQ_FIRST(&fnav_ctxt->fnav_list))) { + TAILQ_REMOVE(&fnav_ctxt->fnav_list, + fnav_filter, entries); + rte_free(fnav_filter); + } + fnav_ctxt->mask_added =3D false; + + if (filter !=3D NULL) { + ret =3D sxe_hw_fnav_sample_rules_table_reinit(hw); + if (ret < 0) { + PMD_LOG_ERR(INIT, "failed to re-initialize fd table."); + goto l_out; + } + } + +l_out: + return ret; +} + +void sxe_fnav_filter_restore(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct sxe_fnav_context *fnav_ctxt =3D &adapter->fnav_ctxt; + struct sxe_fnav_filter *node; + enum rte_fdir_mode fnav_mode =3D SXE_DEV_FNAV_CONF(dev)->mode; + + if (fnav_mode =3D=3D RTE_FDIR_MODE_PERFECT) { + TAILQ_FOREACH(node, &fnav_ctxt->fnav_list, entries) { + (void)sxe_hw_fnav_specific_rule_add(hw, + &node->sxe_fnav, + node->soft_id, + node->queue); + } + } else { + TAILQ_FOREACH(node, &fnav_ctxt->fnav_list, entries) { + sxe_hw_fnav_sample_rule_configure(hw, + node->sxe_fnav.ntuple.flow_type, + node->fnavhash, + node->queue); + } + } + +} + +#endif diff --git a/drivers/net/sxe/pf/sxe_fnav.h b/drivers/net/sxe/pf/sxe_fnav.h new file mode 100644 index 0000000000..2b4eb81de6 --- /dev/null +++ b/drivers/net/sxe/pf/sxe_fnav.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ +#ifndef __SXE_FNAV_H__ +#define __SXE_FNAV_H__ + +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL +#define SXE_MAX_FLX_SOURCE_OFF 62 + +#define SXE_MAX_FNAV_FILTER_NUM (1024 * 32) + +struct sxe_hw_fnav_mask { + u16 vlan_tci_mask; + u32 src_ipv4_mask; + u32 dst_ipv4_mask; + u16 src_ipv6_mask; + u16 dst_ipv6_mask; + u16 src_port_mask; + u16 dst_port_mask; + u16 flex_bytes_mask; +}; + +struct sxe_fnav_filter { + TAILQ_ENTRY(sxe_fnav_filter) entries; + union sxe_fnav_rule_info sxe_fnav; + u32 fnavflags; + u32 fnavhash; + u32 soft_id; + u8 queue; +}; + +TAILQ_HEAD(sxe_fnav_filter_list, sxe_fnav_filter); + +struct sxe_fnav_rule { + struct sxe_hw_fnav_mask mask; + union sxe_fnav_rule_info sxe_fnav; + bool b_spec; + bool b_mask; + enum rte_fdir_mode mode; + u32 fnavflags; + u32 soft_id; + u8 queue; + u8 flex_bytes_offset; +}; + +struct sxe_fnav_context { + struct sxe_hw_fnav_mask mask; + u8 flex_bytes_offset; + struct sxe_fnav_filter_list fnav_list; + struct sxe_fnav_filter **hash_map; + struct rte_hash *hash_handle; + bool mask_added; +}; + +s32 sxe_fnav_filter_configure(struct rte_eth_dev *dev); + +s32 sxe_fnav_mask_set(struct rte_eth_dev *dev); + +s32 sxe_fnav_filter_remove(struct sxe_fnav_context *fnav_ctxt, + union sxe_fnav_rule_info *key); + +struct sxe_fnav_filter * +sxe_fnav_filter_lookup(struct sxe_fnav_context *fnav_ctxt, + union sxe_fnav_rule_info *key); + +s32 sxe_fnav_filter_insert(struct sxe_fnav_context *fnav_ctxt, + struct sxe_fnav_filter *fnav_filter); + +u32 sxe_fnav_perfect_hash_compute(union sxe_fnav_rule_info *rule_info, + enum rte_eth_fdir_pballoc_type pballoc); + +u32 sxe_fnav_signature_hash_compute(union sxe_fnav_rule_info *rule_info, + enum rte_eth_fdir_pballoc_type pballoc); + +void sxe_fnav_filter_restore(struct rte_eth_dev *dev); + +s32 sxe_fnav_filter_delete_all(struct rte_eth_dev *dev); + +#endif +#endif diff --git a/drivers/net/sxe/pf/sxe_irq.c b/drivers/net/sxe/pf/sxe_irq.c index 90c1e168f8..e7995d85d9 100644 --- a/drivers/net/sxe/pf/sxe_irq.c +++ b/drivers/net/sxe/pf/sxe_irq.c @@ -31,17 +31,17 @@ #include "sxe_compat_version.h" #include "sxe_vf.h" =20 -#define SXE_LINK_DOWN_TIMEOUT 4000=20 -#define SXE_LINK_UP_TIMEOUT 1000=20 +#define SXE_LINK_DOWN_TIMEOUT 4000 +#define SXE_LINK_UP_TIMEOUT 1000 =20 -#define SXE_IRQ_MAILBOX (u32)(1 << 1) -#define SXE_IRQ_MACSEC (u32)(1 << 2) +#define SXE_IRQ_MAILBOX (u32)(1 << 1) +#define SXE_IRQ_MACSEC (u32)(1 << 2) =20 -#define SXE_LINK_UP_TIME 90=20 +#define SXE_LINK_UP_TIME 90 =20 -#define SXE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET +#define SXE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET =20 -#define SXE_RX_VEC_BASE RTE_INTR_VEC_RXTX_OFFSET +#define SXE_RX_VEC_BASE RTE_INTR_VEC_RXTX_OFFSET =20 static void sxe_link_info_output(struct rte_eth_dev *dev) { @@ -63,7 +63,6 @@ static void sxe_link_info_output(struct rte_eth_dev *dev) pci_dev->addr.devid, pci_dev->addr.function); =20 - return; } =20 void sxe_event_irq_delayed_handler(void *param) @@ -94,9 +93,8 @@ void sxe_event_irq_delayed_handler(void *param) rte_spinlock_unlock(&adapter->irq_ctxt.event_irq_lock); =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SRIOV - if (eicr & SXE_EICR_MAILBOX) { + if (eicr & SXE_EICR_MAILBOX) sxe_mbx_irq_handler(eth_dev); - } #endif =20 if (irq->action & SXE_IRQ_LINK_UPDATE) { @@ -116,7 +114,6 @@ void sxe_event_irq_delayed_handler(void *param) =20 rte_intr_ack(intr_handle); =20 - return; } =20 static void sxe_lsc_irq_handler(struct rte_eth_dev *eth_dev) @@ -134,12 +131,12 @@ static void sxe_lsc_irq_handler(struct rte_eth_dev *e= th_dev) =20 if (!link.link_status && !link_up) { PMD_LOG_DEBUG(DRV, "link change irq, down->down, do nothing."); - goto l_out; + return; } =20 if (irq->to_pcs_init) { PMD_LOG_DEBUG(DRV, "to set pcs init, do nothing."); - goto l_out; + return; } =20 PMD_LOG_INFO(DRV, "link change irq handler start"); @@ -150,8 +147,8 @@ static void sxe_lsc_irq_handler(struct rte_eth_dev *eth= _dev) SXE_LINK_UP_TIMEOUT; =20 if (rte_eal_alarm_set(timeout * 1000, - sxe_event_irq_delayed_handler, - (void *)eth_dev) < 0) { + sxe_event_irq_delayed_handler, + (void *)eth_dev) < 0) { PMD_LOG_ERR(DRV, "submit event irq delay handle fail."); } else { irq->enable_mask &=3D ~SXE_EIMS_LSC; @@ -159,8 +156,6 @@ static void sxe_lsc_irq_handler(struct rte_eth_dev *eth= _dev) =20 PMD_LOG_INFO(DRV, "link change irq handler end"); =20 -l_out: - return; } =20 static s32 sxe_event_irq_action(struct rte_eth_dev *eth_dev) @@ -187,7 +182,7 @@ static s32 sxe_event_irq_action(struct rte_eth_dev *eth= _dev) return 0; } =20 -STATIC void sxe_event_irq_handler(void *data) +static void sxe_event_irq_handler(void *data) { struct rte_eth_dev *eth_dev =3D (struct rte_eth_dev *)data; struct sxe_adapter *adapter =3D eth_dev->data->dev_private; @@ -208,17 +203,14 @@ STATIC void sxe_event_irq_handler(void *data) =20 rte_spinlock_unlock(&adapter->irq_ctxt.event_irq_lock); =20 - if (eicr & SXE_EICR_LSC) { + if (eicr & SXE_EICR_LSC) irq->action |=3D SXE_IRQ_LINK_UPDATE; - } =20 - if (eicr & SXE_EICR_MAILBOX) { + if (eicr & SXE_EICR_MAILBOX) irq->action |=3D SXE_IRQ_MAILBOX; - } =20 - if (eicr & SXE_EICR_LINKSEC) { + if (eicr & SXE_EICR_LINKSEC) irq->action |=3D SXE_IRQ_MACSEC; - } =20 sxe_event_irq_action(eth_dev); =20 @@ -226,7 +218,6 @@ STATIC void sxe_event_irq_handler(void *data) sxe_hw_specific_irq_enable(hw, irq->enable_mask); rte_spinlock_unlock(&adapter->irq_ctxt.event_irq_lock); =20 - return; } =20 void sxe_irq_init(struct rte_eth_dev *eth_dev) @@ -247,7 +238,7 @@ void sxe_irq_init(struct rte_eth_dev *eth_dev) u32 gpie =3D 0; =20 if ((irq_handle->type =3D=3D RTE_INTR_HANDLE_UIO) || - (irq_handle->type =3D=3D RTE_INTR_HANDLE_VFIO_MSIX)) { + (irq_handle->type =3D=3D RTE_INTR_HANDLE_VFIO_MSIX)) { gpie =3D sxe_hw_irq_general_reg_get(hw); =20 gpie |=3D SXE_GPIE_MSIX_MODE | SXE_GPIE_OCD; @@ -257,7 +248,6 @@ void sxe_irq_init(struct rte_eth_dev *eth_dev) =20 sxe_hw_specific_irq_enable(hw, irq->enable_mask); #endif - return; } =20 static s32 sxe_irq_general_config(struct rte_eth_dev *dev) @@ -271,7 +261,7 @@ static s32 sxe_irq_general_config(struct rte_eth_dev *d= ev) =20 gpie =3D sxe_hw_irq_general_reg_get(hw); if (!rte_intr_dp_is_en(handle) && - !(gpie & (SXE_GPIE_MSIX_MODE | SXE_GPIE_PBA_SUPPORT))) { + !(gpie & (SXE_GPIE_MSIX_MODE | SXE_GPIE_PBA_SUPPORT))) { ret =3D -SXE_ERR_CONFIG; gpie |=3D SXE_GPIE_MSIX_MODE; PMD_LOG_INFO(DRV, "rx queue irq num:%d gpie:0x%x.", @@ -304,14 +294,13 @@ static void sxe_msix_configure(struct rte_eth_dev *de= v) ret =3D sxe_irq_general_config(dev); if (ret) { PMD_LOG_INFO(DRV, "unsupport msi-x, no need config irq"); - goto l_out; + return; } =20 - if (rte_intr_allow_others(handle)) { + if (rte_intr_allow_others(handle)) vector =3D base =3D SXE_RX_VEC_BASE; - } =20 - irq_interval =3D SXE_EITR_INTERVAL_US(SXE_QUEUE_ITR_INTERVAL_DEFAULT); + irq_interval =3D SXE_EITR_INTERVAL_US(SXE_QUEUE_ITR_INTERVAL); =20 if (rte_intr_dp_is_en(handle)) { for (queue_id =3D 0; queue_id < dev->data->nb_rx_queues; @@ -331,9 +320,8 @@ static void sxe_msix_configure(struct rte_eth_dev *dev) queue_id, rx_queue->reg_idx, vector); - if (vector < base + handle->nb_efd - 1) { + if (vector < base + handle->nb_efd - 1) vector++; - } } sxe_hw_event_irq_map(hw, 1, SXE_MISC_VEC_ID); } @@ -346,8 +334,6 @@ static void sxe_msix_configure(struct rte_eth_dev *dev) value &=3D ~(SXE_EIMS_OTHER | SXE_EIMS_MAILBOX | SXE_EIMS_LSC); sxe_hw_event_irq_auto_clear_set(hw, value); =20 -l_out: - return; } =20 s32 sxe_irq_configure(struct rte_eth_dev *eth_dev) @@ -358,12 +344,12 @@ s32 sxe_irq_configure(struct rte_eth_dev *eth_dev) s32 ret =3D 0; =20 if ((rte_intr_cap_multiple(handle) || - !RTE_ETH_DEV_SRIOV(eth_dev).active) && - eth_dev->data->dev_conf.intr_conf.rxq !=3D 0) { + !RTE_ETH_DEV_SRIOV(eth_dev).active) && + eth_dev->data->dev_conf.intr_conf.rxq !=3D 0) { irq_num =3D eth_dev->data->nb_rx_queues; if (irq_num > SXE_QUEUE_IRQ_NUM_MAX) { PMD_LOG_ERR(DRV, "irq_num:%u exceed limit:%u ", - irq_num, SXE_QUEUE_IRQ_NUM_MAX); + irq_num, SXE_QUEUE_IRQ_NUM_MAX); ret =3D -ENOTSUP; goto l_out; } @@ -371,15 +357,15 @@ s32 sxe_irq_configure(struct rte_eth_dev *eth_dev) if (rte_intr_efd_enable(handle, irq_num)) { ret =3D -SXE_ERR_CONFIG; PMD_LOG_ERR(DRV, - "intr_handle type:%d irq num:%d invalid", - handle->type, irq_num); + "intr_handle type:%d irq num:%d invalid", + handle->type, irq_num); goto l_out; } } =20 if (rte_intr_dp_is_en(handle) && !handle->intr_vec) { handle->intr_vec =3D rte_zmalloc("intr_vec", - eth_dev->data->nb_rx_queues * sizeof(u32), 0); + eth_dev->data->nb_rx_queues * sizeof(u32), 0); if (handle->intr_vec =3D=3D NULL) { PMD_LOG_ERR(DRV, "rx queue irq vector " "allocate %zuB memory fail.", @@ -394,14 +380,14 @@ s32 sxe_irq_configure(struct rte_eth_dev *eth_dev) sxe_irq_enable(eth_dev); =20 PMD_LOG_INFO(DRV, - "intr_conf rxq:%u intr_handle type:%d rx queue num:%d " - "queue irq num:%u total irq num:%u " - "config done", - eth_dev->data->dev_conf.intr_conf.rxq, - handle->type, - eth_dev->data->nb_rx_queues, - handle->nb_efd, - handle->max_intr); + "intr_conf rxq:%u intr_handle type:%d rx queue num:%d " + "queue irq num:%u total irq num:%u " + "config done", + eth_dev->data->dev_conf.intr_conf.rxq, + handle->type, + eth_dev->data->nb_rx_queues, + handle->nb_efd, + handle->max_intr); =20 l_out: return ret; @@ -418,35 +404,32 @@ void sxe_irq_enable(struct rte_eth_dev *eth_dev) if (rte_intr_allow_others(handle)) { sxe_link_info_output(eth_dev); =20 - if (eth_dev->data->dev_conf.intr_conf.lsc !=3D 0) { + if (eth_dev->data->dev_conf.intr_conf.lsc !=3D 0) irq->enable_mask |=3D SXE_EIMS_LSC; - } else { + else irq->enable_mask &=3D ~SXE_EIMS_LSC; - } + } else { rte_intr_callback_unregister(handle, - sxe_event_irq_handler, eth_dev); - if (eth_dev->data->dev_conf.intr_conf.lsc !=3D 0) { + sxe_event_irq_handler, eth_dev); + if (eth_dev->data->dev_conf.intr_conf.lsc !=3D 0) PMD_LOG_ERR(DRV, "event irq not support."); - } } =20 /* check if rxq interrupt is enabled */ if (eth_dev->data->dev_conf.intr_conf.rxq !=3D 0 && - rte_intr_dp_is_en(handle)) { + rte_intr_dp_is_en(handle)) irq->enable_mask |=3D SXE_EIMS_RTX_QUEUE; - } =20 rte_intr_enable(handle); =20 sxe_hw_specific_irq_enable(hw, irq->enable_mask); =20 PMD_LOG_INFO(DRV, - "intr_handle type:%d enable irq mask:0x%x", - handle->type, - irq->enable_mask); + "intr_handle type:%d enable irq mask:0x%x", + handle->type, + irq->enable_mask); =20 - return; } =20 void sxe_irq_vec_free(struct rte_intr_handle *handle) @@ -456,7 +439,6 @@ void sxe_irq_vec_free(struct rte_intr_handle *handle) handle->intr_vec =3D NULL; } =20 - return; } =20 void sxe_irq_disable(struct rte_eth_dev *eth_dev) @@ -473,7 +455,6 @@ void sxe_irq_disable(struct rte_eth_dev *eth_dev) rte_intr_efd_disable(handle); sxe_irq_vec_free(handle); =20 - return; } =20 void sxe_irq_uninit(struct rte_eth_dev *eth_dev) @@ -492,14 +473,13 @@ void sxe_irq_uninit(struct rte_eth_dev *eth_dev) break; } else if (ret !=3D -EAGAIN) { PMD_LOG_ERR(DRV, - "irq handler unregister fail, next to retry"); + "irq handler unregister fail, next to retry"); } rte_delay_ms(100); } while (retry++ < (10 + SXE_LINK_UP_TIME)); =20 rte_eal_alarm_cancel(sxe_event_irq_delayed_handler, eth_dev); =20 - return; } =20 s32 sxe_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, u16 queue_id) @@ -528,7 +508,7 @@ s32 sxe_rx_queue_intr_enable(struct rte_eth_dev *eth_de= v, u16 queue_id) rte_intr_ack(intr_handle); =20 PMD_LOG_INFO(DRV, "queue_id:%u irq enabled enable_mask:0x%x.", - queue_id, irq->enable_mask); + queue_id, irq->enable_mask); =20 return 0; } @@ -555,7 +535,7 @@ s32 sxe_rx_queue_intr_disable(struct rte_eth_dev *eth_d= ev, u16 queue_id) } =20 PMD_LOG_INFO(DRV, "queue_id:%u irq disabled enable_mask:0x%x.", - queue_id, irq->enable_mask); + queue_id, irq->enable_mask); =20 return 0; } diff --git a/drivers/net/sxe/pf/sxe_irq.h b/drivers/net/sxe/pf/sxe_irq.h index 322d7023c9..7b63013545 100644 --- a/drivers/net/sxe/pf/sxe_irq.h +++ b/drivers/net/sxe/pf/sxe_irq.h @@ -15,21 +15,22 @@ #include "sxe_compat_platform.h" #include "sxe_compat_version.h" =20 -#define SXE_QUEUE_IRQ_NUM_MAX 15 +#define SXE_QUEUE_IRQ_NUM_MAX 15 =20 -#define SXE_QUEUE_ITR_INTERVAL_DEFAULT 500=20 +#define SXE_QUEUE_ITR_INTERVAL_DEFAULT 500 +#define SXE_QUEUE_ITR_INTERVAL 3 =20 #define SXE_EITR_INTERVAL_UNIT_NS 2048 -#define SXE_EITR_ITR_INT_SHIFT 3 -#define SXE_IRQ_ITR_MASK (0x00000FF8) +#define SXE_EITR_ITR_INT_SHIFT 3 +#define SXE_IRQ_ITR_MASK (0x00000FF8) #define SXE_EITR_INTERVAL_US(us) \ (((us) * 1000 / SXE_EITR_INTERVAL_UNIT_NS << SXE_EITR_ITR_INT_SHIFT) & \ SXE_IRQ_ITR_MASK) =20 struct sxe_irq_context { - u32 action;=20=20=20=20=20=20=20=20=20=20 - u32 enable_mask;=20=20=20=20 - u32 enable_mask_original;=20 + u32 action; + u32 enable_mask; + u32 enable_mask_original; rte_spinlock_t event_irq_lock; bool to_pcs_init; }; diff --git a/drivers/net/sxe/pf/sxe_macsec.c b/drivers/net/sxe/pf/sxe_macse= c.c new file mode 100644 index 0000000000..4a49405a95 --- /dev/null +++ b/drivers/net/sxe/pf/sxe_macsec.c @@ -0,0 +1,260 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_MACSEC + +#include +#include +#include +#include "sxe_dpdk_version.h" +#if defined DPDK_20_11_5 || defined DPDK_19_11_6 +#include +#include +#elif defined DPDK_21_11_5 +#include +#include +#else +#include +#include +#endif + +#include "sxe_logs.h" +#include "sxe.h" +#include "sxe_macsec.h" +#include "rte_pmd_sxe.h" + +void sxe_macsec_enable(struct rte_eth_dev *dev, + struct sxe_macsec_context *macsec_ctxt) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct rte_eth_link link; + + u32 tx_mode =3D macsec_ctxt->encrypt_en ? SXE_LSECTXCTRL_AUTH_ENCRYPT : + SXE_LSECTXCTRL_AUTH; + u32 rx_mode =3D SXE_LSECRXCTRL_STRICT; + + rte_eth_linkstatus_get(dev, &link); + + sxe_hw_macsec_enable(hw, link.link_status, tx_mode, + rx_mode, SXE_LSECTXCTRL_PNTHRSH_MASK); + + PMD_LOG_INFO(INIT, "link status:%u tx mode:%u rx mode:%u " + " pn_thrsh:0x%x macsec enabled", + link.link_status, + tx_mode, rx_mode, + SXE_LSECTXCTRL_PNTHRSH_MASK); + +} + +static void sxe_macsec_disable(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_hw *hw =3D &adapter->hw; + struct rte_eth_link link; + + rte_eth_linkstatus_get(dev, &link); + + sxe_hw_macsec_disable(hw, link.link_status); + + PMD_LOG_INFO(INIT, "link status:%u macsec disabled ", link.link_status); + +} + +static void sxe_macsec_configure_save(struct rte_eth_dev *dev, + struct sxe_macsec_context *user_macsec) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_macsec_context *macsec_ctxt =3D &adapter->macsec_ctxt; + + macsec_ctxt->offload_en =3D user_macsec->offload_en; + macsec_ctxt->encrypt_en =3D user_macsec->encrypt_en; + macsec_ctxt->replayprotect_en =3D user_macsec->replayprotect_en; + +} + +static void sxe_macsec_configure_reset(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_macsec_context *macsec_ctxt =3D &adapter->macsec_ctxt; + + macsec_ctxt->offload_en =3D 0; + macsec_ctxt->encrypt_en =3D 0; + macsec_ctxt->replayprotect_en =3D 0; + +} + +s32 rte_pmd_sxe_macsec_enable(u16 port, u8 en, u8 rp_en) +{ + struct rte_eth_dev *dev; + struct sxe_macsec_context user_macsec; + s32 ret =3D 0; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + dev =3D &rte_eth_devices[port]; + + if (!is_sxe_supported(dev)) { + ret =3D -ENOTSUP; + PMD_LOG_ERR(INIT, "port:%u not support macsec.", port); + goto l_out; + } + + user_macsec.offload_en =3D true; + user_macsec.encrypt_en =3D en; + user_macsec.replayprotect_en =3D rp_en; + + sxe_macsec_configure_save(dev, &user_macsec); + sxe_macsec_enable(dev, &user_macsec); + +l_out: + return ret; +} + +s32 rte_pmd_sxe_macsec_disable(u16 port) +{ + struct rte_eth_dev *dev; + s32 ret =3D 0; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + dev =3D &rte_eth_devices[port]; + + if (!is_sxe_supported(dev)) { + ret =3D -ENOTSUP; + PMD_LOG_ERR(INIT, "port:%u not support macsec.", port); + goto l_out; + } + + sxe_macsec_configure_reset(dev); + sxe_macsec_disable(dev); + +l_out: + return ret; +} + +s32 rte_pmd_sxe_macsec_txsc_configure(u16 port, u8 *mac) +{ + struct rte_eth_dev *dev; + struct sxe_adapter *adapter; + s32 ret =3D 0; + u8 mac_addr[SXE_MAC_ADDR_LEN + 2]; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + dev =3D &rte_eth_devices[port]; + + if (!is_sxe_supported(dev)) { + ret =3D -ENOTSUP; + PMD_LOG_ERR(INIT, "port:%u not support macsec.", port); + goto l_out; + } + + rte_memcpy(mac_addr, mac, SXE_MAC_ADDR_LEN); + adapter =3D dev->data->dev_private; + sxe_hw_macsec_txsc_set(&adapter->hw, (*(u32 *)mac_addr), (*(u32 *)&mac_ad= dr[4])); + + PMD_LOG_INFO(DRV, "tx sc mac_addr:"MAC_FMT" configure done", + MAC_ADDR(mac_addr)); +l_out: + return ret; +} + +s32 rte_pmd_sxe_macsec_rxsc_configure(u16 port, u8 *mac, u16 pi) +{ + struct rte_eth_dev *dev; + struct sxe_adapter *adapter; + s32 ret =3D 0; + u8 mac_addr[SXE_MAC_ADDR_LEN + 2]; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + dev =3D &rte_eth_devices[port]; + + if (!is_sxe_supported(dev)) { + ret =3D -ENOTSUP; + PMD_LOG_ERR(INIT, "port:%u not support macsec.", port); + goto l_out; + } + + rte_memcpy(mac_addr, mac, SXE_MAC_ADDR_LEN); + adapter =3D dev->data->dev_private; + sxe_hw_macsec_rxsc_set(&adapter->hw, (*(u32 *)mac_addr), (*(u32 *)&mac_ad= dr[4]), pi); + + PMD_LOG_INFO(DRV, "rx sc mac_addr:"MAC_FMT" pi:%u configure done", + MAC_ADDR(mac_addr), pi); +l_out: + return ret; +} + +s32 rte_pmd_sxe_macsec_txsa_configure(u16 port, u8 sa_idx, u8 an, + u32 pn, u8 *keys) +{ + struct rte_eth_dev *dev; + struct sxe_adapter *adapter; + s32 ret =3D 0; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + dev =3D &rte_eth_devices[port]; + + if (!is_sxe_supported(dev)) { + ret =3D -ENOTSUP; + PMD_LOG_ERR(DRV, "port:%u not support macsec.(err:%d)", port, ret); + goto l_out; + } + + if (sa_idx >=3D SXE_LINKSEC_MAX_SA_COUNT) { + ret =3D -EINVAL; + PMD_LOG_ERR(DRV, "port:%u sa_idx:%u invalid.(err:%d)", + port, sa_idx, ret); + goto l_out; + } + + adapter =3D dev->data->dev_private; + sxe_hw_macsec_tx_sa_configure(&adapter->hw, sa_idx, an, rte_cpu_to_be_32(= pn), (u32 *)keys); + + PMD_LOG_INFO(DRV, "port:%u sa_idx:%u an:%u pn:0x%x keys:0x%x " + "tx sa configure done", + port, sa_idx, an, pn, *(u32 *)keys); + +l_out: + return ret; +} + +s32 rte_pmd_sxe_macsec_rxsa_configure(u16 port, u8 sa_idx, u8 an, + u32 pn, u8 *keys) +{ + struct rte_eth_dev *dev; + struct sxe_adapter *adapter; + s32 ret =3D 0; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); + + dev =3D &rte_eth_devices[port]; + + if (!is_sxe_supported(dev)) { + ret =3D -ENOTSUP; + PMD_LOG_ERR(DRV, "port:%u not support macsec.(err:%d)", port, ret); + goto l_out; + } + + if (sa_idx >=3D SXE_LINKSEC_MAX_SA_COUNT) { + ret =3D -EINVAL; + PMD_LOG_ERR(DRV, "port:%u sa_idx:%u invalid.(err:%d)", + port, sa_idx, ret); + goto l_out; + } + + adapter =3D dev->data->dev_private; + sxe_hw_macsec_rx_sa_configure(&adapter->hw, sa_idx, an, rte_cpu_to_be_32(= pn), (u32 *)keys); + + PMD_LOG_INFO(DRV, "port:%u sa_idx:%u an:%u pn:0x%x keys:0x%x " + "rx sa configure done", + port, sa_idx, an, pn, *(u32 *)keys); + +l_out: + return ret; +} + +#endif diff --git a/drivers/net/sxe/pf/sxe_macsec.h b/drivers/net/sxe/pf/sxe_macse= c.h new file mode 100644 index 0000000000..5497ad360d --- /dev/null +++ b/drivers/net/sxe/pf/sxe_macsec.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ + +#ifndef __SXE_DPDK_MACSEC_H__ +#define __SXE_DPDK_MACSEC_H__ + +#include "sxe_types.h" + +struct sxe_macsec_context { + u8 offload_en; + u8 encrypt_en; + u8 replayprotect_en; +}; + +void sxe_macsec_enable(struct rte_eth_dev *dev, + struct sxe_macsec_context *macsec_ctxt); + +#endif + diff --git a/drivers/net/sxe/pf/sxe_main.c b/drivers/net/sxe/pf/sxe_main.c index 3f30f26508..d25b1d9250 100644 --- a/drivers/net/sxe/pf/sxe_main.c +++ b/drivers/net/sxe/pf/sxe_main.c @@ -45,7 +45,7 @@ static const struct rte_pci_id sxe_pci_tbl[] =3D { =20 s8 g_log_filename[LOG_FILE_NAME_LEN] =3D {0}; =20 -bool is_log_created =3D false; +bool is_log_created; =20 #ifdef SXE_DPDK_DEBUG void sxe_log_stream_init(void) @@ -56,14 +56,13 @@ void sxe_log_stream_init(void) u8 len; s8 time[40]; =20 - if (is_log_created) { - goto l_out; - } + if (is_log_created) + return; =20 memset(g_log_filename, 0, LOG_FILE_NAME_LEN); =20 len =3D snprintf(g_log_filename, LOG_FILE_NAME_LEN, "%s%s.", - LOG_FILE_PATH, LOG_FILE_PREFIX); + LOG_FILE_PATH, LOG_FILE_PREFIX); =20 gettimeofday(&tv, NULL); td =3D localtime(&tv.tv_sec); @@ -75,8 +74,8 @@ void sxe_log_stream_init(void) fp =3D fopen(g_log_filename, "w+"); if (fp =3D=3D NULL) { PMD_LOG_ERR(INIT, "open log file:%s fail, errno:%d %s.", - g_log_filename, errno, strerror(errno)); - goto l_out; + g_log_filename, errno, strerror(errno)); + return; } =20 PMD_LOG_NOTICE(INIT, "log stream file:%s.", g_log_filename); @@ -85,8 +84,6 @@ void sxe_log_stream_init(void) =20 is_log_created =3D true; =20 -l_out: - return; } #endif =20 @@ -148,14 +145,14 @@ static s32 sxe_remove(struct rte_pci_device *pci_dev) return ret; } =20 -STATIC struct rte_pci_driver rte_sxe_pmd =3D { +static struct rte_pci_driver rte_sxe_pmd =3D { .id_table =3D sxe_pci_tbl, .drv_flags =3D RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, - .probe =3D sxe_probe, - .remove =3D sxe_remove, + .probe =3D sxe_probe, + .remove =3D sxe_remove, }; =20 -STATIC s32 sxe_mng_reset(struct sxe_hw *hw, bool enable) +static s32 sxe_mng_reset(struct sxe_hw *hw, bool enable) { s32 ret; sxe_mng_rst_s mng_rst; @@ -234,7 +231,6 @@ void sxe_hw_start(struct sxe_hw *hw) hw->mac.auto_restart =3D true; PMD_LOG_INFO(INIT, "auto_restart:%u.\n", hw->mac.auto_restart); =20 - return; } =20 static bool is_device_supported(struct rte_eth_dev *dev, @@ -242,9 +238,8 @@ static bool is_device_supported(struct rte_eth_dev *dev, { bool ret =3D true; =20 - if (strcmp(dev->device->driver->name, drv->driver.name)) { + if (strcmp(dev->device->driver->name, drv->driver.name)) ret =3D false; - } =20 return ret; } diff --git a/drivers/net/sxe/pf/sxe_offload.c b/drivers/net/sxe/pf/sxe_offl= oad.c index deea11451a..e47cf29330 100644 --- a/drivers/net/sxe/pf/sxe_offload.c +++ b/drivers/net/sxe/pf/sxe_offload.c @@ -15,7 +15,7 @@ #include "sxe_queue_common.h" #include "sxe_offload_common.h" =20 -STATIC u8 rss_sxe_key[40] =3D { +static u8 rss_sxe_key[40] =3D { 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2, 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0, 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4, @@ -29,7 +29,7 @@ STATIC u8 rss_sxe_key[40] =3D { #define SXE_8_BIT_MASK UINT8_MAX =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL -u8* sxe_rss_hash_key_get(void) +u8 *sxe_rss_hash_key_get(void) { return rss_sxe_key; } @@ -65,7 +65,6 @@ void sxe_rss_disable(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); =20 sxe_hw_rss_cap_switch(hw, false); - return; } =20 void sxe_rss_hash_set(struct sxe_hw *hw, @@ -91,34 +90,28 @@ void sxe_rss_hash_set(struct sxe_hw *hw, } =20 rss_hf =3D rss_conf->rss_hf; - if (rss_hf & RTE_ETH_RSS_IPV4) { + if (rss_hf & RTE_ETH_RSS_IPV4) rss_field |=3D SXE_MRQC_RSS_FIELD_IPV4; - } =20 - if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) { + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) rss_field |=3D SXE_MRQC_RSS_FIELD_IPV4_TCP; - } =20 - if (rss_hf & RTE_ETH_RSS_IPV6) { + if (rss_hf & RTE_ETH_RSS_IPV6) rss_field |=3D SXE_MRQC_RSS_FIELD_IPV6; - } =20 - if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) { + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) rss_field |=3D SXE_MRQC_RSS_FIELD_IPV6_TCP; - } =20 - if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) { + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) rss_field |=3D SXE_MRQC_RSS_FIELD_IPV4_UDP; - } =20 - if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) { + if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) rss_field |=3D SXE_MRQC_RSS_FIELD_IPV6_UDP; - } + sxe_hw_rss_field_set(hw, rss_field); =20 sxe_hw_rss_cap_switch(hw, true); =20 - return; } =20 void sxe_rss_configure(struct rte_eth_dev *dev) @@ -128,15 +121,14 @@ void sxe_rss_configure(struct rte_eth_dev *dev) struct sxe_hw *hw =3D &adapter->hw; u16 i; u16 j; - u8 rss_indir_tbl[SXE_MAX_RETA_ENTRIES];=20=20=20=20 + u8 rss_indir_tbl[SXE_MAX_RETA_ENTRIES]; =20 PMD_INIT_FUNC_TRACE(); =20 if (adapter->rss_reta_updated =3D=3D false) { for (i =3D 0, j =3D 0; i < SXE_MAX_RETA_ENTRIES; i++, j++) { - if (j =3D=3D dev->data->nb_rx_queues) { + if (j =3D=3D dev->data->nb_rx_queues) j =3D 0; - } =20 rss_indir_tbl[i] =3D j; } @@ -148,17 +140,14 @@ void sxe_rss_configure(struct rte_eth_dev *dev) if ((rss_conf->rss_hf & SXE_RSS_OFFLOAD_ALL) =3D=3D 0) { PMD_LOG_INFO(INIT, "user rss config match hw supports is 0"); sxe_rss_disable(dev); - goto l_end; + return; } =20 - if (rss_conf->rss_key =3D=3D NULL) { - rss_conf->rss_key =3D rss_sxe_key;=20 - } + if (rss_conf->rss_key =3D=3D NULL) + rss_conf->rss_key =3D rss_sxe_key; =20 sxe_rss_hash_set(hw, rss_conf); =20 -l_end: - return; } =20 s32 sxe_rss_reta_update(struct rte_eth_dev *dev, @@ -197,15 +186,13 @@ s32 sxe_rss_reta_update(struct rte_eth_dev *dev, shift =3D i % RTE_ETH_RETA_GROUP_SIZE; mask =3D (u8)((reta_conf[idx].mask >> shift) & SXE_4_BIT_MASK); - if (!mask) { + if (!mask) continue; - } =20 - if (mask =3D=3D SXE_4_BIT_MASK) { + if (mask =3D=3D SXE_4_BIT_MASK) r =3D 0; - } else { + else r =3D sxe_hw_rss_redir_tbl_get_by_idx(hw, i); - } =20 for (j =3D 0, reta =3D 0; j < SXE_4_BIT_WIDTH; j++) { if (mask & (0x1 << j)) { @@ -251,9 +238,8 @@ s32 sxe_rss_reta_query(struct rte_eth_dev *dev, shift =3D i % RTE_ETH_RETA_GROUP_SIZE; mask =3D (u8)((reta_conf[idx].mask >> shift) & SXE_4_BIT_MASK); - if (!mask) { + if (!mask) continue; - } =20 reta =3D sxe_hw_rss_redir_tbl_get_by_idx(hw, i); for (j =3D 0; j < SXE_4_BIT_WIDTH; j++) { @@ -280,7 +266,7 @@ s32 sxe_rss_hash_update(struct rte_eth_dev *dev, rss_hf =3D (rss_conf->rss_hf & SXE_RSS_OFFLOAD_ALL); =20 if (!sxe_hw_is_rss_enabled(hw)) { - if (rss_hf !=3D 0){ + if (rss_hf !=3D 0) { PMD_LOG_ERR(DRV, "rss not init but want set"); ret =3D -EINVAL; goto l_end; @@ -289,7 +275,7 @@ s32 sxe_rss_hash_update(struct rte_eth_dev *dev, goto l_end; } =20 - if (rss_hf =3D=3D 0){ + if (rss_hf =3D=3D 0) { PMD_LOG_ERR(DRV, "rss init but want disable it"); ret =3D -EINVAL; goto l_end; @@ -302,7 +288,7 @@ s32 sxe_rss_hash_update(struct rte_eth_dev *dev, } =20 s32 sxe_rss_hash_conf_get(struct rte_eth_dev *dev, - struct rte_eth_rss_conf *rss_conf) + struct rte_eth_rss_conf *rss_conf) { struct sxe_adapter *adapter =3D dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; @@ -332,29 +318,23 @@ s32 sxe_rss_hash_conf_get(struct rte_eth_dev *dev, =20 rss_hf =3D 0; rss_field =3D sxe_hw_rss_field_get(hw); - if (rss_field & SXE_MRQC_RSS_FIELD_IPV4) { + if (rss_field & SXE_MRQC_RSS_FIELD_IPV4) rss_hf |=3D RTE_ETH_RSS_IPV4; - } =20 - if (rss_field & SXE_MRQC_RSS_FIELD_IPV4_TCP) { + if (rss_field & SXE_MRQC_RSS_FIELD_IPV4_TCP) rss_hf |=3D RTE_ETH_RSS_NONFRAG_IPV4_TCP; - } =20 - if (rss_field & SXE_MRQC_RSS_FIELD_IPV4_UDP) { + if (rss_field & SXE_MRQC_RSS_FIELD_IPV4_UDP) rss_hf |=3D RTE_ETH_RSS_NONFRAG_IPV4_UDP; - } =20 - if (rss_field & SXE_MRQC_RSS_FIELD_IPV6) { + if (rss_field & SXE_MRQC_RSS_FIELD_IPV6) rss_hf |=3D RTE_ETH_RSS_IPV6; - } =20 - if (rss_field & SXE_MRQC_RSS_FIELD_IPV6_TCP) { + if (rss_field & SXE_MRQC_RSS_FIELD_IPV6_TCP) rss_hf |=3D RTE_ETH_RSS_NONFRAG_IPV6_TCP; - } =20 - if (rss_field & SXE_MRQC_RSS_FIELD_IPV6_UDP) { + if (rss_field & SXE_MRQC_RSS_FIELD_IPV6_UDP) rss_hf |=3D RTE_ETH_RSS_NONFRAG_IPV6_UDP; - } =20 PMD_LOG_DEBUG(DRV, "got rss hash func=3D0x%"SXE_PRIX64, rss_hf); rss_conf->rss_hf =3D rss_hf; diff --git a/drivers/net/sxe/pf/sxe_offload.h b/drivers/net/sxe/pf/sxe_offl= oad.h index d1f651feb6..458b6464c5 100644 --- a/drivers/net/sxe/pf/sxe_offload.h +++ b/drivers/net/sxe/pf/sxe_offload.h @@ -16,7 +16,7 @@ RTE_ETH_RSS_NONFRAG_IPV6_UDP) =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_FILTER_CTRL -u8* sxe_rss_hash_key_get(void); +u8 *sxe_rss_hash_key_get(void); #endif =20 void sxe_rss_hash_set(struct sxe_hw *hw, @@ -46,6 +46,6 @@ s32 sxe_rss_hash_update(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_conf); =20 s32 sxe_rss_hash_conf_get(struct rte_eth_dev *dev, - struct rte_eth_rss_conf *rss_conf); + struct rte_eth_rss_conf *rss_conf); =20 #endif diff --git a/drivers/net/sxe/pf/sxe_phy.c b/drivers/net/sxe/pf/sxe_phy.c index 595bbcbc25..fade4bbf90 100644 --- a/drivers/net/sxe/pf/sxe_phy.c +++ b/drivers/net/sxe/pf/sxe_phy.c @@ -30,16 +30,16 @@ #include "sxe_compat_version.h" =20 #define SXE_WAIT_LINK_UP_FAILED 1 -#define SXE_WARNING_TIMEOUT 9000=20 -#define SXE_CHG_SFP_RATE_MS 40=20=20=20 -#define SXE_1G_WAIT_PCS_MS 100=20=20 -#define SXE_10G_WAIT_PCS_MS 100=20=20 -#define SXE_HZ_TRANSTO_MS 1000 -#define SXE_AN_COMPLETE_TIME 5=20=20=20=20 -#define SXE_10G_WAIT_13_TIME 13=20=20=20 -#define SXE_10G_WAIT_5_TIME 5=20=20=20=20 - -STATIC void *sxe_setup_link_thread_handler(void *param) +#define SXE_WARNING_TIMEOUT 9000 +#define SXE_CHG_SFP_RATE_MS 40 +#define SXE_1G_WAIT_PCS_MS 100 +#define SXE_10G_WAIT_PCS_MS 100 +#define SXE_HZ_TRANSTO_MS 1000 +#define SXE_AN_COMPLETE_TIME 5 +#define SXE_10G_WAIT_13_TIME 13 +#define SXE_10G_WAIT_5_TIME 5 + +static void *sxe_setup_link_thread_handler(void *param) { s32 ret; struct rte_eth_dev *dev =3D (struct rte_eth_dev *)param; @@ -59,14 +59,13 @@ STATIC void *sxe_setup_link_thread_handler(void *param) speed =3D (conf_speeds & allowed_speeds) ? (conf_speeds & allowed_speeds)= : allowed_speeds; =20 - if (adapter->phy_ctxt.sfp_info.multispeed_fiber) { + if (adapter->phy_ctxt.sfp_info.multispeed_fiber) ret =3D sxe_multispeed_sfp_link_configure(dev, speed, true); - } else { + else ret =3D sxe_sfp_link_configure(dev); - } - if (ret) { + + if (ret) PMD_LOG_ERR(INIT, "link setup failed, ret=3D%d", ret); - } =20 irq->action &=3D ~SXE_IRQ_LINK_CONFIG; rte_atomic32_clear(&adapter->link_thread_running); @@ -84,17 +83,15 @@ void sxe_wait_setup_link_complete(struct rte_eth_dev *d= ev, timeout--; =20 if (timeout_ms) { - if (!timeout) { - goto l_end; - } + if (!timeout) + return; + } else if (!timeout) { timeout =3D SXE_WARNING_TIMEOUT; PMD_LOG_ERR(INIT, "link thread not complete too long time!"); } } =20 -l_end: - return; } =20 static s32 sxe_an_cap_get(struct sxe_adapter *adapter, sxe_an_cap_s *an_ca= p) @@ -105,9 +102,8 @@ static s32 sxe_an_cap_get(struct sxe_adapter *adapter, = sxe_an_cap_s *an_cap) ret =3D sxe_driver_cmd_trans(hw, SXE_CMD_AN_CAP_GET, NULL, 0, (void *)an_cap, sizeof(*an_cap)); - if (ret) { + if (ret) PMD_LOG_ERR(INIT, "hdc trans failed ret=3D%d, cmd:negotiaton cap get", r= et); - } =20 return ret; } @@ -136,9 +132,8 @@ s32 sxe_link_update(struct rte_eth_dev *dev, int wait_t= o_complete) goto l_end; } =20 - if (dev->data->dev_conf.intr_conf.lsc) { + if (dev->data->dev_conf.intr_conf.lsc) wait_to_complete =3D 0; - } =20 sxe_link_info_get(adapter, &link_speed, &orig_link_up); sxe_link_info_get(adapter, &link_speed, &link_up); @@ -151,9 +146,8 @@ s32 sxe_link_update(struct rte_eth_dev *dev, int wait_t= o_complete) =20 if (wait_to_complete) { for (i =3D 0; i < SXE_LINK_UP_TIME; i++) { - if (link_up =3D=3D true) { + if (link_up =3D=3D true) break; - } =20 rte_delay_us_sleep(100000); =20 @@ -199,9 +193,8 @@ s32 sxe_link_update(struct rte_eth_dev *dev, int wait_t= o_complete) } else { for (i =3D 0; i < SXE_AN_COMPLETE_TIME; i++) { sxe_an_cap_get(adapter, &an_cap); - if (an_cap.peer.remote_fault !=3D SXE_REMOTE_UNKNOWN) { + if (an_cap.peer.remote_fault !=3D SXE_REMOTE_UNKNOWN) break; - } rte_delay_us_sleep(100000); } } @@ -252,9 +245,9 @@ s32 sxe_link_status_update(struct rte_eth_dev *dev) link.link_speed =3D RTE_ETH_SPEED_NUM_1G; for (i =3D 0; i < SXE_AN_COMPLETE_TIME; i++) { sxe_an_cap_get(adapter, &an_cap); - if (an_cap.peer.remote_fault !=3D SXE_REMOTE_UNKNOWN) { + if (an_cap.peer.remote_fault !=3D SXE_REMOTE_UNKNOWN) break; - } + rte_delay_us_sleep(100000); } break; @@ -306,7 +299,7 @@ int sxe_dev_set_link_down(struct rte_eth_dev *dev) } =20 =20 -STATIC s32 sxe_sfp_eeprom_read(struct sxe_adapter *adapter, u16 offset, +static s32 sxe_sfp_eeprom_read(struct sxe_adapter *adapter, u16 offset, u16 len, u8 *data) { s32 ret; @@ -392,21 +385,19 @@ void sxe_sfp_tx_laser_enable(struct sxe_adapter *adap= ter) { sxe_sfp_tx_laser_ctrl(adapter, false); =20 - return; } =20 void sxe_sfp_tx_laser_disable(struct sxe_adapter *adapter) { sxe_sfp_tx_laser_ctrl(adapter, true); =20 - return; } =20 s32 sxe_sfp_reset(struct sxe_adapter *adapter) { PMD_LOG_INFO(INIT, "auto_restart:%u.\n", adapter->hw.mac.auto_restart); =20 - if(adapter->hw.mac.auto_restart) { + if (adapter->hw.mac.auto_restart) { sxe_sfp_tx_laser_disable(adapter); sxe_sfp_tx_laser_enable(adapter); adapter->hw.mac.auto_restart =3D false; @@ -423,7 +414,7 @@ void sxe_sfp_link_capabilities_get(struct sxe_adapter *= adapter, u32 *speed, *speed =3D 0; =20 if (sfp->type =3D=3D SXE_SFP_TYPE_1G_CU || - sfp->type =3D=3D SXE_SFP_TYPE_1G_SXLX ) { + sfp->type =3D=3D SXE_SFP_TYPE_1G_SXLX) { *speed =3D SXE_LINK_SPEED_1GB_FULL; *autoneg =3D true; goto l_end; @@ -439,7 +430,6 @@ void sxe_sfp_link_capabilities_get(struct sxe_adapter *= adapter, u32 *speed, =20 l_end: PMD_LOG_INFO(INIT, "sfp link speed cap=3D%d", *speed); - return; } =20 s32 sxe_sfp_rate_select(struct sxe_adapter *adapter, sxe_sfp_rate_e rate) @@ -453,22 +443,29 @@ s32 sxe_sfp_rate_select(struct sxe_adapter *adapter, = sxe_sfp_rate_e rate) ret =3D sxe_driver_cmd_trans(hw, SXE_CMD_RATE_SELECT, &rate_able, sizeof(rate_able), NULL, 0); - if (ret) { + if (ret) PMD_LOG_ERR(INIT, "sfp rate select failed, ret=3D%d", ret); - } =20 PMD_LOG_INFO(INIT, "sfp tx rate select end, rate=3D%d", rate); =20 return ret; } =20 -s32 sxe_pcs_sds_init(struct sxe_adapter *adapter, +s32 sxe_pcs_sds_init(struct rte_eth_dev *dev, sxe_pcs_mode_e mode, u32 max_frame) { s32 ret; + bool keep_crc =3D false; sxe_pcs_cfg_s pcs_cfg; + struct sxe_adapter *adapter =3D dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; struct sxe_irq_context *irq =3D &adapter->irq_ctxt; + struct rte_eth_rxmode *rx_conf =3D &dev->data->dev_conf.rxmode; + + if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) { + keep_crc =3D true; + } + sxe_hw_crc_strip_config(hw, keep_crc); =20 pcs_cfg.mode =3D mode; pcs_cfg.mtu =3D max_frame; @@ -486,7 +483,7 @@ s32 sxe_pcs_sds_init(struct sxe_adapter *adapter, sxe_fc_mac_addr_set(adapter); =20 LOG_INFO_BDF("mode:%u max_frame:0x%x pcs sds init done.\n", - mode, max_frame); + mode, max_frame); l_end: return ret; } @@ -510,15 +507,14 @@ s32 sxe_conf_speed_get(struct rte_eth_dev *dev, u32 *= conf_speeds) =20 *conf_speeds =3D SXE_LINK_SPEED_UNKNOWN; if (*link_speeds =3D=3D RTE_ETH_LINK_SPEED_AUTONEG) { - *conf_speeds =3D SXE_LINK_SPEED_1GB_FULL | \ + *conf_speeds =3D SXE_LINK_SPEED_1GB_FULL | SXE_LINK_SPEED_10GB_FULL; } else { - if (*link_speeds & RTE_ETH_LINK_SPEED_10G) { + if (*link_speeds & RTE_ETH_LINK_SPEED_10G) *conf_speeds |=3D SXE_LINK_SPEED_10GB_FULL; - } - if (*link_speeds & RTE_ETH_LINK_SPEED_1G) { + + if (*link_speeds & RTE_ETH_LINK_SPEED_1G) *conf_speeds |=3D SXE_LINK_SPEED_1GB_FULL; - } } =20 l_end: @@ -556,11 +552,10 @@ s32 sxe_multispeed_sfp_link_configure(struct rte_eth_= dev *dev, u32 speed, bool i =20 rte_delay_us_sleep((SXE_CHG_SFP_RATE_MS * SXE_HZ_TRANSTO_MS)); =20 - ret =3D sxe_pcs_sds_init(adapter, SXE_PCS_MODE_10GBASE_KR_WO, + ret =3D sxe_pcs_sds_init(dev, SXE_PCS_MODE_10GBASE_KR_WO, frame_size); - if (ret) { + if (ret) goto l_end; - } =20 =20 for (i =3D 0; i < wait_time; i++) { @@ -581,9 +576,8 @@ s32 sxe_multispeed_sfp_link_configure(struct rte_eth_de= v *dev, u32 speed, bool i irq->to_pcs_init =3D true; =20 speedcnt++; - if (highest_link_speed =3D=3D SXE_LINK_SPEED_UNKNOWN) { + if (highest_link_speed =3D=3D SXE_LINK_SPEED_UNKNOWN) highest_link_speed =3D SXE_LINK_SPEED_1GB_FULL; - } =20 ret =3D sxe_sfp_rate_select(adapter, SXE_SFP_RATE_1G); if (ret) { @@ -593,11 +587,10 @@ s32 sxe_multispeed_sfp_link_configure(struct rte_eth_= dev *dev, u32 speed, bool i =20 rte_delay_us_sleep((SXE_CHG_SFP_RATE_MS * SXE_HZ_TRANSTO_MS)); =20 - ret =3D sxe_pcs_sds_init(adapter, SXE_PCS_MODE_1000BASE_KX_W, + ret =3D sxe_pcs_sds_init(dev, SXE_PCS_MODE_1000BASE_KX_W, frame_size); - if (ret) { + if (ret) goto l_end; - } =20 =20 rte_delay_us_sleep(SXE_1G_WAIT_PCS_MS * SXE_HZ_TRANSTO_MS); @@ -613,20 +606,18 @@ s32 sxe_multispeed_sfp_link_configure(struct rte_eth_= dev *dev, u32 speed, bool i PMD_LOG_WARN(INIT, "1G link cfg failed, retry..."); } =20 - if (speedcnt > 1) { + if (speedcnt > 1) ret =3D sxe_multispeed_sfp_link_configure(dev, highest_link_speed, is_in= _thread); - } + l_out: =20 adapter->phy_ctxt.autoneg_advertised =3D 0; =20 - if (speed & SXE_LINK_SPEED_10GB_FULL) { + if (speed & SXE_LINK_SPEED_10GB_FULL) adapter->phy_ctxt.autoneg_advertised |=3D SXE_LINK_SPEED_10GB_FULL; - } =20 - if (speed & SXE_LINK_SPEED_1GB_FULL) { + if (speed & SXE_LINK_SPEED_1GB_FULL) adapter->phy_ctxt.autoneg_advertised |=3D SXE_LINK_SPEED_1GB_FULL; - } =20 l_end: return ret; @@ -645,7 +636,6 @@ void sxe_link_info_get(struct sxe_adapter *adapter, u32= *link_speed, bool *link_ *link_speed =3D sxe_hw_link_speed_get(hw); } =20 - return; } =20 static s32 sxe_sfp_fc_autoneg(struct sxe_adapter *adapter) @@ -704,18 +694,17 @@ static void sxe_fc_autoneg(struct sxe_adapter *adapte= r) goto l_end; } =20 - if(link_speed !=3D SXE_LINK_SPEED_1GB_FULL){ - PMD_LOG_INFO(INIT, "link speed=3D%x, (0x80=3D10G, 0x20=3D1G), dont fc au= toneg", link_speed); + if (link_speed !=3D SXE_LINK_SPEED_1GB_FULL) { + PMD_LOG_INFO(INIT, "link speed=3D%x, (0x80=3D10G, 0x20=3D1G), " + "dont fc autoneg", link_speed); goto l_end; } =20 ret =3D sxe_sfp_fc_autoneg(adapter); l_end: - if(ret) { + if (ret) hw->fc.current_mode =3D hw->fc.requested_mode; - } =20 - return; } =20 s32 sxe_fc_enable(struct sxe_adapter *adapter) @@ -732,9 +721,9 @@ s32 sxe_fc_enable(struct sxe_adapter *adapter) =20 for (i =3D 0; i < MAX_TRAFFIC_CLASS; i++) { if ((hw->fc.current_mode & SXE_FC_TX_PAUSE) && - hw->fc.high_water[i]) { + hw->fc.high_water[i]) { if (!hw->fc.low_water[i] || - hw->fc.low_water[i] >=3D hw->fc.high_water[i]) { + hw->fc.low_water[i] >=3D hw->fc.high_water[i]) { PMD_LOG_DEBUG(INIT, "invalid water mark configuration, " "tc[%u] low_water=3D%u, high_water=3D%u", i, hw->fc.low_water[i], @@ -751,9 +740,8 @@ s32 sxe_fc_enable(struct sxe_adapter *adapter) sxe_fc_autoneg(adapter); =20 ret =3D sxe_hw_fc_enable(hw); - if (ret) { + if (ret) PMD_LOG_ERR(INIT, "link fc enable failed, ret=3D%d", ret); - } =20 l_end: return ret; @@ -787,9 +775,8 @@ s32 sxe_pfc_enable(struct sxe_adapter *adapter, u8 tc_i= dx) sxe_fc_autoneg(adapter); =20 ret =3D sxe_hw_pfc_enable(hw, tc_idx); - if (ret) { + if (ret) PMD_LOG_ERR(INIT, "link fc enable failed, ret=3D%d", ret); - } =20 l_ret: return ret; @@ -828,15 +815,15 @@ s32 sxe_sfp_identify(struct sxe_adapter *adapter) =20 if (sfp_comp_code[SXE_SFF_CABLE_TECHNOLOGY] & SXE_SFF_DA_PASSIVE_CABLE) { sfp_type =3D SXE_SFP_TYPE_DA_CU; - } else if (sfp_comp_code[SXE_SFF_10GBE_COMP_CODES] & \ + } else if (sfp_comp_code[SXE_SFF_10GBE_COMP_CODES] & (SXE_SFF_10GBASESR_CAPABLE | SXE_SFF_10GBASELR_CAPABLE)) { sfp_type =3D SXE_SFP_TYPE_SRLR; - } else if (sfp_comp_code[SXE_SFF_1GBE_COMP_CODES] & \ + } else if (sfp_comp_code[SXE_SFF_1GBE_COMP_CODES] & SXE_SFF_1GBASET_CAPABLE) { sfp_type =3D SXE_SFP_TYPE_1G_CU; - } else if ((sfp_comp_code[SXE_SFF_1GBE_COMP_CODES] & \ - SXE_SFF_1GBASESX_CAPABLE) || \ - (sfp_comp_code[SXE_SFF_1GBE_COMP_CODES] & \ + } else if ((sfp_comp_code[SXE_SFF_1GBE_COMP_CODES] & + SXE_SFF_1GBASESX_CAPABLE) || + (sfp_comp_code[SXE_SFF_1GBE_COMP_CODES] & SXE_SFF_1GBASELX_CAPABLE)) { sfp_type =3D SXE_SFP_TYPE_1G_SXLX; } else { @@ -844,13 +831,13 @@ s32 sxe_sfp_identify(struct sxe_adapter *adapter) } =20 sfp->multispeed_fiber =3D false; - if (((sfp_comp_code[SXE_SFF_1GBE_COMP_CODES] & \ + if (((sfp_comp_code[SXE_SFF_1GBE_COMP_CODES] & SXE_SFF_1GBASESX_CAPABLE) && - (sfp_comp_code[SXE_SFF_10GBE_COMP_CODES] & \ + (sfp_comp_code[SXE_SFF_10GBE_COMP_CODES] & SXE_SFF_10GBASESR_CAPABLE)) || - ((sfp_comp_code[SXE_SFF_1GBE_COMP_CODES] & \ + ((sfp_comp_code[SXE_SFF_1GBE_COMP_CODES] & SXE_SFF_1GBASELX_CAPABLE) && - (sfp_comp_code[SXE_SFF_10GBE_COMP_CODES] & \ + (sfp_comp_code[SXE_SFF_10GBE_COMP_CODES] & SXE_SFF_10GBASELR_CAPABLE))) { sfp->multispeed_fiber =3D true; } @@ -874,22 +861,20 @@ s32 sxe_sfp_link_configure(struct rte_eth_dev *dev) =20 sxe_sfp_link_capabilities_get(adapter, &speed, &an); =20 - if (SXE_LINK_SPEED_1GB_FULL =3D=3D speed) { + if (speed =3D=3D SXE_LINK_SPEED_1GB_FULL) { pcs_mode =3D SXE_PCS_MODE_1000BASE_KX_W; adapter->phy_ctxt.autoneg_advertised =3D SXE_LINK_SPEED_1GB_FULL; - } else if (SXE_LINK_SPEED_10GB_FULL =3D=3D speed) { + } else if (speed =3D=3D SXE_LINK_SPEED_10GB_FULL) { pcs_mode =3D SXE_PCS_MODE_10GBASE_KR_WO; adapter->phy_ctxt.autoneg_advertised =3D SXE_LINK_SPEED_10GB_FULL; } =20 - ret =3D sxe_pcs_sds_init(adapter, pcs_mode, frame_size); - if (ret) { + ret =3D sxe_pcs_sds_init(dev, pcs_mode, frame_size); + if (ret) PMD_LOG_ERR(INIT, "pcs sds init failed, ret=3D%d", ret); - } =20 - if (SXE_LINK_SPEED_1GB_FULL =3D=3D speed) { + if (speed =3D=3D SXE_LINK_SPEED_1GB_FULL) sxe_link_status_update(dev); - } =20 PMD_LOG_INFO(INIT, "link :cfg speed=3D%x, pcs_mode=3D%x, atuoreg=3D%d", speed, pcs_mode, an); @@ -926,7 +911,7 @@ int sxe_get_module_info(struct rte_eth_dev *dev, page_swap =3D true; } =20 - if ((sff8472_rev =3D=3D SXE_SFF_8472_UNSUP) || page_swap || \ + if ((sff8472_rev =3D=3D SXE_SFF_8472_UNSUP) || page_swap || !(addr_mode & SXE_SFF_DDM_IMPLEMENTED)) { info->type =3D RTE_ETH_MODULE_SFF_8079; info->eeprom_len =3D RTE_ETH_MODULE_SFF_8079_LEN; @@ -980,11 +965,10 @@ s32 sxe_phy_init(struct sxe_adapter *adapter) s32 ret =3D 0; enum sxe_media_type media_type =3D sxe_media_type_get(adapter); =20 - if (SXE_MEDIA_TYPE_FIBER =3D=3D media_type) { + if (media_type =3D=3D SXE_MEDIA_TYPE_FIBER) { ret =3D sxe_sfp_identify(adapter); - if (ret) { + if (ret) PMD_LOG_ERR(INIT, "phy identify failed, ret=3D%d", ret); - } } else { PMD_LOG_ERR(INIT, "phy init failed, only support SFP."); } diff --git a/drivers/net/sxe/pf/sxe_phy.h b/drivers/net/sxe/pf/sxe_phy.h index b0ec2388b9..3d4328be31 100644 --- a/drivers/net/sxe/pf/sxe_phy.h +++ b/drivers/net/sxe/pf/sxe_phy.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright (C), 2022, Linkdata Technology Co., Ltd. */ -#ifndef __SXE_PHY_H__ -#define __SXE_PHY_H__ +#ifndef __SXE_PHY_H__ +#define __SXE_PHY_H__ =20 #include #include "drv_msg.h" @@ -10,17 +10,17 @@ #include "sxe_msg.h" =20 #define SXE_SFF_BASE_ADDR 0x0 -#define SXE_SFF_IDENTIFIER 0x0=20=20 -#define SXE_SFF_10GBE_COMP_CODES 0x3=20=20 -#define SXE_SFF_1GBE_COMP_CODES 0x6=20=20 -#define SXE_SFF_CABLE_TECHNOLOGY 0x8=20=20 -#define SXE_SFF_8472_DIAG_MONITOR_TYPE 0x5C=20 -#define SXE_SFF_8472_COMPLIANCE 0x5E=20 +#define SXE_SFF_IDENTIFIER 0x0 +#define SXE_SFF_10GBE_COMP_CODES 0x3 +#define SXE_SFF_1GBE_COMP_CODES 0x6 +#define SXE_SFF_CABLE_TECHNOLOGY 0x8 +#define SXE_SFF_8472_DIAG_MONITOR_TYPE 0x5C +#define SXE_SFF_8472_COMPLIANCE 0x5E =20 #define SXE_SFF_IDENTIFIER_SFP 0x3 -#define SXE_SFF_ADDRESSING_MODE 0x4=20=20 +#define SXE_SFF_ADDRESSING_MODE 0x4 #define SXE_SFF_8472_UNSUP 0x0 -#define SXE_SFF_DDM_IMPLEMENTED 0x40=20 +#define SXE_SFF_DDM_IMPLEMENTED 0x40 #define SXE_SFF_DA_PASSIVE_CABLE 0x4 #define SXE_SFF_DA_ACTIVE_CABLE 0x8 #define SXE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4 @@ -30,16 +30,16 @@ #define SXE_SFF_10GBASESR_CAPABLE 0x10 #define SXE_SFF_10GBASELR_CAPABLE 0x20 =20 -#define SXE_SFP_COMP_CODE_SIZE 10=20=20 -#define SXE_SFP_EEPROM_SIZE_MAX 512=20 +#define SXE_SFP_COMP_CODE_SIZE 10 +#define SXE_SFP_EEPROM_SIZE_MAX 512 =20 -#define SXE_IRQ_LINK_UPDATE (u32)(1 << 0) -#define SXE_IRQ_LINK_CONFIG (u32)(1 << 3) +#define SXE_IRQ_LINK_UPDATE (u32)(1 << 0) +#define SXE_IRQ_LINK_CONFIG (u32)(1 << 3) struct sxe_adapter; =20 enum sxe_media_type { SXE_MEDIA_TYPE_UNKWON =3D 0, - SXE_MEDIA_TYPE_FIBER =3D 1,=20 + SXE_MEDIA_TYPE_FIBER =3D 1, }; =20 enum sxe_phy_idx { @@ -48,24 +48,24 @@ enum sxe_phy_idx { }; =20 enum sxe_sfp_type { - SXE_SFP_TYPE_DA_CU =3D 0,=20 - SXE_SFP_TYPE_SRLR =3D 1,=20 - SXE_SFP_TYPE_1G_CU =3D 2,=20 - SXE_SFP_TYPE_1G_SXLX =3D 4,=20 - SXE_SFP_TYPE_UNKNOWN =3D 0xFFFF , + SXE_SFP_TYPE_DA_CU =3D 0, + SXE_SFP_TYPE_SRLR =3D 1, + SXE_SFP_TYPE_1G_CU =3D 2, + SXE_SFP_TYPE_1G_SXLX =3D 4, + SXE_SFP_TYPE_UNKNOWN =3D 0xFFFF, }; =20 struct sxe_sfp_info { enum sxe_sfp_type type; - bool multispeed_fiber;=20 + bool multispeed_fiber; }; =20 struct sxe_phy_context { - bool is_sfp;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - bool sfp_tx_laser_disabled;=20=20=20 - u32 speed;=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 - u32 autoneg_advertised;=20=20=20=20=20=20 - struct sxe_sfp_info sfp_info;=20 + bool is_sfp; + bool sfp_tx_laser_disabled; + u32 speed; + u32 autoneg_advertised; + struct sxe_sfp_info sfp_info; }; =20 s32 sxe_phy_init(struct sxe_adapter *adapter); @@ -93,7 +93,7 @@ int sxe_get_module_eeprom(struct rte_eth_dev *dev, s32 sxe_sfp_identify(struct sxe_adapter *adapter); s32 sxe_sfp_reset(struct sxe_adapter *adapter); =20 -s32 sxe_pcs_sds_init(struct sxe_adapter *adapter,=20 +s32 sxe_pcs_sds_init(struct rte_eth_dev *dev, sxe_pcs_mode_e mode, u32 max_frame); =20 s32 sxe_sfp_rate_select(struct sxe_adapter *adapter, sxe_sfp_rate_e rate); @@ -115,7 +115,4 @@ s32 sxe_sfp_link_configure(struct rte_eth_dev *dev); =20 void sxe_mac_configure(struct sxe_adapter *adapter); =20 -s32 sxe_pcs_sds_init(struct sxe_adapter *adapter, sxe_pcs_mode_e mode, - u32 max_frame); - #endif diff --git a/drivers/net/sxe/pf/sxe_pmd_hdc.c b/drivers/net/sxe/pf/sxe_pmd_= hdc.c index 9137776a01..39fc782b2d 100644 --- a/drivers/net/sxe/pf/sxe_pmd_hdc.c +++ b/drivers/net/sxe/pf/sxe_pmd_hdc.c @@ -42,13 +42,11 @@ void sxe_hdc_channel_init(void) { s32 ret; ret =3D sem_init(sxe_hdc_sema_get(), 0, 1); - if (ret) { - PMD_LOG_ERR(INIT, "hdc sem init failed=EF=BC=8Cret=3D%d",ret); - } + if (ret) + PMD_LOG_ERR(INIT, "hdc sem init failed=EF=BC=8Cret=3D%d", ret); =20 sxe_trace_id_gen(); =20 - return; } =20 void sxe_hdc_channel_uninit(void) @@ -56,7 +54,6 @@ void sxe_hdc_channel_uninit(void) sem_destroy(sxe_hdc_sema_get()); sxe_trace_id_clean(); =20 - return; } =20 static s32 sxe_fw_time_sync_process(struct sxe_hw *hw) @@ -69,9 +66,8 @@ static s32 sxe_fw_time_sync_process(struct sxe_hw *hw) ret =3D sxe_driver_cmd_trans(hw, SXE_CMD_TINE_SYNC, (void *)×tamp, sizeof(timestamp), NULL, 0); - if (ret) { - LOG_ERROR_BDF("hdc trans failed ret=3D%d, cmd:time sync\n",ret); - } + if (ret) + LOG_ERROR_BDF("hdc trans failed ret=3D%d, cmd:time sync\n", ret); =20 return ret; } @@ -85,14 +81,14 @@ s32 sxe_fw_time_sync(struct sxe_hw *hw) =20 status =3D sxe_hw_hdc_fw_status_get(hw); if (status !=3D SXE_FW_START_STATE_FINISHED) { - LOG_ERROR_BDF("fw[%p] status[0x%x] is not good",hw, status); + LOG_ERROR_BDF("fw[%p] status[0x%x] is not good", hw, status); ret =3D -SXE_FW_STATUS_ERR; goto l_ret; } =20 ret_v =3D sxe_fw_time_sync_process(hw); if (ret_v) { - LOG_WARN_BDF("fw time sync failed, ret_v=3D%d\n",ret_v); + LOG_WARN_BDF("fw time sync failed, ret_v=3D%d\n", ret_v); goto l_ret; } =20 @@ -108,7 +104,6 @@ static inline s32 sxe_hdc_lock_get(struct sxe_hw *hw) static inline void sxe_hdc_lock_release(struct sxe_hw *hw) { sxe_hw_hdc_lock_release(hw, SXE_HDC_RELEASELOCK_MAX); - return; } =20 static inline s32 sxe_poll_fw_ack(struct sxe_hw *hw, u32 timeout) @@ -120,11 +115,10 @@ static inline s32 sxe_poll_fw_ack(struct sxe_hw *hw, = u32 timeout) =20 for (i =3D 0; i < timeout; i++) { fw_ov =3D sxe_hw_hdc_is_fw_over_set(hw); - if (fw_ov) { + if (fw_ov) break; - } =20 - msleep(10); + mdelay(10); } =20 if (i >=3D timeout) { @@ -142,13 +136,12 @@ static inline s32 sxe_poll_fw_ack(struct sxe_hw *hw, = u32 timeout) static inline void hdc_channel_clear(struct sxe_hw *hw) { sxe_hw_hdc_fw_ov_clear(hw); - return; } =20 static s32 hdc_packet_ack_get(struct sxe_hw *hw, u64 trace_id, HdcHeader_u *pkt_header) { - s32 ret =3D 0; + s32 ret =3D 0; u32 timeout =3D SXE_HDC_WAIT_TIME; struct sxe_adapter *adapter =3D hw->adapter; UNUSED(trace_id); @@ -163,7 +156,7 @@ static s32 hdc_packet_ack_get(struct sxe_hw *hw, u64 tr= ace_id, goto l_out; } =20 - pkt_header->dw0 =3D sxe_hw_hdc_fw_ack_header_get(hw);; + pkt_header->dw0 =3D sxe_hw_hdc_fw_ack_header_get(hw); if (pkt_header->head.errCode =3D=3D PKG_ERR_PKG_SKIP) { ret =3D -SXE_HDC_PKG_SKIP_ERR; goto l_out; @@ -189,9 +182,8 @@ static void hdc_packet_header_fill(HdcHeader_u *pkt_hea= der, =20 pkt_header->head.totalLen =3D SXE_HDC_LEN_TO_REG(total_len); =20 - if (pkt_index =3D=3D 0 && is_read =3D=3D 0) { + if (pkt_index =3D=3D 0 && is_read =3D=3D 0) pkt_header->head.startPkg =3D SXE_HDC_BIT_1; - } =20 if (pkt_index =3D=3D (pkt_num - 1)) { pkt_header->head.endPkg =3D SXE_HDC_BIT_1; @@ -204,37 +196,33 @@ static void hdc_packet_header_fill(HdcHeader_u *pkt_h= eader, pkt_header->head.isRd =3D is_read; pkt_header->head.msi =3D 0; =20 - return ; } =20 static inline void hdc_packet_send_done(struct sxe_hw *hw) { sxe_hw_hdc_packet_send_done(hw); - return; } =20 static inline void hdc_packet_header_send(struct sxe_hw *hw, u32 header) { sxe_hw_hdc_packet_header_send(hw, header); - return; } =20 static inline void hdc_packet_data_dword_send(struct sxe_hw *hw, u16 dword_index, u32 value) { sxe_hw_hdc_packet_data_dword_send(hw, dword_index, value); - return; } =20 static void hdc_packet_send(struct sxe_hw *hw, u64 trace_id, HdcHeader_u *pkt_header, u8 *data, u16 data_len) { - u16 dw_idx =3D 0; - u16 pkt_len =3D 0; - u16 offset =3D 0; - u32 pkg_data =3D 0; + u16 dw_idx =3D 0; + u16 pkt_len =3D 0; + u16 offset =3D 0; + u32 pkg_data =3D 0; struct sxe_adapter *adapter =3D hw->adapter; UNUSED(trace_id); =20 @@ -244,9 +232,8 @@ static void hdc_packet_send(struct sxe_hw *hw, u64 trac= e_id, =20 hdc_packet_header_send(hw, pkt_header->dw0); =20 - if (data =3D=3D NULL || data_len =3D=3D 0) { - goto l_send_done; - } + if (data =3D=3D NULL || data_len =3D=3D 0) + goto l_send_done; =20 pkt_len =3D SXE_HDC_LEN_FROM_REG(pkt_header->head.len); for (dw_idx =3D 0; dw_idx < pkt_len; dw_idx++) { @@ -273,7 +260,6 @@ static void hdc_packet_send(struct sxe_hw *hw, u64 trac= e_id, =20 hdc_packet_send_done(hw); =20 - return; } =20 static inline u32 hdc_packet_data_dword_rcv(struct sxe_hw *hw, @@ -286,16 +272,16 @@ static void hdc_resp_data_rcv(struct sxe_hw *hw, u64 = trace_id, HdcHeader_u *pkt_header, u8 *out_data, u16 out_len) { - u16 dw_idx =3D 0; - u16 dw_num =3D 0; - u16 offset =3D 0; - u32 pkt_data; + u16 dw_idx =3D 0; + u16 dw_num =3D 0; + u16 offset =3D 0; + u32 pkt_data; struct sxe_adapter *adapter =3D hw->adapter; UNUSED(trace_id); =20 dw_num =3D SXE_HDC_LEN_FROM_REG(pkt_header->head.len); for (dw_idx =3D 0; dw_idx < dw_num; dw_idx++) { - pkt_data=3D hdc_packet_data_dword_rcv(hw, dw_idx); + pkt_data =3D hdc_packet_data_dword_rcv(hw, dw_idx); offset =3D dw_idx * ONE_DWORD_LEN; LOG_DEBUG_BDF("trace_id=3D0x%"SXE_PRIX64" get data from reg[%u] dword=3D= 0x%x\n", trace_id, dw_idx, pkt_data); @@ -309,18 +295,17 @@ static void hdc_resp_data_rcv(struct sxe_hw *hw, u64 = trace_id, } } =20 - return; } =20 -STATIC s32 hdc_req_process(struct sxe_hw *hw, u64 trace_id, +static s32 hdc_req_process(struct sxe_hw *hw, u64 trace_id, u8 *in_data, u16 in_len) { - s32 ret =3D 0; + s32 ret =3D 0; u32 total_len =3D 0; - u16 pkt_num =3D 0; - u16 index =3D 0; - u16 offset =3D 0; - HdcHeader_u pkt_header; + u16 pkt_num =3D 0; + u16 index =3D 0; + u16 offset =3D 0; + HdcHeader_u pkt_header; bool is_retry =3D false; struct sxe_adapter *adapter =3D hw->adapter; =20 @@ -343,27 +328,26 @@ STATIC s32 hdc_req_process(struct sxe_hw *hw, u64 tra= ce_id, hdc_packet_send(hw, trace_id, &pkt_header, in_data + offset, in_len); =20 - if (index =3D=3D pkt_num - 1) { + if (index =3D=3D pkt_num - 1) break; - } =20 ret =3D hdc_packet_ack_get(hw, trace_id, &pkt_header); if (ret =3D=3D -EINTR) { LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" interrupted\n", trace= _id); goto l_out; } else if (ret =3D=3D -SXE_HDC_PKG_SKIP_ERR) { - LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" req ack" + LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" req ack " "failed, retry\n", trace_id); if (is_retry) { ret =3D -SXE_HDC_RETRY_ERR; goto l_out; } =20 - index --; + index--; is_retry =3D true; continue; } else if (ret !=3D SXE_HDC_SUCCESS) { - LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" req ack" + LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" req ack " "failed, ret=3D%d\n", trace_id, ret); ret =3D -SXE_HDC_RETRY_ERR; goto l_out; @@ -382,36 +366,36 @@ STATIC s32 hdc_req_process(struct sxe_hw *hw, u64 tra= ce_id, static s32 hdc_resp_process(struct sxe_hw *hw, u64 trace_id, u8 *out_data, u16 out_len) { - s32 ret; - u32 req_dwords; - u32 resp_len; - u32 resp_dwords; - u16 pkt_num; - u16 index; - u16 offset; + s32 ret; + u32 req_dwords; + u32 resp_len; + u32 resp_dwords; + u16 pkt_num; + u16 index; + u16 offset; HdcHeader_u pkt_header; - bool retry =3D false; + bool retry =3D false; struct sxe_adapter *adapter =3D hw->adapter; =20 - LOG_DEBUG_BDF("hdc trace_id=3D0x%"SXE_PRIX64" req's last cmd ack get\n",t= race_id); + LOG_DEBUG_BDF("hdc trace_id=3D0x%"SXE_PRIX64" req's last cmd ack get\n", = trace_id); ret =3D hdc_packet_ack_get(hw, trace_id, &pkt_header); if (ret =3D=3D -EINTR) { LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" interrupted\n", trace_= id); goto l_out; - } else if(ret) { + } else if (ret) { LOG_ERROR_BDF("hdc trace_id=3D0x%"SXE_PRIX64" ack get failed, ret=3D%d\n= ", trace_id, ret); ret =3D -SXE_HDC_RETRY_ERR; goto l_out; } =20 - LOG_DEBUG_BDF("hdc trace_id=3D0x%"SXE_PRIX64" req's last cmd ack get" - "succeed header[0x%x]\n",trace_id, pkt_header.dw0); + LOG_DEBUG_BDF("hdc trace_id=3D0x%"SXE_PRIX64" req's last cmd ack get " + "succeed header[0x%x]\n", trace_id, pkt_header.dw0); =20 if (!pkt_header.head.startPkg) { ret =3D -SXE_HDC_RETRY_ERR; LOG_ERROR_BDF("trace_id=3D0x%"SXE_PRIX64" ack header has error=EF=BC=9A" - "not set start bit\n",trace_id); + "not set start bit\n", trace_id); goto l_out; } =20 @@ -420,16 +404,15 @@ static s32 hdc_resp_process(struct sxe_hw *hw, u64 tr= ace_id, if (resp_dwords > req_dwords) { ret =3D -SXE_HDC_RETRY_ERR; LOG_ERROR_BDF("trace_id=3D0x%"SXE_PRIX64" rsv len check failed:" - "resp_dwords=3D%u, req_dwords=3D%u\n",trace_id, + "resp_dwords=3D%u, req_dwords=3D%u\n", trace_id, resp_dwords, req_dwords); goto l_out; } =20 resp_len =3D resp_dwords << 2; LOG_DEBUG_BDF("outlen =3D %u bytes, resp_len =3D %u bytes\n", out_len, re= sp_len); - if (resp_len > out_len) { + if (resp_len > out_len) resp_len =3D out_len; - } =20 hdc_resp_data_rcv(hw, trace_id, &pkt_header, out_data, resp_len); =20 @@ -449,19 +432,19 @@ static s32 hdc_resp_process(struct sxe_hw *hw, u64 tr= ace_id, LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" interrupted\n", trace= _id); goto l_out; } else if (ret =3D=3D -SXE_HDC_PKG_SKIP_ERR) { - LOG_ERROR_BDF("trace_id=3D0x%"SXE_PRIX64" hdc resp ack polling" + LOG_ERROR_BDF("trace_id=3D0x%"SXE_PRIX64" hdc resp ack polling " "failed, ret=3D%d\n", trace_id, ret); if (retry) { ret =3D -SXE_HDC_RETRY_ERR; goto l_out; } =20 - index --; + index--; retry =3D true; continue; } else if (ret !=3D SXE_HDC_SUCCESS) { - LOG_ERROR_BDF("trace_id=3D0x%"SXE_PRIX64" hdc resp ack polling" - "failed, ret=3D%d\n",trace_id, ret); + LOG_ERROR_BDF("trace_id=3D0x%"SXE_PRIX64" hdc resp ack polling " + "failed, ret=3D%d\n", trace_id, ret); ret =3D -SXE_HDC_RETRY_ERR; goto l_out; } @@ -491,7 +474,7 @@ static s32 sxe_hdc_packet_trans(struct sxe_hw *hw, u64 = trace_id, =20 status =3D sxe_hw_hdc_fw_status_get(hw); if (status !=3D SXE_FW_START_STATE_FINISHED) { - LOG_ERROR_BDF("fw[%p] status[0x%x] is not good\n",hw, status); + LOG_ERROR_BDF("fw[%p] status[0x%x] is not good\n", hw, status); ret =3D -SXE_FW_STATUS_ERR; goto l_ret; } @@ -514,16 +497,16 @@ static s32 sxe_hdc_packet_trans(struct sxe_hw *hw, u6= 4 trace_id, ret =3D hdc_req_process(hw, trace_id, trans_info->in.data, trans_info->in.len); if (ret) { - LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" req process" - "failed, ret=3D%d\n",trace_id, ret); + LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" req process " + "failed, ret=3D%d\n", trace_id, ret); goto l_hdc_lock_release; } =20 ret =3D hdc_resp_process(hw, trace_id, trans_info->out.data, trans_info->out.len); if (ret) { - LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" resp process" - "failed, ret=3D%d\n",trace_id, ret); + LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" resp process " + "failed, ret=3D%d\n", trace_id, ret); } =20 l_hdc_lock_release: @@ -532,7 +515,7 @@ static s32 sxe_hdc_packet_trans(struct sxe_hw *hw, u64 = trace_id, return ret; } =20 -STATIC s32 sxe_hdc_cmd_process(struct sxe_hw *hw, u64 trace_id, +static s32 sxe_hdc_cmd_process(struct sxe_hw *hw, u64 trace_id, struct sxe_hdc_trans_info *trans_info) { s32 ret; @@ -548,22 +531,22 @@ STATIC s32 sxe_hdc_cmd_process(struct sxe_hw *hw, u64= trace_id, goto l_ret; } =20 - LOG_DEBUG_BDF("hw[%p] cmd trace=3D0x%"SXE_PRIX64" \n",hw, trace_id); -=09 + LOG_DEBUG_BDF("hw[%p] cmd trace=3D0x%"SXE_PRIX64"\n", hw, trace_id); + ret =3D sem_wait(sxe_hdc_sema_get()); if (ret) { LOG_WARN_BDF("hw[%p] hdc concurrency full\n", hw); goto l_ret; } =20 - for (retry_idx =3D 0; retry_idx < 250; retry_idx++ ) { + for (retry_idx =3D 0; retry_idx < 250; retry_idx++) { ret =3D sxe_hdc_packet_trans(hw, trace_id, trans_info); if (ret =3D=3D SXE_SUCCESS) { goto l_up; } else if (ret =3D=3D -SXE_HDC_RETRY_ERR) { rte_delay_ms(10); continue; - } else { + } else { LOG_ERROR_BDF("sxe hdc packet trace_id=3D0x%"SXE_PRIX64 " trans error, ret=3D%d\n", trace_id, ret); ret =3D -EFAULT; @@ -572,16 +555,16 @@ STATIC s32 sxe_hdc_cmd_process(struct sxe_hw *hw, u64= trace_id, } =20 l_up: - LOG_DEBUG_BDF("hw[%p] cmd trace=3D0x%"SXE_PRIX64"\n",hw, trace_id); + LOG_DEBUG_BDF("hw[%p] cmd trace=3D0x%"SXE_PRIX64"\n", hw, trace_id); sem_post(sxe_hdc_sema_get()); l_ret: ret =3D pthread_sigmask(SIG_SETMASK, &old_mask, NULL); - if (ret) { + if (ret) LOG_ERROR_BDF("hdc restore old signal mask failed, ret=3D%d\n", ret); - } - if (ret =3D=3D -SXE_HDC_RETRY_ERR) { + + if (ret =3D=3D -SXE_HDC_RETRY_ERR) ret =3D -EFAULT; - } + return ret; } =20 @@ -590,7 +573,6 @@ static void sxe_cmd_hdr_init(struct sxe_hdc_cmd_hdr *cm= d_hdr, { cmd_hdr->cmd_type =3D cmd_type; cmd_hdr->cmd_sub_type =3D 0; - return; } =20 static void sxe_driver_cmd_msg_init(struct sxe_hdc_drv_cmd_msg *msg, @@ -603,11 +585,9 @@ static void sxe_driver_cmd_msg_init(struct sxe_hdc_drv= _cmd_msg *msg, msg->length.req_len =3D SXE_HDC_MSG_HDR_SIZE + req_len; msg->traceid =3D trace_id; =20 - if (req_data && req_len !=3D 0) { + if (req_data && req_len !=3D 0) memcpy(msg->body, (u8 *)req_data, req_len); - } =20 - return; } =20 static void sxe_hdc_trans_info_init( @@ -619,7 +599,6 @@ static void sxe_hdc_trans_info_init( trans_info->in.len =3D in_len; trans_info->out.data =3D out_data_buf; trans_info->out.len =3D out_len; - return; } =20 s32 sxe_driver_cmd_trans(struct sxe_hw *hw, u16 opcode, @@ -647,16 +626,16 @@ s32 sxe_driver_cmd_trans(struct sxe_hw *hw, u16 opcod= e, =20 in_data_buf =3D rte_zmalloc("pmd hdc in buffer", in_len, RTE_CACHE_LINE_S= IZE); if (in_data_buf =3D=3D NULL) { - LOG_ERROR_BDF("cmd trace_id=3D0x%"SXE_PRIX64" kzalloc indata" - "mem len[%u] failed\n",trace_id, in_len); + LOG_ERROR_BDF("cmd trace_id=3D0x%"SXE_PRIX64" kzalloc indata " + "mem len[%u] failed\n", trace_id, in_len); ret =3D -ENOMEM; goto l_ret; } =20 out_data_buf =3D rte_zmalloc("pmd hdc out buffer", out_len, RTE_CACHE_LIN= E_SIZE); if (out_data_buf =3D=3D NULL) { - LOG_ERROR_BDF("cmd trace_id=3D0x%"SXE_PRIX64" kzalloc out_data" - "mem len[%u] failed\n",trace_id, out_len); + LOG_ERROR_BDF("cmd trace_id=3D0x%"SXE_PRIX64" kzalloc out_data " + "mem len[%u] failed\n", trace_id, out_len); ret =3D -ENOMEM; goto l_in_buf_free; } @@ -678,7 +657,7 @@ s32 sxe_driver_cmd_trans(struct sxe_hw *hw, u16 opcode, ret =3D sxe_hdc_cmd_process(hw, trace_id, &trans_info); if (ret) { LOG_ERROR_BDF("hdc cmd trace_id=3D0x%"SXE_PRIX64" hdc cmd process" - " failed, ret=3D%d\n",trace_id, ret); + " failed, ret=3D%d\n", trace_id, ret); goto l_out_buf_free; } =20 @@ -700,9 +679,8 @@ s32 sxe_driver_cmd_trans(struct sxe_hw *hw, u16 opcode, goto l_out_buf_free; } =20 - if (resp_len !=3D 0) { + if (resp_len !=3D 0) memcpy(resp_data, ack->body, resp_len); - } =20 LOG_DEBUG_BDF("driver get hdc ack trace_id=3D0x%"SXE_PRIX64"," " ack_len=3D%u, ack_data_len=3D%u\n", diff --git a/drivers/net/sxe/pf/sxe_pmd_hdc.h b/drivers/net/sxe/pf/sxe_pmd_= hdc.h index 13671f3a83..98e6599b9d 100644 --- a/drivers/net/sxe/pf/sxe_pmd_hdc.h +++ b/drivers/net/sxe/pf/sxe_pmd_hdc.h @@ -8,18 +8,18 @@ #include "sxe_hw.h" #include "sxe_errno.h" =20 -#define SXE_HDC_SUCCESS 0 -#define SXE_HDC_FALSE SXE_ERR_HDC(1) -#define SXE_HDC_INVAL_PARAM SXE_ERR_HDC(2) -#define SXE_HDC_BUSY SXE_ERR_HDC(3) -#define SXE_HDC_FW_OPS_FAILED SXE_ERR_HDC(4) -#define SXE_HDC_FW_OV_TIMEOUT SXE_ERR_HDC(5) -#define SXE_HDC_REQ_ACK_HEAD_ERR SXE_ERR_HDC(6) -#define SXE_HDC_REQ_ACK_TLEN_ERR SXE_ERR_HDC(7) -#define SXE_HDC_PKG_SKIP_ERR SXE_ERR_HDC(8) -#define SXE_HDC_PKG_OTHER_ERR SXE_ERR_HDC(9) -#define SXE_HDC_RETRY_ERR SXE_ERR_HDC(10) -#define SXE_FW_STATUS_ERR SXE_ERR_HDC(11) +#define SXE_HDC_SUCCESS 0 +#define SXE_HDC_FALSE SXE_ERR_HDC(1) +#define SXE_HDC_INVAL_PARAM SXE_ERR_HDC(2) +#define SXE_HDC_BUSY SXE_ERR_HDC(3) +#define SXE_HDC_FW_OPS_FAILED SXE_ERR_HDC(4) +#define SXE_HDC_FW_OV_TIMEOUT SXE_ERR_HDC(5) +#define SXE_HDC_REQ_ACK_HEAD_ERR SXE_ERR_HDC(6) +#define SXE_HDC_REQ_ACK_TLEN_ERR SXE_ERR_HDC(7) +#define SXE_HDC_PKG_SKIP_ERR SXE_ERR_HDC(8) +#define SXE_HDC_PKG_OTHER_ERR SXE_ERR_HDC(9) +#define SXE_HDC_RETRY_ERR SXE_ERR_HDC(10) +#define SXE_FW_STATUS_ERR SXE_ERR_HDC(11) =20 struct sxe_hdc_data_info { u8 *data; @@ -31,8 +31,8 @@ struct sxe_hdc_trans_info { struct sxe_hdc_data_info out; }; =20 -s32 sxe_driver_cmd_trans(struct sxe_hw *hw, u16 opcode,=20 - void *req_data, u16 req_len,=20 +s32 sxe_driver_cmd_trans(struct sxe_hw *hw, u16 opcode, + void *req_data, u16 req_len, void *resp_data, u16 resp_len); =20 void sxe_hdc_channel_init(void); diff --git a/drivers/net/sxe/pf/sxe_ptp.c b/drivers/net/sxe/pf/sxe_ptp.c index 166665ad11..5e7fa05307 100644 --- a/drivers/net/sxe/pf/sxe_ptp.c +++ b/drivers/net/sxe/pf/sxe_ptp.c @@ -34,7 +34,6 @@ static void sxe_timecounters_start(struct rte_eth_dev *de= v) adapter->ptp_ctxt.tx_hwtstamp_nsec =3D 0; adapter->ptp_ctxt.tx_hwtstamp_sec =3D 0; =20 - return; } =20 s32 sxe_timesync_enable(struct rte_eth_dev *dev) @@ -45,7 +44,7 @@ s32 sxe_timesync_enable(struct rte_eth_dev *dev) =20 sxe_hw_ptp_init(hw); =20 -=09=20 + sxe_hw_ptp_timestamp_mode_set(hw, true, 0, tses); =20 sxe_hw_ptp_timestamp_enable(hw); @@ -93,7 +92,7 @@ s32 sxe_timesync_read_rx_timestamp(struct rte_eth_dev *de= v, =20 rx_tstamp_cycles =3D sxe_hw_ptp_rx_timestamp_get(hw); ns =3D rte_timecounter_update(&adapter->ptp_ctxt.rx_tstamp_tc, rx_tstamp_= cycles); - PMD_LOG_DEBUG(DRV, "got rx_tstamp_cycles =3D %"SXE_PRIU64"ns=3D%"SXE_PRIU= 64,=20 + PMD_LOG_DEBUG(DRV, "got rx_tstamp_cycles =3D %"SXE_PRIU64"ns=3D%"SXE_PRIU= 64, rx_tstamp_cycles, ns); *timestamp =3D rte_ns_to_timespec(ns); =20 @@ -126,9 +125,8 @@ s32 sxe_timesync_read_tx_timestamp(struct rte_eth_dev *= dev, sxe_hw_ptp_tx_timestamp_get(hw, &ts_sec, &ts_ns); if (ts_ns !=3D adapter->ptp_ctxt.tx_hwtstamp_nsec || ts_sec !=3D adapter->ptp_ctxt.tx_hwtstamp_sec) { - for (i =3D 0; i < SXE_TXTS_POLL_CHECK; i++) { + for (i =3D 0; i < SXE_TXTS_POLL_CHECK; i++) sxe_hw_ptp_tx_timestamp_get(hw, &last_sec, &last_ns); - } =20 for (; i < SXE_TXTS_POLL; i++) { sxe_hw_ptp_tx_timestamp_get(hw, &ts_sec, &ts_ns); @@ -147,7 +145,7 @@ s32 sxe_timesync_read_tx_timestamp(struct rte_eth_dev *= dev, } else { adapter->ptp_ctxt.tx_hwtstamp_nsec =3D ts_ns; adapter->ptp_ctxt.tx_hwtstamp_sec =3D ts_sec; - tx_tstamp_cycles =3D=20 + tx_tstamp_cycles =3D sxe_timesync_tx_tstamp_cycles_get(adapter); ns =3D rte_timecounter_update(&adapter->ptp_ctxt.tx_tstamp_tc, tx_tstamp_cycles); @@ -181,14 +179,14 @@ s32 sxe_timesync_read_time(struct rte_eth_dev *dev, s= truct timespec *ts) =20 systime_cycles =3D sxe_hw_ptp_systime_get(hw); ns =3D rte_timecounter_update(&adapter->ptp_ctxt.systime_tc, systime_cycl= es); - PMD_LOG_DEBUG(DRV, "got systime_cycles =3D %"SXE_PRIU64"ns=3D%"SXE_PRIU64= ,=20 + PMD_LOG_DEBUG(DRV, "got systime_cycles =3D %"SXE_PRIU64"ns=3D%"SXE_PRIU64, systime_cycles, ns); *ts =3D rte_ns_to_timespec(ns); =20 return 0; } =20 -s32 sxe_timesync_write_time(struct rte_eth_dev *dev,=20 +s32 sxe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) { u64 ns; diff --git a/drivers/net/sxe/pf/sxe_ptp.h b/drivers/net/sxe/pf/sxe_ptp.h index 367c1a34a0..14971b2d50 100644 --- a/drivers/net/sxe/pf/sxe_ptp.h +++ b/drivers/net/sxe/pf/sxe_ptp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright (C), 2022, Linkdata Technology Co., Ltd. */ -=20 + #ifndef __SXE_PTP_H__ #define __SXE_PTP_H__ =20 @@ -20,7 +20,7 @@ s32 sxe_timesync_adjust_time(struct rte_eth_dev *dev, s64= delta); =20 s32 sxe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts); =20 -s32 sxe_timesync_write_time(struct rte_eth_dev *dev,=20 +s32 sxe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts); =20 #endif diff --git a/drivers/net/sxe/pf/sxe_queue.c b/drivers/net/sxe/pf/sxe_queue.c index 8a0042022b..98e4a5c1ac 100644 --- a/drivers/net/sxe/pf/sxe_queue.c +++ b/drivers/net/sxe/pf/sxe_queue.c @@ -27,7 +27,7 @@ #endif #include "sxe_compat_version.h" =20 -#define SXE_RXQ_SCAN_INTERVAL 4 +#define SXE_RXQ_SCAN_INTERVAL 4 =20 #ifndef DEFAULT_TX_RS_THRESH #define DEFAULT_TX_RS_THRESH 32 @@ -39,9 +39,9 @@ =20 #define RTE_SXE_WAIT_100_US 100 =20 -#define SXE_MMW_SIZE_DEFAULT 0x4 -#define SXE_MMW_SIZE_JUMBO_FRAME 0x14 -#define SXE_MAX_JUMBO_FRAME_SIZE 0x2600=20 +#define SXE_MMW_SIZE_DEFAULT 0x4 +#define SXE_MMW_SIZE_JUMBO_FRAME 0x14 +#define SXE_MAX_JUMBO_FRAME_SIZE 0x2600 =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SRIOV static s32 sxe_vf_rss_rxq_num_validate(struct rte_eth_dev *dev, u16 rxq_nu= m) @@ -67,7 +67,7 @@ static s32 sxe_vf_rss_rxq_num_validate(struct rte_eth_dev= *dev, u16 rxq_num) RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =3D pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; =20 - PMD_LOG_INFO(INIT, "enable sriov, vfs num:%u, %u pool mode, %u queue pre = pool" + PMD_LOG_INFO(INIT, "enable sriov, vfs num:%u, %u pool mode, %u queue pre = pool " "vm total queue num are %u", pci_dev->max_vfs, RTE_ETH_DEV_SRIOV(dev).active, @@ -85,38 +85,38 @@ s32 sxe_sriov_mq_mode_check(struct rte_eth_dev *dev) u16 tx_q_num =3D dev->data->nb_tx_queues; =20 switch (dev_conf->rxmode.mq_mode) { - case RTE_ETH_MQ_RX_VMDQ_DCB: - PMD_LOG_INFO(INIT, "RTE_ETH_MQ_RX_VMDQ_DCB mode supported in sriov"); - break; + case RTE_ETH_MQ_RX_VMDQ_DCB: + PMD_LOG_INFO(INIT, "RTE_ETH_MQ_RX_VMDQ_DCB mode supported in sriov"); + break; + + case RTE_ETH_MQ_RX_VMDQ_DCB_RSS: + PMD_LOG_ERR(INIT, "RTE_ETH_MQ_RX_VMDQ_DCB_RSS mode unsupported in sriov"= ); + ret =3D -EINVAL; + goto l_end; =20 - case RTE_ETH_MQ_RX_VMDQ_DCB_RSS: - PMD_LOG_ERR(INIT, "RTE_ETH_MQ_RX_VMDQ_DCB_RSS mode unsupported in sriov= "); + case RTE_ETH_MQ_RX_RSS: + case RTE_ETH_MQ_RX_VMDQ_RSS: + dev->data->dev_conf.rxmode.mq_mode =3D RTE_ETH_MQ_RX_VMDQ_RSS; + if ((rx_q_num <=3D RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) && + sxe_vf_rss_rxq_num_validate(dev, rx_q_num)) { + PMD_LOG_ERR(INIT, "sriov is active, invalid queue number[%d], " + " for vmdq rss, allowed value are 1, 2 or 4", + rx_q_num); ret =3D -EINVAL; goto l_end; + } + break; =20 - case RTE_ETH_MQ_RX_RSS: - case RTE_ETH_MQ_RX_VMDQ_RSS: - dev->data->dev_conf.rxmode.mq_mode =3D RTE_ETH_MQ_RX_VMDQ_RSS; - if ((rx_q_num <=3D RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) &&=20 - sxe_vf_rss_rxq_num_validate(dev, rx_q_num)) { - PMD_LOG_ERR(INIT, "sriov is active, invalid queue number[%d], " - " for vmdq rss, allowed value are 1, 2 or 4", - rx_q_num); - ret =3D -EINVAL; - goto l_end; - } - break; - - case RTE_ETH_MQ_RX_VMDQ_ONLY: - case RTE_ETH_MQ_RX_NONE: - dev->data->dev_conf.rxmode.mq_mode =3D RTE_ETH_MQ_RX_VMDQ_ONLY; - break; + case RTE_ETH_MQ_RX_VMDQ_ONLY: + case RTE_ETH_MQ_RX_NONE: + dev->data->dev_conf.rxmode.mq_mode =3D RTE_ETH_MQ_RX_VMDQ_ONLY; + break; =20 - default: - PMD_LOG_ERR(INIT, "sriov is active, wrong mq_mode rx %d", - dev_conf->rxmode.mq_mode); - ret =3D -EINVAL; - goto l_end; + default: + PMD_LOG_ERR(INIT, "sriov is active, wrong mq_mode rx %d", + dev_conf->rxmode.mq_mode); + ret =3D -EINVAL; + goto l_end; } =20 switch (dev_conf->txmode.mq_mode) { @@ -129,7 +129,7 @@ s32 sxe_sriov_mq_mode_check(struct rte_eth_dev *dev) ret =3D -EINVAL; goto l_end; =20 - default:=20 + default: dev->data->dev_conf.txmode.mq_mode =3D RTE_ETH_MQ_TX_VMDQ_ONLY; break; } @@ -174,9 +174,9 @@ static inline s32 sxe_non_sriov_mq_mode_check(struct rt= e_eth_dev *dev) goto l_end; } =20 - if (!((dev_conf->rx_adv_conf.vmdq_dcb_conf.nb_queue_pools =3D=3D \ - RTE_ETH_16_POOLS ) || ( - dev_conf->rx_adv_conf.vmdq_dcb_conf.nb_queue_pools =3D=3D \ + if (!((dev_conf->rx_adv_conf.vmdq_dcb_conf.nb_queue_pools =3D=3D + RTE_ETH_16_POOLS) || ( + dev_conf->rx_adv_conf.vmdq_dcb_conf.nb_queue_pools =3D=3D RTE_ETH_32_POOLS))) { PMD_LOG_ERR(INIT, "VMDQ+DCB selected," " nb_queue_pools must be %d or %d", @@ -215,9 +215,9 @@ static inline s32 sxe_non_sriov_mq_mode_check(struct rt= e_eth_dev *dev) goto l_end; } =20 - if (!((dev_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools =3D=3D \ - RTE_ETH_16_POOLS ) || ( - dev_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools =3D=3D \ + if (!((dev_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools =3D=3D + RTE_ETH_16_POOLS) || ( + dev_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools =3D=3D RTE_ETH_32_POOLS))) { PMD_LOG_ERR(INIT, "VMDQ+DCB selected," " nb_queue_pools must be %d or %d", @@ -275,7 +275,6 @@ void sxe_tx_queue_info_get(struct rte_eth_dev *dev, u16= queue_id, { __sxe_tx_queue_info_get(dev, queue_id, q_info); =20 - return; } =20 s32 __rte_cold sxe_txq_arg_validate(struct rte_eth_dev *dev, u16 ring_dept= h, @@ -295,16 +294,15 @@ s32 __rte_cold sxe_txq_arg_validate(struct rte_eth_de= v *dev, u16 ring_depth, *rs_thresh =3D (DEFAULT_TX_RS_THRESH + *free_thresh > ring_depth) ? ring_depth - *free_thresh : DEFAULT_TX_RS_THRESH; =20 - if (tx_conf->tx_rs_thresh > 0) { + if (tx_conf->tx_rs_thresh > 0) *rs_thresh =3D tx_conf->tx_rs_thresh; - } =20 if (*rs_thresh + *free_thresh > ring_depth) { PMD_LOG_ERR(INIT, "tx_rs_thresh + tx_free_thresh must not " - "exceed nb_desc. (tx_rs_thresh=3D%u " - "tx_free_thresh=3D%u nb_desc=3D%u port =3D %d)", - *rs_thresh, *free_thresh, - ring_depth, dev->data->port_id); + "exceed nb_desc. (tx_rs_thresh=3D%u " + "tx_free_thresh=3D%u nb_desc=3D%u port =3D %d)", + *rs_thresh, *free_thresh, + ring_depth, dev->data->port_id); goto l_end; } =20 @@ -326,34 +324,34 @@ s32 __rte_cold sxe_txq_arg_validate(struct rte_eth_de= v *dev, u16 ring_depth, =20 if (*free_thresh >=3D (ring_depth - 3)) { PMD_LOG_ERR(INIT, "tx_rs_thresh must be less than the " - "tx_free_thresh must be less than the number of " - "TX descriptors minus 3. (tx_free_thresh=3D%u " - "port=3D%d)", - *free_thresh, dev->data->port_id); + "tx_free_thresh must be less than the number of " + "TX descriptors minus 3. (tx_free_thresh=3D%u " + "port=3D%d)", + *free_thresh, dev->data->port_id); goto l_end; } =20 if (*rs_thresh > *free_thresh) { PMD_LOG_ERR(INIT, "tx_rs_thresh must be less than or equal to " - "tx_free_thresh. (tx_free_thresh=3D%u " - "tx_rs_thresh=3D%u port=3D%d)", - *free_thresh, *rs_thresh, dev->data->port_id); + "tx_free_thresh. (tx_free_thresh=3D%u " + "tx_rs_thresh=3D%u port=3D%d)", + *free_thresh, *rs_thresh, dev->data->port_id); goto l_end; } =20 if ((ring_depth % *rs_thresh) !=3D 0) { PMD_LOG_ERR(INIT, "tx_rs_thresh must be a divisor of the " - "number of TX descriptors. (tx_rs_thresh=3D%u " - "port=3D%d, ring_depth=3D%d)", - *rs_thresh, dev->data->port_id, ring_depth); + "number of TX descriptors. (tx_rs_thresh=3D%u " + "port=3D%d, ring_depth=3D%d)", + *rs_thresh, dev->data->port_id, ring_depth); goto l_end; } =20 if ((*rs_thresh > 1) && (tx_conf->tx_thresh.wthresh !=3D 0)) { PMD_LOG_ERR(INIT, "TX WTHRESH must be set to 0 if " - "tx_rs_thresh is greater than 1. " - "(tx_rs_thresh=3D%u port=3D%d)", - *rs_thresh, dev->data->port_id); + "tx_rs_thresh is greater than 1. " + "(tx_rs_thresh=3D%u port=3D%d)", + *rs_thresh, dev->data->port_id); goto l_end; } =20 @@ -365,11 +363,9 @@ s32 __rte_cold sxe_txq_arg_validate(struct rte_eth_dev= *dev, u16 ring_depth, =20 static void __rte_cold sxe_tx_buffer_ring_free(sxe_tx_queue_s *txq) { - if (txq !=3D NULL && txq->buffer_ring !=3D NULL) { + if (txq !=3D NULL && txq->buffer_ring !=3D NULL) rte_free(txq->buffer_ring); - } =20 - return; } =20 static void __rte_cold sxe_tx_queue_mbufs_release(sxe_tx_queue_s *txq) @@ -385,28 +381,24 @@ static void __rte_cold sxe_tx_queue_mbufs_release(sxe= _tx_queue_s *txq) } } =20 - return; } =20 void __rte_cold sxe_tx_queue_free(sxe_tx_queue_s *txq) { __sxe_tx_queue_free(txq); =20 - return; } =20 #if defined DPDK_20_11_5 || defined DPDK_19_11_6 void __rte_cold sxe_tx_queue_release(void *txq) { sxe_tx_queue_free(txq); - return; } #else void __rte_cold sxe_tx_queue_release(struct rte_eth_dev *dev, u16 queue_idx) { sxe_tx_queue_free(dev->data->tx_queues[queue_idx]); - return; } #endif =20 @@ -414,34 +406,32 @@ static void __rte_cold sxe_tx_queue_init(sxe_tx_queue= _s *txq) { u16 prev, i; volatile sxe_tx_data_desc_u *txd; - static const sxe_tx_data_desc_u zeroed_desc =3D {{0}}; + static const sxe_tx_data_desc_u zeroed_desc =3D { {0} }; struct sxe_tx_buffer *tx_buffer =3D txq->buffer_ring; =20 - for (i =3D 0; i < txq->ring_depth; i++) { + for (i =3D 0; i < txq->ring_depth; i++) txq->desc_ring[i] =3D zeroed_desc; - } =20 prev =3D txq->ring_depth - 1; for (i =3D 0; i < txq->ring_depth; i++) { txd =3D &txq->desc_ring[i]; txd->wb.status =3D rte_cpu_to_le_32(SXE_TX_DESC_STAT_DD); - tx_buffer[i].mbuf =3D NULL; - tx_buffer[i].last_id =3D i; + tx_buffer[i].mbuf =3D NULL; + tx_buffer[i].last_id =3D i; tx_buffer[prev].next_id =3D i; prev =3D i; } =20 - txq->ctx_curr =3D 0; + txq->ctx_curr =3D 0; txq->desc_used_num =3D 0; txq->desc_free_num =3D txq->ring_depth - 1; txq->next_to_use =3D 0; txq->next_to_clean =3D txq->ring_depth - 1; - txq->next_dd =3D txq->rs_thresh - 1; - txq->next_rs =3D txq->rs_thresh - 1; + txq->next_dd =3D txq->rs_thresh - 1; + txq->next_rs =3D txq->rs_thresh - 1; memset((void *)&txq->ctx_cache, 0, SXE_CTXT_DESC_NUM * sizeof(struct sxe_ctxt_info)); =20 - return; } =20 sxe_tx_queue_s * __rte_cold sxe_tx_queue_alloc( @@ -545,7 +535,6 @@ void sxe_rx_queue_info_get(struct rte_eth_dev *dev, u16= queue_id, { __sxe_rx_queue_info_get(dev, queue_id, qinfo); =20 - return; } =20 s32 __rte_cold sxe_rx_queue_mbufs_alloc(struct sxe_rx_queue *rxq) @@ -557,7 +546,7 @@ s32 __rte_cold sxe_rx_queue_start(struct rte_eth_dev *d= ev, u16 queue_id) { struct sxe_adapter *adapter =3D dev->data->dev_private; - struct sxe_hw *hw =3D &adapter->hw; + struct sxe_hw *hw =3D &adapter->hw; struct sxe_rx_queue *rxq; u16 reg_idx; s32 ret; @@ -570,7 +559,7 @@ s32 __rte_cold sxe_rx_queue_start(struct rte_eth_dev *d= ev, ret =3D sxe_rx_queue_mbufs_alloc(rxq); if (ret) { PMD_LOG_ERR(INIT, "could not alloc mbuf for queue:%d", - queue_id); + queue_id); goto l_end; } =20 @@ -583,7 +572,7 @@ s32 __rte_cold sxe_rx_queue_start(struct rte_eth_dev *d= ev, return ret; } =20 -STATIC void __rte_cold sxe_rx_queue_sc_mbufs_free(struct rte_mbuf *mbuf) +static void __rte_cold sxe_rx_queue_sc_mbufs_free(struct rte_mbuf *mbuf) { u16 i; u16 num_segs =3D mbuf->nb_segs; @@ -595,17 +584,16 @@ STATIC void __rte_cold sxe_rx_queue_sc_mbufs_free(str= uct rte_mbuf *mbuf) mbuf =3D next_seg; } =20 - return; } =20 void __rte_cold sxe_rx_queue_mbufs_free(struct sxe_rx_queue *rxq) { u16 i; -=09 + #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD if (rxq->is_using_sse) { sxe_rx_queue_vec_mbufs_release(rxq); - goto l_out; + return; } #endif =20 @@ -636,32 +624,24 @@ void __rte_cold sxe_rx_queue_mbufs_free(struct sxe_rx= _queue *rxq) } } =20 -#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD -l_out: -#endif - - return; } =20 void __rte_cold sxe_rx_queue_init(bool rx_batch_alloc_allowed, struct sxe_rx_queue *rxq) { - static const sxe_rx_data_desc_u zeroed_desc =3D {{0}}; + static const sxe_rx_data_desc_u zeroed_desc =3D { {0} }; u16 i; u16 len =3D rxq->ring_depth; =20 - if (rx_batch_alloc_allowed) { + if (rx_batch_alloc_allowed) len +=3D RTE_PMD_SXE_MAX_RX_BURST; - } =20 - for (i =3D 0; i < len; i++) { + for (i =3D 0; i < len; i++) rxq->desc_ring[i] =3D zeroed_desc; - } =20 memset(&rxq->fake_mbuf, 0, sizeof(rxq->fake_mbuf)); - for (i =3D rxq->ring_depth; i < len; ++i) { + for (i =3D rxq->ring_depth; i < len; ++i) rxq->buffer_ring[i].mbuf =3D &rxq->fake_mbuf; - } =20 rxq->completed_pkts_num =3D 0; rxq->next_ret_pkg =3D 0; @@ -670,9 +650,8 @@ void __rte_cold sxe_rx_queue_init(bool rx_batch_alloc_a= llowed, rxq->hold_num =3D 0; =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD - if (rxq->pkt_first_seg !=3D NULL) { + if (rxq->pkt_first_seg !=3D NULL) rte_pktmbuf_free(rxq->pkt_first_seg); - } =20 rxq->pkt_first_seg =3D NULL; rxq->pkt_last_seg =3D NULL; @@ -683,34 +662,30 @@ void __rte_cold sxe_rx_queue_init(bool rx_batch_alloc= _allowed, #endif #endif =20 - return; } =20 void __rte_cold sxe_rx_queue_free(struct sxe_rx_queue *rxq) { __sxe_rx_queue_free(rxq); - return; } =20 #if defined DPDK_20_11_5 || defined DPDK_19_11_6 void __rte_cold sxe_rx_queue_release(void *rxq) { sxe_rx_queue_free(rxq); - return; } #else void __rte_cold sxe_rx_queue_release(struct rte_eth_dev *dev, u16 queue_idx) { sxe_rx_queue_free(dev->data->rx_queues[queue_idx]); - return; } #endif =20 s32 __rte_cold sxe_rx_queue_stop(struct rte_eth_dev *dev, u16 queue_id) { struct sxe_adapter *adapter =3D dev->data->dev_private; - struct sxe_hw *hw =3D &adapter->hw; + struct sxe_hw *hw =3D &adapter->hw; struct sxe_rx_queue *rxq; u16 reg_idx; =20 @@ -745,7 +720,7 @@ u32 sxe_rx_queue_count(void *rx_queue) #else rxq =3D rx_queue; #endif -=09 + desc =3D &(rxq->desc_ring[rxq->processing_idx]); =20 while ((count < rxq->ring_depth) && @@ -766,18 +741,16 @@ void __rte_cold sxe_txrx_queues_clear(struct rte_eth_= dev *dev, bool rx_batch_all { __sxe_txrx_queues_clear(dev, rx_batch_alloc_allowed); =20 - return; } =20 void sxe_queues_free(struct rte_eth_dev *dev) { __sxe_queues_free(dev); - return; } =20 const struct sxe_txq_ops def_txq_ops =3D { - .init =3D sxe_tx_queue_init, - .mbufs_release =3D sxe_tx_queue_mbufs_release, + .init =3D sxe_tx_queue_init, + .mbufs_release =3D sxe_tx_queue_mbufs_release, .buffer_ring_free =3D sxe_tx_buffer_ring_free, }; =20 @@ -791,19 +764,18 @@ void sxe_multi_queue_tx_configure(struct rte_eth_dev = *dev) struct sxe_hw *hw =3D (&((struct sxe_adapter *)(dev->data->dev_private))-= >hw); u16 pools_num =3D RTE_ETH_DEV_SRIOV(dev).active; bool sriov_active =3D !!pools_num; - bool vmdq_active =3D (dev->data->dev_conf.txmode.mq_mode =3D=3D=20 + bool vmdq_active =3D (dev->data->dev_conf.txmode.mq_mode =3D=3D RTE_ETH_MQ_TX_VMDQ_ONLY); =20 sxe_hw_tx_multi_queue_configure(hw, vmdq_active, sriov_active, pools_num); =20 - return; } =20 #if defined DPDK_20_11_5 || defined DPDK_21_11_5 || defined DPDK_19_11_6 -s32 sxe_queue_rate_limit_set(struct rte_eth_dev *dev,=20 +s32 sxe_queue_rate_limit_set(struct rte_eth_dev *dev, u16 queue_idx, u16 tx_rate) #else -s32 sxe_queue_rate_limit_set(struct rte_eth_dev *dev,=20 +s32 sxe_queue_rate_limit_set(struct rte_eth_dev *dev, u16 queue_idx, u32 tx_rate) #endif { @@ -838,11 +810,11 @@ s32 sxe_queue_rate_limit_set(struct rte_eth_dev *dev, rxmode =3D &dev->data->dev_conf.rxmode; =20 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && - (rxmode->max_rx_pkt_len >=3D SXE_MAX_JUMBO_FRAME_SIZE)) { + (rxmode->max_rx_pkt_len >=3D SXE_MAX_JUMBO_FRAME_SIZE)) { #else if (dev->data->mtu + SXE_ETH_OVERHEAD >=3D SXE_MAX_JUMBO_FRAME_SIZE) { #endif - sxe_hw_dcb_max_mem_window_set(hw,=20 + sxe_hw_dcb_max_mem_window_set(hw, SXE_MMW_SIZE_JUMBO_FRAME); } else { sxe_hw_dcb_max_mem_window_set(hw, SXE_MMW_SIZE_DEFAULT); diff --git a/drivers/net/sxe/pf/sxe_queue.h b/drivers/net/sxe/pf/sxe_queue.h index ef3036a07d..9f73a2ac3f 100644 --- a/drivers/net/sxe/pf/sxe_queue.h +++ b/drivers/net/sxe/pf/sxe_queue.h @@ -7,40 +7,40 @@ #include "sxe_dpdk_version.h" #include "sxe_queue_common.h" =20 -#define SXE_TXRX_RING_NUM_MAX 64=20=20 +#define SXE_TXRX_RING_NUM_MAX 64 =20 -#define SXE_TX_MAX_SEG 40 +#define SXE_TX_MAX_SEG 40 =20 #define SXE_MIN_RING_DESC 32 #define SXE_MAX_RING_DESC 4096 =20 -#define SXE_MMW_SIZE_DEFAULT 0x4 -#define SXE_MMW_SIZE_JUMBO_FRAME 0x14 -#define SXE_MAX_JUMBO_FRAME_SIZE 0x2600=20 +#define SXE_MMW_SIZE_DEFAULT 0x4 +#define SXE_MMW_SIZE_JUMBO_FRAME 0x14 +#define SXE_MAX_JUMBO_FRAME_SIZE 0x2600 =20 #define SXE_DEFAULT_RX_FREE_THRESH 32 -#define SXE_DEFAULT_RX_PTHRESH 8 -#define SXE_DEFAULT_RX_HTHRESH 8 -#define SXE_DEFAULT_RX_WTHRESH 0 +#define SXE_DEFAULT_RX_PTHRESH 8 +#define SXE_DEFAULT_RX_HTHRESH 8 +#define SXE_DEFAULT_RX_WTHRESH 0 =20 #define SXE_DEFAULT_TX_FREE_THRESH 32 -#define SXE_DEFAULT_TX_PTHRESH 32 -#define SXE_DEFAULT_TX_HTHRESH 0 -#define SXE_DEFAULT_TX_WTHRESH 0 +#define SXE_DEFAULT_TX_PTHRESH 32 +#define SXE_DEFAULT_TX_HTHRESH 0 +#define SXE_DEFAULT_TX_WTHRESH 0 #define SXE_DEFAULT_TX_RSBIT_THRESH 32 =20 -#define SXE_ALIGN 128 +#define SXE_ALIGN 128 #define SXE_RX_DESC_RING_ALIGN (SXE_ALIGN / sizeof(sxe_rx_data_desc_u)) #define SXE_TX_DESC_RING_ALIGN (SXE_ALIGN / sizeof(sxe_tx_data_desc_u)) =20 -#define SXE_TX_MAX_SEG 40 +#define SXE_TX_MAX_SEG 40 #define RTE_SXE_REGISTER_POLL_WAIT_10_MS 10 =20 typedef union sxe_tx_data_desc sxe_tx_data_desc_u; typedef struct sxe_rx_buffer sxe_rx_buffer_s; typedef union sxe_rx_data_desc sxe_rx_data_desc_u; -typedef struct sxe_tx_queue sxe_tx_queue_s; -typedef struct sxe_rx_queue sxe_rx_queue_s; +typedef struct sxe_tx_queue sxe_tx_queue_s; +typedef struct sxe_rx_queue sxe_rx_queue_s; =20 struct sxe_tx_context_desc { __le32 vlan_macip_lens; @@ -127,7 +127,7 @@ s32 sxe_queue_rate_limit_set(struct rte_eth_dev *dev, u16 queue_idx, u16 tx_rate); =20 #else -s32 sxe_queue_rate_limit_set(struct rte_eth_dev *dev,=20 +s32 sxe_queue_rate_limit_set(struct rte_eth_dev *dev, u16 queue_idx, u32 tx_rate); #endif =20 @@ -144,4 +144,4 @@ s32 sxe_sriov_mq_mode_check(struct rte_eth_dev *dev); =20 void __rte_cold sxe_rx_queue_mbufs_free(sxe_rx_queue_s *rxq); =20 -#endif=20 +#endif diff --git a/drivers/net/sxe/pf/sxe_rx.c b/drivers/net/sxe/pf/sxe_rx.c index febd9fc634..e0074021b4 100644 --- a/drivers/net/sxe/pf/sxe_rx.c +++ b/drivers/net/sxe/pf/sxe_rx.c @@ -68,51 +68,51 @@ #define SXE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP 0x2F #define SXE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP 0x4F =20 -#define SXE_PACKET_TYPE_NVGRE 0x00 -#define SXE_PACKET_TYPE_NVGRE_IPV4 0x01 -#define SXE_PACKET_TYPE_NVGRE_IPV4_TCP 0x11 -#define SXE_PACKET_TYPE_NVGRE_IPV4_UDP 0x21 -#define SXE_PACKET_TYPE_NVGRE_IPV4_SCTP 0x41 -#define SXE_PACKET_TYPE_NVGRE_IPV4_EXT 0x03 -#define SXE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP 0x13 -#define SXE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP 0x23 -#define SXE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP 0x43 -#define SXE_PACKET_TYPE_NVGRE_IPV6 0x04 -#define SXE_PACKET_TYPE_NVGRE_IPV6_TCP 0x14 -#define SXE_PACKET_TYPE_NVGRE_IPV6_UDP 0x24 -#define SXE_PACKET_TYPE_NVGRE_IPV6_SCTP 0x44 -#define SXE_PACKET_TYPE_NVGRE_IPV6_EXT 0x0C -#define SXE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP 0x1C -#define SXE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP 0x2C -#define SXE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP 0x4C -#define SXE_PACKET_TYPE_NVGRE_IPV4_IPV6 0x05 -#define SXE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP 0x15 -#define SXE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP 0x25 -#define SXE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT 0x0D +#define SXE_PACKET_TYPE_NVGRE 0x00 +#define SXE_PACKET_TYPE_NVGRE_IPV4 0x01 +#define SXE_PACKET_TYPE_NVGRE_IPV4_TCP 0x11 +#define SXE_PACKET_TYPE_NVGRE_IPV4_UDP 0x21 +#define SXE_PACKET_TYPE_NVGRE_IPV4_SCTP 0x41 +#define SXE_PACKET_TYPE_NVGRE_IPV4_EXT 0x03 +#define SXE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP 0x13 +#define SXE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP 0x23 +#define SXE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP 0x43 +#define SXE_PACKET_TYPE_NVGRE_IPV6 0x04 +#define SXE_PACKET_TYPE_NVGRE_IPV6_TCP 0x14 +#define SXE_PACKET_TYPE_NVGRE_IPV6_UDP 0x24 +#define SXE_PACKET_TYPE_NVGRE_IPV6_SCTP 0x44 +#define SXE_PACKET_TYPE_NVGRE_IPV6_EXT 0x0C +#define SXE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP 0x1C +#define SXE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP 0x2C +#define SXE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP 0x4C +#define SXE_PACKET_TYPE_NVGRE_IPV4_IPV6 0x05 +#define SXE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP 0x15 +#define SXE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP 0x25 +#define SXE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT 0x0D #define SXE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP 0x1D #define SXE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP 0x2D =20 -#define SXE_PACKET_TYPE_VXLAN 0x80 -#define SXE_PACKET_TYPE_VXLAN_IPV4 0x81 -#define SXE_PACKET_TYPE_VXLAN_IPV4_TCP 0x91 -#define SXE_PACKET_TYPE_VXLAN_IPV4_UDP 0xA1 -#define SXE_PACKET_TYPE_VXLAN_IPV4_SCTP 0xC1 -#define SXE_PACKET_TYPE_VXLAN_IPV4_EXT 0x83 -#define SXE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP 0x93 -#define SXE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP 0xA3 -#define SXE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP 0xC3 -#define SXE_PACKET_TYPE_VXLAN_IPV6 0x84 -#define SXE_PACKET_TYPE_VXLAN_IPV6_TCP 0x94 -#define SXE_PACKET_TYPE_VXLAN_IPV6_UDP 0xA4 -#define SXE_PACKET_TYPE_VXLAN_IPV6_SCTP 0xC4 -#define SXE_PACKET_TYPE_VXLAN_IPV6_EXT 0x8C -#define SXE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP 0x9C -#define SXE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP 0xAC -#define SXE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP 0xCC -#define SXE_PACKET_TYPE_VXLAN_IPV4_IPV6 0x85 -#define SXE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP 0x95 -#define SXE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP 0xA5 -#define SXE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT 0x8D +#define SXE_PACKET_TYPE_VXLAN 0x80 +#define SXE_PACKET_TYPE_VXLAN_IPV4 0x81 +#define SXE_PACKET_TYPE_VXLAN_IPV4_TCP 0x91 +#define SXE_PACKET_TYPE_VXLAN_IPV4_UDP 0xA1 +#define SXE_PACKET_TYPE_VXLAN_IPV4_SCTP 0xC1 +#define SXE_PACKET_TYPE_VXLAN_IPV4_EXT 0x83 +#define SXE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP 0x93 +#define SXE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP 0xA3 +#define SXE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP 0xC3 +#define SXE_PACKET_TYPE_VXLAN_IPV6 0x84 +#define SXE_PACKET_TYPE_VXLAN_IPV6_TCP 0x94 +#define SXE_PACKET_TYPE_VXLAN_IPV6_UDP 0xA4 +#define SXE_PACKET_TYPE_VXLAN_IPV6_SCTP 0xC4 +#define SXE_PACKET_TYPE_VXLAN_IPV6_EXT 0x8C +#define SXE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP 0x9C +#define SXE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP 0xAC +#define SXE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP 0xCC +#define SXE_PACKET_TYPE_VXLAN_IPV4_IPV6 0x85 +#define SXE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP 0x95 +#define SXE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP 0xA5 +#define SXE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT 0x8D #define SXE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP 0x9D #define SXE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP 0xAD =20 @@ -426,7 +426,6 @@ void sxe_rx_mbuf_common_header_fill( desc.wb.lower.hi_dword.csum_ip.ip_id); } =20 - return; } =20 static inline void sxe_rx_resource_prefetch(u16 next_idx, @@ -441,7 +440,6 @@ static inline void sxe_rx_resource_prefetch(u16 next_id= x, rte_sxe_prefetch(&buf_ring[next_idx]); } =20 - return; } =20 u16 sxe_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts, @@ -459,9 +457,8 @@ static inline u16 sxe_ret_pkts_to_user(sxe_rx_queue_s *= rxq, =20 pkts_num =3D (u16)RTE_MIN(pkts_num, rxq->completed_pkts_num); =20 - for (i =3D 0; i < pkts_num; ++i) { + for (i =3D 0; i < pkts_num; ++i) rx_pkts[i] =3D completed_mbuf[i]; - } =20 /* Update completed packets num and next available position */ rxq->completed_pkts_num =3D (u16)(rxq->completed_pkts_num - pkts_num); @@ -494,9 +491,8 @@ static inline u16 sxe_rx_hw_ring_scan(sxe_rx_queue_s *r= xq) =20 status =3D rx_desc->wb.upper.status_error; =20 - if (!(status & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD))) { + if (!(status & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD))) goto l_end; - } =20 for (i =3D 0; i < RTE_PMD_SXE_MAX_RX_BURST; i +=3D LOOK_AHEAD, rx_desc +=3D LOOK_AHEAD, rx_buf +=3D LOOK_AHEAD) { @@ -531,24 +527,21 @@ static inline u16 sxe_rx_hw_ring_scan(sxe_rx_queue_s = *rxq) pkt_info[j], status_arr[j]); } =20 - for (j =3D 0; j < LOOK_AHEAD; ++j) { + for (j =3D 0; j < LOOK_AHEAD; ++j) rxq->completed_ring[i + j] =3D rx_buf[j].mbuf; - } =20 - if (num_dd_set !=3D LOOK_AHEAD) { + if (num_dd_set !=3D LOOK_AHEAD) break; - } } =20 - for (i =3D 0; i < done_num; ++i) { + for (i =3D 0; i < done_num; ++i) rxq->buffer_ring[rxq->processing_idx + i].mbuf =3D NULL; - } =20 l_end: return done_num; } =20 -STATIC inline s32 sxe_rx_bufs_batch_alloc(sxe_rx_queue_s *rxq, +static inline s32 sxe_rx_bufs_batch_alloc(sxe_rx_queue_s *rxq, bool reset_mbuf) { volatile union sxe_rx_data_desc *desc_ring; @@ -568,7 +561,7 @@ STATIC inline s32 sxe_rx_bufs_batch_alloc(sxe_rx_queue_= s *rxq, rxq->batch_alloc_trigger, rxq->batch_alloc_size); =20 diag =3D rte_mempool_get_bulk(rxq->mb_pool, (void *)buf_ring, - rxq->batch_alloc_size); + rxq->batch_alloc_size); if (unlikely(diag !=3D 0)) { LOG_DEBUG("port_id=3D%u, rxq=3D%u buffer alloc failed\n", rxq->port_id, rxq->queue_id); @@ -579,9 +572,8 @@ STATIC inline s32 sxe_rx_bufs_batch_alloc(sxe_rx_queue_= s *rxq, desc_ring =3D &rxq->desc_ring[alloc_idx]; for (i =3D 0; i < rxq->batch_alloc_size; ++i) { mbuf =3D buf_ring[i].mbuf; - if (reset_mbuf) { + if (reset_mbuf) mbuf->port =3D rxq->port_id; - } =20 rte_mbuf_refcnt_set(mbuf, 1); mbuf->data_off =3D RTE_PKTMBUF_HEADROOM; @@ -592,9 +584,8 @@ STATIC inline s32 sxe_rx_bufs_batch_alloc(sxe_rx_queue_= s *rxq, } =20 rxq->batch_alloc_trigger =3D rxq->batch_alloc_trigger + rxq->batch_alloc_= size; - if (rxq->batch_alloc_trigger >=3D rxq->ring_depth) { + if (rxq->batch_alloc_trigger >=3D rxq->ring_depth) rxq->batch_alloc_trigger =3D rxq->batch_alloc_size - 1; - } =20 l_end: return ret; @@ -629,7 +620,7 @@ static inline u16 sxe_burst_pkts_recv(void *rx_queue, u32 i, j; =20 LOG_ERROR("rx mbuf alloc failed port_id=3D%u " - "queue_id=3D%u", (unsigned) rxq->port_id, + "queue_id=3D%u", (unsigned int) rxq->port_id, (u16)rxq->queue_id); =20 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=3D @@ -637,9 +628,8 @@ static inline u16 sxe_burst_pkts_recv(void *rx_queue, =20 rxq->completed_pkts_num =3D 0; rxq->processing_idx =3D (u16)(rxq->processing_idx - done_num); - for (i =3D 0, j =3D rxq->processing_idx; i < done_num; ++i, ++j) { + for (i =3D 0, j =3D rxq->processing_idx; i < done_num; ++i, ++j) rxq->buffer_ring[j].mbuf =3D rxq->completed_ring[i]; - } =20 done_num =3D 0; goto l_end; @@ -649,9 +639,8 @@ static inline u16 sxe_burst_pkts_recv(void *rx_queue, SXE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr, alloced_idx); } =20 - if (rxq->processing_idx >=3D rxq->ring_depth) { + if (rxq->processing_idx >=3D rxq->ring_depth) rxq->processing_idx =3D 0; - } =20 if (rxq->completed_pkts_num) { done_num =3D sxe_ret_pkts_to_user(rxq, rx_pkts, pkts_num); @@ -690,9 +679,8 @@ u16 sxe_batch_alloc_pkts_recv(void *rx_queue, ret =3D sxe_burst_pkts_recv(rx_queue, &rx_pkts[done_num], n); done_num =3D (u16)(done_num + ret); pkts_num =3D (u16)(pkts_num - ret); - if (ret < n) { + if (ret < n) break; - } } =20 l_end: @@ -714,8 +702,7 @@ static inline s32 sxe_lro_new_mbufs_alloc(sxe_rx_queue_= s *rxq, "port_id=3D%u queue_id=3D%u", rxq->port_id, rxq->queue_id); =20 - rte_eth_devices[rxq->port_id].data-> - rx_mbuf_alloc_failed++; + rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++; ret =3D -ENOMEM; goto l_end; } @@ -736,8 +723,7 @@ static inline s32 sxe_lro_new_mbufs_alloc(sxe_rx_queue_= s *rxq, "port_id=3D%u queue_id=3D%u", rxq->port_id, rxq->queue_id); =20 - rte_eth_devices[rxq->port_id].data-> - rx_mbuf_alloc_failed++; + rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++; ret =3D -ENOMEM; goto l_end; } @@ -764,7 +750,6 @@ static inline void sxe_rx_resource_update(sxe_rx_buffer= _s *rx_buf, rx_buf->mbuf =3D NULL; } =20 - return; } =20 static inline u16 sxe_rx_next_idx_get(union sxe_rx_data_desc *desc, @@ -797,7 +782,6 @@ static inline void sxe_lro_first_seg_update(struct rte_= mbuf **first_seg, (*first_seg)->pkt_len +=3D data_len; (*first_seg)->nb_segs++; } - return; } =20 static inline void sxe_mbuf_fields_process(struct rte_mbuf *first_seg, @@ -816,9 +800,8 @@ static inline void sxe_mbuf_fields_process(struct rte_m= buf *first_seg, if (unlikely(cur_mbuf->data_len <=3D rxq->crc_len)) { struct rte_mbuf *lp; =20 - for (lp =3D first_seg; lp->next !=3D cur_mbuf; lp =3D lp->next) { + for (lp =3D first_seg; lp->next !=3D cur_mbuf; lp =3D lp->next) ; - } =20 first_seg->nb_segs--; lp->data_len -=3D rxq->crc_len - cur_mbuf->data_len; @@ -829,7 +812,6 @@ static inline void sxe_mbuf_fields_process(struct rte_m= buf *first_seg, } =20 rte_packet_prefetch((u8 *)first_seg->buf_addr + first_seg->data_off); - return; } =20 static inline u16 sxe_lro_pkts_recv(void *rx_queue, @@ -843,7 +825,7 @@ static inline u16 sxe_lro_pkts_recv(void *rx_queue, u16 cur_idx =3D rxq->processing_idx; u16 done_num =3D 0; u16 hold_num =3D rxq->hold_num; - u16 prev_idx =3D rxq->processing_idx;=20 + u16 prev_idx =3D rxq->processing_idx; s32 err; =20 while (done_num < pkts_num) { @@ -865,9 +847,8 @@ static inline u16 sxe_lro_pkts_recv(void *rx_queue, cur_desc =3D &desc_ring[cur_idx]; staterr =3D rte_le_to_cpu_32(cur_desc->wb.upper.status_error); =20 - if (!(staterr & SXE_RXDADV_STAT_DD)) { + if (!(staterr & SXE_RXDADV_STAT_DD)) break; - } =20 __atomic_thread_fence(__ATOMIC_ACQUIRE); =20 @@ -890,9 +871,8 @@ static inline u16 sxe_lro_pkts_recv(void *rx_queue, is_eop =3D !!(staterr & SXE_RXDADV_STAT_EOP); =20 next_idx =3D cur_idx + 1; - if (next_idx =3D=3D rxq->ring_depth) { + if (next_idx =3D=3D rxq->ring_depth) next_idx =3D 0; - } =20 sxe_rx_resource_prefetch(next_idx, buf_ring, desc_ring); =20 @@ -962,10 +942,10 @@ u16 sxe_single_alloc_lro_pkts_recv(void *rx_queue, return sxe_lro_pkts_recv(rx_queue, rx_pkts, pkts_num, false); } =20 -void __rte_cold sxe_rx_function_set(struct rte_eth_dev *dev, bool rx_batch= _alloc_allowed, bool *rx_vec_allowed) +void __rte_cold sxe_rx_function_set(struct rte_eth_dev *dev, + bool rx_batch_alloc_allowed, bool *rx_vec_allowed) { __sxe_rx_function_set(dev, rx_batch_alloc_allowed, rx_vec_allowed); - return; } =20 #ifdef ETH_DEV_RX_DESC_DONE @@ -985,9 +965,8 @@ s32 sxe_rx_descriptor_done(void *rx_queue, u16 offset) } =20 index =3D rxq->processing_idx + offset; - if (index >=3D rxq->ring_depth) { + if (index >=3D rxq->ring_depth) index -=3D rxq->ring_depth; - } =20 desc =3D &rxq->desc_ring[index]; is_done =3D !!(desc->wb.upper.status_error & @@ -1028,17 +1007,15 @@ s32 sxe_rx_descriptor_status(void *rx_queue, u16 of= fset) } =20 desc =3D rxq->processing_idx + offset; - if (desc >=3D rxq->ring_depth) { + if (desc >=3D rxq->ring_depth) desc -=3D rxq->ring_depth; - } =20 status =3D &rxq->desc_ring[desc].wb.upper.status_error; - if (*status & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD)) { + if (*status & rte_cpu_to_le_32(SXE_RXDADV_STAT_DD)) ret =3D RTE_ETH_RX_DESC_DONE; - } =20 l_end: - LOG_DEBUG("rx queue[%u] get desc status=3D%d\n",rxq->queue_id, ret); + LOG_DEBUG("rx queue[%u] get desc status=3D%d\n", rxq->queue_id, ret); return ret; } =20 @@ -1049,7 +1026,7 @@ s32 __rte_cold sxe_rx_queue_setup(struct rte_eth_dev = *dev, struct rte_mempool *mp) { struct sxe_adapter *adapter =3D dev->data->dev_private; - struct sxe_hw *hw =3D &adapter->hw; + struct sxe_hw *hw =3D &adapter->hw; struct rx_setup rx_setup =3D { 0 }; s32 ret; =20 @@ -1065,9 +1042,8 @@ s32 __rte_cold sxe_rx_queue_setup(struct rte_eth_dev = *dev, rx_setup.rx_batch_alloc_allowed =3D &adapter->rx_batch_alloc_allowed; =20 ret =3D __sxe_rx_queue_setup(&rx_setup, false); - if (ret) { + if (ret) LOG_ERROR_BDF("rx queue setup fail.(err:%d)", ret); - } =20 return ret; } @@ -1083,7 +1059,6 @@ static void sxe_rx_mode_configure(struct sxe_hw *hw) flt_ctrl |=3D SXE_FCTRL_PMCF; LOG_DEBUG("write flt_ctrl=3D0x%x", flt_ctrl); sxe_hw_rx_mode_set(hw, flt_ctrl); - return; } =20 static inline void @@ -1096,63 +1071,52 @@ static inline void for (i =3D 0; i < dev->data->nb_rx_queues; i++) { rxq =3D dev->data->rx_queues[i]; =20 - if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) { + if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) rxq->crc_len =3D RTE_ETHER_CRC_LEN; - } else { + else rxq->crc_len =3D 0; - } =20 - rxq->offloads |=3D RTE_ETH_RX_OFFLOAD_VLAN_STRIP; + if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { + rx_conf->offloads |=3D RTE_ETH_RX_OFFLOAD_VLAN_STRIP; + } } =20 - return; } =20 static inline void sxe_rx_offload_configure(struct rte_eth_dev *dev) { struct sxe_adapter *adapter =3D dev->data->dev_private; - struct sxe_hw *hw =3D &adapter->hw; + struct sxe_hw *hw =3D &adapter->hw; struct rte_eth_rxmode *rx_conf =3D &dev->data->dev_conf.rxmode; - bool crc_strp_on; bool ip_csum_offload; =20 - if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) { - crc_strp_on =3D false; - } else { - crc_strp_on =3D true; - } - sxe_hw_rx_dma_ctrl_init(hw, crc_strp_on); + sxe_hw_rx_dma_ctrl_init(hw); =20 #if defined DPDK_20_11_5 || defined DPDK_19_11_6 - if (rx_conf->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { + if (rx_conf->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) adapter->mtu =3D rx_conf->max_rx_pkt_len - SXE_ETH_OVERHEAD; - } #else - if (dev->data->mtu > RTE_ETHER_MTU) { + if (dev->data->mtu > RTE_ETHER_MTU) adapter->mtu =3D dev->data->mtu; - } #endif =20 - rx_conf->offloads |=3D RTE_ETH_RX_OFFLOAD_VLAN_STRIP; + rx_conf->offloads &=3D ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP; =20 - if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { + if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) dev->data->scattered_rx =3D 1; - } =20 sxe_hw_rx_udp_frag_checksum_disable(hw); =20 - if (rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM) { + if (rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM) ip_csum_offload =3D true; - } else { + else ip_csum_offload =3D false; - } =20 sxe_hw_rx_ip_checksum_offload_switch(hw, ip_csum_offload); =20 sxe_rx_queue_offload_configure(dev); =20 - return; } =20 static inline void sxe_rx_queue_attr_configure( @@ -1160,7 +1124,7 @@ static inline void sxe_rx_queue_attr_configure( sxe_rx_queue_s *queue) { struct sxe_adapter *adapter =3D dev->data->dev_private; - struct sxe_hw *hw =3D &adapter->hw; + struct sxe_hw *hw =3D &adapter->hw; u32 srrctl_size; u64 desc_dma_addr; u32 desc_mem_len; @@ -1182,9 +1146,8 @@ static inline void sxe_rx_queue_attr_configure( sxe_hw_rx_rcv_ctl_configure(hw, reg_idx, SXE_LRO_HDR_SIZE, buf_size); =20 - if (queue->drop_en) { + if (queue->drop_en) sxe_hw_rx_drop_switch(hw, reg_idx, true); - } =20 sxe_hw_rx_desc_thresh_set(hw, reg_idx); =20 @@ -1194,12 +1157,10 @@ static inline void sxe_rx_queue_attr_configure( buf_size =3D (u16) ((srrctl_size & SXE_SRRCTL_BSIZEPKT_MASK) << SXE_SRRCTL_BSIZEPKT_SHIFT); =20 - if (frame_size + 2 * SXE_VLAN_TAG_SIZE > buf_size) { + if (frame_size + 2 * SXE_VLAN_TAG_SIZE > buf_size) dev->data->scattered_rx =3D 1; - } =20 sxe_hw_rx_ring_switch(hw, reg_idx, true); - return; } =20 static inline void sxe_rx_queue_configure(struct rte_eth_dev *dev) @@ -1207,10 +1168,9 @@ static inline void sxe_rx_queue_configure(struct rte= _eth_dev *dev) u16 i; sxe_rx_queue_s **queue =3D (sxe_rx_queue_s **)dev->data->rx_queues; =20 - for (i =3D 0; i < dev->data->nb_rx_queues; i++) { + for (i =3D 0; i < dev->data->nb_rx_queues; i++) sxe_rx_queue_attr_configure(dev, queue[i]); - } - return; + } =20 static u32 sxe_lro_max_desc_get(struct rte_mempool *pool) @@ -1221,15 +1181,14 @@ static u32 sxe_lro_max_desc_get(struct rte_mempool = *pool) u16 maxdesc =3D RTE_IPV4_MAX_PKT_LEN / (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM); =20 - if (maxdesc >=3D 16) { + if (maxdesc >=3D 16) desc_num =3D SXE_LROCTL_MAXDESC_16; - } else if (maxdesc >=3D 8) { + else if (maxdesc >=3D 8) desc_num =3D SXE_LROCTL_MAXDESC_8; - } else if (maxdesc >=3D 4) { + else if (maxdesc >=3D 4) desc_num =3D SXE_LROCTL_MAXDESC_4; - } else { + else desc_num =3D SXE_LROCTL_MAXDESC_1; - } =20 return desc_num; } @@ -1250,9 +1209,8 @@ static s32 sxe_lro_sanity_check(struct rte_eth_dev *d= ev, bool *lro_capable) } =20 dev->dev_ops->dev_infos_get(dev, &dev_info); - if (dev_info.rx_offload_capa & RTE_ETH_RX_OFFLOAD_TCP_LRO) { + if (dev_info.rx_offload_capa & RTE_ETH_RX_OFFLOAD_TCP_LRO) *lro_capable =3D true; - } =20 if (!(*lro_capable) && (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)) { PMD_LOG_CRIT(INIT, "lro is requested on HW that doesn't " @@ -1274,18 +1232,15 @@ static void sxe_lro_hw_configure(struct sxe_hw *hw,= bool lro_capable, =20 sxe_hw_rx_dma_lro_ctrl_set(hw); =20 - if ((lro_capable) && (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)) { + if ((lro_capable) && (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)) is_enable =3D true; - } else { + else is_enable =3D false; - } =20 - if (is_enable) { + if (is_enable) sxe_hw_rx_nfs_filter_disable(hw); - } =20 sxe_hw_rx_lro_enable(hw, is_enable); - return; } =20 static void sxe_lro_irq_configure(struct sxe_hw *hw, u16 reg_idx, @@ -1293,12 +1248,11 @@ static void sxe_lro_irq_configure(struct sxe_hw *hw= , u16 reg_idx, { u32 irq_interval; =20 - irq_interval =3D SXE_EITR_INTERVAL_US(SXE_QUEUE_ITR_INTERVAL_DEFAULT); + irq_interval =3D SXE_EITR_INTERVAL_US(SXE_QUEUE_ITR_INTERVAL); sxe_hw_ring_irq_interval_set(hw, reg_idx, irq_interval); =20 sxe_hw_ring_irq_map(hw, false, reg_idx, irq_idx); =20 - return; } =20 static void sxe_lro_hw_queue_configure(struct rte_eth_dev *dev, @@ -1317,13 +1271,12 @@ static void sxe_lro_hw_queue_configure(struct rte_e= th_dev *dev, sxe_lro_irq_configure(hw, reg_idx, i); } =20 - return; } =20 static s32 sxe_lro_configure(struct rte_eth_dev *dev) { struct sxe_adapter *adapter =3D dev->data->dev_private; - struct sxe_hw *hw =3D &adapter->hw; + struct sxe_hw *hw =3D &adapter->hw; struct rte_eth_rxmode *rx_conf =3D &dev->data->dev_conf.rxmode; bool lro_capable =3D false; =20 @@ -1365,7 +1318,7 @@ static s32 __rte_cold sxe_rx_start(struct rte_eth_dev= *dev) if (!rxq->deferred_start) { ret =3D sxe_rx_queue_start(dev, i); if (ret < 0) { - PMD_LOG_ERR(INIT, "rx queue[%u] start failed",i); + PMD_LOG_ERR(INIT, "rx queue[%u] start failed", i); goto l_end; } } @@ -1378,7 +1331,7 @@ static s32 __rte_cold sxe_rx_start(struct rte_eth_dev= *dev) s32 __rte_cold sxe_rx_configure(struct rte_eth_dev *dev) { struct sxe_adapter *adapter =3D dev->data->dev_private; - struct sxe_hw *hw =3D &adapter->hw; + struct sxe_hw *hw =3D &adapter->hw; s32 ret; =20 PMD_INIT_FUNC_TRACE(); @@ -1402,7 +1355,8 @@ s32 __rte_cold sxe_rx_configure(struct rte_eth_dev *d= ev) } =20 #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD - sxe_rx_function_set(dev, adapter->rx_batch_alloc_allowed, &adapter->rx_ve= c_allowed); + sxe_rx_function_set(dev, adapter->rx_batch_alloc_allowed, + &adapter->rx_vec_allowed); #else sxe_rx_function_set(dev, adapter->rx_batch_alloc_allowed, NULL); #endif @@ -1419,34 +1373,28 @@ s32 __rte_cold sxe_rx_configure(struct rte_eth_dev = *dev) =20 static void sxe_vmdq_rx_mode_get(u32 rx_mask, u32 *orig_val) { - if (rx_mask & RTE_ETH_VMDQ_ACCEPT_UNTAG) { + if (rx_mask & RTE_ETH_VMDQ_ACCEPT_UNTAG) *orig_val |=3D SXE_VMOLR_AUPE; - } =20 - if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_MC) { + if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_MC) *orig_val |=3D SXE_VMOLR_ROMPE; - } =20 - if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_UC) { + if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_UC) *orig_val |=3D SXE_VMOLR_ROPE; - } =20 - if (rx_mask & RTE_ETH_VMDQ_ACCEPT_BROADCAST) { + if (rx_mask & RTE_ETH_VMDQ_ACCEPT_BROADCAST) *orig_val |=3D SXE_VMOLR_BAM; - } =20 - if (rx_mask & RTE_ETH_VMDQ_ACCEPT_MULTICAST) { + if (rx_mask & RTE_ETH_VMDQ_ACCEPT_MULTICAST) *orig_val |=3D SXE_VMOLR_MPE; - } =20 - return; } =20 static void sxe_vmdq_rx_hw_configure(struct rte_eth_dev *dev) { struct rte_eth_vmdq_rx_conf *cfg; struct sxe_adapter *adapter =3D dev->data->dev_private; - struct sxe_hw *hw =3D &adapter->hw; + struct sxe_hw *hw =3D &adapter->hw; enum rte_eth_nb_pools pools_num; u32 rx_mode =3D 0; u16 i; @@ -1472,11 +1420,9 @@ static void sxe_vmdq_rx_hw_configure(struct rte_eth_= dev *dev) cfg->pool_map[i].pools); } =20 - if (cfg->enable_loop_back) { + if (cfg->enable_loop_back) sxe_hw_vmdq_loopback_configure(hw); - } =20 - return; } =20 s32 sxe_rx_features_configure(struct rte_eth_dev *dev) @@ -1530,8 +1476,8 @@ s32 sxe_rx_features_configure(struct rte_eth_dev *dev) } =20 LOG_INFO("pool num:%u rx mq_mode:0x%x configure result:%d.", - RTE_ETH_DEV_SRIOV(dev).active, - dev->data->dev_conf.rxmode.mq_mode, ret); + RTE_ETH_DEV_SRIOV(dev).active, + dev->data->dev_conf.rxmode.mq_mode, ret); =20 return ret; } diff --git a/drivers/net/sxe/pf/sxe_rx.h b/drivers/net/sxe/pf/sxe_rx.h index 7322a54a2c..19854d4cf4 100644 --- a/drivers/net/sxe/pf/sxe_rx.h +++ b/drivers/net/sxe/pf/sxe_rx.h @@ -14,10 +14,10 @@ #define SXE_RXDADV_ERR_CKSUM_BIT 30 #define SXE_RXDADV_ERR_CKSUM_MSK 3 =20 -#define SXE_PACKET_TYPE_MAX 0X80 -#define SXE_PACKET_TYPE_TN_MAX 0X100 -#define SXE_PACKET_TYPE_MASK 0X7F -#define SXE_RXD_STAT_TMST 0x10000=20=20=20 +#define SXE_PACKET_TYPE_MAX 0X80 +#define SXE_PACKET_TYPE_TN_MAX 0X100 +#define SXE_PACKET_TYPE_MASK 0X7F +#define SXE_RXD_STAT_TMST 0x10000 =20 #define SXE_DESCS_PER_LOOP 4 =20 @@ -40,9 +40,8 @@ static inline u64 sxe_rx_desc_status_to_pkt_flags(u32 rx_= status, pkt_flags =3D (rx_status & SXE_RXD_STAT_VP) ? vlan_flags : 0; =20 #ifdef RTE_LIBRTE_IEEE1588 - if (rx_status & SXE_RXD_STAT_TMST) { + if (rx_status & SXE_RXD_STAT_TMST) pkt_flags =3D pkt_flags | RTE_MBUF_F_RX_IEEE1588_TMST; - } #endif return pkt_flags; } @@ -62,7 +61,7 @@ static inline u64 sxe_rx_desc_error_to_pkt_flags(u32 rx_s= tatus) SXE_RXDADV_ERR_CKSUM_BIT) & SXE_RXDADV_ERR_CKSUM_MSK]; =20 if ((rx_status & SXE_RXD_STAT_OUTERIPCS) && - (rx_status & SXE_RXDADV_ERR_OUTERIPER)) { + (rx_status & SXE_RXDADV_ERR_OUTERIPER)) { pkt_flags |=3D RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD; } =20 @@ -101,9 +100,8 @@ static inline u32 sxe_rxd_pkt_info_to_pkt_type(u32 pkt_= info, u16 ptype_mask) { =20 - if (unlikely(pkt_info & SXE_RXDADV_PKTTYPE_ETQF)) { + if (unlikely(pkt_info & SXE_RXDADV_PKTTYPE_ETQF)) return RTE_PTYPE_UNKNOWN; - } =20 pkt_info =3D (pkt_info >> SXE_RXDADV_PKTTYPE_ETQF_SHIFT) & ptype_mask; =20 @@ -126,21 +124,21 @@ static inline bool __rte_cold =20 if (!(rxq->batch_alloc_size >=3D RTE_PMD_SXE_MAX_RX_BURST)) { PMD_LOG_DEBUG(INIT, "rx burst batch alloc check: " - "rxq->batch_alloc_size=3D%d, " - "RTE_PMD_SXE_MAX_RX_BURST=3D%d", - rxq->batch_alloc_size, RTE_PMD_SXE_MAX_RX_BURST); + "rxq->batch_alloc_size=3D%d, " + "RTE_PMD_SXE_MAX_RX_BURST=3D%d", + rxq->batch_alloc_size, RTE_PMD_SXE_MAX_RX_BURST); support =3D false; } else if (!(rxq->batch_alloc_size < rxq->ring_depth)) { PMD_LOG_DEBUG(INIT, "rx burst batch alloc check: " - "rxq->batch_alloc_size=3D%d, " - "rxq->ring_depth=3D%d", - rxq->batch_alloc_size, rxq->ring_depth); + "rxq->batch_alloc_size=3D%d, " + "rxq->ring_depth=3D%d", + rxq->batch_alloc_size, rxq->ring_depth); support =3D false; } else if (!((rxq->ring_depth % rxq->batch_alloc_size) =3D=3D 0)) { PMD_LOG_DEBUG(INIT, "rx burst batch alloc preconditions: " - "rxq->nb_rx_desc=3D%d, " - "rxq->batch_alloc_size=3D%d", - rxq->ring_depth, rxq->batch_alloc_size); + "rxq->nb_rx_desc=3D%d, " + "rxq->batch_alloc_size=3D%d", + rxq->ring_depth, rxq->batch_alloc_size); support =3D false; } =20 @@ -149,7 +147,8 @@ static inline bool __rte_cold =20 s32 sxe_rx_configure(struct rte_eth_dev *dev); =20 -void sxe_rx_function_set(struct rte_eth_dev *dev, bool rx_batch_alloc_allo= wed, bool *rx_vec_allowed); +void sxe_rx_function_set(struct rte_eth_dev *dev, + bool rx_batch_alloc_allowed, bool *rx_vec_allowed); =20 #ifdef ETH_DEV_RX_DESC_DONE s32 sxe_rx_descriptor_done(void *rx_queue, u16 offset); @@ -157,10 +156,10 @@ s32 sxe_rx_descriptor_done(void *rx_queue, u16 offset= ); =20 s32 sxe_rx_descriptor_status(void *rx_queue, u16 offset); =20 -u16 sxe_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts,u16 num_pkts); +u16 sxe_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts, u16 num_pkts); =20 s32 sxe_rx_queue_setup(struct rte_eth_dev *dev, - u16 queue_idx,u16 num_desc, + u16 queue_idx, u16 num_desc, unsigned int socket_id, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp); diff --git a/drivers/net/sxe/pf/sxe_stats.c b/drivers/net/sxe/pf/sxe_stats.c index 5d9de2991c..9e1943336d 100644 --- a/drivers/net/sxe/pf/sxe_stats.c +++ b/drivers/net/sxe/pf/sxe_stats.c @@ -14,8 +14,7 @@ #define SXE_STAT_MAP_CNT 4 #define SXE_STAT_MAP_MASK 0x0F =20 -#define SXE_QUEUE_STAT_COUNT \ - (sizeof(stats_info->hw_stats.qprc) / sizeof(stats_info->hw_stats.qprc[= 0])) +#define SXE_QUEUE_STAT_COUNT ARRAY_SIZE(stats_info->hw_stats.qprc) =20 static const struct sxe_stats_field sxe_xstats_sw_field[] =3D { {"rx_l3_l4_xsum_error", offsetof(struct sxe_sw_stats, @@ -75,10 +74,10 @@ static const struct sxe_stats_field sxe_xstats_fc_field= [] =3D { }; =20 #define SXE_XSTAT_SW_CNT (sizeof(sxe_xstats_sw_field) / \ - sizeof(sxe_xstats_sw_field[0])) + sizeof(sxe_xstats_sw_field[0])) =20 #define SXE_XSTAT_MAC_CNT (sizeof(sxe_xstats_mac_field) / \ - sizeof(sxe_xstats_mac_field[0])) + sizeof(sxe_xstats_mac_field[0])) =20 #define SXE_XSTAT_FC_CNT (sizeof(sxe_xstats_fc_field) / \ sizeof(sxe_xstats_fc_field[0])) @@ -102,8 +101,8 @@ s32 sxe_eth_stats_get(struct rte_eth_dev *eth_dev, struct sxe_stats_info *stats_info =3D &adapter->stats_info; struct sxe_hw *hw =3D &adapter->hw; u32 i; - u64 rx_packets =3D 0;=20 - u64 rx_bytes =3D 0;=20=20=20 + u64 rx_packets =3D 0; + u64 rx_bytes =3D 0; s32 ret =3D 0; =20 sxe_hw_stats_get(hw, &stats_info->hw_stats); @@ -117,7 +116,7 @@ s32 sxe_eth_stats_get(struct rte_eth_dev *eth_dev, for (i =3D 0; i < SXE_QUEUE_STAT_COUNT; i++) { rx_packets +=3D stats_info->hw_stats.qprc[i]; rx_bytes +=3D stats_info->hw_stats.qbrc[i]; -=09 + stats->q_ipackets[i] =3D stats_info->hw_stats.qprc[i]; stats->q_opackets[i] =3D stats_info->hw_stats.qptc[i]; stats->q_ibytes[i] =3D stats_info->hw_stats.qbrc[i]; @@ -153,7 +152,7 @@ static s32 sxe_hw_xstat_offset_get(u32 id, u32 *offset) } else { ret =3D -SXE_ERR_PARAM; PMD_LOG_ERR(DRV, "invalid id:%u exceed stats size cnt:%u.", - id, size); + id, size); } =20 return ret; @@ -169,7 +168,7 @@ static s32 sxe_sw_xstat_offset_get(u32 id, u32 *offset) } else { ret =3D -SXE_ERR_PARAM; PMD_LOG_ERR(DRV, "invalid id:%u exceed stats size cnt:%u.", - id, size); + id, size); } =20 return ret; @@ -185,26 +184,25 @@ static s32 sxe_fc_xstat_field_offset_get(u32 id, u8 p= riority, u32 *offset) } else { ret =3D -SXE_ERR_PARAM; PMD_LOG_ERR(DRV, "invalid id:%u exceed stats size cnt:%u.", - id, size); + id, size); } =20 return ret; } =20 -static void sxe_sw_stats_get(struct rte_eth_dev *eth_dev,=20 +static void sxe_sw_stats_get(struct rte_eth_dev *eth_dev, struct sxe_sw_stats *stats) { u32 i; u64 hw_csum_rx_error =3D 0; sxe_rx_queue_s *rxq; -=09 + for (i =3D 0; i < eth_dev->data->nb_rx_queues; i++) { rxq =3D eth_dev->data->rx_queues[i]; hw_csum_rx_error +=3D rxq->rx_stats.csum_err; } stats->hw_csum_rx_error =3D hw_csum_rx_error; =20 - return; } =20 s32 sxe_xstats_get(struct rte_eth_dev *eth_dev, @@ -222,14 +220,14 @@ s32 sxe_xstats_get(struct rte_eth_dev *eth_dev, =20 cnt =3D SXE_XSTAT_CNT; PMD_LOG_INFO(DRV, "xstat size:%u. hw xstat field cnt:%lu " - "fc xstat field cnt:%lu ", cnt, - SXE_XSTAT_MAC_CNT, - SXE_XSTAT_FC_CNT); + "fc xstat field cnt:%lu ", cnt, + SXE_XSTAT_MAC_CNT, + SXE_XSTAT_FC_CNT); =20 if (usr_cnt < cnt) { ret =3D cnt; PMD_LOG_ERR(DRV, "user usr_cnt:%u less than stats cnt:%u.", - usr_cnt, cnt); + usr_cnt, cnt); goto l_out; } =20 @@ -336,7 +334,7 @@ s32 sxe_xstats_names_get(__rte_unused struct rte_eth_de= v *dev, if (usr_cnt < SXE_XSTAT_CNT) { ret =3D -SXE_ERR_PARAM; PMD_LOG_ERR(DRV, "max:%lu usr_cnt:%u invalid.(err:%d)", - SXE_XSTAT_CNT, usr_cnt, ret); + SXE_XSTAT_CNT, usr_cnt, ret); goto l_out; } =20 @@ -385,8 +383,8 @@ static s32 sxe_all_xstats_value_get(struct rte_eth_dev = *eth_dev, =20 if (usr_cnt < size) { PMD_LOG_WARN(DRV, "ids null usr_cnt:%u less than xstats" - " cnt:%u, return xstat cnt.", - usr_cnt, size); + " cnt:%u, return xstat cnt.", + usr_cnt, size); ret =3D size; goto l_out; } @@ -396,7 +394,7 @@ static s32 sxe_all_xstats_value_get(struct rte_eth_dev = *eth_dev, =20 if (values =3D=3D NULL) { PMD_LOG_WARN(DRV, "ids and values null, " - "read clean stats regs"); + "read clean stats regs"); ret =3D 0; goto l_out; } @@ -523,19 +521,18 @@ s32 sxe_queue_stats_mapping_set(struct rte_eth_dev *e= th_dev, if (reg_idx >=3D SXE_QUEUE_STATS_MAP_REG_NUM) { ret =3D -EIO; PMD_LOG_ERR(DRV, "invalid queue_id:%u reg_idx exceeded " - "max map cnt:%u.(err:%d)", - queue_id, SXE_QUEUE_STATS_MAP_REG_NUM, ret); + "max map cnt:%u.(err:%d)", + queue_id, SXE_QUEUE_STATS_MAP_REG_NUM, ret); goto l_out; } =20 map_idx =3D (u8)(queue_id % SXE_STAT_MAP_CNT); map_mask <<=3D (SXE_STAT_MAP_WIDTH * map_idx); =20 - if (!is_rx) { + if (!is_rx) stats_map->txq_stats_map[reg_idx] &=3D ~map_mask; - } else { + else stats_map->rxq_stats_map[reg_idx] &=3D ~map_mask; - } =20 qsmr_mask =3D (stat_reg_idx & SXE_STAT_MAP_MASK) << (SXE_STAT_MAP_WIDTH *= map_idx); if (!is_rx) { @@ -547,12 +544,12 @@ s32 sxe_queue_stats_mapping_set(struct rte_eth_dev *e= th_dev, } =20 PMD_LOG_INFO(DRV, "port %u %s queue_id %d stat map to stat reg[%u] " - "%s[%u] 0x%08x ", - (u16)(eth_dev->data->port_id), is_rx ? "RX" : "TX", - queue_id, stat_reg_idx, - is_rx ? "RQSMR" : "TQSM", reg_idx, - is_rx ? stats_map->rxq_stats_map[reg_idx] : - stats_map->txq_stats_map[reg_idx]); + "%s[%u] 0x%08x ", + (u16)(eth_dev->data->port_id), is_rx ? "RX" : "TX", + queue_id, stat_reg_idx, + is_rx ? "RQSMR" : "TQSM", reg_idx, + is_rx ? stats_map->rxq_stats_map[reg_idx] : + stats_map->txq_stats_map[reg_idx]); =20 l_out: return ret; @@ -570,7 +567,6 @@ void sxe_queue_stats_map_restore(struct rte_eth_dev *et= h_dev) sxe_hw_rxq_stat_map_set(hw, reg_idx, stats_map->rxq_stats_map[reg_idx]); } =20 - return; } =20 void sxe_queue_stats_map_reset(struct rte_eth_dev *eth_dev) @@ -588,6 +584,5 @@ void sxe_queue_stats_map_reset(struct rte_eth_dev *eth_= dev) sxe_hw_rxq_stat_map_set(hw, reg_idx, 0); } =20 - return; } =20 diff --git a/drivers/net/sxe/pf/sxe_stats.h b/drivers/net/sxe/pf/sxe_stats.h index 792a160753..8be0ce9448 100644 --- a/drivers/net/sxe/pf/sxe_stats.h +++ b/drivers/net/sxe/pf/sxe_stats.h @@ -14,7 +14,7 @@ #define SXE_STATS_FIELD_NAME_SIZE 50 =20 struct sxe_sw_stats { - u64 hw_csum_rx_error;=20=20 + u64 hw_csum_rx_error; }; =20 struct sxe_stats_map { @@ -23,9 +23,9 @@ struct sxe_stats_map { }; =20 struct sxe_stats_info { - struct sxe_sw_stats sw_stats;=20=20 - struct sxe_mac_stats hw_stats;=20=20=09 - struct sxe_stats_map stats_map;=20 + struct sxe_sw_stats sw_stats; + struct sxe_mac_stats hw_stats; + struct sxe_stats_map stats_map; }; =20 struct sxe_stats_field { diff --git a/drivers/net/sxe/pf/sxe_tm.c b/drivers/net/sxe/pf/sxe_tm.c new file mode 100644 index 0000000000..4a87f255be --- /dev/null +++ b/drivers/net/sxe/pf/sxe_tm.c @@ -0,0 +1,1115 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ + +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_TM + +#include +#include "rte_ethdev.h" +#include "rte_tm_driver.h" +#include "rte_tm.h" +#include "sxe_dpdk_version.h" +#if defined(DPDK_20_11_5) || defined(DPDK_21_11_5) || defined(DPDK_19_11_6) +#include +#else +#include +#endif + +#include "sxe.h" +#include "sxe_logs.h" +#include "sxe_hw.h" +#include "sxe_queue.h" + +void sxe_tm_ctxt_init(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_tm_context *tm_ctxt =3D &adapter->tm_ctxt; + + TAILQ_INIT(&tm_ctxt->shaper_profile_list); + + tm_ctxt->root =3D NULL; + TAILQ_INIT(&tm_ctxt->queue_list); + TAILQ_INIT(&tm_ctxt->tc_list); + tm_ctxt->tc_node_num =3D 0; + tm_ctxt->queue_node_num =3D 0; + tm_ctxt->committed =3D false; + +} + +void sxe_tm_ctxt_uninit(struct rte_eth_dev *dev) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_tm_context *tm_ctxt =3D &adapter->tm_ctxt; + + struct sxe_tm_shaper_profile *shaper_profile; + struct sxe_tm_node *tm_node; + + while ((tm_node =3D TAILQ_FIRST(&tm_ctxt->queue_list))) { + TAILQ_REMOVE(&tm_ctxt->queue_list, tm_node, node); + rte_free(tm_node); + } + tm_ctxt->queue_node_num =3D 0; + + while ((tm_node =3D TAILQ_FIRST(&tm_ctxt->tc_list))) { + TAILQ_REMOVE(&tm_ctxt->tc_list, tm_node, node); + rte_free(tm_node); + } + tm_ctxt->tc_node_num =3D 0; + + if (tm_ctxt->root) { + rte_free(tm_ctxt->root); + tm_ctxt->root =3D NULL; + } + + while ((shaper_profile =3D TAILQ_FIRST(&tm_ctxt->shaper_profile_list))) { + TAILQ_REMOVE(&tm_ctxt->shaper_profile_list, shaper_profile, node); + rte_free(shaper_profile); + } + +} + +static inline u8 sxe_tcs_num_get(struct rte_eth_dev *dev) +{ + struct rte_eth_conf *eth_conf; + u8 tcs_num =3D 0; + + eth_conf =3D &dev->data->dev_conf; + if (eth_conf->txmode.mq_mode =3D=3D RTE_ETH_MQ_TX_DCB) { + tcs_num =3D eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs; + } else if (eth_conf->txmode.mq_mode =3D=3D RTE_ETH_MQ_TX_VMDQ_DCB) { + if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools =3D=3D + RTE_ETH_32_POOLS) { + tcs_num =3D RTE_ETH_4_TCS; + } else { + tcs_num =3D RTE_ETH_8_TCS; + } + } else { + tcs_num =3D 1; + } + + return tcs_num; +} + +static s32 sxe_capabilities_get(struct rte_eth_dev *dev, + struct rte_tm_capabilities *cap, + struct rte_tm_error *error) +{ + UNUSED(dev); + s32 ret =3D 0; + + if (!cap || !error) { + PMD_LOG_ERR(DRV, "sxe get tm cap failed, cap or error is NULL"); + ret =3D -EINVAL; + goto l_end; + } + + error->type =3D RTE_TM_ERROR_TYPE_NONE; + memset(cap, 0, sizeof(struct rte_tm_capabilities)); + + cap->n_nodes_max =3D 1 + MAX_TRAFFIC_CLASS + SXE_HW_TXRX_RING_NUM_MAX; + + cap->n_levels_max =3D 3; + cap->non_leaf_nodes_identical =3D 1; + cap->leaf_nodes_identical =3D 1; + cap->shaper_n_max =3D cap->n_nodes_max; + cap->shaper_private_n_max =3D cap->n_nodes_max; + cap->shaper_private_dual_rate_n_max =3D 0; + cap->shaper_private_rate_min =3D 0; + cap->shaper_private_rate_max =3D 1250000000ull; +#ifndef DPDK_19_11_6 + cap->shaper_private_packet_mode_supported =3D 0; + cap->shaper_private_byte_mode_supported =3D 1; +#endif + + cap->shaper_shared_n_max =3D 0; + cap->shaper_shared_n_nodes_per_shaper_max =3D 0; + cap->shaper_shared_n_shapers_per_node_max =3D 0; + cap->shaper_shared_dual_rate_n_max =3D 0; + cap->shaper_shared_rate_min =3D 0; + cap->shaper_shared_rate_max =3D 0; +#ifndef DPDK_19_11_6 + cap->shaper_shared_packet_mode_supported =3D 0; + cap->shaper_shared_byte_mode_supported =3D 0; +#endif + cap->sched_n_children_max =3D SXE_HW_TXRX_RING_NUM_MAX; + + cap->sched_sp_n_priorities_max =3D 1; + cap->sched_wfq_n_children_per_group_max =3D 0; + cap->sched_wfq_n_groups_max =3D 0; +#ifndef DPDK_19_11_6 + cap->sched_wfq_packet_mode_supported =3D 0; + cap->sched_wfq_byte_mode_supported =3D 0; +#endif + cap->sched_wfq_weight_max =3D 1; + cap->cman_head_drop_supported =3D 0; + cap->dynamic_update_mask =3D 0; + cap->shaper_pkt_length_adjust_min =3D RTE_TM_ETH_FRAMING_OVERHEAD; + cap->shaper_pkt_length_adjust_max =3D RTE_TM_ETH_FRAMING_OVERHEAD_FCS; + cap->cman_wred_context_n_max =3D 0; + cap->cman_wred_context_private_n_max =3D 0; + cap->cman_wred_context_shared_n_max =3D 0; + cap->cman_wred_context_shared_n_nodes_per_context_max =3D 0; + cap->cman_wred_context_shared_n_contexts_per_node_max =3D 0; + cap->stats_mask =3D 0; + +l_end: + return ret; +} + +static s32 sxe_shaper_profile_param_check( + struct rte_tm_shaper_params *profile, + struct rte_tm_error *error) +{ + s32 ret =3D -EINVAL; + + if (profile->committed.rate) { + error->type =3D RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_RATE; + error->message =3D "committed rate not supported"; + goto l_end; + } + + if (profile->committed.size) { + error->type =3D RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_SIZE; + error->message =3D "committed bucket size not supported"; + goto l_end; + } + + if (profile->peak.size) { + error->type =3D RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_SIZE; + error->message =3D "peak bucket size not supported"; + goto l_end; + } + + if (profile->pkt_length_adjust) { + error->type =3D RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PKT_ADJUST_LEN; + error->message =3D "packet length adjustment not supported"; + goto l_end; + } + + ret =3D 0; +l_end: + return ret; +} + +static inline struct sxe_tm_shaper_profile *sxe_shaper_profile_search( + struct rte_eth_dev *dev, + u32 id) +{ + struct sxe_tm_shaper_profile *profile =3D NULL; + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_tm_context *tm_ctxt =3D &adapter->tm_ctxt; + struct sxe_shaper_profile_list *shaper_profile_list =3D + &tm_ctxt->shaper_profile_list; + struct sxe_tm_shaper_profile *shaper_profile; + + TAILQ_FOREACH(shaper_profile, shaper_profile_list, node) { + if (id =3D=3D shaper_profile->id) { + profile =3D shaper_profile; + PMD_LOG_DEBUG(DRV, "got shaper_profile in idx[%u]", id); + } + } + + return profile; +} + +static s32 sxe_shaper_profile_add(struct rte_eth_dev *dev, + u32 id, + struct rte_tm_shaper_params *profile, + struct rte_tm_error *error) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_tm_context *tm_ctxt =3D &adapter->tm_ctxt; + struct sxe_tm_shaper_profile *shaper_profile; + s32 ret; + + if (!profile || !error) { + ret =3D -EINVAL; + PMD_LOG_ERR(DRV, "shaper profile add failed, profile or error NULL"); + goto l_end; + } + + ret =3D sxe_shaper_profile_param_check(profile, error); + if (ret) { + PMD_LOG_ERR(DRV, "sxe_shaper_profile_param_check err=3D%d", ret); + goto l_end; + } + + shaper_profile =3D sxe_shaper_profile_search(dev, id); + if (shaper_profile) { + error->type =3D RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID; + error->message =3D "profile ID exist"; + ret =3D -EINVAL; + goto l_end; + } + + shaper_profile =3D rte_zmalloc("sxe_tm_shaper_profile", + sizeof(struct sxe_tm_shaper_profile), + 0); + if (!shaper_profile) { + ret =3D -ENOMEM; + PMD_LOG_ERR(DRV, "shaper profile id[%u] alloc mem failed", + id); + goto l_end; + } + + shaper_profile->id =3D id; + rte_memcpy(&shaper_profile->profile, profile, + sizeof(struct rte_tm_shaper_params)); + TAILQ_INSERT_TAIL(&tm_ctxt->shaper_profile_list, + shaper_profile, node); + +l_end: + return ret; +} + +static s32 sxe_shaper_profile_del(struct rte_eth_dev *dev, + u32 id, + struct rte_tm_error *error) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_tm_context *tm_ctxt =3D &adapter->tm_ctxt; + struct sxe_tm_shaper_profile *shaper_profile; + s32 ret =3D -EINVAL; + + if (!error) { + PMD_LOG_ERR(DRV, "shaper profile del failed, error is NULL"); + goto l_end; + } + + shaper_profile =3D sxe_shaper_profile_search(dev, id); + if (!shaper_profile) { + error->type =3D RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID; + error->message =3D "profile ID not exist"; + goto l_end; + } + + if (shaper_profile->ref_cnt) { + error->type =3D RTE_TM_ERROR_TYPE_SHAPER_PROFILE; + error->message =3D "profile in use"; + goto l_end; + } + + TAILQ_REMOVE(&tm_ctxt->shaper_profile_list, shaper_profile, node); + rte_free(shaper_profile); + + ret =3D 0; + +l_end: + return ret; +} + +static inline s32 sxe_non_leaf_node_param_check( + struct rte_tm_node_params *params, + struct rte_tm_error *error) +{ + s32 ret =3D -EINVAL; + + + if (params->nonleaf.wfq_weight_mode) { + error->type =3D + RTE_TM_ERROR_TYPE_NODE_PARAMS_WFQ_WEIGHT_MODE; + error->message =3D "WFQ not supported"; + goto l_end; + } + + if (params->nonleaf.n_sp_priorities !=3D 1) { + error->type =3D + RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SP_PRIORITIES; + error->message =3D "SP priority not supported"; + goto l_end; + } + + ret =3D 0; +l_end: + return ret; +} + +static inline s32 sxe_leaf_node_param_check( + struct rte_tm_node_params *params, + struct rte_tm_error *error) +{ + s32 ret =3D -EINVAL; + + if (params->leaf.cman) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_PARAMS_CMAN; + error->message =3D "Congestion management not supported"; + goto l_end; + } + + if (params->leaf.wred.wred_profile_id !=3D RTE_TM_WRED_PROFILE_ID_NONE) { + error->type =3D + RTE_TM_ERROR_TYPE_NODE_PARAMS_WRED_PROFILE_ID; + error->message =3D "WRED not supported"; + goto l_end; + } + + if (params->leaf.wred.shared_wred_context_id) { + error->type =3D + RTE_TM_ERROR_TYPE_NODE_PARAMS_SHARED_WRED_CONTEXT_ID; + error->message =3D "WRED not supported"; + goto l_end; + } + + if (params->leaf.wred.n_shared_wred_contexts) { + error->type =3D + RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SHARED_WRED_CONTEXTS; + error->message =3D "WRED not supported"; + goto l_end; + } + + ret =3D 0; + +l_end: + return ret; +} + +static s32 sxe_node_param_check(struct rte_eth_dev *dev, u32 node_id, + u32 priority, u32 weight, u32 level_id, + struct rte_tm_node_params *params, + struct rte_tm_error *error) +{ + s32 ret =3D -EINVAL; + + if (node_id =3D=3D RTE_TM_NODE_ID_NULL) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "invalid node id"; + goto l_end; + } + + if (priority) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_PRIORITY; + error->message =3D "priority should be 0"; + goto l_end; + } + + if (weight !=3D 1) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_WEIGHT; + error->message =3D "weight must be 1"; + goto l_end; + } + + if (params->shared_shaper_id) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_PARAMS_SHARED_SHAPER_ID; + error->message =3D "shared shaper not supported"; + goto l_end; + } + + if (params->n_shared_shapers) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SHARED_SHAPERS; + error->message =3D "shared shaper not supported"; + goto l_end; + } + + if (node_id >=3D dev->data->nb_tx_queues && level_id !=3D SXE_TM_NODE_TYP= E_QUEUE) { + ret =3D sxe_non_leaf_node_param_check(params, error); + PMD_LOG_INFO(DRV, "non leaf param check ret=3D%d", ret); + goto l_end; + } + + ret =3D sxe_leaf_node_param_check(params, error); + PMD_LOG_INFO(DRV, "leaf param check ret=3D%d", ret); + +l_end: + return ret; +} + +static inline struct sxe_tm_node *sxe_tm_node_search( + struct rte_eth_dev *dev, u32 node_id, + enum sxe_tm_node_type *node_type) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_tm_context *tm_ctxt =3D &adapter->tm_ctxt; + struct sxe_tm_node *target_node =3D NULL; + struct sxe_tm_node *tmp_node =3D NULL; + + if (tm_ctxt->root && tm_ctxt->root->id =3D=3D node_id) { + *node_type =3D SXE_TM_NODE_TYPE_PORT; + target_node =3D tm_ctxt->root; + goto l_end; + } + + TAILQ_FOREACH(tmp_node, &tm_ctxt->tc_list, node) { + if (tmp_node->id =3D=3D node_id) { + *node_type =3D SXE_TM_NODE_TYPE_TC; + target_node =3D tmp_node; + goto l_end; + } + } + + TAILQ_FOREACH(tmp_node, &tm_ctxt->queue_list, node) { + if (tmp_node->id =3D=3D node_id) { + *node_type =3D SXE_TM_NODE_TYPE_QUEUE; + target_node =3D tmp_node; + } + } + +l_end: + return target_node; +} + +static void sxe_tc_owned_queues_get(struct rte_eth_dev *dev, + u16 tc_idx, u16 *base, u16 *num) +{ + u8 tcs_num =3D sxe_tcs_num_get(dev); + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); + u16 vf_num =3D pci_dev->max_vfs; + + *base =3D 0; + *num =3D 0; + + if (vf_num) { + if (tcs_num =3D=3D 1) { + if (vf_num >=3D RTE_ETH_32_POOLS) { + *num =3D 2; + *base =3D vf_num * 2; + } else if (vf_num >=3D RTE_ETH_16_POOLS) { + *num =3D 4; + *base =3D vf_num * 4; + } else { + *num =3D 8; + *base =3D vf_num * 8; + } + } else { + *num =3D 1; + *base =3D vf_num * tcs_num + tc_idx; + } + } else { + if (tcs_num =3D=3D RTE_ETH_8_TCS) { + switch (tc_idx) { + case 0: + *base =3D 0; + *num =3D 32; + break; + case 1: + *base =3D 32; + *num =3D 32; + break; + case 2: + *base =3D 64; + *num =3D 16; + break; + case 3: + *base =3D 80; + *num =3D 16; + break; + case 4: + *base =3D 96; + *num =3D 8; + break; + case 5: + *base =3D 104; + *num =3D 8; + break; + case 6: + *base =3D 112; + *num =3D 8; + break; + case 7: + *base =3D 120; + *num =3D 8; + break; + default: + return; + } + } else { + switch (tc_idx) { + case 0: + *base =3D 0; + *num =3D 64; + break; + case 1: + *base =3D 64; + *num =3D 32; + break; + case 2: + *base =3D 96; + *num =3D 16; + break; + case 3: + *base =3D 112; + *num =3D 16; + break; + default: + return; + } + } + } + +} + +static s32 sxe_node_add_param_check(struct rte_eth_dev *dev, u32 node_id, + u32 priority, u32 weight, u32 level_id, + struct rte_tm_node_params *params, + struct rte_tm_error *error) +{ + s32 ret; + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_tm_context *tm_ctxt =3D &adapter->tm_ctxt; + + if (!params || !error) { + ret =3D -EINVAL; + PMD_LOG_ERR(DRV, "node add failed because params or error NULL"); + goto l_end; + } + + if (tm_ctxt->committed) { + error->type =3D RTE_TM_ERROR_TYPE_UNSPECIFIED; + error->message =3D "already committed"; + ret =3D -EINVAL; + goto l_end; + } + + ret =3D sxe_node_param_check(dev, node_id, priority, weight, level_id, + params, error); + PMD_LOG_DEBUG(DRV, "sxe_node_param_check ret=3D%d", ret); + +l_end: + return ret; +} + +static s32 sxe_node_add(struct rte_eth_dev *dev, u32 node_id, + u32 parent_node_id, u32 priority, + u32 weight, u32 level_id, + struct rte_tm_node_params *params, + struct rte_tm_error *error) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_tm_context *tm_ctxt =3D &adapter->tm_ctxt; + + enum sxe_tm_node_type node_type =3D SXE_TM_NODE_TYPE_MAX; + enum sxe_tm_node_type parent_node_type =3D SXE_TM_NODE_TYPE_MAX; + struct sxe_tm_shaper_profile *shaper_profile =3D NULL; + struct sxe_tm_node *tm_node; + struct sxe_tm_node *parent_node; + u8 tcs_num; + u16 q_base =3D 0; + u16 q_nb =3D 0; + s32 ret; + + ret =3D sxe_node_add_param_check(dev, node_id, priority, weight, level_id, + params, error); + if (ret) { + PMD_LOG_ERR(DRV, "sxe_node_add_param_check err =3D %d", ret); + goto l_end; + } + + ret =3D -EINVAL; + if (sxe_tm_node_search(dev, node_id, &node_type)) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "node id already used"; + goto l_end; + } + + if (params->shaper_profile_id !=3D RTE_TM_SHAPER_PROFILE_ID_NONE) { + shaper_profile =3D sxe_shaper_profile_search( + dev, params->shaper_profile_id); + if (!shaper_profile) { + error->type =3D + RTE_TM_ERROR_TYPE_NODE_PARAMS_SHAPER_PROFILE_ID; + error->message =3D "shaper profile not exist"; + goto l_end; + } + } + + if (parent_node_id =3D=3D RTE_TM_NODE_ID_NULL) { + if (level_id !=3D RTE_TM_NODE_LEVEL_ID_ANY && + level_id > SXE_TM_NODE_TYPE_PORT) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_PARAMS; + error->message =3D "Wrong level"; + goto l_end; + } + + if (tm_ctxt->root) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID; + error->message =3D "already have a root"; + goto l_end; + } + + tm_node =3D rte_zmalloc("sxe_tm_node", + sizeof(struct sxe_tm_node), + 0); + if (!tm_node) { + ret =3D -ENOMEM; + PMD_LOG_ERR(DRV, "tm node mem alloc faield"); + goto l_end; + } + + tm_node->id =3D node_id; + tm_node->priority =3D priority; + tm_node->weight =3D weight; + tm_node->ref_cnt =3D 0; + tm_node->no =3D 0; + tm_node->parent =3D NULL; + tm_node->shaper_profile =3D shaper_profile; + rte_memcpy(&tm_node->params, params, + sizeof(struct rte_tm_node_params)); + tm_ctxt->root =3D tm_node; + + if (shaper_profile) + shaper_profile->ref_cnt++; + + ret =3D 0; + goto l_end; + } + + parent_node =3D sxe_tm_node_search(dev, parent_node_id, + &parent_node_type); + if (!parent_node) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID; + error->message =3D "parent not exist"; + goto l_end; + } + + if (parent_node_type !=3D SXE_TM_NODE_TYPE_PORT && + parent_node_type !=3D SXE_TM_NODE_TYPE_TC) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID; + error->message =3D "parent is not port or TC"; + goto l_end; + } + + if (level_id !=3D RTE_TM_NODE_LEVEL_ID_ANY && + level_id !=3D parent_node_type + 1) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_PARAMS; + error->message =3D "Wrong level"; + goto l_end; + } + + if (parent_node_type =3D=3D SXE_TM_NODE_TYPE_PORT) { + tcs_num =3D sxe_tcs_num_get(dev); + if (tm_ctxt->tc_node_num >=3D tcs_num) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "too many TCs"; + goto l_end; + } + } else { + if (tm_ctxt->queue_node_num >=3D dev->data->nb_tx_queues) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "too many queues"; + goto l_end; + } + + sxe_tc_owned_queues_get(dev, parent_node->no, &q_base, &q_nb); + if (parent_node->ref_cnt >=3D q_nb) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "too many queues than TC supported"; + goto l_end; + } + + if (node_id >=3D dev->data->nb_tx_queues) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "too large queue id"; + goto l_end; + } + } + + tm_node =3D rte_zmalloc("sxe_tm_node", + sizeof(struct sxe_tm_node), + 0); + if (!tm_node) { + ret =3D -ENOMEM; + PMD_LOG_ERR(DRV, "tm node mem alloc faield"); + goto l_end; + } + + tm_node->id =3D node_id; + tm_node->priority =3D priority; + tm_node->weight =3D weight; + tm_node->ref_cnt =3D 0; + tm_node->parent =3D parent_node; + tm_node->shaper_profile =3D shaper_profile; + rte_memcpy(&tm_node->params, params, + sizeof(struct rte_tm_node_params)); + if (parent_node_type =3D=3D SXE_TM_NODE_TYPE_PORT) { + tm_node->no =3D parent_node->ref_cnt; + TAILQ_INSERT_TAIL(&tm_ctxt->tc_list, + tm_node, node); + tm_ctxt->tc_node_num++; + } else { + tm_node->no =3D q_base + parent_node->ref_cnt; + TAILQ_INSERT_TAIL(&tm_ctxt->queue_list, + tm_node, node); + tm_ctxt->queue_node_num++; + } + + tm_node->parent->ref_cnt++; + + if (shaper_profile) + shaper_profile->ref_cnt++; + + ret =3D 0; +l_end: + return ret; +} + +static s32 sxe_node_delete(struct rte_eth_dev *dev, u32 node_id, + struct rte_tm_error *error) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_tm_context *tm_ctxt =3D &adapter->tm_ctxt; + + enum sxe_tm_node_type node_type =3D SXE_TM_NODE_TYPE_MAX; + struct sxe_tm_node *tm_node; + s32 ret =3D -EINVAL; + + if (!error) { + PMD_LOG_ERR(DRV, "tm node del faield because error is NULL"); + goto l_end; + } + + if (tm_ctxt->committed) { + error->type =3D RTE_TM_ERROR_TYPE_UNSPECIFIED; + error->message =3D "already committed"; + goto l_end; + } + + if (node_id =3D=3D RTE_TM_NODE_ID_NULL) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "invalid node id"; + goto l_end; + } + + tm_node =3D sxe_tm_node_search(dev, node_id, &node_type); + if (!tm_node) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "no such node"; + goto l_end; + } + + if (tm_node->ref_cnt) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D + "cannot delete a node which has children"; + goto l_end; + } + + if (node_type =3D=3D SXE_TM_NODE_TYPE_PORT) { + if (tm_node->shaper_profile) + tm_node->shaper_profile->ref_cnt--; + rte_free(tm_node); + tm_ctxt->root =3D NULL; + ret =3D 0; + goto l_end; + } + + if (tm_node->shaper_profile) + tm_node->shaper_profile->ref_cnt--; + + tm_node->parent->ref_cnt--; + if (node_type =3D=3D SXE_TM_NODE_TYPE_TC) { + TAILQ_REMOVE(&tm_ctxt->tc_list, tm_node, node); + tm_ctxt->tc_node_num--; + } else { + TAILQ_REMOVE(&tm_ctxt->queue_list, tm_node, node); + tm_ctxt->queue_node_num--; + } + rte_free(tm_node); + + ret =3D 0; + +l_end: + return ret; +} + +static s32 sxe_node_type_get(struct rte_eth_dev *dev, u32 node_id, + s32 *is_leaf, struct rte_tm_error *error) +{ + enum sxe_tm_node_type node_type =3D SXE_TM_NODE_TYPE_MAX; + struct sxe_tm_node *tm_node; + s32 ret =3D -EINVAL; + + if (!is_leaf || !error) { + PMD_LOG_ERR(DRV, "%s faield because " + "error or is_leaf is NULL", __func__); + goto l_end; + } + + if (node_id =3D=3D RTE_TM_NODE_ID_NULL) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "invalid node id"; + goto l_end; + } + + tm_node =3D sxe_tm_node_search(dev, node_id, &node_type); + if (!tm_node) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "no such node"; + goto l_end; + } + + if (node_type =3D=3D SXE_TM_NODE_TYPE_QUEUE) + *is_leaf =3D true; + else + *is_leaf =3D false; + + ret =3D 0; + +l_end: + return ret; +} + +static s32 sxe_level_capabilities_get(struct rte_eth_dev *dev __rte_unused, + u32 level_id, + struct rte_tm_level_capabilities *cap, + struct rte_tm_error *error) +{ + s32 ret =3D -EINVAL; + + if (!cap || !error) { + PMD_LOG_ERR(DRV, "get level[%u] capabilities faield because " + "cap or error is NULL", level_id); + goto l_end; + } + + if (level_id >=3D SXE_TM_NODE_TYPE_MAX) { + error->type =3D RTE_TM_ERROR_TYPE_LEVEL_ID; + error->message =3D "too deep level"; + goto l_end; + } + + if (level_id =3D=3D SXE_TM_NODE_TYPE_PORT) { + cap->n_nodes_max =3D 1; + cap->n_nodes_nonleaf_max =3D 1; + cap->n_nodes_leaf_max =3D 0; + } else if (level_id =3D=3D SXE_TM_NODE_TYPE_TC) { + cap->n_nodes_max =3D MAX_TRAFFIC_CLASS; + cap->n_nodes_nonleaf_max =3D MAX_TRAFFIC_CLASS; + cap->n_nodes_leaf_max =3D 0; + } else { + cap->n_nodes_max =3D SXE_HW_TXRX_RING_NUM_MAX; + cap->n_nodes_nonleaf_max =3D 0; + cap->n_nodes_leaf_max =3D SXE_HW_TXRX_RING_NUM_MAX; + } + + cap->non_leaf_nodes_identical =3D true; + cap->leaf_nodes_identical =3D true; + + if (level_id !=3D SXE_TM_NODE_TYPE_QUEUE) { + cap->nonleaf.shaper_private_supported =3D true; + cap->nonleaf.shaper_private_dual_rate_supported =3D false; + cap->nonleaf.shaper_private_rate_min =3D 0; + cap->nonleaf.shaper_private_rate_max =3D 1250000000ull; +#ifndef DPDK_19_11_6 + cap->nonleaf.shaper_private_packet_mode_supported =3D 0; + cap->nonleaf.shaper_private_byte_mode_supported =3D 1; +#endif + cap->nonleaf.shaper_shared_n_max =3D 0; +#ifndef DPDK_19_11_6 + cap->nonleaf.shaper_shared_packet_mode_supported =3D 0; + cap->nonleaf.shaper_shared_byte_mode_supported =3D 0; +#endif + if (level_id =3D=3D SXE_TM_NODE_TYPE_PORT) { + cap->nonleaf.sched_n_children_max =3D + SXE_DCB_MAX_TRAFFIC_CLASS; + } else { + cap->nonleaf.sched_n_children_max =3D + SXE_HW_TXRX_RING_NUM_MAX; + } + + cap->nonleaf.sched_sp_n_priorities_max =3D 1; + cap->nonleaf.sched_wfq_n_children_per_group_max =3D 0; + cap->nonleaf.sched_wfq_n_groups_max =3D 0; + cap->nonleaf.sched_wfq_weight_max =3D 1; +#ifndef DPDK_19_11_6 + cap->nonleaf.sched_wfq_packet_mode_supported =3D 0; + cap->nonleaf.sched_wfq_byte_mode_supported =3D 0; +#endif + cap->nonleaf.stats_mask =3D 0; + + ret =3D 0; + goto l_end; + } + + cap->leaf.shaper_private_supported =3D true; + cap->leaf.shaper_private_dual_rate_supported =3D false; + cap->leaf.shaper_private_rate_min =3D 0; + cap->leaf.shaper_private_rate_max =3D 1250000000ull; +#ifndef DPDK_19_11_6 + cap->leaf.shaper_private_packet_mode_supported =3D 0; + cap->leaf.shaper_private_byte_mode_supported =3D 1; +#endif + cap->leaf.shaper_shared_n_max =3D 0; +#ifndef DPDK_19_11_6 + cap->leaf.shaper_shared_packet_mode_supported =3D 0; + cap->leaf.shaper_shared_byte_mode_supported =3D 0; +#endif + cap->leaf.cman_head_drop_supported =3D false; + cap->leaf.cman_wred_context_private_supported =3D true; + cap->leaf.cman_wred_context_shared_n_max =3D 0; + cap->leaf.stats_mask =3D 0; + + ret =3D 0; +l_end: + return ret; +} + +static s32 sxe_node_capabilities_get(struct rte_eth_dev *dev, + u32 node_id, + struct rte_tm_node_capabilities *cap, + struct rte_tm_error *error) +{ + enum sxe_tm_node_type node_type =3D SXE_TM_NODE_TYPE_MAX; + struct sxe_tm_node *tm_node; + s32 ret =3D -EINVAL; + + if (!cap || !error) { + PMD_LOG_ERR(DRV, "get node[%u] capabilities faield because " + "cap or error is NULL", node_id); + goto l_end; + } + + if (node_id =3D=3D RTE_TM_NODE_ID_NULL) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "invalid node id"; + goto l_end; + } + + tm_node =3D sxe_tm_node_search(dev, node_id, &node_type); + if (!tm_node) { + error->type =3D RTE_TM_ERROR_TYPE_NODE_ID; + error->message =3D "no such node"; + goto l_end; + } + + cap->shaper_private_supported =3D true; + cap->shaper_private_dual_rate_supported =3D false; + cap->shaper_private_rate_min =3D 0; + cap->shaper_private_rate_max =3D 1250000000ull; +#ifndef DPDK_19_11_6 + cap->shaper_private_packet_mode_supported =3D 0; + cap->shaper_private_byte_mode_supported =3D 1; +#endif + cap->shaper_shared_n_max =3D 0; +#ifndef DPDK_19_11_6 + cap->shaper_shared_packet_mode_supported =3D 0; + cap->shaper_shared_byte_mode_supported =3D 0; +#endif + + if (node_type =3D=3D SXE_TM_NODE_TYPE_QUEUE) { + cap->leaf.cman_head_drop_supported =3D false; + cap->leaf.cman_wred_context_private_supported =3D true; + cap->leaf.cman_wred_context_shared_n_max =3D 0; + } else { + if (node_type =3D=3D SXE_TM_NODE_TYPE_PORT) { + cap->nonleaf.sched_n_children_max =3D MAX_TRAFFIC_CLASS; + } else { + cap->nonleaf.sched_n_children_max =3D + SXE_HW_TXRX_RING_NUM_MAX; + } + + cap->nonleaf.sched_sp_n_priorities_max =3D 1; + cap->nonleaf.sched_wfq_n_children_per_group_max =3D 0; + cap->nonleaf.sched_wfq_n_groups_max =3D 0; + cap->nonleaf.sched_wfq_weight_max =3D 1; +#ifndef DPDK_19_11_6 + cap->nonleaf.sched_wfq_packet_mode_supported =3D 0; + cap->nonleaf.sched_wfq_byte_mode_supported =3D 0; +#endif + } + + cap->stats_mask =3D 0; + + ret =3D 0; +l_end: + return ret; +} + +static s32 sxe_hierarchy_commit(struct rte_eth_dev *dev, + s32 clear_on_fail, + struct rte_tm_error *error) +{ + struct sxe_adapter *adapter =3D dev->data->dev_private; + struct sxe_tm_context *tm_ctxt =3D &adapter->tm_ctxt; + + struct sxe_tm_node *tm_node; + u64 bw; + s32 ret =3D -EINVAL; + + if (!error) { + PMD_LOG_ERR(DRV, "%s faield because " + "error is NULL", __func__); + goto l_end; + } + + if (!tm_ctxt->root) { + PMD_LOG_INFO(DRV, "tm hierarchy committed"); + goto done; + } + + if (tm_ctxt->root->shaper_profile && + tm_ctxt->root->shaper_profile->profile.peak.rate) { + error->type =3D RTE_TM_ERROR_TYPE_SHAPER_PROFILE; + error->message =3D "no port max bandwidth"; + goto fail_clear; + } + + TAILQ_FOREACH(tm_node, &tm_ctxt->tc_list, node) { + if (tm_node->shaper_profile && + tm_node->shaper_profile->profile.peak.rate) { + error->type =3D RTE_TM_ERROR_TYPE_SHAPER_PROFILE; + error->message =3D "no TC max bandwidth"; + goto fail_clear; + } + } + + TAILQ_FOREACH(tm_node, &tm_ctxt->queue_list, node) { + if (tm_node->shaper_profile) + bw =3D tm_node->shaper_profile->profile.peak.rate; + else + bw =3D 0; + + if (bw) { + bw =3D bw * 8 / 1000 / 1000; + ret =3D sxe_queue_rate_limit_set(dev, tm_node->no, bw); + if (ret) { + error->type =3D RTE_TM_ERROR_TYPE_SHAPER_PROFILE; + error->message =3D + "failed to set queue max bandwidth"; + goto fail_clear; + } + } + } + +done: + tm_ctxt->committed =3D true; + ret =3D 0; + goto l_end; + +fail_clear: + if (clear_on_fail) { + sxe_tm_ctxt_uninit(dev); + sxe_tm_ctxt_init(dev); + } +l_end: + return ret; +} + +static const struct rte_tm_ops sxe_tm_ops =3D { + .capabilities_get =3D sxe_capabilities_get, + .shaper_profile_add =3D sxe_shaper_profile_add, + .shaper_profile_delete =3D sxe_shaper_profile_del, + .node_add =3D sxe_node_add, + .node_delete =3D sxe_node_delete, + .node_type_get =3D sxe_node_type_get, + .level_capabilities_get =3D sxe_level_capabilities_get, + .node_capabilities_get =3D sxe_node_capabilities_get, + .hierarchy_commit =3D sxe_hierarchy_commit, +}; + +s32 sxe_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *arg) +{ + s32 ret =3D 0; + + if (!arg) { + ret =3D -EINVAL; + PMD_LOG_ERR(DRV, "%s faield because " + "arg is NULL", __func__); + goto l_end; + } + + *(const void **)arg =3D &sxe_tm_ops; + +l_end: + return ret; +} + +#endif diff --git a/drivers/net/sxe/pf/sxe_tm.h b/drivers/net/sxe/pf/sxe_tm.h new file mode 100644 index 0000000000..cc736b167f --- /dev/null +++ b/drivers/net/sxe/pf/sxe_tm.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ + +#ifndef __SXE_TM_H__ +#define __SXE_TM_H__ + +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_TM +#include + +#include "sxe_types.h" + +enum sxe_tm_node_type { + SXE_TM_NODE_TYPE_PORT, + SXE_TM_NODE_TYPE_TC, + SXE_TM_NODE_TYPE_QUEUE, + SXE_TM_NODE_TYPE_MAX, +}; + +struct sxe_tm_shaper_profile { + TAILQ_ENTRY(sxe_tm_shaper_profile) node; + u32 id; + u32 ref_cnt; + struct rte_tm_shaper_params profile; +}; + +struct sxe_tm_node { + TAILQ_ENTRY(sxe_tm_node) node; + u32 id; + u32 priority; + u32 weight; + u32 ref_cnt; + u16 no; + struct sxe_tm_node *parent; + struct sxe_tm_shaper_profile *shaper_profile; + struct rte_tm_node_params params; +}; + +TAILQ_HEAD(sxe_shaper_profile_list, sxe_tm_shaper_profile); +TAILQ_HEAD(sxe_tm_node_list, sxe_tm_node); + +struct sxe_tm_context { + struct sxe_shaper_profile_list shaper_profile_list; + struct sxe_tm_node *root; + struct sxe_tm_node_list tc_list; + struct sxe_tm_node_list queue_list; + u32 tc_node_num; + u32 queue_node_num; + bool committed; +}; + +void sxe_tm_ctxt_init(struct rte_eth_dev *dev); + +void sxe_tm_ctxt_uninit(struct rte_eth_dev *dev); + +s32 sxe_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *arg); + +#endif +#endif diff --git a/drivers/net/sxe/pf/sxe_tx.c b/drivers/net/sxe/pf/sxe_tx.c index 6b92e6faed..5ccd6f5432 100644 --- a/drivers/net/sxe/pf/sxe_tx.c +++ b/drivers/net/sxe/pf/sxe_tx.c @@ -44,31 +44,29 @@ RTE_MBUF_F_TX_IP_CKSUM | \ RTE_MBUF_F_TX_L4_MASK | \ RTE_MBUF_F_TX_TCP_SEG | \ - RTE_MBUF_F_TX_MACSEC | \ + RTE_MBUF_F_TX_MACSEC | \ RTE_MBUF_F_TX_OUTER_IP_CKSUM | \ SXE_TX_IEEE1588_TMST) =20 #define SXE_TX_OFFLOAD_NOTSUP_MASK (RTE_MBUF_F_TX_OFFLOAD_MASK ^ SXE_TX_OF= FLOAD_MASK) #define RTE_SXE_MAX_TX_FREE_BUF_SZ 64 -#define SXE_TXD_IDX_SHIFT 4=20 +#define SXE_TXD_IDX_SHIFT 4 #define SXE_TX_MIN_PKT_LEN 14 =20 -extern const struct sxe_txq_ops def_txq_ops; - void __rte_cold sxe_tx_function_set(struct rte_eth_dev *dev, sxe_tx_queue_s *txq) { /* Offload off and signle simple tx code path < 32 use simple tx code pat= h */ if ((txq->offloads =3D=3D 0) && - (txq->rs_thresh >=3D RTE_PMD_SXE_MAX_TX_BURST)){ + (txq->rs_thresh >=3D RTE_PMD_SXE_MAX_TX_BURST)) { dev->tx_pkt_prepare =3D NULL; #if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD if (txq->rs_thresh <=3D RTE_SXE_MAX_TX_FREE_BUF_SZ && #ifndef DPDK_19_11_6 - rte_vect_get_max_simd_bitwidth() >=3D RTE_VECT_SIMD_128 && + rte_vect_get_max_simd_bitwidth() >=3D RTE_VECT_SIMD_128 && #endif - (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || - sxe_txq_vec_setup(txq) =3D=3D 0)) { + (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || + sxe_txq_vec_setup(txq) =3D=3D 0)) { dev->tx_pkt_burst =3D sxe_pkts_vector_xmit; PMD_LOG_INFO(INIT, "using vector tx code path"); } else { @@ -81,19 +79,18 @@ void __rte_cold sxe_tx_function_set(struct rte_eth_dev = *dev, #endif =20 } else { - dev->tx_pkt_burst =3D sxe_pkts_xmit_with_offload;; + dev->tx_pkt_burst =3D sxe_pkts_xmit_with_offload; dev->tx_pkt_prepare =3D sxe_prep_pkts; =20 PMD_LOG_INFO(INIT, "using full-featured tx code path"); PMD_LOG_INFO(INIT, " - offloads =3D 0x%" PRIx64, - (long unsigned int)txq->offloads); + (unsigned long)txq->offloads); PMD_LOG_INFO(INIT, " - tx_rs_thresh =3D %d " "[RTE_PMD_SXE_MAX_TX_BURST=3D%d]", txq->rs_thresh, RTE_PMD_SXE_MAX_TX_BURST); } =20 - return; } =20 int __rte_cold sxe_tx_queue_setup(struct rte_eth_dev *dev, @@ -132,12 +129,10 @@ static void __rte_cold sxe_tx_start(struct rte_eth_de= v *dev) txq =3D dev->data->tx_queues[i]; sxe_hw_tx_desc_thresh_set(hw, txq->reg_idx, txq->wthresh, txq->hthresh, txq->pthresh); - if (!txq->tx_deferred_start) { + if (!txq->tx_deferred_start) sxe_tx_queue_start(dev, i); - } } =20 - return; } =20 static void sxe_tx_buf_configure(struct sxe_hw *hw) @@ -152,7 +147,6 @@ static void sxe_tx_buf_configure(struct sxe_hw *hw) =20 sxe_hw_mac_pad_enable(hw); =20 - return; } =20 void __rte_cold sxe_tx_configure(struct rte_eth_dev *dev) @@ -180,7 +174,6 @@ void __rte_cold sxe_tx_configure(struct rte_eth_dev *de= v) =20 sxe_tx_start(dev); =20 - return; } =20 static inline void sxe_single_desc_fill(volatile sxe_tx_data_desc_u *desc, @@ -199,7 +192,6 @@ static inline void sxe_single_desc_fill(volatile sxe_tx= _data_desc_u *desc, rte_cpu_to_le_32(pkt_len << SXE_TX_DESC_PAYLEN_SHIFT); rte_sxe_prefetch(&(*pkts)->pool); =20 - return; } =20 #define TX4_PER_LOOP 4 @@ -227,7 +219,6 @@ static inline void sxe_four_desc_fill(volatile sxe_tx_d= ata_desc_u *desc, rte_sxe_prefetch(&(*pkts)->pool); } =20 - return; } =20 static inline void sxe_tx_ring_fill(sxe_tx_queue_s *txq, @@ -242,9 +233,8 @@ static inline void sxe_tx_ring_fill(sxe_tx_queue_s *txq, leftover =3D (pkts_num & ((u32) TX4_PER_LOOP_MASK)); =20 for (i =3D 0; i < mainpart; i +=3D TX4_PER_LOOP) { - for (j =3D 0; j < TX4_PER_LOOP; ++j) { + for (j =3D 0; j < TX4_PER_LOOP; ++j) (buffer + i + j)->mbuf =3D *(pkts + i + j); - } sxe_four_desc_fill(desc + i, pkts + i); } =20 @@ -256,7 +246,6 @@ static inline void sxe_tx_ring_fill(sxe_tx_queue_s *txq, } } =20 - return; } =20 s32 sxe_tx_bufs_free(sxe_tx_queue_s *txq) @@ -279,14 +268,13 @@ s32 sxe_tx_bufs_free(sxe_tx_queue_s *txq) mbuf =3D rte_pktmbuf_prefree_seg(buffer->mbuf); buffer->mbuf =3D NULL; =20 - if (unlikely(mbuf =3D=3D NULL)) { + if (unlikely(mbuf =3D=3D NULL)) continue; - } =20 if (mbuf_free_num >=3D RTE_SXE_MAX_TX_FREE_BUF_SZ || - (mbuf_free_num > 0 && mbuf->pool !=3D free_mbuf[0]->pool)) { + (mbuf_free_num > 0 && mbuf->pool !=3D free_mbuf[0]->pool)) { rte_mempool_put_bulk(free_mbuf[0]->pool, - (void **)free_mbuf, mbuf_free_num); + (void **)free_mbuf, mbuf_free_num); mbuf_free_num =3D 0; } =20 @@ -298,11 +286,10 @@ s32 sxe_tx_bufs_free(sxe_tx_queue_s *txq) (void **)free_mbuf, mbuf_free_num); } =20 - txq->next_dd +=3D txq->rs_thresh; + txq->next_dd +=3D txq->rs_thresh; txq->desc_free_num +=3D txq->rs_thresh; - if (txq->next_dd >=3D txq->ring_depth) { + if (txq->next_dd >=3D txq->ring_depth) txq->next_dd =3D txq->rs_thresh - 1; - } =20 ret =3D txq->rs_thresh; =20 @@ -317,9 +304,8 @@ static inline u16 sxe_pkts_xmit(void *tx_queue, sxe_tx_queue_s *txq =3D (sxe_tx_queue_s *)tx_queue; volatile sxe_tx_data_desc_u *desc_ring =3D txq->desc_ring; =20 - if (txq->desc_free_num < txq->free_thresh) { + if (txq->desc_free_num < txq->free_thresh) sxe_tx_bufs_free(txq); - } =20 xmit_pkts_num =3D (u16)RTE_MIN(txq->desc_free_num, xmit_pkts_num); if (unlikely(xmit_pkts_num =3D=3D 0)) { @@ -350,14 +336,12 @@ static inline u16 sxe_pkts_xmit(void *tx_queue, desc_ring[txq->next_rs].read.cmd_type_len |=3D rte_cpu_to_le_32(SXE_TX_DESC_RS_MASK); txq->next_rs =3D (u16)(txq->next_rs + txq->rs_thresh); - if (txq->next_rs >=3D txq->ring_depth) { + if (txq->next_rs >=3D txq->ring_depth) txq->next_rs =3D (u16)(txq->rs_thresh - 1); - } } =20 - if (txq->next_to_use >=3D txq->ring_depth) { + if (txq->next_to_use >=3D txq->ring_depth) txq->next_to_use =3D 0; - } =20 rte_wmb(); rte_write32_wc_relaxed((rte_cpu_to_le_32(txq->next_to_use)), @@ -387,13 +371,12 @@ u16 sxe_pkts_simple_xmit(void *tx_queue, struct rte_m= buf **tx_pkts, u16 pkts_num ret =3D sxe_pkts_xmit(tx_queue, &(tx_pkts[xmit_pkts_num]), need_xmit_pkts); =20 - pkts_num -=3D ret; + pkts_num -=3D ret; xmit_pkts_num +=3D ret; =20 /* Don't have enough desc */ - if (ret < need_xmit_pkts) { + if (ret < need_xmit_pkts) break; - } } =20 LOG_DEBUG("simple xmit:port_id=3D%u, queue_id=3D%u, " @@ -421,9 +404,8 @@ u16 sxe_pkts_vector_xmit(void *tx_queue, struct rte_mbu= f **tx_pkts, =20 xmit_pkts_num +=3D ret; pkts_num -=3D ret; - if (ret < need_xmit_pkts) { + if (ret < need_xmit_pkts) break; - } } =20 return xmit_pkts_num; @@ -484,21 +466,21 @@ static inline bool sxe_cache_ctxt_desc_match( { bool ret; =20 - ol_info->l2_len =3D pkt->l2_len; - ol_info->l3_len =3D pkt->l3_len; - ol_info->l4_len =3D pkt->l4_len; - ol_info->vlan_tci =3D pkt->vlan_tci; - ol_info->tso_segsz =3D pkt->tso_segsz; + ol_info->l2_len =3D pkt->l2_len; + ol_info->l3_len =3D pkt->l3_len; + ol_info->l4_len =3D pkt->l4_len; + ol_info->vlan_tci =3D pkt->vlan_tci; + ol_info->tso_segsz =3D pkt->tso_segsz; ol_info->outer_l2_len =3D pkt->outer_l2_len; ol_info->outer_l3_len =3D pkt->outer_l3_len; =20 if (likely((txq->ctx_cache[txq->ctx_curr].flags =3D=3D flags) && (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] =3D=3D - (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0] - & ol_info->data[0])) && + (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0] + & ol_info->data[0])) && (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] =3D=3D - (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1] - & ol_info->data[1])))) { + (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1] + & ol_info->data[1])))) { =20 ret =3D false; goto l_end; @@ -508,11 +490,11 @@ static inline bool sxe_cache_ctxt_desc_match( =20 if (likely((txq->ctx_cache[txq->ctx_curr].flags =3D=3D flags) && (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] =3D=3D - (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0] - & ol_info->data[0])) && + (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0] + & ol_info->data[0])) && (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] =3D=3D - (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1] - & ol_info->data[1])))) { + (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1] + & ol_info->data[1])))) { =20 ret =3D false; goto l_end; @@ -545,9 +527,8 @@ static inline void sxe_ctxt_desc_fill(sxe_tx_queue_s *t= xq, =20 mss_l4len_idx |=3D (ctx_idx << SXE_TXD_IDX_SHIFT); =20 - if (ol_flags & RTE_MBUF_F_TX_VLAN) { + if (ol_flags & RTE_MBUF_F_TX_VLAN) tx_offload_mask.vlan_tci |=3D ~0; - } =20 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) { if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) { @@ -614,14 +595,14 @@ static inline void sxe_ctxt_desc_fill(sxe_tx_queue_s = *txq, tx_offload_mask.outer_l3_len |=3D ~0; tx_offload_mask.l2_len |=3D ~0; seqnum_seed |=3D tx_offload.outer_l3_len - << SXE_TX_CTXTD_OUTER_IPLEN_SHIFT; + << SXE_TX_CTXTD_OUTER_IPLEN_SHIFT; seqnum_seed |=3D tx_offload.l2_len - << SXE_TX_CTXTD_TUNNEL_LEN_SHIFT; + << SXE_TX_CTXTD_TUNNEL_LEN_SHIFT; vlan_macip_lens |=3D (tx_offload.outer_l2_len << - SXE_TX_CTXTD_MACLEN_SHIFT); + SXE_TX_CTXTD_MACLEN_SHIFT); } else { vlan_macip_lens |=3D (tx_offload.l2_len << - SXE_TX_CTXTD_MACLEN_SHIFT); + SXE_TX_CTXTD_MACLEN_SHIFT); } =20 txq->ctx_cache[ctx_idx].flags =3D ol_flags; @@ -629,31 +610,27 @@ static inline void sxe_ctxt_desc_fill(sxe_tx_queue_s = *txq, tx_offload_mask.data[0] & tx_offload.data[0]; txq->ctx_cache[ctx_idx].tx_offload.data[1] =3D tx_offload_mask.data[1] & tx_offload.data[1]; - txq->ctx_cache[ctx_idx].tx_offload_mask =3D tx_offload_mask; + txq->ctx_cache[ctx_idx].tx_offload_mask =3D tx_offload_mask; =20 ctx_txd->type_tucmd_mlhl =3D rte_cpu_to_le_32(type_tucmd_mlhl); ctx_txd->vlan_macip_lens =3D rte_cpu_to_le_32(vlan_macip_lens); ctx_txd->mss_l4len_idx =3D rte_cpu_to_le_32(mss_l4len_idx); - ctx_txd->seqnum_seed =3D seqnum_seed; + ctx_txd->seqnum_seed =3D seqnum_seed; =20 - return; } =20 static inline u32 sxe_tx_desc_csum_info_setup(u64 ol_flags) { u32 desc_csum =3D 0; =20 - if ((ol_flags & RTE_MBUF_F_TX_L4_MASK) !=3D RTE_MBUF_F_TX_L4_NO_CKSUM) { + if ((ol_flags & RTE_MBUF_F_TX_L4_MASK) !=3D RTE_MBUF_F_TX_L4_NO_CKSUM) desc_csum |=3D SXE_TXD_POPTS_TXSM; - } =20 - if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) { + if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) desc_csum |=3D SXE_TXD_POPTS_IXSM; - } =20 - if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) { + if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) desc_csum |=3D SXE_TXD_POPTS_TXSM; - } =20 return desc_csum; } @@ -662,22 +639,18 @@ static inline u32 sxe_tx_desc_cmdtype_setup(u64 ol_fl= ags) { u32 cmdtype =3D 0; =20 - if (ol_flags & RTE_MBUF_F_TX_VLAN) { + if (ol_flags & RTE_MBUF_F_TX_VLAN) cmdtype |=3D SXE_TX_DESC_VLE; - } =20 - if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) { + if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) cmdtype |=3D SXE_TXD_DCMD_TSE; - } =20 - if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) { + if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) cmdtype |=3D (1 << SXE_TX_OUTERIPCS_SHIFT); - } =20 #ifdef SXE_DPDK_MACSEC - if (ol_flags & RTE_MBUF_F_TX_MACSEC) { + if (ol_flags & RTE_MBUF_F_TX_MACSEC) cmdtype |=3D SXE_TXD_MAC_LINKSEC; - } #endif =20 return cmdtype; @@ -697,9 +670,8 @@ static inline s32 sxe_xmit_cleanup(sxe_tx_queue_s *txq) =20 desc_to_clean_to =3D (u16)(ntc + txq->rs_thresh); =20 - if (desc_to_clean_to >=3D ring_depth) { + if (desc_to_clean_to >=3D ring_depth) desc_to_clean_to =3D (u16)(desc_to_clean_to - ring_depth); - } =20 desc_to_clean_to =3D buffer_ring[desc_to_clean_to].last_id; =20 @@ -749,9 +721,8 @@ static inline s32 sxe_tx_pkt_desc_clean( txq->port_id, txq->queue_idx); =20 ret =3D sxe_xmit_cleanup(txq); - if (ret) { + if (ret) goto l_end; - } =20 if (unlikely(need_desc_num > txq->rs_thresh)) { LOG_DEBUG( @@ -769,9 +740,8 @@ static inline s32 sxe_tx_pkt_desc_clean( /* Clean up enought desc */ while (need_desc_num > txq->desc_free_num) { ret =3D sxe_xmit_cleanup(txq); - if (ret) { + if (ret) goto l_end; - } } } =20 @@ -791,20 +761,19 @@ u16 __sxe_pkts_xmit_with_offload(void *tx_queue, stru= ct rte_mbuf **tx_pkts, u16 sxe_tx_queue_s *txq =3D tx_queue; u32 pkt_len, cmd_type_len, olinfo_status; u16 need_desc_num, last_desc_idx, xmit_num, ntu, seg_len; - volatile sxe_tx_data_desc_u *tail_desc =3D NULL;=20 + volatile sxe_tx_data_desc_u *tail_desc =3D NULL; volatile sxe_tx_data_desc_u *desc_ring, *desc; struct sxe_tx_buffer *buffer_ring, *buffer, *next_buffer; =20 ol_info.data[SXE_CTXT_DESC_0] =3D 0; ol_info.data[SXE_CTXT_DESC_1] =3D 0; - ntu =3D txq->next_to_use; + ntu =3D txq->next_to_use; desc_ring =3D txq->desc_ring; buffer_ring =3D txq->buffer_ring; - buffer =3D &buffer_ring[ntu]; + buffer =3D &buffer_ring[ntu]; =20 - if (txq->desc_free_num < txq->free_thresh) { + if (txq->desc_free_num < txq->free_thresh) sxe_xmit_cleanup(txq); - } =20 /* Refresh cache, pre fetch data to cache */ rte_sxe_prefetch(&buffer->mbuf->pool); @@ -815,38 +784,35 @@ u16 __sxe_pkts_xmit_with_offload(void *tx_queue, stru= ct rte_mbuf **tx_pkts, u16 pkt_len =3D pkt->pkt_len; =20 ol_req =3D pkt->ol_flags & SXE_TX_OFFLOAD_MASK; - if (ol_req) { + if (ol_req) new_ctx =3D sxe_cache_ctxt_desc_match(txq, pkt, ol_req, &ol_info); - } =20 need_desc_num =3D (u16)(pkt->nb_segs + new_ctx); =20 if (tail_desc !=3D NULL && - need_desc_num + txq->desc_used_num >=3D txq->rs_thresh) { + need_desc_num + txq->desc_used_num >=3D txq->rs_thresh) { tail_desc->read.cmd_type_len |=3D rte_cpu_to_le_32(SXE_TX_DESC_RS_MASK); } =20 last_desc_idx =3D (u16) (ntu + need_desc_num - 1); =20 - if (last_desc_idx >=3D txq->ring_depth) { + if (last_desc_idx >=3D txq->ring_depth) last_desc_idx =3D (u16) (last_desc_idx - txq->ring_depth); - } =20 LOG_DEBUG("port_id=3D%u queue_id=3D%u pktlen=3D%u" " next_to_ues=3D%u last_desc_idx=3D%u", - (unsigned) txq->port_id, - (unsigned) txq->queue_idx, - (unsigned) pkt_len, - (unsigned) ntu, - (unsigned) last_desc_idx); + (unsigned int) txq->port_id, + (unsigned int) txq->queue_idx, + (unsigned int) pkt_len, + (unsigned int) ntu, + (unsigned int) last_desc_idx); =20 if (need_desc_num > txq->desc_free_num) { ret =3D sxe_tx_pkt_desc_clean(txq, need_desc_num); - if(ret) { - if (0 =3D=3D xmit_num) { + if (ret) { + if (xmit_num =3D=3D 0) goto l_end; - } =20 goto l_end_of_tx; } @@ -854,9 +820,8 @@ u16 __sxe_pkts_xmit_with_offload(void *tx_queue, struct= rte_mbuf **tx_pkts, u16 =20 cmd_type_len =3D SXE_TX_DESC_TYPE_DATA | SXE_TX_DESC_IFCS; #ifdef RTE_LIBRTE_IEEE1588 - if (pkt->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST) { + if (pkt->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST) cmd_type_len |=3D SXE_TXD_MAC_1588; - } #endif =20 olinfo_status =3D 0; @@ -891,10 +856,10 @@ u16 __sxe_pkts_xmit_with_offload(void *tx_queue, stru= ct rte_mbuf **tx_pkts, u16 =20 LOG_DEBUG("tx need offload, port_id=3D%u " "queue_id=3D%u pktlen=3D%u, ctxt_id=3D%u", - (unsigned) txq->port_id, - (unsigned) txq->queue_idx, - (unsigned) pkt_len, - (unsigned) txq->ctx_curr); + (unsigned int) txq->port_id, + (unsigned int) txq->queue_idx, + (unsigned int) pkt_len, + (unsigned int) txq->ctx_curr); =20 cmd_type_len |=3D sxe_tx_desc_cmdtype_setup(pkt->ol_flags); olinfo_status |=3D sxe_tx_desc_csum_info_setup(pkt->ol_flags); @@ -908,11 +873,10 @@ u16 __sxe_pkts_xmit_with_offload(void *tx_queue, stru= ct rte_mbuf **tx_pkts, u16 next_buffer =3D &buffer_ring[buffer->next_id]; =20 rte_prefetch0(&next_buffer->mbuf->pool); - if (buffer->mbuf !=3D NULL) { + if (buffer->mbuf !=3D NULL) rte_pktmbuf_free_seg(buffer->mbuf); - } =20 - buffer->mbuf =3D m_seg;=20=20 + buffer->mbuf =3D m_seg; =20 seg_len =3D m_seg->data_len; =20 @@ -956,8 +920,8 @@ u16 __sxe_pkts_xmit_with_offload(void *tx_queue, struct= rte_mbuf **tx_pkts, u16 rte_wmb(); =20 LOG_DEBUG("port_id=3D%u queue_idx=3D%u next_to_use=3D%u xmit_num=3D%u", - (unsigned) txq->port_id, (unsigned) txq->queue_idx, - (unsigned) ntu, (unsigned) xmit_num); + (unsigned int) txq->port_id, (unsigned int) txq->queue_idx, + (unsigned int) ntu, (unsigned int) xmit_num); =20 rte_write32_wc_relaxed(ntu, txq->tdt_reg_addr); =20 @@ -980,7 +944,7 @@ u32 sxe_tx_done_cleanup_full(sxe_tx_queue_s *txq, u32 f= ree_cnt) u16 nb_tx_to_clean; struct sxe_tx_buffer *buffer_ring =3D txq->buffer_ring; =20 - ntu =3D txq->next_to_use; + ntu =3D txq->next_to_use; tx_id =3D buffer_ring[ntu].next_id; =20 if (txq->desc_free_num =3D=3D 0 && sxe_xmit_cleanup(txq)) { @@ -991,12 +955,11 @@ u32 sxe_tx_done_cleanup_full(sxe_tx_queue_s *txq, u32= free_cnt) nb_tx_to_clean =3D txq->desc_free_num; nb_tx_free_last =3D txq->desc_free_num; =20 - if (!free_cnt) { + if (!free_cnt) free_cnt =3D txq->ring_depth; - } =20 for (pkt_cnt =3D 0; pkt_cnt < free_cnt; ) { - for (i =3D 0; i < (nb_tx_to_clean && pkt_cnt < free_cnt && \ + for (i =3D 0; i < (nb_tx_to_clean && pkt_cnt < free_cnt && tx_id !=3D ntu); i++) { if (buffer_ring[tx_id].mbuf !=3D NULL) { rte_pktmbuf_free_seg(buffer_ring[tx_id].mbuf); @@ -1008,15 +971,14 @@ u32 sxe_tx_done_cleanup_full(sxe_tx_queue_s *txq, u3= 2 free_cnt) tx_id =3D buffer_ring[tx_id].next_id; } =20 - if (txq->rs_thresh > txq->ring_depth - txq->desc_free_num || \ + if (txq->rs_thresh > txq->ring_depth - txq->desc_free_num || tx_id =3D=3D ntu) { break; } =20 if (pkt_cnt < free_cnt) { - if (sxe_xmit_cleanup(txq)) { + if (sxe_xmit_cleanup(txq)) break; - } =20 nb_tx_to_clean =3D txq->desc_free_num - nb_tx_free_last; nb_tx_free_last =3D txq->desc_free_num; @@ -1031,21 +993,18 @@ int sxe_tx_done_cleanup_simple(sxe_tx_queue_s *txq, = u32 free_cnt) { int i, n, cnt; =20 - if (free_cnt =3D=3D 0 || free_cnt > txq->ring_depth) { + if (free_cnt =3D=3D 0 || free_cnt > txq->ring_depth) free_cnt =3D txq->ring_depth; - } =20 cnt =3D free_cnt - free_cnt % txq->rs_thresh; =20 for (i =3D 0; i < cnt; i +=3D n) { - if (txq->ring_depth - txq->desc_free_num < txq->rs_thresh) { + if (txq->ring_depth - txq->desc_free_num < txq->rs_thresh) break; - } =20 n =3D sxe_tx_bufs_free(txq); - if (n =3D=3D 0) { + if (n =3D=3D 0) break; - } } =20 return i; @@ -1056,9 +1015,8 @@ int sxe_tx_done_cleanup(void *tx_queue, u32 free_cnt) s32 ret; =20 ret =3D __sxe_tx_done_cleanup(tx_queue, free_cnt); - if (ret) { + if (ret) PMD_LOG_ERR(INIT, "tx cleanup fail.(err:%d)", ret); - } =20 return ret; } diff --git a/drivers/net/sxe/pf/sxe_tx.h b/drivers/net/sxe/pf/sxe_tx.h index 78249c3340..ec731d8fcc 100644 --- a/drivers/net/sxe/pf/sxe_tx.h +++ b/drivers/net/sxe/pf/sxe_tx.h @@ -28,4 +28,4 @@ u32 sxe_tx_done_cleanup_full(sxe_tx_queue_s *txq, u32 fre= e_cnt); =20 s32 sxe_tx_bufs_free(sxe_tx_queue_s *txq); =20 -#endif=20 +#endif diff --git a/drivers/net/sxe/pf/sxe_vec_common.h b/drivers/net/sxe/pf/sxe_v= ec_common.h new file mode 100644 index 0000000000..3be75ad8e5 --- /dev/null +++ b/drivers/net/sxe/pf/sxe_vec_common.h @@ -0,0 +1,328 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ +#ifndef __SXE_VEC_COMMON_H__ +#define __SXE_VEC_COMMON_H__ + +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD +#include +#include + +#if defined DPDK_20_11_5 || defined DPDK_19_11_6 +#include +#include +#elif defined DPDK_21_11_5 +#include +#include +#include +#else +#include +#include +#include +#endif +#include "sxe.h" +#include "sxe_rx.h" + +#define RTE_SXE_MAX_TX_FREE_BUF_SZ 64 +#define SXE_TXD_STAT_DD 0x00000001 + +static __rte_always_inline s32 +sxe_tx_bufs_vec_free(struct sxe_tx_queue *txq) +{ + struct sxe_tx_buffer_vec *txep; + u32 status; + u32 n; + u32 i; + s32 ret; + s32 nb_free =3D 0; + struct rte_mbuf *m, *free[RTE_SXE_MAX_TX_FREE_BUF_SZ]; + + status =3D txq->desc_ring[txq->next_dd].wb.status; + if (!(status & SXE_TXD_STAT_DD)) { + ret =3D 0; + goto out; + } + + n =3D txq->rs_thresh; + + txep =3D &txq->buffer_ring_vec[txq->next_dd - (n - 1)]; + m =3D rte_pktmbuf_prefree_seg(txep[0].mbuf); + + if (likely(m !=3D NULL)) { + free[0] =3D m; + nb_free =3D 1; + for (i =3D 1; i < n; i++) { + m =3D rte_pktmbuf_prefree_seg(txep[i].mbuf); + if (likely(m !=3D NULL)) { + if (likely(m->pool =3D=3D free[0]->pool)) { + free[nb_free++] =3D m; + } else { + rte_mempool_put_bulk(free[0]->pool, + (void *)free, nb_free); + free[0] =3D m; + nb_free =3D 1; + } + } + } + rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free); + } else { + for (i =3D 1; i < n; i++) { + m =3D rte_pktmbuf_prefree_seg(txep[i].mbuf); + if (m !=3D NULL) + rte_mempool_put(m->pool, m); + } + } + + txq->desc_free_num =3D (u16)(txq->desc_free_num + txq->rs_thresh); + txq->next_dd =3D (u16)(txq->next_dd + txq->rs_thresh); + if (txq->next_dd >=3D txq->ring_depth) + txq->next_dd =3D (u16)(txq->rs_thresh - 1); + + ret =3D txq->rs_thresh; +out: + return ret; +} + +static inline u16 +sxe_packets_reassemble(sxe_rx_queue_s *rxq, struct rte_mbuf **rx_bufs, + u16 bufs_num, u8 *split_flags) +{ + struct rte_mbuf *pkts[bufs_num]; + struct rte_mbuf *start =3D rxq->pkt_first_seg; + struct rte_mbuf *end =3D rxq->pkt_last_seg; + u32 pkt_idx, buf_idx; + + for (buf_idx =3D 0, pkt_idx =3D 0; buf_idx < bufs_num; buf_idx++) { + if (end !=3D NULL) { + end->next =3D rx_bufs[buf_idx]; + rx_bufs[buf_idx]->data_len +=3D rxq->crc_len; + + start->nb_segs++; + start->pkt_len +=3D rx_bufs[buf_idx]->data_len; + end =3D end->next; + + if (!split_flags[buf_idx]) { + start->hash =3D end->hash; + start->ol_flags =3D end->ol_flags; + start->pkt_len -=3D rxq->crc_len; + if (end->data_len > rxq->crc_len) { + end->data_len -=3D rxq->crc_len; + } else { + struct rte_mbuf *secondlast =3D start; + + start->nb_segs--; + while (secondlast->next !=3D end) + secondlast =3D secondlast->next; + + secondlast->data_len -=3D (rxq->crc_len - + end->data_len); + secondlast->next =3D NULL; + rte_pktmbuf_free_seg(end); + } + pkts[pkt_idx++] =3D start; + start =3D end =3D NULL; + } + } else { + if (!split_flags[buf_idx]) { + pkts[pkt_idx++] =3D rx_bufs[buf_idx]; + continue; + } + end =3D start =3D rx_bufs[buf_idx]; + rx_bufs[buf_idx]->data_len +=3D rxq->crc_len; + rx_bufs[buf_idx]->pkt_len +=3D rxq->crc_len; + } + } + + rxq->pkt_first_seg =3D start; + rxq->pkt_last_seg =3D end; + memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts))); + + return pkt_idx; +} + +static inline void +sxe_rx_vec_mbufs_release(sxe_rx_queue_s *rxq) +{ + u16 i; + + if (rxq->buffer_ring =3D=3D NULL || rxq->realloc_num >=3D rxq->ring_depth) + return; + + if (rxq->realloc_num =3D=3D 0) { + for (i =3D 0; i < rxq->ring_depth; i++) { + if (rxq->buffer_ring[i].mbuf !=3D NULL) + rte_pktmbuf_free_seg(rxq->buffer_ring[i].mbuf); + } + } else { + for (i =3D rxq->processing_idx; + i !=3D rxq->realloc_start; + i =3D (i + 1) % rxq->ring_depth) { + if (rxq->buffer_ring[i].mbuf !=3D NULL) + rte_pktmbuf_free_seg(rxq->buffer_ring[i].mbuf); + } + } + + rxq->realloc_num =3D rxq->ring_depth; + + memset(rxq->buffer_ring, 0, sizeof(rxq->buffer_ring[0]) * rxq->ring_depth= ); + +} + +static inline s32 +sxe_default_rxq_vec_setup(sxe_rx_queue_s *rxq) +{ + uintptr_t p; + struct rte_mbuf mbuf =3D { .buf_addr =3D 0 }; + + mbuf.nb_segs =3D 1; + mbuf.data_off =3D RTE_PKTMBUF_HEADROOM; + mbuf.port =3D rxq->port_id; + rte_mbuf_refcnt_set(&mbuf, 1); + + rte_compiler_barrier(); + p =3D (uintptr_t)&mbuf.rearm_data; + rxq->mbuf_init_value =3D *(u64 *)p; + + return 0; +} + +static inline s32 +sxe_default_rx_vec_condition_check(struct rte_eth_dev *dev) +{ + s32 ret =3D 0; + +#ifndef RTE_LIBRTE_IEEE1588 + struct rte_eth_fdir_conf *fnav_conf =3D SXE_DEV_FNAV_CONF(dev); + if (fnav_conf->mode !=3D RTE_FDIR_MODE_NONE) + ret =3D -1; +#else + RTE_SET_USED(dev); + ret =3D -1; +#endif + + return ret; +} + +static __rte_always_inline void +sxe_vec_mbuf_fill(struct sxe_tx_buffer_vec *buffer_ring, + struct rte_mbuf **tx_pkts, u16 pkts_num) +{ + s32 i; + + for (i =3D 0; i < pkts_num; ++i) + buffer_ring[i].mbuf =3D tx_pkts[i]; + +} + +static inline void +sxe_tx_queue_vec_init(sxe_tx_queue_s *txq) +{ + u16 i; + volatile sxe_tx_data_desc_u *txd; + static const sxe_tx_data_desc_u zeroed_desc =3D { {0} }; + struct sxe_tx_buffer_vec *tx_buffer =3D txq->buffer_ring_vec; + + for (i =3D 0; i < txq->ring_depth; i++) + txq->desc_ring[i] =3D zeroed_desc; + + for (i =3D 0; i < txq->ring_depth; i++) { + txd =3D &txq->desc_ring[i]; + txd->wb.status =3D SXE_TX_DESC_STAT_DD; + tx_buffer[i].mbuf =3D NULL; + } + + txq->ctx_curr =3D 0; + txq->desc_used_num =3D 0; + txq->desc_free_num =3D txq->ring_depth - 1; + txq->next_to_use =3D 0; + txq->next_to_clean =3D txq->ring_depth - 1; + txq->next_dd =3D txq->rs_thresh - 1; + txq->next_rs =3D txq->rs_thresh - 1; + memset((void *)&txq->ctx_cache, 0, + SXE_CTXT_DESC_NUM * sizeof(struct sxe_ctxt_info)); + +} + +static inline void +sxe_tx_mbufs_vec_release(sxe_tx_queue_s *txq) +{ + u16 i; + struct sxe_tx_buffer_vec *tx_buffer; + const u16 max_desc =3D (u16)(txq->ring_depth - 1); + + if (txq->buffer_ring_vec =3D=3D NULL || txq->desc_free_num =3D=3D max_des= c) + return; + + for (i =3D txq->next_dd - (txq->rs_thresh - 1); + i !=3D txq->next_to_use; + i =3D (i + 1) % txq->ring_depth) { + tx_buffer =3D &txq->buffer_ring_vec[i]; + rte_pktmbuf_free_seg(tx_buffer->mbuf); + } + txq->desc_free_num =3D max_desc; + + for (i =3D 0; i < txq->ring_depth; i++) { + tx_buffer =3D &txq->buffer_ring_vec[i]; + tx_buffer->mbuf =3D NULL; + } + +} + +static inline void +sxe_tx_buffer_ring_vec_free(sxe_tx_queue_s *txq) +{ + if (txq =3D=3D NULL) + return; + + if (txq->buffer_ring_vec !=3D NULL) { + rte_free(txq->buffer_ring_vec - 1); + txq->buffer_ring_vec =3D NULL; + } + +} + +static inline s32 +sxe_default_txq_vec_setup(sxe_tx_queue_s *txq, + const struct sxe_txq_ops *txq_ops) +{ + s32 ret =3D 0; + + if (txq->buffer_ring_vec =3D=3D NULL) { + ret =3D -1; + goto l_out; + } + + txq->buffer_ring_vec =3D txq->buffer_ring_vec + 1; + txq->ops =3D txq_ops; + +l_out: + return ret; +} + +static inline int +sxe_tx_done_cleanup_vec(sxe_tx_queue_s *txq, u32 free_cnt) +{ + UNUSED(txq); + UNUSED(free_cnt); + + return -ENOTSUP; +} + +s32 sxe_txq_vec_setup(sxe_tx_queue_s *txq); + +s32 sxe_rx_vec_condition_check(struct rte_eth_dev *dev); + +s32 sxe_rxq_vec_setup(sxe_rx_queue_s *rxq); + +void sxe_rx_queue_vec_mbufs_release(sxe_rx_queue_s *rxq); + +u16 sxe_scattered_pkts_vec_recv(void *rx_queue, struct rte_mbuf **rx_pkts,= u16 pkts_num); + +u16 sxe_pkts_vec_recv(void *rx_queue, struct rte_mbuf **rx_pkts, u16 pkts_= num); + +u16 +__sxe_pkts_vector_xmit(void *tx_queue, struct rte_mbuf **tx_pkts, + u16 pkts_num); + +#endif +#endif diff --git a/drivers/net/sxe/pf/sxe_vec_neon.c b/drivers/net/sxe/pf/sxe_vec= _neon.c new file mode 100644 index 0000000000..6f9fdbd659 --- /dev/null +++ b/drivers/net/sxe/pf/sxe_vec_neon.c @@ -0,0 +1,606 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ + +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD +#include +#include "sxe_dpdk_version.h" +#if defined DPDK_20_11_5 || defined DPDK_19_11_6 +#include +#else +#include +#endif +#include + +#include +#include "sxe_vec_common.h" + +#define RTE_SXE_DESCS_PER_LOOP 4 +#define SXE_PACKET_TYPE_MASK_TUNNEL 0xFF +#define SXE_PACKET_TYPE_SHIFT 0x04 +#define SXE_RXDADV_ERR_TCPE 0x40000000 +#define SXE_VPMD_DESC_EOP_MASK 0x02020202 +#define SXE_UINT8_BIT (CHAR_BIT * sizeof(u8)) + +#pragma GCC diagnostic ignored "-Wcast-qual" + +static inline void +sxe_rxq_rearm(struct sxe_rx_queue *rxq) +{ + s32 i; + u16 rx_id; + volatile union sxe_rx_data_desc *rxdp; + struct sxe_rx_buffer *rxep =3D &rxq->buffer_ring[rxq->realloc_start]; + struct rte_mbuf *mb0, *mb1; + uint64x2_t dma_addr0, dma_addr1; + uint64x2_t zero =3D vdupq_n_u64(0); + u64 paddr; + uint8x8_t p; + + rxdp =3D rxq->desc_ring + rxq->realloc_start; + + if (unlikely(rte_mempool_get_bulk(rxq->mb_pool, + (void *)rxep, + RTE_PMD_SXE_MAX_RX_BURST) < 0)) { + if (rxq->realloc_num + RTE_PMD_SXE_MAX_RX_BURST >=3D + rxq->ring_depth) { + for (i =3D 0; i < RTE_SXE_DESCS_PER_LOOP; i++) { + rxep[i].mbuf =3D &rxq->fake_mbuf; + vst1q_u64((u64 *)&rxdp[i].read, + zero); + } + } + rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=3D + RTE_PMD_SXE_MAX_RX_BURST; + return; + } + + p =3D vld1_u8((u8 *)&rxq->mbuf_init_value); + + for (i =3D 0; i < RTE_PMD_SXE_MAX_RX_BURST; i +=3D 2, rxep +=3D 2) { + mb0 =3D rxep[0].mbuf; + mb1 =3D rxep[1].mbuf; + + vst1_u8((u8 *)&mb0->rearm_data, p); + paddr =3D mb0->buf_iova + RTE_PKTMBUF_HEADROOM; + dma_addr0 =3D vsetq_lane_u64(paddr, zero, 0); + + vst1q_u64((u64 *)&rxdp++->read, dma_addr0); + + vst1_u8((u8 *)&mb1->rearm_data, p); + paddr =3D mb1->buf_iova + RTE_PKTMBUF_HEADROOM; + dma_addr1 =3D vsetq_lane_u64(paddr, zero, 0); + vst1q_u64((u64 *)&rxdp++->read, dma_addr1); + } + + rxq->realloc_start +=3D RTE_PMD_SXE_MAX_RX_BURST; + if (rxq->realloc_start >=3D rxq->ring_depth) + rxq->realloc_start =3D 0; + + rxq->realloc_num -=3D RTE_PMD_SXE_MAX_RX_BURST; + + rx_id =3D (u16)((rxq->realloc_start =3D=3D 0) ? + (rxq->ring_depth - 1) : (rxq->realloc_start - 1)); + + sxe_write_addr(rx_id, rxq->rdt_reg_addr); + +} + +static inline void +sxe_desc_to_olflags_v(uint8x16x2_t sterr_tmp1, uint8x16x2_t sterr_tmp2, + uint8x16_t staterr, u8 vlan_flags, u16 udp_p_flag, + struct rte_mbuf **rx_pkts) +{ + u16 udp_p_flag_hi; + uint8x16_t ptype, udp_csum_skip; + uint32x4_t temp_udp_csum_skip =3D {0, 0, 0, 0}; + uint8x16_t vtag_lo, vtag_hi, vtag; + uint8x16_t temp_csum; + uint32x4_t csum =3D {0, 0, 0, 0}; + + union { + u16 e[4]; + u64 word; + } vol; + + const uint8x16_t rsstype_msk =3D { + 0x0F, 0x0F, 0x0F, 0x0F, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00}; + + const uint8x16_t rss_flags =3D { + 0, RTE_MBUF_F_RX_RSS_HASH, RTE_MBUF_F_RX_RSS_HASH, RTE_MBUF_F_RX_RSS_HA= SH, + 0, RTE_MBUF_F_RX_RSS_HASH, 0, RTE_MBUF_F_RX_RSS_HASH, + RTE_MBUF_F_RX_RSS_HASH, 0, 0, 0, + 0, 0, 0, RTE_MBUF_F_RX_FDIR}; + + const uint8x16_t vlan_csum_msk =3D { + SXE_RXD_STAT_VP, SXE_RXD_STAT_VP, + SXE_RXD_STAT_VP, SXE_RXD_STAT_VP, + 0, 0, 0, 0, + 0, 0, 0, 0, + (SXE_RXDADV_ERR_TCPE | SXE_RXDADV_ERR_IPE) >> 24, + (SXE_RXDADV_ERR_TCPE | SXE_RXDADV_ERR_IPE) >> 24, + (SXE_RXDADV_ERR_TCPE | SXE_RXDADV_ERR_IPE) >> 24, + (SXE_RXDADV_ERR_TCPE | SXE_RXDADV_ERR_IPE) >> 24}; + + const uint8x16_t vlan_csum_map_lo =3D { + RTE_MBUF_F_RX_IP_CKSUM_GOOD, + RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD, + RTE_MBUF_F_RX_IP_CKSUM_BAD, + RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD, + 0, 0, 0, 0, + vlan_flags | RTE_MBUF_F_RX_IP_CKSUM_GOOD, + vlan_flags | RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD, + vlan_flags | RTE_MBUF_F_RX_IP_CKSUM_BAD, + vlan_flags | RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD, + 0, 0, 0, 0}; + + const uint8x16_t vlan_csum_map_hi =3D { + RTE_MBUF_F_RX_L4_CKSUM_GOOD >> sizeof(u8), 0, + RTE_MBUF_F_RX_L4_CKSUM_GOOD >> sizeof(u8), 0, + 0, 0, 0, 0, + RTE_MBUF_F_RX_L4_CKSUM_GOOD >> sizeof(u8), 0, + RTE_MBUF_F_RX_L4_CKSUM_GOOD >> sizeof(u8), 0, + 0, 0, 0, 0}; + + udp_p_flag_hi =3D udp_p_flag >> 8; + + const uint8x16_t udp_hdr_p_msk =3D { + 0, 0, 0, 0, + udp_p_flag_hi, udp_p_flag_hi, udp_p_flag_hi, udp_p_flag_hi, + 0, 0, 0, 0, + 0, 0, 0, 0}; + + const uint8x16_t udp_csum_bad_shuf =3D { + 0xFF, ~(u8)RTE_MBUF_F_RX_L4_CKSUM_BAD, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0}; + + ptype =3D vzipq_u8(sterr_tmp1.val[0], sterr_tmp2.val[0]).val[0]; + + udp_csum_skip =3D vandq_u8(ptype, udp_hdr_p_msk); + + temp_udp_csum_skip =3D vcopyq_laneq_u32(temp_udp_csum_skip, 0, + vreinterpretq_u32_u8(udp_csum_skip), 1); + + ptype =3D vandq_u8(ptype, rsstype_msk); + ptype =3D vqtbl1q_u8(rss_flags, ptype); + + vtag =3D vandq_u8(staterr, vlan_csum_msk); + + temp_csum =3D vshrq_n_u8(vtag, 6); + + csum =3D vsetq_lane_u32(vgetq_lane_u32(vreinterpretq_u32_u8(temp_csum), 3= ), csum, 0); + vtag =3D vorrq_u8(vreinterpretq_u8_u32(csum), vtag); + + vtag_hi =3D vqtbl1q_u8(vlan_csum_map_hi, vtag); + vtag_hi =3D vshrq_n_u8(vtag_hi, 7); + + vtag_lo =3D vqtbl1q_u8(vlan_csum_map_lo, vtag); + vtag_lo =3D vorrq_u8(ptype, vtag_lo); + + udp_csum_skip =3D vshrq_n_u8(vreinterpretq_u8_u32(temp_udp_csum_skip), 1); + udp_csum_skip =3D vqtbl1q_u8(udp_csum_bad_shuf, udp_csum_skip); + vtag_lo =3D vandq_u8(vtag_lo, udp_csum_skip); + + vtag =3D vzipq_u8(vtag_lo, vtag_hi).val[0]; + vol.word =3D vgetq_lane_u64(vreinterpretq_u64_u8(vtag), 0); + + rx_pkts[0]->ol_flags =3D vol.e[0]; + rx_pkts[1]->ol_flags =3D vol.e[1]; + rx_pkts[2]->ol_flags =3D vol.e[2]; + rx_pkts[3]->ol_flags =3D vol.e[3]; +} + +static inline u32 +sxe_get_packet_type(u32 pkt_info, + u32 etqf_check, + u32 tunnel_check) +{ + u32 rte; + + if (etqf_check) { + rte =3D RTE_PTYPE_UNKNOWN; + goto out; + } + + if (tunnel_check) { + pkt_info &=3D SXE_PACKET_TYPE_MASK_TUNNEL; + rte =3D sxe_ptype_table_tn[pkt_info]; + goto out; + } + + pkt_info &=3D SXE_PACKET_TYPE_MASK; + rte =3D sxe_ptype_table[pkt_info]; + +out: + return rte; +} + +static inline void +sxe_desc_to_ptype_v(uint64x2_t descs[4], u16 pkt_type_mask, + struct rte_mbuf **rx_pkts) +{ + uint32x4_t etqf_check, tunnel_check; + uint32x4_t etqf_mask =3D vdupq_n_u32(0x8000); + uint32x4_t tunnel_mask =3D vdupq_n_u32(0x10000); + uint32x4_t ptype_mask =3D vdupq_n_u32((u32)pkt_type_mask); + uint32x4_t ptype0 =3D vzipq_u32(vreinterpretq_u32_u64(descs[0]), + vreinterpretq_u32_u64(descs[2])).val[0]; + uint32x4_t ptype1 =3D vzipq_u32(vreinterpretq_u32_u64(descs[1]), + vreinterpretq_u32_u64(descs[3])).val[0]; + + ptype0 =3D vzipq_u32(ptype0, ptype1).val[0]; + + etqf_check =3D vandq_u32(ptype0, etqf_mask); + tunnel_check =3D vandq_u32(ptype0, tunnel_mask); + + ptype0 =3D vandq_u32(vshrq_n_u32(ptype0, SXE_PACKET_TYPE_SHIFT), + ptype_mask); + + rx_pkts[0]->packet_type =3D + sxe_get_packet_type(vgetq_lane_u32(ptype0, 0), + vgetq_lane_u32(etqf_check, 0), + vgetq_lane_u32(tunnel_check, 0)); + rx_pkts[1]->packet_type =3D + sxe_get_packet_type(vgetq_lane_u32(ptype0, 1), + vgetq_lane_u32(etqf_check, 1), + vgetq_lane_u32(tunnel_check, 1)); + rx_pkts[2]->packet_type =3D + sxe_get_packet_type(vgetq_lane_u32(ptype0, 2), + vgetq_lane_u32(etqf_check, 2), + vgetq_lane_u32(tunnel_check, 2)); + rx_pkts[3]->packet_type =3D + sxe_get_packet_type(vgetq_lane_u32(ptype0, 3), + vgetq_lane_u32(etqf_check, 3), + vgetq_lane_u32(tunnel_check, 3)); +} + +static inline u16 +sxe_recv_raw_pkts_vec(struct sxe_rx_queue *rxq, struct rte_mbuf **rx_pkts, + u16 nb_pkts, u8 *split_packet) +{ + volatile union sxe_rx_data_desc *rxdp; + struct sxe_rx_buffer *sw_ring; + u16 nb_pkts_recd; + s32 pos; + u16 rte; + uint8x16_t shuf_msk =3D { + 0xFF, 0xFF, + 0xFF, 0xFF, + 12, 13, + 0xFF, 0xFF, + 12, 13, + 14, 15, + 4, 5, 6, 7 + }; + uint16x8_t crc_adjust =3D {0, 0, rxq->crc_len, 0, + rxq->crc_len, 0, 0, 0}; + u8 vlan_flags; + u16 udp_p_flag =3D 0; + + nb_pkts =3D RTE_ALIGN_FLOOR(nb_pkts, RTE_SXE_DESCS_PER_LOOP); + + rxdp =3D rxq->desc_ring + rxq->processing_idx; + + rte_prefetch_non_temporal(rxdp); + + if (rxq->realloc_num > RTE_PMD_SXE_MAX_RX_BURST) + sxe_rxq_rearm(rxq); + + if (!(rxdp->wb.upper.status_error & + rte_cpu_to_le_32(SXE_RXDADV_STAT_DD))) { + rte =3D 0; + goto out; + } + + udp_p_flag =3D SXE_RXDADV_PKTTYPE_UDP; + + sw_ring =3D &rxq->buffer_ring[rxq->processing_idx]; + + RTE_BUILD_BUG_ON((RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED) > UIN= T8_MAX); + vlan_flags =3D rxq->vlan_flags & UINT8_MAX; + + for (pos =3D 0, nb_pkts_recd =3D 0; pos < nb_pkts; + pos +=3D RTE_SXE_DESCS_PER_LOOP, + rxdp +=3D RTE_SXE_DESCS_PER_LOOP) { + uint64x2_t descs[RTE_SXE_DESCS_PER_LOOP]; + uint8x16_t pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4; + uint8x16x2_t sterr_tmp1, sterr_tmp2; + uint64x2_t mbp1, mbp2; + uint8x16_t staterr; + uint16x8_t tmp; + u32 stat; + + mbp1 =3D vld1q_u64((u64 *)&sw_ring[pos]); + + vst1q_u64((u64 *)&rx_pkts[pos], mbp1); + + mbp2 =3D vld1q_u64((u64 *)&sw_ring[pos + 2]); + + descs[0] =3D vld1q_u64((u64 *)(rxdp)); + descs[1] =3D vld1q_u64((u64 *)(rxdp + 1)); + descs[2] =3D vld1q_u64((u64 *)(rxdp + 2)); + descs[3] =3D vld1q_u64((u64 *)(rxdp + 3)); + + vst1q_u64((u64 *)&rx_pkts[pos + 2], mbp2); + + if (split_packet) { + rte_mbuf_prefetch_part2(rx_pkts[pos]); + rte_mbuf_prefetch_part2(rx_pkts[pos + 1]); + rte_mbuf_prefetch_part2(rx_pkts[pos + 2]); + rte_mbuf_prefetch_part2(rx_pkts[pos + 3]); + } + + pkt_mb4 =3D vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk); + pkt_mb3 =3D vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk); + + pkt_mb2 =3D vqtbl1q_u8(vreinterpretq_u8_u64(descs[1]), shuf_msk); + pkt_mb1 =3D vqtbl1q_u8(vreinterpretq_u8_u64(descs[0]), shuf_msk); + + sterr_tmp2 =3D vzipq_u8(vreinterpretq_u8_u64(descs[1]), + vreinterpretq_u8_u64(descs[3])); + sterr_tmp1 =3D vzipq_u8(vreinterpretq_u8_u64(descs[0]), + vreinterpretq_u8_u64(descs[2])); + + staterr =3D vzipq_u8(sterr_tmp1.val[1], sterr_tmp2.val[1]).val[0]; + + sxe_desc_to_olflags_v(sterr_tmp1, sterr_tmp2, staterr, vlan_flags, + udp_p_flag, &rx_pkts[pos]); + + tmp =3D vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust); + pkt_mb4 =3D vreinterpretq_u8_u16(tmp); + tmp =3D vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust); + pkt_mb3 =3D vreinterpretq_u8_u16(tmp); + + vst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1, + pkt_mb4); + vst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1, + pkt_mb3); + + tmp =3D vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust); + pkt_mb2 =3D vreinterpretq_u8_u16(tmp); + tmp =3D vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust); + pkt_mb1 =3D vreinterpretq_u8_u16(tmp); + + if (split_packet) { + stat =3D vgetq_lane_u32(vreinterpretq_u32_u8(staterr), 0); + *(s32 *)split_packet =3D ~stat & SXE_VPMD_DESC_EOP_MASK; + + split_packet +=3D RTE_SXE_DESCS_PER_LOOP; + } + + staterr =3D vshlq_n_u8(staterr, SXE_UINT8_BIT - 1); + staterr =3D vreinterpretq_u8_s8 + (vshrq_n_s8(vreinterpretq_s8_u8(staterr), + SXE_UINT8_BIT - 1)); + stat =3D ~vgetq_lane_u32(vreinterpretq_u32_u8(staterr), 0); + + rte_prefetch_non_temporal(rxdp + RTE_SXE_DESCS_PER_LOOP); + + vst1q_u8((u8 *)&rx_pkts[pos + 1]->rx_descriptor_fields1, + pkt_mb2); + vst1q_u8((u8 *)&rx_pkts[pos]->rx_descriptor_fields1, + pkt_mb1); + + sxe_desc_to_ptype_v(descs, rxq->pkt_type_mask, &rx_pkts[pos]); + + if (unlikely(stat =3D=3D 0)) { + nb_pkts_recd +=3D RTE_SXE_DESCS_PER_LOOP; + } else { + nb_pkts_recd +=3D __builtin_ctz(stat) / SXE_UINT8_BIT; + break; + } + } + + rxq->processing_idx =3D (u16)(rxq->processing_idx + nb_pkts_recd); + rxq->processing_idx =3D (u16)(rxq->processing_idx & (rxq->ring_depth - 1)= ); + rxq->realloc_num =3D (u16)(rxq->realloc_num + nb_pkts_recd); + + rte =3D nb_pkts_recd; + +out: + return rte; +} + +u16 +sxe_pkts_vec_recv(void *rx_queue, struct rte_mbuf **rx_pkts, u16 nb_pkts) +{ + return sxe_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL); +} + +static u16 +sxe_recv_scattered_burst_vec(void *rx_queue, struct rte_mbuf **rx_pkts, + u16 nb_pkts) +{ + u32 i =3D 0; + struct sxe_rx_queue *rxq =3D rx_queue; + u8 split_flags[RTE_PMD_SXE_MAX_RX_BURST] =3D {0}; + + u16 nb_bufs =3D sxe_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts, + split_flags); + if (nb_bufs =3D=3D 0) + goto l_out; + + const u64 *split_fl64 =3D (u64 *)split_flags; + if (rxq->pkt_first_seg =3D=3D NULL && + split_fl64[0] =3D=3D 0 && split_fl64[1] =3D=3D 0 && + split_fl64[2] =3D=3D 0 && split_fl64[3] =3D=3D 0) + goto l_out; + + if (rxq->pkt_first_seg =3D=3D NULL) { + while (i < nb_bufs && !split_flags[i]) + i++; + if (i =3D=3D nb_bufs) + goto l_out; + rxq->pkt_first_seg =3D rx_pkts[i]; + } + + nb_bufs =3D i + sxe_packets_reassemble(rxq, &rx_pkts[i], nb_bufs - i, + &split_flags[i]); + +l_out: + return nb_bufs; +} + +u16 +sxe_scattered_pkts_vec_recv(void *rx_queue, struct rte_mbuf **rx_pkts, + u16 nb_pkts) +{ + u16 retval =3D 0; + + while (nb_pkts > RTE_PMD_SXE_MAX_RX_BURST) { + u16 burst; + + burst =3D sxe_recv_scattered_burst_vec(rx_queue, + rx_pkts + retval, + RTE_PMD_SXE_MAX_RX_BURST); + retval +=3D burst; + nb_pkts -=3D burst; + if (burst < RTE_PMD_SXE_MAX_RX_BURST) + goto l_out; + } + + retval +=3D sxe_recv_scattered_burst_vec(rx_queue, + rx_pkts + retval, + nb_pkts); +l_out: + return retval; +} + +static inline void +sxe_single_vec_desc_fill(volatile union sxe_tx_data_desc *txdp, + struct rte_mbuf *pkt, u64 flags) +{ + uint64x2_t descriptor =3D { + pkt->buf_iova + pkt->data_off, + (u64)pkt->pkt_len << 46 | flags | pkt->data_len}; + + vst1q_u64((u64 *)&txdp->read, descriptor); +} + +static inline void +sxe_vec_desc_fill(volatile union sxe_tx_data_desc *txdp, + struct rte_mbuf **pkt, u16 nb_pkts, u64 flags) +{ + s32 i; + + for (i =3D 0; i < nb_pkts; ++i, ++txdp, ++pkt) + sxe_single_vec_desc_fill(txdp, *pkt, flags); +} + +u16 __sxe_pkts_vector_xmit(void *tx_queue, struct rte_mbuf **tx_pkts, + u16 nb_pkts) +{ + struct sxe_tx_queue *txq =3D (struct sxe_tx_queue *)tx_queue; + volatile union sxe_tx_data_desc *txdp; + struct sxe_tx_buffer_vec *txep; + u16 n, nb_commit, tx_id; + u64 flags =3D SXE_TX_DESC_FLAGS; + u64 rs =3D SXE_TX_DESC_RS_MASK | SXE_TX_DESC_FLAGS; + s32 i; + + nb_pkts =3D RTE_MIN(nb_pkts, txq->rs_thresh); + + if (txq->desc_free_num < txq->free_thresh) + sxe_tx_bufs_vec_free(txq); + + nb_commit =3D nb_pkts =3D (u16)RTE_MIN(txq->desc_free_num, nb_pkts); + if (unlikely(nb_pkts =3D=3D 0)) + goto l_out; + + tx_id =3D txq->next_to_use; + txdp =3D &txq->desc_ring[tx_id]; + txep =3D &txq->buffer_ring_vec[tx_id]; + + txq->desc_free_num =3D (u16)(txq->desc_free_num - nb_pkts); + + n =3D (u16)(txq->ring_depth - tx_id); + if (nb_commit >=3D n) { + sxe_vec_mbuf_fill(txep, tx_pkts, n); + + for (i =3D 0; i < n - 1; ++i, ++tx_pkts, ++txdp) + sxe_single_vec_desc_fill(txdp, *tx_pkts, flags); + + sxe_single_vec_desc_fill(txdp, *tx_pkts++, rs); + + nb_commit =3D (u16)(nb_commit - n); + + tx_id =3D 0; + txq->next_rs =3D (u16)(txq->rs_thresh - 1); + + txdp =3D &txq->desc_ring[tx_id]; + txep =3D &txq->buffer_ring_vec[tx_id]; + } + + sxe_vec_mbuf_fill(txep, tx_pkts, nb_commit); + sxe_vec_desc_fill(txdp, tx_pkts, nb_commit, flags); + + tx_id =3D (u16)(tx_id + nb_commit); + if (tx_id > txq->next_rs) { + txq->desc_ring[txq->next_rs].read.cmd_type_len |=3D + rte_cpu_to_le_32(SXE_TX_DESC_RS_MASK); + txq->next_rs =3D (u16)(txq->next_rs + + txq->rs_thresh); + } + + txq->next_to_use =3D tx_id; + + sxe_write_addr(txq->next_to_use, txq->tdt_reg_addr); + +l_out: + return nb_pkts; +} + +static void __rte_cold +sxe_tx_queue_release_mbufs_vec(struct sxe_tx_queue *txq) +{ + sxe_tx_mbufs_vec_release(txq); +} + +void __rte_cold +sxe_rx_queue_vec_mbufs_release(struct sxe_rx_queue *rxq) +{ + sxe_rx_vec_mbufs_release(rxq); +} + +static void __rte_cold +sxe_tx_free_swring(struct sxe_tx_queue *txq) +{ + sxe_tx_buffer_ring_vec_free(txq); +} + +static void __rte_cold +sxe_reset_tx_queue(struct sxe_tx_queue *txq) +{ + sxe_tx_queue_vec_init(txq); +} + +static const struct sxe_txq_ops vec_txq_ops =3D { + .init =3D sxe_reset_tx_queue, + .mbufs_release =3D sxe_tx_queue_release_mbufs_vec, + .buffer_ring_free =3D sxe_tx_free_swring, +}; + +s32 __rte_cold +sxe_rxq_vec_setup(struct sxe_rx_queue *rxq) +{ + return sxe_default_rxq_vec_setup(rxq); +} + +s32 __rte_cold +sxe_txq_vec_setup(struct sxe_tx_queue *txq) +{ + return sxe_default_txq_vec_setup(txq, &vec_txq_ops); +} + +s32 __rte_cold +sxe_rx_vec_condition_check(struct rte_eth_dev *dev) +{ + return sxe_default_rx_vec_condition_check(dev); +} + +#endif diff --git a/drivers/net/sxe/pf/sxe_vec_sse.c b/drivers/net/sxe/pf/sxe_vec_= sse.c new file mode 100644 index 0000000000..1c2c319b92 --- /dev/null +++ b/drivers/net/sxe/pf/sxe_vec_sse.c @@ -0,0 +1,634 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C), 2022, Linkdata Technology Co., Ltd. + */ + +#if defined SXE_DPDK_L4_FEATURES && defined SXE_DPDK_SIMD +#include +#include "sxe_dpdk_version.h" +#if defined DPDK_20_11_5 || defined DPDK_19_11_6 +#include +#else +#include +#endif +#include +#include + +#include "sxe_vec_common.h" +#include "sxe_compat_version.h" + +#pragma GCC diagnostic ignored "-Wcast-qual" + +#define SXE_MAX_TX_FREE_BUF_SZ 64 + +static inline void +sxe_rxq_realloc(sxe_rx_queue_s *rx_queue) +{ + s32 i; + u16 rx_index; + volatile union sxe_rx_data_desc *desc_ring; + sxe_rx_buffer_s *buf_ring =3D + &rx_queue->buffer_ring[rx_queue->realloc_start]; + struct rte_mbuf *mbuf_0, *mbuf_1; + __m128i head_room =3D _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, + RTE_PKTMBUF_HEADROOM); + __m128i dma_addr0, dma_addr1; + + const __m128i addr_mask =3D _mm_set_epi64x(0, UINT64_MAX); + + desc_ring =3D rx_queue->desc_ring + rx_queue->realloc_start; + + if (rte_mempool_get_bulk(rx_queue->mb_pool, + (void *)buf_ring, + RTE_PMD_SXE_MAX_RX_BURST) < 0) { + if (rx_queue->realloc_num + RTE_PMD_SXE_MAX_RX_BURST >=3D + rx_queue->ring_depth) { + dma_addr0 =3D _mm_setzero_si128(); + for (i =3D 0; i < SXE_DESCS_PER_LOOP; i++) { + buf_ring[i].mbuf =3D &rx_queue->fake_mbuf; + _mm_store_si128((__m128i *)&desc_ring[i].read, + dma_addr0); + } + } + rte_eth_devices[rx_queue->port_id].data->rx_mbuf_alloc_failed +=3D + RTE_PMD_SXE_MAX_RX_BURST; + return; + } + + for (i =3D 0; i < RTE_PMD_SXE_MAX_RX_BURST; i +=3D 2, buf_ring +=3D 2) { + __m128i vaddr0, vaddr1; + + mbuf_0 =3D buf_ring[0].mbuf; + mbuf_1 =3D buf_ring[1].mbuf; + + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=3D + offsetof(struct rte_mbuf, buf_addr) + 8); + + vaddr0 =3D _mm_loadu_si128((__m128i *)&(mbuf_0->buf_addr)); + vaddr1 =3D _mm_loadu_si128((__m128i *)&(mbuf_1->buf_addr)); + + dma_addr0 =3D _mm_unpackhi_epi64(vaddr0, vaddr0); + dma_addr1 =3D _mm_unpackhi_epi64(vaddr1, vaddr1); + + dma_addr0 =3D _mm_add_epi64(dma_addr0, head_room); + dma_addr1 =3D _mm_add_epi64(dma_addr1, head_room); + + dma_addr0 =3D _mm_and_si128(dma_addr0, addr_mask); + dma_addr1 =3D _mm_and_si128(dma_addr1, addr_mask); + + _mm_store_si128((__m128i *)&desc_ring++->read, dma_addr0); + _mm_store_si128((__m128i *)&desc_ring++->read, dma_addr1); + } + + rx_queue->realloc_start +=3D RTE_PMD_SXE_MAX_RX_BURST; + if (rx_queue->realloc_start >=3D rx_queue->ring_depth) + rx_queue->realloc_start =3D 0; + + rx_queue->realloc_num -=3D RTE_PMD_SXE_MAX_RX_BURST; + + rx_index =3D (u16) ((rx_queue->realloc_start =3D=3D 0) ? + (rx_queue->ring_depth - 1) : (rx_queue->realloc_start - 1)); + + SXE_PCI_REG_WC_WRITE_RELAXED(rx_queue->rdt_reg_addr, rx_index); + +} + +static inline void +sxe_desc_to_olflags(__m128i descs[4], __m128i mbuf_init, u8 vlan_flags, + u16 udp_p_flag, struct rte_mbuf **rx_pkts) +{ + __m128i ptype0, ptype1, vtype0, vtype1, csum, udp_csum_skip; + __m128i rearm0, rearm1, rearm2, rearm3; + + const __m128i rsstype_mask =3D _mm_set_epi16( + 0x0000, 0x0000, 0x0000, 0x0000, + 0x000F, 0x000F, 0x000F, 0x000F); + + const __m128i ol_flags_mask =3D _mm_set_epi16( + 0x0000, 0x0000, 0x0000, 0x0000, + 0x00FF, 0x00FF, 0x00FF, 0x00FF); + + const __m128i rss_flags =3D _mm_set_epi8(RTE_MBUF_F_RX_FDIR, 0, 0, 0, + 0, 0, 0, RTE_MBUF_F_RX_RSS_HASH, + RTE_MBUF_F_RX_RSS_HASH, 0, RTE_MBUF_F_RX_RSS_HASH, 0, + RTE_MBUF_F_RX_RSS_HASH, RTE_MBUF_F_RX_RSS_HASH, RTE_MBUF_F_RX_RSS_HASH,= 0); + + const __m128i vlan_csum_mask =3D _mm_set_epi16( + (SXE_RXDADV_ERR_L4E | SXE_RXDADV_ERR_IPE) >> 16, + (SXE_RXDADV_ERR_L4E | SXE_RXDADV_ERR_IPE) >> 16, + (SXE_RXDADV_ERR_L4E | SXE_RXDADV_ERR_IPE) >> 16, + (SXE_RXDADV_ERR_L4E | SXE_RXDADV_ERR_IPE) >> 16, + SXE_RXD_STAT_VP, SXE_RXD_STAT_VP, + SXE_RXD_STAT_VP, SXE_RXD_STAT_VP); + + const __m128i vlan_csum_map_low =3D _mm_set_epi8( + 0, 0, 0, 0, + vlan_flags | RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD, + vlan_flags | RTE_MBUF_F_RX_IP_CKSUM_BAD, + vlan_flags | RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD, + vlan_flags | RTE_MBUF_F_RX_IP_CKSUM_GOOD, + 0, 0, 0, 0, + RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD, + RTE_MBUF_F_RX_IP_CKSUM_BAD, + RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD, + RTE_MBUF_F_RX_IP_CKSUM_GOOD); + + const __m128i vlan_csum_map_high =3D _mm_set_epi8( + 0, 0, 0, 0, + 0, RTE_MBUF_F_RX_L4_CKSUM_GOOD >> sizeof(u8), 0, + RTE_MBUF_F_RX_L4_CKSUM_GOOD >> sizeof(u8), + 0, 0, 0, 0, + 0, RTE_MBUF_F_RX_L4_CKSUM_GOOD >> sizeof(u8), 0, + RTE_MBUF_F_RX_L4_CKSUM_GOOD >> sizeof(u8)); + + const __m128i udp_hdr_p_msk =3D _mm_set_epi16 + (0, 0, 0, 0, + udp_p_flag, udp_p_flag, udp_p_flag, udp_p_flag); + + const __m128i udp_csum_bad_shuf =3D _mm_set_epi8 + (0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, ~(u8)RTE_MBUF_F_RX_L4_CKSUM_BAD, 0xFF); + + ptype0 =3D _mm_unpacklo_epi16(descs[0], descs[1]); + ptype1 =3D _mm_unpacklo_epi16(descs[2], descs[3]); + + vtype0 =3D _mm_unpackhi_epi16(descs[0], descs[1]); + vtype1 =3D _mm_unpackhi_epi16(descs[2], descs[3]); + + ptype0 =3D _mm_unpacklo_epi32(ptype0, ptype1); + + udp_csum_skip =3D _mm_and_si128(ptype0, udp_hdr_p_msk); + + ptype0 =3D _mm_and_si128(ptype0, rsstype_mask); + + ptype0 =3D _mm_shuffle_epi8(rss_flags, ptype0); + + vtype1 =3D _mm_unpacklo_epi32(vtype0, vtype1); + vtype1 =3D _mm_and_si128(vtype1, vlan_csum_mask); + + csum =3D _mm_srli_epi16(vtype1, 14); + + csum =3D _mm_srli_si128(csum, 8); + vtype1 =3D _mm_or_si128(csum, vtype1); + + vtype0 =3D _mm_shuffle_epi8(vlan_csum_map_high, vtype1); + vtype0 =3D _mm_slli_epi16(vtype0, sizeof(u8)); + + vtype1 =3D _mm_shuffle_epi8(vlan_csum_map_low, vtype1); + vtype1 =3D _mm_and_si128(vtype1, ol_flags_mask); + vtype1 =3D _mm_or_si128(vtype0, vtype1); + + vtype1 =3D _mm_or_si128(ptype0, vtype1); + + udp_csum_skip =3D _mm_srli_epi16(udp_csum_skip, 9); + udp_csum_skip =3D _mm_shuffle_epi8(udp_csum_bad_shuf, udp_csum_skip); + vtype1 =3D _mm_and_si128(vtype1, udp_csum_skip); + + rearm0 =3D _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtype1, 8), 0x10); + rearm1 =3D _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtype1, 6), 0x10); + rearm2 =3D _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtype1, 4), 0x10); + rearm3 =3D _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtype1, 2), 0x10); + + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=3D + offsetof(struct rte_mbuf, rearm_data) + 8); + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=3D + RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16)); + + _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0); + _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1); + _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2); + _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3); + +} + +static inline u32 sxe_packet_type_get(int index, + u32 pkt_info, + u32 etqf_check) +{ + if (etqf_check & (0x02 << (index * SXE_DESCS_PER_LOOP))) + return RTE_PTYPE_UNKNOWN; + + pkt_info &=3D SXE_PACKET_TYPE_MASK; + return sxe_ptype_table[pkt_info]; +} + +static inline void +sxe_desc_to_ptype_vec(__m128i descs[4], u16 pkt_type_mask, + struct rte_mbuf **rx_pkts) +{ + __m128i etqf_mask =3D _mm_set_epi64x(0x800000008000LL, 0x800000008000LL); + __m128i ptype_mask =3D _mm_set_epi32( + pkt_type_mask, pkt_type_mask, pkt_type_mask, pkt_type_mask); + + u32 etqf_check, pkt_info; + + __m128i ptype0 =3D _mm_unpacklo_epi32(descs[0], descs[2]); + __m128i ptype1 =3D _mm_unpacklo_epi32(descs[1], descs[3]); + + ptype0 =3D _mm_unpacklo_epi32(ptype0, ptype1); + + etqf_check =3D _mm_movemask_epi8(_mm_and_si128(ptype0, etqf_mask)); + + ptype0 =3D _mm_and_si128(_mm_srli_epi32(ptype0, SXE_RXDADV_PKTTYPE_ETQF_S= HIFT), + ptype_mask); + + + pkt_info =3D _mm_extract_epi32(ptype0, 0); + rx_pkts[0]->packet_type =3D + sxe_packet_type_get(0, pkt_info, etqf_check); + pkt_info =3D _mm_extract_epi32(ptype0, 1); + rx_pkts[1]->packet_type =3D + sxe_packet_type_get(1, pkt_info, etqf_check); + pkt_info =3D _mm_extract_epi32(ptype0, 2); + rx_pkts[2]->packet_type =3D + sxe_packet_type_get(2, pkt_info, etqf_check); + pkt_info =3D _mm_extract_epi32(ptype0, 3); + rx_pkts[3]->packet_type =3D + sxe_packet_type_get(3, pkt_info, etqf_check); + +} + +static inline u16 +sxe_raw_pkts_vec_recv(sxe_rx_queue_s *rx_queue, struct rte_mbuf **rx_pkts, + u16 pkts_num, u8 *split_packet) +{ + volatile union sxe_rx_data_desc *desc_ring; + sxe_rx_buffer_s *buffer_ring; + u16 pkts_recd_num; + s32 pos; + u64 var; + __m128i shuf_msk; + __m128i crc_adjust =3D _mm_set_epi16( + 0, 0, 0, + -rx_queue->crc_len, + 0, + -rx_queue->crc_len, + 0, 0 + ); + + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=3D + offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4); + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=3D + offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8); + __m128i dd_check, eop_check; + __m128i mbuf_init; + u8 vlan_flags; + u16 udp_p_flag =3D 0; + + pkts_num =3D RTE_MIN(pkts_num, RTE_PMD_SXE_MAX_RX_BURST); + + pkts_num =3D RTE_ALIGN_FLOOR(pkts_num, SXE_DESCS_PER_LOOP); + + desc_ring =3D rx_queue->desc_ring + rx_queue->processing_idx; + + rte_prefetch0(desc_ring); + + if (rx_queue->realloc_num > RTE_PMD_SXE_MAX_RX_BURST) + sxe_rxq_realloc(rx_queue); + + if (!(desc_ring->wb.upper.status_error & + rte_cpu_to_le_32(SXE_RXDADV_STAT_DD))) { + pkts_recd_num =3D 0; + goto l_out; + } + + udp_p_flag =3D SXE_RXDADV_PKTTYPE_UDP; + + dd_check =3D _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL); + + eop_check =3D _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL); + + shuf_msk =3D _mm_set_epi8( + 7, 6, 5, 4, + 15, 14, + 13, 12, + 0xFF, 0xFF, + 13, 12, + 0xFF, 0xFF, + 0xFF, 0xFF + ); + + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=3D + offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4); + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=3D + offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8); + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=3D + offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10); + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=3D + offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12); + + mbuf_init =3D _mm_set_epi64x(0, rx_queue->mbuf_init_value); + + buffer_ring =3D &rx_queue->buffer_ring[rx_queue->processing_idx]; + + RTE_BUILD_BUG_ON((RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED) > UIN= T8_MAX); + vlan_flags =3D rx_queue->vlan_flags & UINT8_MAX; + + for (pos =3D 0, pkts_recd_num =3D 0; pos < pkts_num; + pos +=3D SXE_DESCS_PER_LOOP, + desc_ring +=3D SXE_DESCS_PER_LOOP) { + __m128i descs[SXE_DESCS_PER_LOOP]; + __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4; + __m128i zero, staterr, state_err1, state_err2; + __m128i mbp1; +#if defined(RTE_ARCH_X86_64) + __m128i mbp2; +#endif + + mbp1 =3D _mm_loadu_si128((__m128i *)&buffer_ring[pos]); + + descs[3] =3D _mm_loadu_si128((__m128i *)(desc_ring + 3)); + rte_compiler_barrier(); + + _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1); + +#if defined(RTE_ARCH_X86_64) + mbp2 =3D _mm_loadu_si128((__m128i *)&buffer_ring[pos+2]); +#endif + + descs[2] =3D _mm_loadu_si128((__m128i *)(desc_ring + 2)); + rte_compiler_barrier(); + descs[1] =3D _mm_loadu_si128((__m128i *)(desc_ring + 1)); + rte_compiler_barrier(); + descs[0] =3D _mm_loadu_si128((__m128i *)(desc_ring)); + +#if defined(RTE_ARCH_X86_64) + _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2); +#endif + + if (split_packet) { + rte_mbuf_prefetch_part2(rx_pkts[pos]); + rte_mbuf_prefetch_part2(rx_pkts[pos + 1]); + rte_mbuf_prefetch_part2(rx_pkts[pos + 2]); + rte_mbuf_prefetch_part2(rx_pkts[pos + 3]); + } + + rte_compiler_barrier(); + + pkt_mb4 =3D _mm_shuffle_epi8(descs[3], shuf_msk); + pkt_mb3 =3D _mm_shuffle_epi8(descs[2], shuf_msk); + pkt_mb2 =3D _mm_shuffle_epi8(descs[1], shuf_msk); + pkt_mb1 =3D _mm_shuffle_epi8(descs[0], shuf_msk); + + state_err2 =3D _mm_unpackhi_epi32(descs[3], descs[2]); + state_err1 =3D _mm_unpackhi_epi32(descs[1], descs[0]); + + sxe_desc_to_olflags(descs, mbuf_init, vlan_flags, udp_p_flag, + &rx_pkts[pos]); + + pkt_mb4 =3D _mm_add_epi16(pkt_mb4, crc_adjust); + pkt_mb3 =3D _mm_add_epi16(pkt_mb3, crc_adjust); + + zero =3D _mm_xor_si128(dd_check, dd_check); + + staterr =3D _mm_unpacklo_epi32(state_err1, state_err2); + + _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1, + pkt_mb4); + _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1, + pkt_mb3); + + pkt_mb2 =3D _mm_add_epi16(pkt_mb2, crc_adjust); + pkt_mb1 =3D _mm_add_epi16(pkt_mb1, crc_adjust); + + if (split_packet) { + __m128i eop_shuf_mask =3D _mm_set_epi8( + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0x04, 0x0C, 0x00, 0x08 + ); + + __m128i eop_bits =3D _mm_andnot_si128(staterr, eop_check); + eop_bits =3D _mm_shuffle_epi8(eop_bits, eop_shuf_mask); + *(int *)split_packet =3D _mm_cvtsi128_si32(eop_bits); + split_packet +=3D SXE_DESCS_PER_LOOP; + } + + staterr =3D _mm_and_si128(staterr, dd_check); + + staterr =3D _mm_packs_epi32(staterr, zero); + + _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1, + pkt_mb2); + _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1, + pkt_mb1); + + sxe_desc_to_ptype_vec(descs, rx_queue->pkt_type_mask, &rx_pkts[pos]); + + var =3D __builtin_popcountll(_mm_cvtsi128_si64(staterr)); + pkts_recd_num +=3D var; + if (likely(var !=3D SXE_DESCS_PER_LOOP)) + break; + } + + rx_queue->processing_idx =3D (u16)(rx_queue->processing_idx + pkts_recd_n= um); + rx_queue->processing_idx =3D (u16)(rx_queue->processing_idx & (rx_queue->= ring_depth - 1)); + rx_queue->realloc_num =3D (u16)(rx_queue->realloc_num + pkts_recd_num); + +l_out: + return pkts_recd_num; +} + +u16 +sxe_pkts_vec_recv(void *rx_queue, struct rte_mbuf **rx_pkts, u16 pkts_num) +{ + return sxe_raw_pkts_vec_recv(rx_queue, rx_pkts, pkts_num, NULL); +} + +static u16 +sxe_scattered_burst_vec_recv(void *rx_queue, struct rte_mbuf **rx_pkts, + u16 pkts_num) +{ + u16 i =3D 0; + u16 bufs_num; + sxe_rx_queue_s *rxq =3D rx_queue; + u8 split_flags[RTE_PMD_SXE_MAX_RX_BURST] =3D {0}; + + bufs_num =3D sxe_raw_pkts_vec_recv(rxq, rx_pkts, pkts_num, + split_flags); + if (bufs_num =3D=3D 0) + goto l_out; + + const u64 *split_flag_64 =3D (u64 *)split_flags; + if (rxq->pkt_first_seg =3D=3D NULL && + split_flag_64[0] =3D=3D 0 && split_flag_64[1] =3D=3D 0 && + split_flag_64[2] =3D=3D 0 && split_flag_64[3] =3D=3D 0) + goto l_out; + + if (rxq->pkt_first_seg =3D=3D NULL) { + while (i < bufs_num && !split_flags[i]) + i++; + if (i =3D=3D bufs_num) + goto l_out; + rxq->pkt_first_seg =3D rx_pkts[i]; + } + + bufs_num =3D i + sxe_packets_reassemble(rxq, &rx_pkts[i], bufs_num - i, + &split_flags[i]); + +l_out: + return bufs_num; +} + +u16 +sxe_scattered_pkts_vec_recv(void *rx_queue, struct rte_mbuf **rx_pkts, + u16 pkts_num) +{ + u16 ret =3D 0; + + while (pkts_num > RTE_PMD_SXE_MAX_RX_BURST) { + u16 burst; + + burst =3D sxe_scattered_burst_vec_recv(rx_queue, + rx_pkts + ret, + RTE_PMD_SXE_MAX_RX_BURST); + ret +=3D burst; + pkts_num -=3D burst; + if (burst < RTE_PMD_SXE_MAX_RX_BURST) + goto l_out; + } + + ret +=3D sxe_scattered_burst_vec_recv(rx_queue, + rx_pkts + ret, + pkts_num); +l_out: + return ret; +} + +void __rte_cold +sxe_rx_queue_vec_mbufs_release(sxe_rx_queue_s *rx_queue) +{ + sxe_rx_vec_mbufs_release(rx_queue); +} + +s32 __rte_cold +sxe_rxq_vec_setup(sxe_rx_queue_s *rx_queue) +{ + return sxe_default_rxq_vec_setup(rx_queue); +} + +s32 __rte_cold +sxe_rx_vec_condition_check(struct rte_eth_dev *dev) +{ + return sxe_default_rx_vec_condition_check(dev); +} + +static inline void +sxe_single_vec_desc_fill(volatile sxe_tx_data_desc_u *desc_ring, + struct rte_mbuf *pkts, u64 flags) +{ + __m128i descriptor =3D _mm_set_epi64x((u64)pkts->pkt_len << 46 | + flags | pkts->data_len, + pkts->buf_iova + pkts->data_off); + _mm_store_si128((__m128i *)&desc_ring->read, descriptor); +} + +static inline void +sxe_vec_desc_fill(volatile sxe_tx_data_desc_u *desc_ring, + struct rte_mbuf **pkts, u16 pkts_num, u64 flags) +{ + s32 i; + + for (i =3D 0; i < pkts_num; ++i, ++desc_ring, ++pkts) + sxe_single_vec_desc_fill(desc_ring, *pkts, flags); + +} + +u16 +__sxe_pkts_vector_xmit(void *tx_queue, struct rte_mbuf **tx_pkts, + u16 pkts_num) +{ + sxe_tx_queue_s *txq =3D (sxe_tx_queue_s *)tx_queue; + volatile sxe_tx_data_desc_u *desc_ring; + struct sxe_tx_buffer_vec *buffer_ring; + u16 n, commit_num, ntu, xmit_pkts_num; + u64 flags =3D SXE_TX_DESC_FLAGS; + u64 rs_flags =3D SXE_TX_DESC_RS_MASK | SXE_TX_DESC_FLAGS; + s32 i; + + if (txq->desc_free_num < txq->free_thresh) + sxe_tx_bufs_vec_free(txq); + + xmit_pkts_num =3D RTE_MIN(pkts_num, txq->rs_thresh); + xmit_pkts_num =3D (u16)RTE_MIN(txq->desc_free_num, xmit_pkts_num); + + commit_num =3D xmit_pkts_num; + if (unlikely(commit_num =3D=3D 0)) + goto l_out; + + ntu =3D txq->next_to_use; + desc_ring =3D &txq->desc_ring[ntu]; + buffer_ring =3D &txq->buffer_ring_vec[ntu]; + + txq->desc_free_num =3D (u16)(txq->desc_free_num - xmit_pkts_num); + + n =3D (u16)(txq->ring_depth - ntu); + if (commit_num >=3D n) { + sxe_vec_mbuf_fill(buffer_ring, tx_pkts, n); + + for (i =3D 0; i < n - 1; ++i, ++tx_pkts, ++desc_ring) + sxe_single_vec_desc_fill(desc_ring, *tx_pkts, flags); + + sxe_single_vec_desc_fill(desc_ring, *tx_pkts++, rs_flags); + + commit_num =3D (u16)(commit_num - n); + + ntu =3D 0; + txq->next_rs =3D (u16)(txq->rs_thresh - 1); + + desc_ring =3D &txq->desc_ring[ntu]; + buffer_ring =3D &txq->buffer_ring_vec[ntu]; + } + + sxe_vec_mbuf_fill(buffer_ring, tx_pkts, commit_num); + + sxe_vec_desc_fill(desc_ring, tx_pkts, commit_num, flags); + + ntu =3D (u16)(ntu + commit_num); + if (ntu > txq->next_rs) { + txq->desc_ring[txq->next_rs].read.cmd_type_len |=3D + rte_cpu_to_le_32(SXE_TX_DESC_RS_MASK); + txq->next_rs =3D (u16)(txq->next_rs + + txq->rs_thresh); + } + + txq->next_to_use =3D ntu; + rte_wmb(); + rte_write32_wc_relaxed((rte_cpu_to_le_32(txq->next_to_use)), + txq->tdt_reg_addr); + +l_out: + return xmit_pkts_num; +} + +static void __rte_cold +sxe_tx_queue_init(sxe_tx_queue_s *tx_queue) +{ + sxe_tx_queue_vec_init(tx_queue); +} + +static void __rte_cold +sxe_tx_queue_mbufs_release(sxe_tx_queue_s *tx_queue) +{ + sxe_tx_mbufs_vec_release(tx_queue); +} + +static void __rte_cold +sxe_tx_buffer_ring_free(sxe_tx_queue_s *tx_queue) +{ + sxe_tx_buffer_ring_vec_free(tx_queue); +} + +static const struct sxe_txq_ops txq_vec_ops =3D { + .init =3D sxe_tx_queue_init, + .mbufs_release =3D sxe_tx_queue_mbufs_release, + .buffer_ring_free =3D sxe_tx_buffer_ring_free, +}; + +s32 __rte_cold +sxe_txq_vec_setup(sxe_tx_queue_s *tx_queue) +{ + return sxe_default_txq_vec_setup(tx_queue, &txq_vec_ops); +} + +#endif diff --git a/drivers/net/sxe/pf/sxe_vf.c b/drivers/net/sxe/pf/sxe_vf.c index 74a0bbb370..4b8813e6de 100644 --- a/drivers/net/sxe/pf/sxe_vf.c +++ b/drivers/net/sxe/pf/sxe_vf.c @@ -33,7 +33,7 @@ #define SXE_MR_VLAN_MASK 0xFFFFFFFF #define SXE_MR_VLAN_MSB_BIT_OFFSET 32 =20 -#define SXE_MR_VIRTUAL_POOL_MASK 0xFFFFFFFF +#define SXE_MR_VIRTUAL_POOL_MASK 0xFFFFFFFF #define SXE_MR_VIRTUAL_POOL_MSB_BIT_MASK 32 =20 static inline s32 sxe_vf_mac_addr_generate(struct rte_eth_dev *eth_dev, u1= 6 vf_num) @@ -83,7 +83,6 @@ static void sxe_vt_mode_configure(struct rte_eth_dev *eth= _dev) sxe_hw_pcie_vt_mode_set(hw, pcie_ext); sxe_hw_irq_general_reg_set(hw, gpie); =20 - return; } =20 s32 sxe_vt_init(struct rte_eth_dev *eth_dev) @@ -126,13 +125,13 @@ s32 sxe_vt_init(struct rte_eth_dev *eth_dev) memset(mirror_info, 0, sizeof(struct sxe_mirror_info)); #endif =20 - if (vf_num >=3D RTE_ETH_32_POOLS) {=20 + if (vf_num >=3D RTE_ETH_32_POOLS) { nb_queue =3D 2; RTE_ETH_DEV_SRIOV(eth_dev).active =3D RTE_ETH_64_POOLS; - } else if (vf_num >=3D RTE_ETH_16_POOLS) {=20 + } else if (vf_num >=3D RTE_ETH_16_POOLS) { nb_queue =3D 4; RTE_ETH_DEV_SRIOV(eth_dev).active =3D RTE_ETH_32_POOLS; - } else {=20 + } else { nb_queue =3D 8; RTE_ETH_DEV_SRIOV(eth_dev).active =3D RTE_ETH_16_POOLS; } @@ -150,7 +149,7 @@ s32 sxe_vt_init(struct rte_eth_dev *eth_dev) sxe_vt_mode_configure(eth_dev); =20 LOG_INFO_BDF("vf_num:%d domain id:%u init done.", - vf_num, (*vf_info)->domain_id); + vf_num, (*vf_info)->domain_id); =20 l_out: return ret; @@ -166,7 +165,7 @@ static void sxe_pf_pool_enable(struct rte_eth_dev *eth_= dev, u16 vf_num) struct sxe_adapter *adapter =3D eth_dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; u32 enable_mask =3D ~0; - u8 vf_reg_idx =3D ((vf_num >> 5) > 0) ? 1: 0; + u8 vf_reg_idx =3D ((vf_num >> 5) > 0) ? 1 : 0; u8 vf_bit_index =3D vf_num & ((1 << 5) - 1); =20 sxe_hw_rx_pool_bitmap_set(hw, vf_reg_idx, enable_mask << vf_bit_index); @@ -175,7 +174,6 @@ static void sxe_pf_pool_enable(struct rte_eth_dev *eth_= dev, u16 vf_num) sxe_hw_tx_pool_bitmap_set(hw, vf_reg_idx, enable_mask << vf_bit_index); sxe_hw_tx_pool_bitmap_set(hw, (vf_reg_idx ^ 1), (vf_reg_idx - 1)); =20 - return; } =20 static void sxe_vf_vlan_filter_enable(struct rte_eth_dev *eth_dev) @@ -190,11 +188,9 @@ static void sxe_vf_vlan_filter_enable(struct rte_eth_d= ev *eth_dev) vlan_ctl |=3D SXE_VLNCTRL_VFE; sxe_hw_vlan_type_set(hw, vlan_ctl); =20 - for (i =3D 0; i < SXE_VFT_TBL_SIZE; i++) { + for (i =3D 0; i < SXE_VFT_TBL_SIZE; i++) sxe_hw_vlan_filter_array_write(hw, i, enable_mask); - } =20 - return; } =20 void sxe_vt_configure(struct rte_eth_dev *eth_dev) @@ -207,7 +203,7 @@ void sxe_vt_configure(struct rte_eth_dev *eth_dev) vf_num =3D sxe_vf_num_get(eth_dev); if (vf_num =3D=3D 0) { LOG_WARN_BDF("no vf, no need configure vt"); - goto l_out; + return; } =20 sxe_hw_vt_ctrl_cfg(hw, pf_pool_idx); @@ -229,8 +225,6 @@ void sxe_vt_configure(struct rte_eth_dev *eth_dev) =20 sxe_rx_fc_threshold_set(hw); =20 -l_out: - return; } =20 void sxe_vt_uninit(struct rte_eth_dev *eth_dev) @@ -250,20 +244,17 @@ void sxe_vt_uninit(struct rte_eth_dev *eth_dev) vf_num =3D sxe_vf_num_get(eth_dev); if ((vf_num =3D=3D 0) || (*vf_info) =3D=3D NULL) { LOG_INFO_BDF("vf_num:%u vf_info:%p, no need free vf_info.", - vf_num, *vf_info); - goto l_out; + vf_num, *vf_info); + return; } =20 ret =3D rte_eth_switch_domain_free((*vf_info)->domain_id); - if (ret) { + if (ret) LOG_ERROR_BDF("failed to free switch domain: %d", ret); - } =20 rte_free(*vf_info); *vf_info =3D NULL; =20 -l_out: - return; } =20 s32 sxe_vf_rss_configure(struct rte_eth_dev *dev) @@ -284,17 +275,17 @@ s32 sxe_vf_rss_configure(struct rte_eth_dev *dev) is_4q_per_pool =3D true; break; =20 - default:=20 + default: ret =3D -EINVAL; LOG_ERROR_BDF("invalid pool number:%u in iov mode with rss.(err:%d)", - RTE_ETH_DEV_SRIOV(dev).active, ret); + RTE_ETH_DEV_SRIOV(dev).active, ret); goto l_out; } =20 sxe_hw_rx_multi_ring_configure(hw, 0, is_4q_per_pool, true); =20 LOG_INFO_BDF("pool num:%u is_4q_per_pool:%u configure done.", - RTE_ETH_DEV_SRIOV(dev).active, is_4q_per_pool); + RTE_ETH_DEV_SRIOV(dev).active, is_4q_per_pool); =20 l_out: return ret; @@ -323,7 +314,7 @@ s32 sxe_vf_default_mode_configure(struct rte_eth_dev *d= ev) default: ret =3D -SXE_ERR_CONFIG; LOG_ERROR_BDF("invalid pool number:%u (err:%d)", - RTE_ETH_DEV_SRIOV(dev).active, ret); + RTE_ETH_DEV_SRIOV(dev).active, ret); goto l_out; } =20 @@ -349,7 +340,7 @@ static void sxe_filter_mode_configure(struct rte_eth_de= v *dev) filter_ctrl |=3D (SXE_FCTRL_UPE | SXE_FCTRL_MPE); vm_l2_ctrl |=3D (SXE_VMOLR_ROPE | SXE_VMOLR_MPE); } else { - if (dev->data->all_multicast) {=20 + if (dev->data->all_multicast) { filter_ctrl |=3D SXE_FCTRL_MPE; vm_l2_ctrl |=3D SXE_VMOLR_MPE; } else { @@ -386,7 +377,6 @@ static inline void sxe_vf_flr_handle(struct rte_eth_dev= *dev, u16 vf) =20 sxe_filter_mode_configure(dev); =20 - return; } =20 static s32 sxe_vf_dev_mac_addr_set_handler(struct rte_eth_dev *dev, u32 *m= sgbuf, u32 vf) @@ -403,15 +393,15 @@ static s32 sxe_vf_dev_mac_addr_set_handler(struct rte= _eth_dev *dev, u32 *msgbuf, ret =3D sxe_hw_uc_addr_add(&adapter->hw, rar_idx, mac_msg.uc_addr, vf); if (ret) { LOG_ERROR_BDF("vf:%u mac addr:"MAC_FMT" set fail.(err:%d)", - vf, MAC_ADDR(mac_msg.uc_addr), ret); + vf, MAC_ADDR(mac_msg.uc_addr), ret); } } =20 return ret; } =20 -STATIC s32 sxe_mbx_api_set_handler(struct rte_eth_dev *dev, - u32 *msg, u32 vf_idx) +static s32 sxe_mbx_api_set_handler(struct rte_eth_dev *dev, + u32 *msg, u32 vf_idx) { struct sxe_adapter *adapter =3D dev->data->dev_private; struct sxe_mbx_api_msg *api_msg =3D (struct sxe_mbx_api_msg *)msg; @@ -433,8 +423,7 @@ STATIC s32 sxe_mbx_api_set_handler(struct rte_eth_dev *= dev, } =20 LOG_INFO_BDF("mailbox api version:0x%x.(err:%d)", - vf_info->mbx_version, - ret); + vf_info->mbx_version, ret); =20 return ret; } @@ -462,8 +451,8 @@ static s32 sxe_pf_ring_info_get(struct rte_eth_dev *dev= , u32 *msgbuf, u32 vf) default: ret =3D -SXE_ERR_CONFIG; LOG_ERROR_BDF("mailbod version:0x%x not support get ring" - " info.(err:%d)", - vf_info->mbx_version, ret); + " info.(err:%d)", + vf_info->mbx_version, ret); goto l_out; } =20 @@ -493,7 +482,7 @@ static s32 sxe_pf_ring_info_get(struct rte_eth_dev *dev= , u32 *msgbuf, u32 vf) default: ret =3D -SXE_ERR_CONFIG; LOG_ERROR_BDF("vf:%u sriov enable, tx queue mode:0x%x " - "invalid pool num:%u.(err:%d)", + "invalid pool num:%u.(err:%d)", vf, dev->data->dev_conf.txmode.mq_mode, vmdq_dcb_tx_conf->nb_queue_pools, @@ -526,8 +515,8 @@ static s32 sxe_pf_ring_info_get(struct rte_eth_dev *dev= , u32 *msgbuf, u32 vf) ring_msg->tc_num =3D num_tcs; =20 LOG_INFO_BDF("max_rx_num:%u max_tx_num:%u default queue:%u tc_num:%u.", - ring_msg->max_rx_num, ring_msg->max_tx_num, - ring_msg->default_tc, ring_msg->tc_num); + ring_msg->max_rx_num, ring_msg->max_tx_num, + ring_msg->default_tc, ring_msg->tc_num); =20 l_out: return ret; @@ -566,11 +555,10 @@ static s32 sxe_vf_vlan_id_set_handler(struct rte_eth_= dev *dev, =20 ret =3D sxe_hw_vlan_filter_configure(hw, vlan_id, vf, vlan_msg->add, fals= e); if (ret =3D=3D 0) { - if (vlan_msg->add) { - vf_info[vf].vlan_cnt++; - } else if (vf_info[vf].vlan_cnt) { + if (vlan_msg->add) + vf_info[vf].vlan_cnt++; + else if (vf_info[vf].vlan_cnt) vf_info[vf].vlan_cnt--; - } } =20 LOG_INFO_BDF("vf[%u] %s vid[%u] done vlan_cnt:%u ret =3D %d", @@ -605,14 +593,14 @@ static s32 sxe_vf_max_frame_set_handler(struct rte_et= h_dev *dev, // fall through default: if ((vf_max_frame > SXE_ETH_MAX_LEN) || - (frame_size > SXE_ETH_MAX_LEN)) { - ret =3D -SXE_ERR_PARAM; + (frame_size > SXE_ETH_MAX_LEN)) { + ret =3D -SXE_ERR_PARAM; LOG_ERROR_BDF("mbx version:0x%x pf max pkt len:0x%x vf:%u" - " max_frames:0x%x max_len:0x%x.(err:%d)", - vf_info->mbx_version, - frame_size, - vf, vf_max_frame, - SXE_ETH_MAX_LEN, ret); + " max_frames:0x%x max_len:0x%x.(err:%d)", + vf_info->mbx_version, + frame_size, + vf, vf_max_frame, + SXE_ETH_MAX_LEN, ret); goto l_out; } break; @@ -620,12 +608,12 @@ static s32 sxe_vf_max_frame_set_handler(struct rte_et= h_dev *dev, =20 if ((vf_max_frame < RTE_ETHER_MIN_LEN) || (vf_max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)) { - ret =3D -SXE_ERR_PARAM; + ret =3D -SXE_ERR_PARAM; LOG_ERROR_BDF("mbx version:0x%x vf:%u invalid max_frame:%u (err:%d)", - vf_info->mbx_version, - vf, - vf_max_frame, - ret); + vf_info->mbx_version, + vf, + vf_max_frame, + ret); goto l_out; } =20 @@ -633,10 +621,10 @@ static s32 sxe_vf_max_frame_set_handler(struct rte_et= h_dev *dev, if (vf_max_frame > cur_max_frs) { ret =3D -SXE_ERR_PARAM; LOG_ERROR_BDF("mbx version:0x%x vf:%u invalid max_frame:%u >=3D cur_max_= frs:%u", - vf_info->mbx_version, - vf, - vf_max_frame, - cur_max_frs); + vf_info->mbx_version, + vf, + vf_max_frame, + cur_max_frs); goto l_out; } =20 @@ -654,7 +642,6 @@ static void sxe_vf_mc_promisc_disable(struct rte_eth_de= v *dev, u32 vf) =20 sxe_hw_pool_rx_mode_set(hw, vm_l2_ctrl, vf); =20 - return; } =20 static s32 sxe_vf_mc_addr_sync(struct rte_eth_dev *dev, @@ -676,7 +663,7 @@ static s32 sxe_vf_mc_addr_sync(struct rte_eth_dev *dev, for (i =3D 0; i < mc_cnt; i++) { vf_info->mc_hash[i] =3D mc_msg->mc_addr_extract[i]; LOG_INFO_BDF("vf_idx:%u mc_cnt:%u mc_hash[%d]:0x%x\n", - vf, mc_cnt, i, vf_info->mc_hash[i]); + vf, mc_cnt, i, vf_info->mc_hash[i]); } =20 if (mc_cnt =3D=3D 0) { @@ -690,7 +677,7 @@ static s32 sxe_vf_mc_addr_sync(struct rte_eth_dev *dev, mta_shift =3D vf_info->mc_hash[i] & SXE_MC_ADDR_BIT_MASK; sxe_hw_mta_hash_table_update(hw, mta_idx, mta_shift); =20 - LOG_INFO_BDF("vf_idx:%u mc_cnt:%u mc_hash[%d]:0x%x" + LOG_INFO_BDF("vf_idx:%u mc_cnt:%u mc_hash[%d]:0x%x " "reg_idx=3D%u, bit_idx=3D%u.\n", vf, mc_cnt, i, vf_info->mc_hash[i], mta_idx, mta_shift); @@ -720,8 +707,8 @@ static s32 sxe_vf_cast_mode_handler(struct rte_eth_dev = *dev, if (cast_msg->cast_mode =3D=3D SXE_CAST_MODE_PROMISC) { ret =3D -EOPNOTSUPP; LOG_ERROR_BDF("mbx api:12 vf:%u cast_mode:0x%x " - "unsupport.(err:%d)", - vf, cast_msg->cast_mode, ret); + "unsupport.(err:%d)", + vf, cast_msg->cast_mode, ret); goto l_out; } break; @@ -730,13 +717,13 @@ static s32 sxe_vf_cast_mode_handler(struct rte_eth_de= v *dev, default: ret =3D -SXE_ERR_PARAM; LOG_ERROR_BDF("vf:%u invalid mbx api version:0x%x.\n", - vf, vf_info->mbx_version); + vf, vf_info->mbx_version); goto l_out; } =20 if (vf_info->cast_mode =3D=3D cast_msg->cast_mode) { LOG_INFO_BDF("vf:%d currut mode equal set mode:0x%x, skip set.", - vf, cast_msg->cast_mode); + vf, cast_msg->cast_mode); goto l_out; } =20 @@ -760,13 +747,13 @@ static s32 sxe_vf_cast_mode_handler(struct rte_eth_de= v *dev, case SXE_CAST_MODE_PROMISC: ret =3D -EOPNOTSUPP; LOG_ERROR_BDF("vf:%d promisc mode not support.(ret:%d)\n", - vf, ret); + vf, ret); goto l_out; =20 default: ret =3D -SXE_ERR_PARAM; LOG_ERROR_BDF("vf:%u invalid cast mode:0x%x.\n", - vf, cast_msg->cast_mode); + vf, cast_msg->cast_mode); goto l_out; } =20 @@ -776,7 +763,7 @@ static s32 sxe_vf_cast_mode_handler(struct rte_eth_dev = *dev, sxe_hw_pool_rx_mode_set(hw, vm_l2_filter, vf); =20 LOG_INFO_BDF("vf:%d filter reg:0x%x mode:%d.\n", - vf, vm_l2_filter, cast_msg->cast_mode); + vf, vm_l2_filter, cast_msg->cast_mode); =20 vf_info->cast_mode =3D cast_msg->cast_mode; =20 @@ -799,13 +786,13 @@ static s32 sxe_vf_uc_addr_sync_handler(struct rte_eth= _dev *dev, (struct rte_ether_addr *)uc_msg->addr)) { ret =3D -SXE_ERR_PARAM; LOG_ERROR_BDF("vf:%u mac addr:"MAC_FMT" invalid.(err:%d).", - vf, MAC_ADDR(uc_msg->addr), ret); + vf, MAC_ADDR(uc_msg->addr), ret); goto l_out; } =20 vf_info->uc_mac_cnt++; rar_idx =3D sxe_sw_uc_entry_vf_add(adapter, vf, (u8 *)uc_msg->addr, true= ); - sxe_hw_uc_addr_add=0D(hw, rar_idx, (u8 *)uc_msg->addr, vf); + sxe_hw_uc_addr_add(hw, rar_idx, (u8 *)uc_msg->addr, vf); } else { if (vf_info->uc_mac_cnt) { sxe_sw_uc_entry_vf_del(adapter, vf, true); @@ -817,7 +804,7 @@ static s32 sxe_vf_uc_addr_sync_handler(struct rte_eth_d= ev *dev, return ret; } =20 -STATIC struct sxe_msg_table msg_table[] =3D { +static struct sxe_msg_table msg_table[] =3D { [SXE_VFREQ_MAC_ADDR_SET] =3D {SXE_VFREQ_MAC_ADDR_SET, sxe_vf_dev_mac_addr= _set_handler}, [SXE_VFREQ_MC_ADDR_SYNC] =3D {SXE_VFREQ_MC_ADDR_SYNC, sxe_vf_mc_addr_sync= }, [SXE_VFREQ_VLAN_SET] =3D {SXE_VFREQ_VLAN_SET, sxe_vf_vlan_id_set_handler}, @@ -840,20 +827,19 @@ static void sxe_vf_pool_enable(struct rte_eth_dev *de= v, u8 vf_idx) =20 enable_pool =3D sxe_hw_tx_pool_bitmap_get(hw, reg_idx); enable_pool |=3D BIT(bit_idx); - sxe_hw_tx_pool_bitmap_set(hw, reg_idx,enable_pool); + sxe_hw_tx_pool_bitmap_set(hw, reg_idx, enable_pool); =20 sxe_hw_vf_queue_drop_enable(hw, vf_idx, RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); =20 enable_pool =3D sxe_hw_rx_pool_bitmap_get(hw, reg_idx); enable_pool |=3D BIT(bit_idx); - sxe_hw_rx_pool_bitmap_set(hw, reg_idx,enable_pool); + sxe_hw_rx_pool_bitmap_set(hw, reg_idx, enable_pool); =20 vf_info->is_ready =3D true; =20 sxe_hw_spoof_count_enable(hw, reg_idx, bit_idx); =20 - return; } =20 static void sxe_vf_reset_msg_handle(struct rte_eth_dev *dev, u8 vf_idx) @@ -885,14 +871,13 @@ static void sxe_vf_reset_msg_handle(struct rte_eth_de= v *dev, u8 vf_idx) adapter->vt_ctxt.vf_info->is_ready =3D true; =20 LOG_INFO_BDF("vf_idx:%d reset msg:0x%x handle done.send mac addr:"MAC_FMT - " mc type:%d to vf.", - vf_idx, reply.msg_type, - MAC_ADDR(mac_addr), SXE_MC_FILTER_TYPE0); + " mc type:%d to vf.", + vf_idx, reply.msg_type, + MAC_ADDR(mac_addr), SXE_MC_FILTER_TYPE0); =20 - return; } =20 -STATIC s32 sxe_req_msg_handle(struct rte_eth_dev *dev, u32 *msg, +static s32 sxe_req_msg_handle(struct rte_eth_dev *dev, u32 *msg, u8 vf_idx) { struct sxe_adapter *adapter =3D dev->data->dev_private; @@ -919,12 +904,12 @@ STATIC s32 sxe_req_msg_handle(struct rte_eth_dev *dev= , u32 *msg, sxe_vf_reset_msg_handle(dev, vf_idx); =20 sxe_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, - &user_param); + &user_param); goto l_out; } =20 sxe_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, - &user_param); + &user_param); =20 LOG_INFO_BDF("vf_idx:%u cmd_id:0x%x user configure:0x%x.", vf_idx, cmd_id, user_param.ret); @@ -940,8 +925,8 @@ STATIC s32 sxe_req_msg_handle(struct rte_eth_dev *dev, = u32 *msg, =20 if (msg_table[cmd_id].msg_func) { if ((user_param.ret =3D=3D RTE_PMD_SXE_MB_EVENT_PROCEED) || - (cmd_id =3D=3D SXE_VFREQ_API_NEGOTIATE) || - (cmd_id =3D=3D SXE_VFREQ_RING_INFO_GET)) { + (cmd_id =3D=3D SXE_VFREQ_API_NEGOTIATE) || + (cmd_id =3D=3D SXE_VFREQ_RING_INFO_GET)) { ret =3D msg_table[cmd_id].msg_func(dev, msg, vf_idx); } LOG_INFO_BDF("msg:0x%x cmd_id:0x%x handle done.ret:%d\n", @@ -955,7 +940,7 @@ STATIC s32 sxe_req_msg_handle(struct rte_eth_dev *dev, = u32 *msg, } else { msg[0] |=3D SXE_MSGTYPE_NACK; LOG_ERROR_BDF("vf_idx:%u msg_type:0x%x cmdId:0x%x invalid.(err:%d)\n", - vf_idx, msg[0], cmd_id, ret); + vf_idx, msg[0], cmd_id, ret); } =20 ret =3D sxe_hw_send_msg_to_vf(hw, msg, SXE_MBX_MSG_NUM, vf_idx); @@ -1012,7 +997,6 @@ static void sxe_vf_ack_msg_handle(struct rte_eth_dev *= eth_dev, u8 vf_idx) SXE_MSG_NUM(sizeof(msg)), vf_idx); } =20 - return; } =20 void sxe_mbx_irq_handler(struct rte_eth_dev *eth_dev) @@ -1030,16 +1014,14 @@ void sxe_mbx_irq_handler(struct rte_eth_dev *eth_de= v) sxe_vf_flr_handle(eth_dev, vf_idx); } =20 - if (sxe_hw_vf_req_check(hw, vf_idx)) { + if (sxe_hw_vf_req_check(hw, vf_idx)) sxe_vf_req_msg_handle(eth_dev, vf_idx); - } =20 - if (sxe_hw_vf_ack_check(hw, vf_idx)) { + if (sxe_hw_vf_ack_check(hw, vf_idx)) sxe_vf_ack_msg_handle(eth_dev, vf_idx); - } + } =20 - return; } =20 #ifdef ETH_DEV_MIRROR_RULE @@ -1051,21 +1033,21 @@ static s32 sxe_mirror_conf_check(struct sxe_hw *hw,= u8 rule_id, if (sxe_hw_vt_status(hw) =3D=3D 0) { ret =3D -ENOTSUP; PMD_LOG_ERR(DRV, "virtual disabled, mirror rule not support.(err:%d)", - ret); + ret); goto l_out; } =20 if (rule_id >=3D SXE_MIRROR_RULES_MAX) { ret =3D -EINVAL; PMD_LOG_ERR(DRV, "invalid rule_id:%u rule id max:%u.(err:%d)", - rule_id, SXE_MIRROR_RULES_MAX, ret); + rule_id, SXE_MIRROR_RULES_MAX, ret); goto l_out; } =20 if (SXE_MIRROR_TYPE_INVALID(rule_type)) { ret =3D -EINVAL; PMD_LOG_ERR(DRV, "unsupported mirror type 0x%x.(err:%d)", - rule_type, ret); + rule_type, ret); } =20 l_out: @@ -1073,8 +1055,8 @@ static s32 sxe_mirror_conf_check(struct sxe_hw *hw, u= 8 rule_id, } =20 static s32 sxe_vlan_mirror_configure(struct rte_eth_dev *dev, - struct rte_eth_mirror_conf *mirror_conf, - u8 rule_id, u8 on) + struct rte_eth_mirror_conf *mirror_conf, + u8 rule_id, u8 on) { struct sxe_adapter *adapter =3D dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; @@ -1096,29 +1078,29 @@ static s32 sxe_vlan_mirror_configure(struct rte_eth= _dev *dev, if (ret < 0) { ret =3D -EINVAL; LOG_ERROR_BDF("vlan_id[%u]:0x%x no matched vlvf." - "(err:%d)", - i, - mirror_conf->vlan.vlan_id[i], - ret); + "(err:%d)", + i, + mirror_conf->vlan.vlan_id[i], + ret); goto l_out; } =20 reg_idx =3D ret; vlvf =3D sxe_hw_vlan_pool_filter_read(hw, reg_idx); if ((vlvf & SXE_VLVF_VIEN) && - ((vlvf & SXE_VLVF_VLANID_MASK) =3D=3D - mirror_conf->vlan.vlan_id[i])) { + ((vlvf & SXE_VLVF_VLANID_MASK) =3D=3D + mirror_conf->vlan.vlan_id[i])) { vlan_mask |=3D (1ULL << reg_idx); } else{ ret =3D -EINVAL; LOG_ERROR_BDF("i:%u vlan_id:0x%x " - "vlvf[%u]:0x%x not meet request." - "(err:%d)", - i, - mirror_conf->vlan.vlan_id[i], - reg_idx, - vlvf, - ret); + "vlvf[%u]:0x%x not meet request." + "(err:%d)", + i, + mirror_conf->vlan.vlan_id[i], + reg_idx, + vlvf, + ret); goto l_out; } } @@ -1136,10 +1118,10 @@ static s32 sxe_vlan_mirror_configure(struct rte_eth= _dev *dev, mirror_info->mr_conf[rule_id].vlan.vlan_id[i] =3D mirror_conf->vlan.vlan_id[i]; LOG_INFO_BDF("rule_id:%u vlan id:0x%x add mirror" - " to dst_pool:%u", - rule_id, - mirror_conf->vlan.vlan_id[i], - mirror_conf->dst_pool); + " to dst_pool:%u", + rule_id, + mirror_conf->vlan.vlan_id[i], + mirror_conf->dst_pool); } } } else { @@ -1150,10 +1132,10 @@ static s32 sxe_vlan_mirror_configure(struct rte_eth= _dev *dev, for (i =3D 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { mirror_info->mr_conf[rule_id].vlan.vlan_id[i] =3D 0; LOG_INFO_BDF("rule_id:%u vlan id:0x%x del mirror" - " from dst_pool:%u", - rule_id, - mirror_conf->vlan.vlan_id[i], - mirror_conf->dst_pool); + " from dst_pool:%u", + rule_id, + mirror_conf->vlan.vlan_id[i], + mirror_conf->dst_pool); } } =20 @@ -1164,8 +1146,8 @@ static s32 sxe_vlan_mirror_configure(struct rte_eth_d= ev *dev, } =20 static void sxe_virtual_pool_mirror_configure(struct rte_eth_dev *dev, - struct rte_eth_mirror_conf *mirror_conf, - u8 rule_id, u8 on) + struct rte_eth_mirror_conf *mirror_conf, + u8 rule_id, u8 on) { struct sxe_adapter *adapter =3D dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; @@ -1185,12 +1167,11 @@ static void sxe_virtual_pool_mirror_configure(struc= t rte_eth_dev *dev, =20 sxe_hw_mirror_virtual_pool_set(hw, rule_id, lsb, msb); =20 - return; } =20 s32 sxe_mirror_rule_set(struct rte_eth_dev *dev, - struct rte_eth_mirror_conf *mirror_conf, - u8 rule_id, u8 on) + struct rte_eth_mirror_conf *mirror_conf, + u8 rule_id, u8 on) { struct sxe_adapter *adapter =3D dev->data->dev_private; struct sxe_hw *hw =3D &adapter->hw; @@ -1201,7 +1182,7 @@ s32 sxe_mirror_rule_set(struct rte_eth_dev *dev, ret =3D sxe_mirror_conf_check(hw, rule_id, mirror_conf->rule_type); if (ret) { LOG_ERROR_BDF("rule_id:%u mirror config param invalid.(err:%d)", - rule_id, ret); + rule_id, ret); goto l_out; } =20 @@ -1219,13 +1200,11 @@ s32 sxe_mirror_rule_set(struct rte_eth_dev *dev, sxe_virtual_pool_mirror_configure(dev, mirror_conf, rule_id, on); } =20 - if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) { + if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) mirror_type |=3D SXE_MRCTL_UPME; - } =20 - if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) { + if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) mirror_type |=3D SXE_MRCTL_DPME; - } =20 sxe_hw_mirror_ctl_set(hw, rule_id, mirror_type, mirror_conf->dst_pool, on= ); =20 @@ -1233,14 +1212,14 @@ s32 sxe_mirror_rule_set(struct rte_eth_dev *dev, mirror_info->mr_conf[rule_id].dst_pool =3D mirror_conf->dst_pool; =20 LOG_INFO_BDF("rule_id:%u mirrror type:0x%x %s success. " - "vlan id mask:0x%"SXE_PRIX64" virtaul pool mask:0x%"SXE_PRIX64 - " dst_pool:%u.", - rule_id, - mirror_conf->rule_type, - on ? "add" : "delete", - mirror_conf->vlan.vlan_mask, - mirror_conf->pool_mask, - mirror_conf->dst_pool); + "vlan id mask:0x%"SXE_PRIX64" virtual pool mask:0x%"SXE_PRIX64 + " dst_pool:%u.", + rule_id, + mirror_conf->rule_type, + on ? "add" : "delete", + mirror_conf->vlan.vlan_mask, + mirror_conf->pool_mask, + mirror_conf->dst_pool); =20 l_out: return ret; @@ -1256,12 +1235,12 @@ s32 sxe_mirror_rule_reset(struct rte_eth_dev *dev, = u8 rule_id) ret =3D sxe_mirror_conf_check(hw, rule_id, SXE_ETH_MIRROR_TYPE_MASK); if (ret) { LOG_ERROR_BDF("rule_id:%u mirror config param invalid.(err:%d)", - rule_id, ret); + rule_id, ret); goto l_out; } =20 memset(&mirror_info->mr_conf[rule_id], 0, - sizeof(struct rte_eth_mirror_conf)); + sizeof(struct rte_eth_mirror_conf)); =20 sxe_hw_mirror_rule_clear(hw, rule_id); =20 diff --git a/drivers/net/sxe/pf/sxe_vf.h b/drivers/net/sxe/pf/sxe_vf.h index 8690b9e7fd..727b26dab9 100644 --- a/drivers/net/sxe/pf/sxe_vf.h +++ b/drivers/net/sxe/pf/sxe_vf.h @@ -17,31 +17,31 @@ =20 #define SXE_MIRROR_RULES_MAX 4 =20 -#define SXE_MSG_NUM(size) DIV_ROUND_UP(size, 4) +#define SXE_MSG_NUM(size) DIV_ROUND_UP(size, 4) =20 -#define SXE_MSGTYPE_ACK 0x80000000 +#define SXE_MSGTYPE_ACK 0x80000000 #define SXE_MSGTYPE_NACK 0x40000000 =20 -#define SXE_VFREQ_RESET 0x01=20 -#define SXE_VFREQ_MAC_ADDR_SET 0x02=20 -#define SXE_VFREQ_MC_ADDR_SYNC 0x03=20 -#define SXE_VFREQ_VLAN_SET 0x04=20 -#define SXE_VFREQ_LPE_SET 0x05=20=20 +#define SXE_VFREQ_RESET 0x01 +#define SXE_VFREQ_MAC_ADDR_SET 0x02 +#define SXE_VFREQ_MC_ADDR_SYNC 0x03 +#define SXE_VFREQ_VLAN_SET 0x04 +#define SXE_VFREQ_LPE_SET 0x05 =20 -#define SXE_VFREQ_UC_ADDR_SYNC 0x06=20=20 +#define SXE_VFREQ_UC_ADDR_SYNC 0x06 =20 -#define SXE_VFREQ_API_NEGOTIATE 0x08=20=20 +#define SXE_VFREQ_API_NEGOTIATE 0x08 =20 -#define SXE_VFREQ_RING_INFO_GET 0x09=20=20 -#define SXE_VFREQ_REDIR_TBL_GET 0x0a -#define SXE_VFREQ_RSS_KEY_GET 0x0b -#define SXE_VFREQ_CAST_MODE_SET 0x0c=20=20 -#define SXE_VFREQ_LINK_ENABLE_GET 0X0d=20=20 -#define SXE_VFREQ_IPSEC_ADD 0x0e -#define SXE_VFREQ_IPSEC_DEL 0x0f -#define SXE_VFREQ_RSS_CONF_GET 0x10 +#define SXE_VFREQ_RING_INFO_GET 0x09 +#define SXE_VFREQ_REDIR_TBL_GET 0x0a +#define SXE_VFREQ_RSS_KEY_GET 0x0b +#define SXE_VFREQ_CAST_MODE_SET 0x0c +#define SXE_VFREQ_LINK_ENABLE_GET 0X0d +#define SXE_VFREQ_IPSEC_ADD 0x0e +#define SXE_VFREQ_IPSEC_DEL 0x0f +#define SXE_VFREQ_RSS_CONF_GET 0x10 =20 -#define SXE_VFREQ_MASK 0xFF +#define SXE_VFREQ_MASK 0xFF =20 #define SXE_MIRROR_TYPE_INVALID(mirror_type) \ ((mirror_type) & ~(u8)(ETH_MIRROR_VIRTUAL_POOL_UP | \ @@ -62,35 +62,35 @@ enum sxe_mbx_api_version { SXE_MBX_API_10 =3D 0, SXE_MBX_API_11, SXE_MBX_API_12, - SXE_MBX_API_13,=20 - SXE_MBX_API_14,=20 + SXE_MBX_API_13, + SXE_MBX_API_14, =20 - SXE_MBX_API_NR,=20 + SXE_MBX_API_NR, }; =20 enum sxe_cast_mode { - SXE_CAST_MODE_NONE =3D 0,=20 - SXE_CAST_MODE_MULTI,=20=20=20=20 - SXE_CAST_MODE_ALLMULTI,=20 - SXE_CAST_MODE_PROMISC,=20=20 + SXE_CAST_MODE_NONE =3D 0, + SXE_CAST_MODE_MULTI, + SXE_CAST_MODE_ALLMULTI, + SXE_CAST_MODE_PROMISC, }; =20 struct sxe_vf_info { - u8 mac_addr[RTE_ETHER_ADDR_LEN];=20 - u16 mc_hash[SXE_VF_MC_ENTRY_NUM_MAX];=20 - u8 mc_hash_used;=20 - u8 cast_mode;=20 - u8 trusted :1;=20=20 - u8 is_ready :1;=20 - u8 spoof_chk_enabled :1;=20 - u8 rss_query_enabled :1;=20 - u8 mac_from_pf :1;=20 - u8 reserved :3;=20=20 + u8 mac_addr[RTE_ETHER_ADDR_LEN]; + u16 mc_hash[SXE_VF_MC_ENTRY_NUM_MAX]; + u8 mc_hash_used; + u8 cast_mode; + u8 trusted :1; + u8 is_ready :1; + u8 spoof_chk_enabled :1; + u8 rss_query_enabled :1; + u8 mac_from_pf :1; + u8 reserved :3; u16 domain_id; - u16 tx_rate;=20=20=20=20 - u32 mbx_version;=20 - u32 vlan_cnt;=20=20=20=20=20 - u32 uc_mac_cnt;=20=20 + u16 tx_rate; + u32 mbx_version; + u32 vlan_cnt; + u32 uc_mac_cnt; }; =20 #ifdef ETH_DEV_MIRROR_RULE @@ -102,10 +102,10 @@ struct sxe_mirror_info { =20 struct sxe_virtual_context { u8 pflink_fullchk; - u32 mbx_version;=20 - struct sxe_vf_info *vf_info;=20=20=20=20 + u32 mbx_version; + struct sxe_vf_info *vf_info; #ifdef ETH_DEV_MIRROR_RULE - struct sxe_mirror_info mr_info;=20 + struct sxe_mirror_info mr_info; #endif }; =20 @@ -115,17 +115,17 @@ struct sxe_msg_table { }; =20 enum RTE_PMD_SXE_MB_event_rsp { - RTE_PMD_SXE_MB_EVENT_NOOP_ACK,=20=20 - RTE_PMD_SXE_MB_EVENT_NOOP_NACK,=20 - RTE_PMD_SXE_MB_EVENT_PROCEED,=20=20=20 - RTE_PMD_SXE_MB_EVENT_MAX=20=20=20=20=20=20=20=20 + RTE_PMD_SXE_MB_EVENT_NOOP_ACK, + RTE_PMD_SXE_MB_EVENT_NOOP_NACK, + RTE_PMD_SXE_MB_EVENT_PROCEED, + RTE_PMD_SXE_MB_EVENT_MAX }; =20 struct rte_pmd_sxe_mb_event_param { - u16 vf_idx;=20=20=20=20=20 - u16 msg_type;=20=20=20 - u16 ret;=20=20=20=20=20=20=20=20 - void *msg;=20=20=20=20=20=20 + u16 vf_idx; + u16 msg_type; + u16 ret; + void *msg; }; =20 struct sxe_mbx_api_msg { @@ -158,10 +158,10 @@ struct sxe_rst_msg { =20 struct sxe_ring_info_msg { u32 msg_type; - u8 max_rx_num;=20 - u8 max_tx_num;=20 - u8 tc_num;=20=20=20=20=20 - u8 default_tc;=20 + u8 max_rx_num; + u8 max_tx_num; + u8 tc_num; + u8 default_tc; }; =20 struct sxe_rss_hash_msg { @@ -178,7 +178,7 @@ struct sxe_vlan_msg { =20 struct sxe_mc_sync_msg { u16 msg_type; - u16 mc_cnt;=20=20 + u16 mc_cnt; u16 mc_addr_extract[SXE_VF_MC_ENTRY_NUM_MAX]; }; =20 @@ -212,8 +212,8 @@ void sxe_mbx_irq_handler(struct rte_eth_dev *eth_dev); =20 #ifdef ETH_DEV_MIRROR_RULE s32 sxe_mirror_rule_set(struct rte_eth_dev *dev, - struct rte_eth_mirror_conf *mirror_conf, - u8 rule_id, u8 on); + struct rte_eth_mirror_conf *mirror_conf, + u8 rule_id, u8 on); =20 s32 sxe_mirror_rule_reset(struct rte_eth_dev *dev, u8 rule_id); =20 diff --git a/drivers/net/sxe/rte_pmd_sxe_version.map b/drivers/net/sxe/rte_= pmd_sxe_version.map index e85eb752b4..1ee53b5969 100644 --- a/drivers/net/sxe/rte_pmd_sxe_version.map +++ b/drivers/net/sxe/rte_pmd_sxe_version.map @@ -1,5 +1,5 @@ DPDK_20.0 { - global:=20 + global: rte_pmd_sxe_tx_loopback_set; rte_pmd_sxe_tc_bw_set; local: *; diff --git a/drivers/net/sxe/version.map b/drivers/net/sxe/version.map index 2064d17939..fe54b7732a 100644 --- a/drivers/net/sxe/version.map +++ b/drivers/net/sxe/version.map @@ -1,19 +1,19 @@ DPDK_21 { - global:=20 + global: rte_pmd_sxe_tx_loopback_set; rte_pmd_sxe_tc_bw_set; local: *; }; =20 DPDK_22 { - global:=20 + global: rte_pmd_sxe_tx_loopback_set; rte_pmd_sxe_tc_bw_set; local: *; }; =20 DPDK_23 { - global:=20 + global: rte_pmd_sxe_tx_loopback_set; rte_pmd_sxe_tc_bw_set; local: *; diff --git a/drivers/net/sxe/vf/sxevf.h b/drivers/net/sxe/vf/sxevf.h index 52d294d869..0db3d73d2c 100644 --- a/drivers/net/sxe/vf/sxevf.h +++ b/drivers/net/sxe/vf/sxevf.h @@ -11,12 +11,12 @@ #include "sxevf_filter.h" #include "sxevf_stats.h" =20 -#define SXEVF_DEVARG_LINK_CHECK "link_check" +#define SXEVF_DEVARG_LINK_CHECK "link_check" =20 struct sxevf_adapter { - s8 name[PCI_PRI_STR_SIZE+1];=20 - u8 max_rx_queue;=20 - u8 max_tx_queue;=20 + s8 name[PCI_PRI_STR_SIZE+1]; + u8 max_rx_queue; + u8 max_tx_queue; =20 struct sxevf_hw hw; struct sxevf_irq_context irq_ctxt; diff --git a/drivers/net/sxe/vf/sxevf_ethdev.c b/drivers/net/sxe/vf/sxevf_e= thdev.c index d656dc83fc..dd39798520 100644 --- a/drivers/net/sxe/vf/sxevf_ethdev.c +++ b/drivers/net/sxe/vf/sxevf_ethdev.c @@ -44,7 +44,7 @@ #include "sxevf_offload.h" #include "sxe_compat_version.h" =20 -#define SXEVF_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN)=20= =20 +#define SXEVF_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN) #define SXEVF_HKEY_MAX_INDEX (10) #define SXEVF_RSS_OFFLOAD_ALL ( \ RTE_ETH_RSS_IPV4 | \ @@ -58,27 +58,27 @@ RTE_ETH_RSS_IPV6_UDP_EX) =20 #define SXEVF_DEFAULT_RX_FREE_THRESH 32 -#define SXEVF_DEFAULT_RX_PTHRESH 8 -#define SXEVF_DEFAULT_RX_HTHRESH 8 -#define SXEVF_DEFAULT_RX_WTHRESH 0 +#define SXEVF_DEFAULT_RX_PTHRESH 8 +#define SXEVF_DEFAULT_RX_HTHRESH 8 +#define SXEVF_DEFAULT_RX_WTHRESH 0 =20 #define SXEVF_DEFAULT_TX_FREE_THRESH 32 -#define SXEVF_DEFAULT_TX_PTHRESH 32 -#define SXEVF_DEFAULT_TX_HTHRESH 0 -#define SXEVF_DEFAULT_TX_WTHRESH 0 +#define SXEVF_DEFAULT_TX_PTHRESH 32 +#define SXEVF_DEFAULT_TX_HTHRESH 0 +#define SXEVF_DEFAULT_TX_WTHRESH 0 #define SXEVF_DEFAULT_TX_RSBIT_THRESH 32 =20 -#define SXEVF_MIN_RING_DESC 32 -#define SXEVF_MAX_RING_DESC 4096 +#define SXEVF_MIN_RING_DESC 32 +#define SXEVF_MAX_RING_DESC 4096 =20 -#define SXEVF_ALIGN 128 -#define SXEVF_RXD_ALIGN (SXEVF_ALIGN / sizeof(sxevf_rx_data_desc_u)) -#define SXEVF_TXD_ALIGN (SXEVF_ALIGN / sizeof(sxevf_tx_data_desc_u)) +#define SXEVF_ALIGN 128 +#define SXEVF_RXD_ALIGN (SXEVF_ALIGN / sizeof(sxevf_rx_data_desc_u)) +#define SXEVF_TXD_ALIGN (SXEVF_ALIGN / sizeof(sxevf_tx_data_desc_u)) =20 -#define SXEVF_TX_MAX_SEG 40 +#define SXEVF_TX_MAX_SEG 40 #define SXEVF_DEFAULT_TX_QUEUE_NUM 1 #define SXEVF_DEFAULT_RX_QUEUE_NUM 1 -#define SXEVF_RX_BUF_MIN 1024 +#define SXEVF_RX_BUF_MIN 1024 #define SXEVF_RX_BUF_LEN_MAX 9728 =20 static const struct rte_eth_desc_lim rx_desc_lim =3D { @@ -100,7 +100,7 @@ static const char * const sxevf_valid_arguments[] =3D { NULL }; =20 -STATIC s32 sxevf_devargs_handle(__rte_unused const char *key, const char *= value, +static s32 sxevf_devargs_handle(__rte_unused const char *key, const char *= value, void *extra_args) { u16 *n =3D extra_args; @@ -125,15 +125,15 @@ STATIC s32 sxevf_devargs_handle(__rte_unused const ch= ar *key, const char *value, return ret; } =20 -STATIC void sxevf_devargs_parse(struct sxevf_adapter *adapter, - struct rte_devargs *devargs) +static void sxevf_devargs_parse(struct sxevf_adapter *adapter, + struct rte_devargs *devargs) { struct rte_kvargs *kvlist; u16 check; =20 if (devargs =3D=3D NULL) { LOG_INFO_BDF("no dev args."); - goto l_out; + return; } =20 kvlist =3D rte_kvargs_parse(devargs->args, sxevf_valid_arguments); @@ -141,17 +141,16 @@ STATIC void sxevf_devargs_parse(struct sxevf_adapter = *adapter, return; =20 if (rte_kvargs_count(kvlist, SXEVF_DEVARG_LINK_CHECK) =3D=3D 1 && - rte_kvargs_process(kvlist, SXEVF_DEVARG_LINK_CHECK, - sxevf_devargs_handle, &check) =3D=3D 0 && - check =3D=3D 1) { + rte_kvargs_process(kvlist, SXEVF_DEVARG_LINK_CHECK, + sxevf_devargs_handle, &check) =3D=3D 0 && + check =3D=3D 1) { adapter->link_check =3D 1; } =20 LOG_INFO_BDF("dev args link_check:%u", adapter->link_check); =20 rte_kvargs_free(kvlist); -l_out: - return; + } =20 static s32 sxevf_hw_dev_reset(struct sxevf_hw *hw) @@ -179,7 +178,7 @@ static s32 sxevf_hw_dev_reset(struct sxevf_hw *hw) if (!retry) { ret =3D -SXEVF_ERR_RESET_FAILED; LOG_ERROR_BDF("retry=EF=BC=9A%u use up, pf has not reset done.(err:%d)\n= ", - SXEVF_RST_CHECK_NUM, ret); + SXEVF_RST_CHECK_NUM, ret); goto l_out; } =20 @@ -192,7 +191,7 @@ static s32 sxevf_hw_dev_reset(struct sxevf_hw *hw) /* Send reset message to pf */ msg.msg_type =3D SXEVF_RESET; ret =3D sxevf_send_and_rcv_msg(hw, (u32 *)&msg, - SXEVF_MSG_NUM(sizeof(msg))); + SXEVF_MSG_NUM(sizeof(msg))); if (ret) { LOG_ERROR_BDF("vf reset msg:%d len:%zu mailbox fail.(err:%d)\n", msg.msg_type, SXEVF_MSG_NUM(sizeof(msg)), ret); @@ -272,7 +271,6 @@ static void sxevf_txrx_start(struct rte_eth_dev *eth_de= v) sxevf_rx_desc_tail_set(hw, rxq->reg_idx, rxq->ring_depth - 1); } =20 - return; } =20 static s32 sxevf_dev_start(struct rte_eth_dev *dev) @@ -330,7 +328,7 @@ static s32 sxevf_dev_stop(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); =20 if (adapter->stop) { - LOG_INFO_BDF("eth dev has been stoped."); + LOG_INFO_BDF("eth dev has been stopped."); goto l_out; } =20 @@ -348,7 +346,7 @@ static s32 sxevf_dev_stop(struct rte_eth_dev *dev) =20 l_out: #ifdef DPDK_19_11_6 - return; + LOG_DEBUG_BDF("at end of vf dev stop."); #else return 0; #endif @@ -372,9 +370,8 @@ static s32 sxevf_dev_close(struct rte_eth_dev *dev) } =20 ret =3D sxevf_hw_dev_reset(hw); - if (ret) { + if (ret) LOG_ERROR_BDF("dev reset fail."); - } =20 sxevf_dev_stop(dev); =20 @@ -386,13 +383,13 @@ static s32 sxevf_dev_close(struct rte_eth_dev *dev) =20 l_out: #ifdef DPDK_19_11_6 - return; + LOG_DEBUG_BDF("at end of vf dev close."); #else return ret; #endif } =20 -STATIC s32 sxevf_dev_reset(struct rte_eth_dev *dev) +static s32 sxevf_dev_reset(struct rte_eth_dev *dev) { s32 ret; =20 @@ -403,24 +400,23 @@ STATIC s32 sxevf_dev_reset(struct rte_eth_dev *dev) } =20 ret =3D sxevf_ethdev_init(dev); - if (ret) { + if (ret) PMD_LOG_ERR(INIT, "dev init fail."); - } =20 l_out: return ret; } =20 static s32 sxevf_dev_info_get(struct rte_eth_dev *dev, - struct rte_eth_dev_info *dev_info) + struct rte_eth_dev_info *dev_info) { struct sxevf_adapter *adapter =3D dev->data->dev_private; struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); =20 dev_info->max_rx_queues =3D adapter->max_rx_queue; dev_info->max_tx_queues =3D adapter->max_tx_queue; - dev_info->min_rx_bufsize =3D SXEVF_RX_BUF_MIN;=20 - dev_info->max_rx_pktlen =3D SXEVF_RX_BUF_LEN_MAX;=20 + dev_info->min_rx_bufsize =3D SXEVF_RX_BUF_MIN; + dev_info->max_rx_pktlen =3D SXEVF_RX_BUF_LEN_MAX; dev_info->max_mtu =3D dev_info->max_rx_pktlen - SXEVF_ETH_OVERHEAD; dev_info->max_mac_addrs =3D adapter->mac_filter_ctxt.uc_table_size; dev_info->max_hash_mac_addrs =3D SXEVF_UTA_HASH_BIT_MAX; @@ -429,7 +425,7 @@ static s32 sxevf_dev_info_get(struct rte_eth_dev *dev, =20 dev_info->rx_queue_offload_capa =3D sxevf_rx_queue_offloads_get(dev); dev_info->rx_offload_capa =3D (sxevf_rx_port_offloads_get(dev) | - dev_info->rx_queue_offload_capa); + dev_info->rx_queue_offload_capa); dev_info->tx_queue_offload_capa =3D sxevf_tx_queue_offloads_get(dev); dev_info->tx_offload_capa =3D sxevf_tx_port_offloads_get(dev); =20 @@ -484,11 +480,11 @@ static s32 sxevf_mtu_set(struct rte_eth_dev *dev, u16= mtu) } =20 if (dev->data->dev_started && !dev->data->scattered_rx && - ((max_frame + 2 * SXEVF_VLAN_TAG_SIZE) > - (dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))) { + ((max_frame + 2 * SXEVF_VLAN_TAG_SIZE) > + (dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))) { ret =3D -EINVAL; LOG_ERROR_BDF("max_frame:%u stop port first.(err:%d)", - max_frame, ret); + max_frame, ret); goto l_out; } =20 @@ -515,11 +511,10 @@ static s32 sxevf_dev_configure(struct rte_eth_dev *de= v) struct sxevf_adapter *adapter =3D dev->data->dev_private; =20 LOG_INFO_BDF("Configured Virtual Function port id: %d", - dev->data->port_id); + dev->data->port_id); =20 - if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) { + if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) dev->data->dev_conf.rxmode.offloads |=3D RTE_ETH_RX_OFFLOAD_RSS_HASH; - } =20 #ifndef RTE_LIBRTE_SXEVF_PF_DISABLE_STRIP_CRC if (conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) { @@ -604,9 +599,8 @@ static u32 sxevf_regs_group_count(const struct sxevf_re= g_info *regs) int i =3D 0; int count =3D 0; =20 - while (regs[i].count) { + while (regs[i].count) count +=3D regs[i++].count; - } =20 return count; }; @@ -618,9 +612,8 @@ u32 sxevf_regs_group_num_get(void) const struct sxevf_reg_info *reg_group; const struct sxevf_reg_info **reg_set =3D sxevf_regs_group; =20 - while ((reg_group =3D reg_set[i++])) { + while ((reg_group =3D reg_set[i++])) count +=3D sxevf_regs_group_count(reg_group); - } =20 PMD_LOG_INFO(INIT, "read regs cnt=3D%u\n", count); =20 @@ -633,18 +626,16 @@ void sxevf_regs_group_read(struct sxevf_hw *hw, u32 *= data) const struct sxevf_reg_info *reg_group; const struct sxevf_reg_info **reg_set =3D sxevf_regs_group; =20 - while ((reg_group =3D reg_set[i++])) { + while ((reg_group =3D reg_set[i++])) cnt +=3D sxevf_hw_regs_group_read(hw, reg_group, &data[cnt]); - } =20 PMD_LOG_INFO(INIT, "read regs cnt=3D%u, regs num=3D%u\n", - cnt, sxevf_regs_group_num_get()); + cnt, sxevf_regs_group_num_get()); =20 - return; } =20 static int sxevf_get_regs(struct rte_eth_dev *dev, - struct rte_dev_reg_info *regs) + struct rte_dev_reg_info *regs) { s32 ret =3D 0; u32 *data =3D regs->data; @@ -676,47 +667,47 @@ static int sxevf_get_regs(struct rte_eth_dev *dev, } =20 static const struct eth_dev_ops sxevf_eth_dev_ops =3D { - .dev_configure =3D sxevf_dev_configure, - .dev_start =3D sxevf_dev_start, - .dev_stop =3D sxevf_dev_stop, - .link_update =3D sxevf_link_update, - .stats_get =3D sxevf_eth_stats_get, - .xstats_get =3D sxevf_xstats_get, - .stats_reset =3D sxevf_dev_stats_reset, - .xstats_reset =3D sxevf_dev_stats_reset, - .xstats_get_names =3D sxevf_xstats_names_get, - .dev_close =3D sxevf_dev_close, - .dev_reset =3D sxevf_dev_reset, + .dev_configure =3D sxevf_dev_configure, + .dev_start =3D sxevf_dev_start, + .dev_stop =3D sxevf_dev_stop, + .link_update =3D sxevf_link_update, + .stats_get =3D sxevf_eth_stats_get, + .xstats_get =3D sxevf_xstats_get, + .stats_reset =3D sxevf_dev_stats_reset, + .xstats_reset =3D sxevf_dev_stats_reset, + .xstats_get_names =3D sxevf_xstats_names_get, + .dev_close =3D sxevf_dev_close, + .dev_reset =3D sxevf_dev_reset, .promiscuous_enable =3D sxevf_promiscuous_enable, .promiscuous_disable =3D sxevf_promiscuous_disable, .allmulticast_enable =3D sxevf_allmulticast_enable, .allmulticast_disable =3D sxevf_allmulticast_disable, - .dev_infos_get =3D sxevf_dev_info_get, + .dev_infos_get =3D sxevf_dev_info_get, .dev_supported_ptypes_get =3D sxevf_dev_supported_ptypes_get, - .mtu_set =3D sxevf_mtu_set, - .vlan_filter_set =3D sxevf_vlan_filter_set, + .mtu_set =3D sxevf_mtu_set, + .vlan_filter_set =3D sxevf_vlan_filter_set, .vlan_strip_queue_set =3D sxevf_vlan_strip_queue_set, - .vlan_offload_set =3D sxevf_vlan_offload_set, - .rx_queue_setup =3D sxevf_rx_queue_setup, - .rx_queue_release =3D sxevf_rx_queue_release, - .tx_queue_setup =3D sxevf_tx_queue_setup, - .tx_queue_release =3D sxevf_tx_queue_release, + .vlan_offload_set =3D sxevf_vlan_offload_set, + .rx_queue_setup =3D sxevf_rx_queue_setup, + .rx_queue_release =3D sxevf_rx_queue_release, + .tx_queue_setup =3D sxevf_tx_queue_setup, + .tx_queue_release =3D sxevf_tx_queue_release, .rx_queue_intr_enable =3D sxevf_rx_queue_intr_enable, .rx_queue_intr_disable =3D sxevf_rx_queue_intr_disable, - .mac_addr_add =3D sxevf_mac_addr_add, - .mac_addr_remove =3D sxevf_mac_addr_remove, - .set_mc_addr_list =3D sxevf_set_mc_addr_list, - .rxq_info_get =3D sxevf_rx_queue_info_get, - .txq_info_get =3D sxevf_tx_queue_info_get, - .mac_addr_set =3D sxevf_default_mac_addr_set, - .get_reg =3D sxevf_get_regs, - .reta_update =3D sxevf_rss_reta_update, - .reta_query =3D sxevf_rss_reta_query, - .rss_hash_update =3D sxevf_rss_hash_update, - .rss_hash_conf_get =3D sxevf_rss_hash_conf_get, - .tx_done_cleanup =3D sxevf_tx_done_cleanup, + .mac_addr_add =3D sxevf_mac_addr_add, + .mac_addr_remove =3D sxevf_mac_addr_remove, + .set_mc_addr_list =3D sxevf_set_mc_addr_list, + .rxq_info_get =3D sxevf_rx_queue_info_get, + .txq_info_get =3D sxevf_tx_queue_info_get, + .mac_addr_set =3D sxevf_default_mac_addr_set, + .get_reg =3D sxevf_get_regs, + .reta_update =3D sxevf_rss_reta_update, + .reta_query =3D sxevf_rss_reta_query, + .rss_hash_update =3D sxevf_rss_hash_update, + .rss_hash_conf_get =3D sxevf_rss_hash_conf_get, + .tx_done_cleanup =3D sxevf_tx_done_cleanup, #ifdef ETH_DEV_OPS_MONITOR - .get_monitor_addr =3D sxe_monitor_addr_get, + .get_monitor_addr =3D sxe_monitor_addr_get, #endif #ifdef ETH_DEV_OPS_HAS_DESC_RELATE .rx_descriptor_status =3D sxevf_rx_descriptor_status, @@ -749,7 +740,7 @@ s32 sxevf_ethdev_init(struct rte_eth_dev *eth_dev) #endif #endif =20 - eth_dev->rx_pkt_burst =3D &sxevf_pkts_recv; + eth_dev->rx_pkt_burst =3D &sxevf_pkts_recv; eth_dev->tx_pkt_burst =3D &sxevf_pkts_xmit_with_offload; =20 if (rte_eal_process_type() !=3D RTE_PROC_PRIMARY) { @@ -758,12 +749,12 @@ s32 sxevf_ethdev_init(struct rte_eth_dev *eth_dev) } =20 sxevf_devargs_parse(eth_dev->data->dev_private, - pci_dev->device.devargs); + pci_dev->device.devargs); =20 rte_eth_copy_pci_info(eth_dev, pci_dev); =20 -#ifdef DPDK_19_11_6 - eth_dev->data->dev_flags |=3D RTE_ETH_DEV_CLOSE_REMOVE; +#ifdef DPDK_19_11_6 + eth_dev->data->dev_flags |=3D RTE_ETH_DEV_CLOSE_REMOVE; #else eth_dev->data->dev_flags |=3D RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; #endif diff --git a/drivers/net/sxe/vf/sxevf_filter.c b/drivers/net/sxe/vf/sxevf_f= ilter.c index 4f788ee4a1..18257ba43e 100644 --- a/drivers/net/sxe/vf/sxevf_filter.c +++ b/drivers/net/sxe/vf/sxevf_filter.c @@ -18,10 +18,10 @@ #include "sxevf_queue.h" #include "sxe_compat_version.h" =20 -#define SXEVF_MAC_ADDR_EXTRACT_MASK (0xFFF)=20 -#define SXEVF_MAC_ADDR_SHIFT (5)=20=20=20=20=20 -#define SXEVF_MAC_ADDR_REG_MASK (0x7F)=20=20 -#define SXEVF_MAC_ADDR_BIT_MASK (0x1F)=20=20 +#define SXEVF_MAC_ADDR_EXTRACT_MASK (0xFFF) +#define SXEVF_MAC_ADDR_SHIFT (5) +#define SXEVF_MAC_ADDR_REG_MASK (0x7F) +#define SXEVF_MAC_ADDR_BIT_MASK (0x1F) =20 #define SXEVF_STRIP_BITMAP_SET(h, q) \ do { \ @@ -57,7 +57,6 @@ static void sxevf_random_mac_addr_generate(struct rte_eth= er_addr *mac_addr) random =3D rte_rand(); memcpy(&mac_addr->addr_bytes[3], &random, 3); =20 - return; } =20 s32 sxevf_mac_addr_init(struct rte_eth_dev *eth_dev) @@ -71,7 +70,7 @@ s32 sxevf_mac_addr_init(struct rte_eth_dev *eth_dev) RTE_ETHER_ADDR_LEN * SXEVF_HW_UC_ENTRY_NUM_MAX, 0); if (eth_dev->data->mac_addrs =3D=3D NULL) { LOG_ERROR_BDF("mac addr allocate %u B fail.", - RTE_ETHER_ADDR_LEN * SXEVF_HW_UC_ENTRY_NUM_MAX); + RTE_ETHER_ADDR_LEN * SXEVF_HW_UC_ENTRY_NUM_MAX); ret =3D -ENOMEM; goto l_out; } @@ -117,15 +116,13 @@ void sxevf_vfta_sync(struct rte_eth_dev *eth_dev, boo= l on) mask =3D 1; for (bit_idx =3D 0; bit_idx < 32; bit_idx++) { vlan_id =3D (reg_idx << 5) + bit_idx; - if (vfta & mask) { + if (vfta & mask) sxevf_vlan_id_set(hw, vlan_id, on); - } mask <<=3D 1; } } } =20 - return; } =20 static void sxevf_vlan_strip_bitmap_set(struct rte_eth_dev *dev, u16 queue= _idx, bool on) @@ -138,20 +135,19 @@ static void sxevf_vlan_strip_bitmap_set(struct rte_et= h_dev *dev, u16 queue_idx, LOG_ERROR_BDF("invalid queue idx:%u exceed max" " queue number:%u.", queue_idx, adapter->max_rx_queue); - goto l_out; + return; } =20 - if (on) { + if (on) SXEVF_STRIP_BITMAP_SET(vlan_ctxt, queue_idx); - } else { + else SXEVF_STRIP_BITMAP_CLEAR(vlan_ctxt, queue_idx); - } =20 if (queue_idx >=3D dev->data->nb_rx_queues) { LOG_ERROR_BDF("invalid queue_idx id:%u exceed rx " " queue number:%u.", queue_idx, dev->data->nb_rx_queues); - goto l_out; + return; } =20 rxq =3D dev->data->rx_queues[queue_idx]; @@ -165,10 +161,8 @@ static void sxevf_vlan_strip_bitmap_set(struct rte_eth= _dev *dev, u16 queue_idx, } =20 LOG_INFO_BDF("queue idx:%u vlan strip on:%d set bitmap and offload done.", - queue_idx, on); + queue_idx, on); =20 -l_out: - return; } =20 static void sxevf_vlan_strip_switch_set(struct rte_eth_dev *dev) @@ -184,26 +178,23 @@ static void sxevf_vlan_strip_switch_set(struct rte_et= h_dev *dev) for (i =3D 0; i < dev->data->nb_rx_queues; i++) { rxq =3D dev->data->rx_queues[i]; =20 - if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { + if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) on =3D true; - } else { + else on =3D false; - } + sxevf_hw_vlan_tag_strip_switch(hw, i, on); =20 sxevf_vlan_strip_bitmap_set(dev, i, on); } =20 - return; } =20 static void sxevf_vlan_offload_configure(struct rte_eth_dev *dev, s32 mask) { - if (mask & RTE_ETH_VLAN_STRIP_MASK) { + if (mask & RTE_ETH_VLAN_STRIP_MASK) sxevf_vlan_strip_switch_set(dev); - } =20 - return; } =20 void sxevf_vlan_filter_configure(struct rte_eth_dev *eth_dev) @@ -213,11 +204,10 @@ void sxevf_vlan_filter_configure(struct rte_eth_dev *= eth_dev) sxevf_vfta_sync(eth_dev, true); =20 vlan_mask =3D RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK | - RTE_ETH_VLAN_EXTEND_MASK; + RTE_ETH_VLAN_EXTEND_MASK; =20 sxevf_vlan_offload_configure(eth_dev, vlan_mask); =20 - return; } =20 s32 sxevf_promiscuous_enable(struct rte_eth_dev *eth_dev) @@ -229,7 +219,7 @@ s32 sxevf_promiscuous_enable(struct rte_eth_dev *eth_de= v) ret =3D sxevf_cast_mode_set(hw, SXEVF_CAST_MODE_PROMISC); if (ret) { LOG_ERROR_BDF("cast mode:0x%x set fail.(err:%d)", - SXEVF_CAST_MODE_PROMISC, ret); + SXEVF_CAST_MODE_PROMISC, ret); } =20 return ret; @@ -242,13 +232,11 @@ s32 sxevf_promiscuous_disable(struct rte_eth_dev *eth= _dev) s32 mode =3D SXEVF_CAST_MODE_NONE; s32 ret; =20 - if (eth_dev->data->all_multicast) { + if (eth_dev->data->all_multicast) mode =3D SXEVF_CAST_MODE_ALLMULTI; - } ret =3D sxevf_cast_mode_set(hw, mode); - if (ret) { + if (ret) LOG_ERROR_BDF("disable mc promiscuous fail.(err:%d)", ret); - } =20 return ret; } @@ -259,15 +247,13 @@ s32 sxevf_allmulticast_enable(struct rte_eth_dev *eth= _dev) struct sxevf_hw *hw =3D &adapter->hw; s32 ret =3D 0; =20 - if (eth_dev->data->promiscuous) { + if (eth_dev->data->promiscuous) goto l_out; - } -=09 + ret =3D sxevf_cast_mode_set(hw, SXEVF_CAST_MODE_ALLMULTI); - if (ret) { + if (ret) LOG_ERROR_BDF("cast mode:0x%x set fail.(err:%d)", - SXEVF_CAST_MODE_ALLMULTI, ret); - } + SXEVF_CAST_MODE_ALLMULTI, ret); =20 l_out: return ret; @@ -279,14 +265,12 @@ s32 sxevf_allmulticast_disable(struct rte_eth_dev *et= h_dev) struct sxevf_hw *hw =3D &adapter->hw; s32 ret =3D 0; =20 - if (eth_dev->data->promiscuous) { + if (eth_dev->data->promiscuous) goto l_out; - } =20 ret =3D sxevf_cast_mode_set(hw, SXEVF_CAST_MODE_MULTI); - if (ret) { + if (ret) LOG_ERROR_BDF("disable mc promiscuous fail.(err:%d)", ret); - } =20 l_out: return ret; @@ -304,18 +288,17 @@ s32 sxevf_vlan_filter_set(struct rte_eth_dev *eth_dev= , u16 vlan_id, s32 on) ret =3D sxevf_vlan_id_set(hw, vlan_id, on); if (ret) { LOG_ERROR_BDF("vlan_id:0x%x status:%u set fail.(err:%d)", - vlan_id, on, ret); + vlan_id, on, ret); goto l_out; } =20 reg_idx =3D (vlan_id >> SXEVF_VLAN_ID_SHIFT) & SXEVF_VLAN_ID_REG_MASK; bit_idx =3D (vlan_id & SXEVF_VLAN_ID_BIT_MASK); =20 - if (on) { + if (on) vlan_ctxt->vlan_table[reg_idx] |=3D (1 << bit_idx); - } else { + else vlan_ctxt->vlan_table[reg_idx] &=3D ~(1 << bit_idx); - } =20 LOG_INFO_BDF("vlan_id:0x%x status:%u set success.", vlan_id, on); =20 @@ -330,8 +313,8 @@ void sxevf_vlan_strip_queue_set(struct rte_eth_dev *dev= , u16 queue, s32 on) =20 if (queue > adapter->max_rx_queue) { LOG_ERROR_BDF("queue id:%u invalid exceed max rx queue num:%u", - queue, adapter->max_rx_queue); - goto l_out; + queue, adapter->max_rx_queue); + return; } =20 sxevf_hw_vlan_tag_strip_switch(hw, queue, on); @@ -340,8 +323,6 @@ void sxevf_vlan_strip_queue_set(struct rte_eth_dev *dev= , u16 queue, s32 on) =20 LOG_INFO_BDF("queue:%u vlan tag strip on:%u done", queue, on); =20 -l_out: - return; } =20 static void sxevf_vlan_strip_offload_configure(struct rte_eth_dev *dev, s3= 2 mask) @@ -365,10 +346,9 @@ static void sxevf_vlan_strip_offload_configure(struct = rte_eth_dev *dev, s32 mask } =20 PMD_LOG_INFO(DRV, "mask:0x%x rx mode offload:0x%"SXE_PRIX64 - " all queue vlan strip offload flag configure done", - mask, rxmode->offloads); + " all queue vlan strip offload flag configure done", + mask, rxmode->offloads); =20 - return; } =20 s32 sxevf_vlan_offload_set(struct rte_eth_dev *dev, s32 mask) @@ -377,13 +357,13 @@ s32 sxevf_vlan_offload_set(struct rte_eth_dev *dev, s= 32 mask) =20 sxevf_vlan_offload_configure(dev, mask); =20 - PMD_LOG_INFO(DRV, "vlan offload mask:0x%d set done.", mask); + PMD_LOG_INFO(DRV, "vlan offload mask:0x%x set done.", mask); =20 return 0; } =20 s32 sxevf_default_mac_addr_set(struct rte_eth_dev *dev, - struct rte_ether_addr *mac_addr) + struct rte_ether_addr *mac_addr) { s32 ret; struct sxevf_adapter *adapter =3D dev->data->dev_private; @@ -392,18 +372,18 @@ s32 sxevf_default_mac_addr_set(struct rte_eth_dev *de= v, ret =3D sxevf_mac_addr_set(hw, mac_addr->addr_bytes); if (ret) { LOG_ERROR_BDF("modify default mac addr to "MAC_FMT" fail.(err:%d)", - MAC_ADDR(mac_addr->addr_bytes), ret); + MAC_ADDR(mac_addr->addr_bytes), ret); } =20 LOG_INFO_BDF("modify default mac addr to "MAC_FMT" success.", - MAC_ADDR(mac_addr->addr_bytes)); + MAC_ADDR(mac_addr->addr_bytes)); =20 return ret; } =20 s32 sxevf_mac_addr_add(struct rte_eth_dev *dev, - struct rte_ether_addr *mac_addr, - __rte_unused u32 rar_idx ,__rte_unused u32 pool) + struct rte_ether_addr *mac_addr, + __rte_unused u32 rar_idx, __rte_unused u32 pool) { s32 ret; struct sxevf_adapter *adapter =3D dev->data->dev_private; @@ -411,23 +391,23 @@ s32 sxevf_mac_addr_add(struct rte_eth_dev *dev, struct sxevf_mac_filter_context *mac_ctxt =3D &adapter->mac_filter_ctxt; =20 if (memcmp(mac_ctxt->def_mac_addr.addr_bytes, mac_addr->addr_bytes, - sizeof(*mac_addr)) =3D=3D 0) { + sizeof(*mac_addr)) =3D=3D 0) { ret =3D -EINVAL; LOG_ERROR_BDF("mac_addr:"MAC_FMT" eaqual to defalut mac addr" - " skip mac addr add.(err:%d)", - MAC_ADDR(mac_addr->addr_bytes), ret); + " skip mac addr add.(err:%d)", + MAC_ADDR(mac_addr->addr_bytes), ret); goto l_out; } =20 ret =3D sxevf_uc_addr_add(hw, 2, mac_addr->addr_bytes); if (ret) { LOG_ERROR_BDF("mac_addr:"MAC_FMT" add fail.(err:%d)", - MAC_ADDR(mac_addr->addr_bytes), ret); + MAC_ADDR(mac_addr->addr_bytes), ret); goto l_out; } =20 LOG_INFO_BDF("mac_addr:"MAC_FMT" add success.", - MAC_ADDR(mac_addr->addr_bytes)); + MAC_ADDR(mac_addr->addr_bytes)); =20 l_out: return ret; @@ -438,24 +418,23 @@ void sxevf_mac_addr_remove(struct rte_eth_dev *dev, u= 32 index) struct sxevf_adapter *adapter =3D dev->data->dev_private; struct sxevf_hw *hw =3D &adapter->hw; struct sxevf_mac_filter_context *mac_ctxt =3D &adapter->mac_filter_ctxt; - struct rte_ether_addr *mac_addr;=20 + struct rte_ether_addr *mac_addr; u8 i; =20 sxevf_uc_addr_add(hw, 0, NULL); =20 for (i =3D 0, mac_addr =3D dev->data->mac_addrs; i < mac_ctxt->uc_table_s= ize; - i++, mac_addr++) { + i++, mac_addr++) { if ((i =3D=3D index) || rte_is_zero_ether_addr(mac_addr) || (memcmp(mac_ctxt->def_mac_addr.addr_bytes, mac_addr->addr_bytes, - sizeof(*mac_addr)) =3D=3D 0)) { + sizeof(*mac_addr)) =3D=3D 0)) { continue; } sxevf_uc_addr_add(hw, 2, mac_addr->addr_bytes); } =20 LOG_INFO_BDF("index:%u mac addr"MAC_FMT" remove success.", - index, MAC_ADDR(dev->data->mac_addrs[index].addr_bytes)); - return; + index, MAC_ADDR(dev->data->mac_addrs[index].addr_bytes)); } =20 static u16 sxevf_hash_mac_addr_parse(u8 *mac_addr) @@ -483,7 +462,7 @@ s32 sxevf_set_mc_addr_list(struct rte_eth_dev *dev, u32 i; =20 msg.msg_type =3D SXEVF_MC_ADDR_SYNC; - msg.mc_cnt =3D min(nb_mc_addr, (u32)SXEVF_MC_ENTRY_NUM_MAX); + msg.mc_cnt =3D RTE_MIN(nb_mc_addr, (u32)SXEVF_MC_ENTRY_NUM_MAX); =20 for (i =3D 0; i < msg.mc_cnt; i++) { msg.mc_addr_extract[i] =3D sxevf_hash_mac_addr_parse(mc_addr_list->addr_= bytes); @@ -494,7 +473,7 @@ s32 sxevf_set_mc_addr_list(struct rte_eth_dev *dev, result =3D (msg.mc_cnt << 16) | msg.msg_type; =20 if (ret || ((result & SXEVF_MC_ADDR_SYNC) && - (result & SXEVF_MSGTYPE_NACK))) { + (result & SXEVF_MSGTYPE_NACK))) { ret =3D ret ? ret : -SXEVF_ERR_MSG_HANDLE_ERR; goto l_out; } diff --git a/drivers/net/sxe/vf/sxevf_filter.h b/drivers/net/sxe/vf/sxevf_f= ilter.h index 9e74718b95..e94be98ec5 100644 --- a/drivers/net/sxe/vf/sxevf_filter.h +++ b/drivers/net/sxe/vf/sxevf_filter.h @@ -13,32 +13,32 @@ #include #endif =20 -#define SXEVF_MTA_ENTRY_NUM_MAX 128 -#define SXEVF_UTA_HASH_BIT_MAX 4096=20 -#define VLAN_N_VID 4096 +#define SXEVF_MTA_ENTRY_NUM_MAX 128 +#define SXEVF_UTA_HASH_BIT_MAX 4096 +#define VLAN_N_VID 4096 #define BYTE_BIT_NUM 8 =20 -#define SXEVF_VLAN_ID_SHIFT (5)=20=20=20=20=20 -#define SXEVF_VLAN_ID_REG_MASK (0x7F)=20=20 -#define SXEVF_VLAN_ID_BIT_MASK (0x1F)=20=20 +#define SXEVF_VLAN_ID_SHIFT (5) +#define SXEVF_VLAN_ID_REG_MASK (0x7F) +#define SXEVF_VLAN_ID_BIT_MASK (0x1F) =20 #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ADDR(x) ((u8*)(x))[0],((u8*)(x))[1], \ - ((u8*)(x))[2],((u8*)(x))[3], \ - ((u8*)(x))[4],((u8*)(x))[5] +#define MAC_ADDR(x) ((u8 *)(x))[0], ((u8 *)(x))[1], \ + ((u8 *)(x))[2], ((u8 *)(x))[3], \ + ((u8 *)(x))[4], ((u8 *)(x))[5] =20 -#define SXEVF_VLAN_STRIP_BITMAP_SIZE \ - (SXEVF_HW_TXRX_RING_NUM_MAX / (sizeof(u32) * BYTE_BIT_NUM)) +#define SXEVF_VLAN_STRIP_BITMAP_SIZE \ + (SXEVF_HW_TXRX_RING_NUM_MAX / (sizeof(u32) * BYTE_BIT_NUM)) =20 struct sxevf_vlan_context { - u32 vlan_table[SXEVF_VFT_TBL_SIZE];=20=20 + u32 vlan_table[SXEVF_VFT_TBL_SIZE]; u32 strip_bitmap[SXEVF_VLAN_STRIP_BITMAP_SIZE]; u32 vlan_table_size; }; =20 struct sxevf_mac_filter_context { - struct rte_ether_addr def_mac_addr;=20 - u8 mc_filter_type;=20=20=20=20=20=20=20=20 + struct rte_ether_addr def_mac_addr; + u8 mc_filter_type; u32 uc_table_size; }; =20 @@ -65,15 +65,16 @@ void sxevf_vlan_strip_queue_set(struct rte_eth_dev *dev= , u16 queue, s32 on); s32 sxevf_vlan_offload_set(struct rte_eth_dev *dev, s32 mask); =20 s32 sxevf_default_mac_addr_set(struct rte_eth_dev *dev, - struct rte_ether_addr *mac_addr); + struct rte_ether_addr *mac_addr); =20 void sxevf_mac_addr_remove(struct rte_eth_dev *dev, u32 index); =20 s32 sxevf_mac_addr_add(struct rte_eth_dev *dev, - struct rte_ether_addr *mac_addr, - __rte_unused u32 rar_idx ,__rte_unused u32 pool); + struct rte_ether_addr *mac_addr, + __rte_unused u32 rar_idx, __rte_unused u32 pool); =20 s32 sxevf_set_mc_addr_list(struct rte_eth_dev *dev, struct rte_ether_addr *mc_addr_list, u32 nb_mc_addr); + #endif diff --git a/drivers/net/sxe/vf/sxevf_irq.c b/drivers/net/sxe/vf/sxevf_irq.c index 646a10d6dc..eb374a920e 100644 --- a/drivers/net/sxe/vf/sxevf_irq.c +++ b/drivers/net/sxe/vf/sxevf_irq.c @@ -30,22 +30,23 @@ #include "sxevf_queue.h" #include "sxe_compat_version.h" =20 -#define SXEVF_IRQ_LINK_CONFIG (u32)(1 << 3) +#define SXEVF_IRQ_LINK_CONFIG (u32)(1 << 3) =20 -#define SXEVF_RX_OTHER_IRQ_MASK (3) +#define SXEVF_RX_OTHER_IRQ_MASK (3) =20 -#define SXEVF_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET +#define SXEVF_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET =20 -#define SXEVF_RX_VEC_BASE RTE_INTR_VEC_RXTX_OFFSET +#define SXEVF_RX_VEC_BASE RTE_INTR_VEC_RXTX_OFFSET =20 #define SXEVF_EITR_INTERVAL_UNIT_NS 2048 -#define SXEVF_EITR_ITR_INT_SHIFT 3 -#define SXEVF_IRQ_ITR_MASK (0x00000FF8) +#define SXEVF_EITR_ITR_INT_SHIFT 3 +#define SXEVF_IRQ_ITR_MASK (0x00000FF8) #define SXEVF_EITR_INTERVAL_US(us) \ (((us) * 1000 / SXEVF_EITR_INTERVAL_UNIT_NS << SXEVF_EITR_ITR_INT_SHIFT) = & \ SXEVF_IRQ_ITR_MASK) =20 -#define SXEVF_QUEUE_ITR_INTERVAL_DEFAULT 500=20 +#define SXEVF_QUEUE_ITR_INTERVAL_DEFAULT 500 +#define SXEVF_QUEUE_ITR_INTERVAL 3 =20 void sxevf_intr_disable(struct rte_eth_dev *eth_dev) { @@ -59,7 +60,6 @@ void sxevf_intr_disable(struct rte_eth_dev *eth_dev) =20 irq_ctxt->enable_mask =3D 0; =20 - return; } =20 void sxevf_intr_enable(struct rte_eth_dev *eth_dev) @@ -74,7 +74,6 @@ void sxevf_intr_enable(struct rte_eth_dev *eth_dev) =20 irq_ctxt->enable_mask =3D SXEVF_RX_OTHER_IRQ_MASK; =20 - return; } =20 static s32 sxevf_ctrl_msg_check(struct rte_eth_dev *eth_dev) @@ -93,7 +92,7 @@ static s32 sxevf_ctrl_msg_check(struct rte_eth_dev *eth_d= ev) =20 if (ctrl_msg & SXEVF_PF_CTRL_MSG_REINIT) { sxe_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_RESET, - NULL); + NULL); PMD_LOG_INFO(DRV, "rcv reinit msg.\n"); } =20 @@ -101,7 +100,7 @@ static s32 sxevf_ctrl_msg_check(struct rte_eth_dev *eth= _dev) return ret; } =20 -STATIC s32 sxevf_link_msg_check(struct rte_eth_dev *eth_dev, bool *link_up) +static s32 sxevf_link_msg_check(struct rte_eth_dev *eth_dev, bool *link_up) { struct sxevf_adapter *adapter =3D eth_dev->data->dev_private; struct sxevf_hw *hw =3D &adapter->hw; @@ -116,18 +115,18 @@ STATIC s32 sxevf_link_msg_check(struct rte_eth_dev *e= th_dev, bool *link_up) } =20 if (ctrl_msg & SXEVF_PF_CTRL_MSG_NETDEV_DOWN) { - *link_up =3D false; - PMD_LOG_INFO(DRV, "rcv ctrl msg:0x%x need link down.\n", ctrl_msg); - } else if (ctrl_msg & SXEVF_PF_CTRL_MSG_LINK_UPDATE) { - *link_up =3D true; - PMD_LOG_INFO(DRV, "rcv ctrl msg:0x%x physical link up.\n", ctrl_msg); - } + *link_up =3D false; + PMD_LOG_INFO(DRV, "rcv ctrl msg:0x%x need link down.\n", ctrl_msg); + } else if (ctrl_msg & SXEVF_PF_CTRL_MSG_LINK_UPDATE) { + *link_up =3D true; + PMD_LOG_INFO(DRV, "rcv ctrl msg:0x%x physical link up.\n", ctrl_msg); + } =20 l_end: return ret; } =20 -STATIC void sxevf_mbx_irq_handler(void *data) +static void sxevf_mbx_irq_handler(void *data) { struct rte_eth_dev *eth_dev =3D (struct rte_eth_dev *)data; =20 @@ -137,7 +136,6 @@ STATIC void sxevf_mbx_irq_handler(void *data) =20 sxevf_intr_enable(eth_dev); =20 - return; } =20 void sxevf_irq_init(struct rte_eth_dev *eth_dev) @@ -153,7 +151,6 @@ void sxevf_irq_init(struct rte_eth_dev *eth_dev) rte_intr_enable(irq_handle); sxevf_intr_enable(eth_dev); =20 - return; } =20 static s32 sxevf_msix_configure(struct rte_eth_dev *dev) @@ -178,9 +175,8 @@ static s32 sxevf_msix_configure(struct rte_eth_dev *dev) goto l_out; } =20 - if (rte_intr_allow_others(handle)) { + if (rte_intr_allow_others(handle)) vector =3D base =3D SXEVF_RX_VEC_BASE; - } =20 for (queue_id =3D 0; queue_id < dev->data->nb_rx_queues; queue_id++) { @@ -194,12 +190,11 @@ static s32 sxevf_msix_configure(struct rte_eth_dev *d= ev) queue_id, rx_queue->reg_idx, vector); - if (vector < base + handle->nb_efd - 1) { + if (vector < base + handle->nb_efd - 1) vector++; - } } =20 - irq_interval =3D SXEVF_EITR_INTERVAL_US(SXEVF_QUEUE_ITR_INTERVAL_DEFAULT); + irq_interval =3D SXEVF_EITR_INTERVAL_US(SXEVF_QUEUE_ITR_INTERVAL); sxevf_ring_irq_interval_set(hw, 0, irq_interval); =20 l_out: @@ -214,20 +209,20 @@ s32 sxevf_irq_configure(struct rte_eth_dev *eth_dev) s32 ret =3D 0; =20 if (rte_intr_cap_multiple(handle) && - eth_dev->data->dev_conf.intr_conf.rxq !=3D 0) { + eth_dev->data->dev_conf.intr_conf.rxq !=3D 0) { irq_num =3D 1; if (rte_intr_efd_enable(handle, irq_num)) { ret =3D -SXE_ERR_CONFIG; PMD_LOG_ERR(DRV, - "intr_handle type:%d irq num:%d invalid", - handle->type, irq_num); + "intr_handle type:%d irq num:%d invalid", + handle->type, irq_num); goto l_out; } } =20 if (rte_intr_dp_is_en(handle) && !handle->intr_vec) { handle->intr_vec =3D rte_zmalloc("intr_vec", - eth_dev->data->nb_rx_queues * sizeof(u32), 0); + eth_dev->data->nb_rx_queues * sizeof(u32), 0); if (handle->intr_vec =3D=3D NULL) { PMD_LOG_ERR(DRV, "rx queue irq vector " "allocate %zuB memory fail.", @@ -251,13 +246,13 @@ s32 sxevf_irq_configure(struct rte_eth_dev *eth_dev) sxevf_intr_enable(eth_dev); =20 PMD_LOG_INFO(DRV, - "intr_handle type:%d rx queue num:%d " - "queue irq num:%u total irq num:%u " - "config done", - handle->type, - eth_dev->data->nb_rx_queues, - handle->nb_efd, - handle->max_intr); + "intr_handle type:%d rx queue num:%d " + "queue irq num:%u total irq num:%u " + "config done", + handle->type, + eth_dev->data->nb_rx_queues, + handle->nb_efd, + handle->max_intr); =20 l_out: return ret; @@ -275,7 +270,6 @@ void sxevf_irq_free(struct rte_eth_dev *eth_dev) handle->intr_vec =3D NULL; } =20 - return; } =20 void sxevf_irq_unregister(struct rte_eth_dev *eth_dev) @@ -285,7 +279,6 @@ void sxevf_irq_unregister(struct rte_eth_dev *eth_dev) =20 rte_intr_callback_unregister(handle, sxevf_mbx_irq_handler, eth_dev); =20 - return; } =20 s32 sxevf_rx_queue_intr_enable(struct rte_eth_dev *dev, u16 queue_id) @@ -299,9 +292,8 @@ s32 sxevf_rx_queue_intr_enable(struct rte_eth_dev *dev,= u16 queue_id) =20 RTE_SET_USED(queue_id); =20 - if (rte_intr_allow_others(intr_handle)) { + if (rte_intr_allow_others(intr_handle)) vector =3D SXEVF_RX_VEC_BASE; - } =20 irq_ctxt->enable_mask |=3D (1 << vector); =20 @@ -323,9 +315,8 @@ s32 sxevf_rx_queue_intr_disable(struct rte_eth_dev *dev= , u16 queue_id) =20 RTE_SET_USED(queue_id); =20 - if (rte_intr_allow_others(intr_handle)) { + if (rte_intr_allow_others(intr_handle)) vector =3D SXEVF_RX_VEC_BASE; - } =20 irq_ctxt->enable_mask &=3D ~(1 << vector); =20 @@ -373,7 +364,6 @@ static void sxevf_physical_link_check(struct rte_eth_de= v *dev, u32 *link_speed, =20 l_end: PMD_LOG_INFO(DRV, "link up status:%d.\n", *link_up); - return; } =20 static void sxevf_link_info_get(struct rte_eth_dev *dev, int wait_to_compl= ete, @@ -385,24 +375,21 @@ static void sxevf_link_info_get(struct rte_eth_dev *d= ev, int wait_to_complete, sxevf_physical_link_check(dev, link_speed, link_up); =20 if ((wait_to_complete =3D=3D 0) && (adapter->link_check =3D=3D 0)) { - if (*link_speed =3D=3D SXEVF_LINK_SPEED_UNKNOWN) { + if (*link_speed =3D=3D SXEVF_LINK_SPEED_UNKNOWN) *link_up =3D false; - } else { + else *link_up =3D true; - } - goto l_end; + return; } =20 if (*link_up) { ret =3D sxevf_link_msg_check(dev, link_up); if (ret) { PMD_LOG_ERR(DRV, "ctrl msg rcv fail, try to next workqueue.\n"); - goto l_end; + return; } } =20 -l_end: - return; } =20 s32 sxevf_link_update(struct rte_eth_dev *dev, int wait_to_complete) @@ -420,9 +407,8 @@ s32 sxevf_link_update(struct rte_eth_dev *dev, int wait= _to_complete) link.link_autoneg =3D !(dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED); =20 - if ((wait_to_complete =3D=3D 0) || dev->data->dev_conf.intr_conf.lsc) { + if ((wait_to_complete =3D=3D 0) || dev->data->dev_conf.intr_conf.lsc) wait_to_complete =3D 0; - } =20 sxevf_link_info_get(dev, wait_to_complete, &link_speed, &link_up); =20 diff --git a/drivers/net/sxe/vf/sxevf_irq.h b/drivers/net/sxe/vf/sxevf_irq.h index 169eb1f0fd..8ebc319e83 100644 --- a/drivers/net/sxe/vf/sxevf_irq.h +++ b/drivers/net/sxe/vf/sxevf_irq.h @@ -14,8 +14,8 @@ #include "sxe_compat_platform.h" =20 struct sxevf_irq_context { - u32 enable_mask;=20=20=20=20 - u32 enable_mask_original;=20 + u32 enable_mask; + u32 enable_mask_original; }; =20 void sxevf_intr_disable(struct rte_eth_dev *eth_dev); diff --git a/drivers/net/sxe/vf/sxevf_main.c b/drivers/net/sxe/vf/sxevf_mai= n.c index 72d600c0b1..1eb4c3b002 100644 --- a/drivers/net/sxe/vf/sxevf_main.c +++ b/drivers/net/sxe/vf/sxevf_main.c @@ -32,15 +32,15 @@ #include "sxevf_ethdev.h" #include "sxe_queue_common.h" =20 -#define PCI_VENDOR_ID_STARS 0x1FF2 -#define SXEVF_DEV_ID_ASIC 0x10A2 +#define PCI_VENDOR_ID_STARS 0x1FF2 +#define SXEVF_DEV_ID_ASIC 0x10A2 =20 static s32 sxevf_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) { s32 ret; =20 - printf("sxe_version[%s], sxe_commit_id[%s], sxe_branch[%s], sxe_build_tim= e[%s]\n",=20 + printf("sxe_version[%s], sxe_commit_id[%s], sxe_branch[%s], sxe_build_tim= e[%s]\n", SXE_VERSION, SXE_COMMIT_ID, SXE_BRANCH, SXE_BUILD_TIME); =20 #ifdef SXE_DPDK_DEBUG @@ -78,17 +78,17 @@ static const struct rte_pci_id sxevf_pci_tbl[] =3D { {.vendor_id =3D 0,} }; =20 -STATIC struct rte_pci_driver rte_sxevf_pmd =3D { +static struct rte_pci_driver rte_sxevf_pmd =3D { .id_table =3D sxevf_pci_tbl, .drv_flags =3D RTE_PCI_DRV_NEED_MAPPING, - .probe =3D sxevf_probe, - .remove =3D sxevf_remove, + .probe =3D sxevf_probe, + .remove =3D sxevf_remove, }; =20 RTE_PMD_REGISTER_PCI(net_sxevf, rte_sxevf_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_sxevf, sxevf_pci_tbl); RTE_PMD_REGISTER_KMOD_DEP(net_sxevf, "* igb_uio | vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(net_sxevf, - SXEVF_DEVARG_LINK_CHECK "=3D<0|1>"); + SXEVF_DEVARG_LINK_CHECK "=3D<0|1>"); =20 #endif diff --git a/drivers/net/sxe/vf/sxevf_msg.c b/drivers/net/sxe/vf/sxevf_msg.c index 6cd64fc1b3..aa832b5aeb 100644 --- a/drivers/net/sxe/vf/sxevf_msg.c +++ b/drivers/net/sxe/vf/sxevf_msg.c @@ -10,8 +10,8 @@ #include "sxe_errno.h" #include "sxe_logs.h" =20 -#define SXEVF_PFMSG_MASK 0xFF00 -#define SXEVF_DEFAULT_TC_NUM 1 +#define SXEVF_PFMSG_MASK 0xFF00 +#define SXEVF_DEFAULT_TC_NUM 1 =20 void sxevf_mbx_init(struct sxevf_hw *hw) { @@ -28,7 +28,6 @@ void sxevf_mbx_init(struct sxevf_hw *hw) =20 hw->mbx.api_version =3D SXEVF_MBX_API_10; =20 - return; } =20 static u32 sxevf_mbx_reg_read(struct sxevf_hw *hw) @@ -47,16 +46,15 @@ static bool sxevf_mbx_bit_check(struct sxevf_hw *hw, u3= 2 mask) bool ret =3D false; u32 value =3D sxevf_mbx_reg_read(hw); =20 - if (value & mask) { + if (value & mask) ret =3D true; - } =20 hw->mbx.reg_value &=3D ~mask; =20 return ret; } =20 -STATIC bool sxevf_pf_msg_check(struct sxevf_hw *hw) +static bool sxevf_pf_msg_check(struct sxevf_hw *hw) { bool ret =3D false; =20 @@ -68,7 +66,7 @@ STATIC bool sxevf_pf_msg_check(struct sxevf_hw *hw) return ret; } =20 -STATIC bool sxevf_pf_ack_check(struct sxevf_hw *hw) +static bool sxevf_pf_ack_check(struct sxevf_hw *hw) { bool ret =3D false; =20 @@ -85,7 +83,7 @@ bool sxevf_pf_rst_check(struct sxevf_hw *hw) bool ret =3D false; =20 if (!sxevf_mbx_bit_check(hw, (SXE_VFMAILBOX_RSTI | - SXE_VFMAILBOX_RSTD))) { + SXE_VFMAILBOX_RSTD))) { hw->mbx.stats.rsts++; ret =3D true; } @@ -93,7 +91,7 @@ bool sxevf_pf_rst_check(struct sxevf_hw *hw) return ret; } =20 -STATIC s32 sxevf_mailbox_lock(struct sxevf_hw *hw) +static s32 sxevf_mailbox_lock(struct sxevf_hw *hw) { u32 mailbox; u32 retry =3D SXEVF_MBX_RETRY_COUNT; @@ -123,10 +121,9 @@ static void sxevf_mailbox_unlock(struct sxevf_hw *hw) mailbox &=3D ~SXE_VFMAILBOX_VFU; sxevf_mailbox_write(hw, mailbox); =20 - return; } =20 -STATIC bool sxevf_msg_poll(struct sxevf_hw *hw) +static bool sxevf_msg_poll(struct sxevf_hw *hw) { struct sxevf_mbx_info *mbx =3D &hw->mbx; u32 retry =3D mbx->retry; @@ -148,7 +145,7 @@ STATIC bool sxevf_msg_poll(struct sxevf_hw *hw) return ret; } =20 -STATIC bool sxevf_ack_poll(struct sxevf_hw *hw) +static bool sxevf_ack_poll(struct sxevf_hw *hw) { struct sxevf_mbx_info *mbx =3D &hw->mbx; u32 retry =3D mbx->retry; @@ -171,7 +168,7 @@ STATIC bool sxevf_ack_poll(struct sxevf_hw *hw) return ret; } =20 -STATIC void sxevf_pf_msg_and_ack_clear(struct sxevf_hw *hw) +static void sxevf_pf_msg_and_ack_clear(struct sxevf_hw *hw) { struct sxevf_adapter *adapter =3D hw->adapter; =20 @@ -180,7 +177,6 @@ STATIC void sxevf_pf_msg_and_ack_clear(struct sxevf_hw = *hw) sxevf_pf_msg_check(hw); sxevf_pf_ack_check(hw); =20 - return; } =20 static s32 sxevf_send_msg_to_pf(struct sxevf_hw *hw, u32 *msg, u16 msg_len) @@ -218,9 +214,8 @@ static s32 sxevf_send_msg_to_pf(struct sxevf_hw *hw, u3= 2 *msg, u16 msg_len) old =3D sxevf_msg_read(hw, 0); msg[0] |=3D (old & SXEVF_PFMSG_MASK); =20 - for (i =3D 0; i < msg_len; i++) { + for (i =3D 0; i < msg_len; i++) sxevf_msg_write(hw, i, msg[i]); - } =20 sxevf_pf_req_irq_trigger(hw); =20 @@ -259,9 +254,8 @@ s32 sxevf_mbx_msg_rcv(struct sxevf_hw *hw, u32 *msg, u1= 6 msg_len) goto l_end; } =20 - for (i =3D 0; i < msg_entry; i++) { + for (i =3D 0; i < msg_entry; i++) msg[i] =3D sxevf_msg_read(hw, i); - } =20 msg[0] &=3D ~SXEVF_PFMSG_MASK; =20 @@ -290,9 +284,8 @@ s32 sxevf_ctrl_msg_rcv(struct sxevf_hw *hw, u32 *msg, u= 16 msg_len) goto l_end; } =20 - for (i =3D 0; i < msg_entry; i++) { + for (i =3D 0; i < msg_entry; i++) msg[i] =3D sxevf_msg_read(hw, i); - } =20 sxevf_mailbox_unlock(hw); =20 @@ -321,9 +314,8 @@ s32 sxevf_ctrl_msg_rcv_and_clear(struct sxevf_hw *hw, u= 32 *msg, u16 msg_len) goto l_end; } =20 - for (i =3D 0; i < msg_entry; i++) { + for (i =3D 0; i < msg_entry; i++) msg[i] =3D sxevf_msg_read(hw, i); - } =20 clear =3D msg[0] & (~SXEVF_PFMSG_MASK); sxevf_msg_write(hw, 0, clear); @@ -375,9 +367,8 @@ s32 sxevf_send_and_rcv_msg(struct sxevf_hw *hw, u32 *ms= g, u8 msg_len) goto l_out; } =20 - if (msg_type =3D=3D SXEVF_RESET) { + if (msg_type =3D=3D SXEVF_RESET) mdelay(10); - } =20 ret =3D sxevf_rcv_msg_from_pf(hw, msg, msg_len); if (ret) { @@ -414,14 +405,12 @@ void sxevf_mbx_api_version_init(struct sxevf_adapter = *adapter) if (!ret && (msg.msg_type =3D=3D (SXEVF_API_NEGOTIATE | SXEVF_MSGTYPE_AC= K))) { hw->mbx.api_version =3D api[idx]; break; - } else { - idx++; } + idx++; } =20 LOG_INFO_BDF("mailbox api version:%u", hw->mbx.api_version); =20 - return; } =20 s32 sxevf_ring_info_get(struct sxevf_adapter *adapter, @@ -433,7 +422,7 @@ s32 sxevf_ring_info_get(struct sxevf_adapter *adapter, =20 req.msg_type =3D SXEVF_RING_INFO_GET; ret =3D sxevf_send_and_rcv_msg(hw, (u32 *)&req, - SXEVF_MSG_NUM(sizeof(req))); + SXEVF_MSG_NUM(sizeof(req))); if (ret) { LOG_ERROR_BDF("msg:0x%x send or rcv reply failed.(err:%d)\n", req.msg_type, ret); @@ -451,23 +440,22 @@ s32 sxevf_ring_info_get(struct sxevf_adapter *adapter, req.max_tx_num, req.max_rx_num, req.tc_num, req.default_tc); =20 if ((req.max_tx_num =3D=3D 0) || - (req.max_tx_num > SXEVF_TXRX_RING_NUM_MAX)) { + (req.max_tx_num > SXEVF_TXRX_RING_NUM_MAX)) { req.max_tx_num =3D SXEVF_TXRX_RING_NUM_MAX; } =20 if ((req.max_rx_num =3D=3D 0) || - (req.max_rx_num > SXEVF_TXRX_RING_NUM_MAX)) { + (req.max_rx_num > SXEVF_TXRX_RING_NUM_MAX)) { req.max_rx_num =3D SXEVF_TXRX_RING_NUM_MAX; } =20 - if (req.tc_num > req.max_rx_num) { + if (req.tc_num > req.max_rx_num) req.tc_num =3D SXEVF_DEFAULT_TC_NUM; - } + *tc_num =3D req.tc_num; =20 - if (req.default_tc > req.max_tx_num) { + if (req.default_tc > req.max_tx_num) req.default_tc =3D 0; - } =20 *default_tc =3D req.default_tc; =20 @@ -491,7 +479,7 @@ s32 sxevf_rss_hash_config_get(struct sxevf_adapter *ada= pter, =20 msg.msg_type =3D SXEVF_RSS_CONF_GET; ret =3D sxevf_send_and_rcv_msg(hw, (u32 *)&msg, - SXEVF_MSG_NUM(sizeof(msg))); + SXEVF_MSG_NUM(sizeof(msg))); if (ret) { LOG_ERROR_BDF("msg:0x%x send or rcv reply failed.(err:%d)\n", msg.msg_type, ret); @@ -555,9 +543,9 @@ s32 sxevf_rx_max_frame_set(struct sxevf_hw *hw, u32 mtu) msg.max_frame =3D mtu; =20 ret =3D sxevf_send_and_rcv_msg(hw, (u32 *)&msg, - SXEVF_MSG_NUM(sizeof(msg))); + SXEVF_MSG_NUM(sizeof(msg))); if (ret || ((msg.msg_type & SXEVF_LPE_SET) && - (msg.msg_type & SXEVF_MSGTYPE_NACK))) { + (msg.msg_type & SXEVF_MSGTYPE_NACK))) { ret =3D ret ? ret : -SXEVF_ERR_MSG_HANDLE_ERR; } =20 @@ -580,14 +568,13 @@ s32 sxevf_vlan_id_set(struct sxevf_hw *hw, u32 vlan_i= d, =20 LOG_INFO_BDF("update vlan[%u], vlan on =3D %s\n", vlan_id, vlan_on ? "yes= " : "no"); ret =3D sxevf_send_and_rcv_msg(hw, (u32 *)&msg, - SXEVF_MSG_NUM(sizeof(msg))); - LOG_INFO_BDF("update vlan[%u] ret =3D %d\n",vlan_id, ret); + SXEVF_MSG_NUM(sizeof(msg))); + LOG_INFO_BDF("update vlan[%u] ret =3D %d\n", vlan_id, ret); =20 msg.msg_type &=3D ~(0xFF << SXEVF_MSGINFO_SHIFT); =20 - if (ret || (msg.msg_type !=3D (SXEVF_VLAN_SET | SXEVF_MSGTYPE_ACK))) { + if (ret || (msg.msg_type !=3D (SXEVF_VLAN_SET | SXEVF_MSGTYPE_ACK))) ret =3D ret ? ret : -SXEVF_ERR_MSG_HANDLE_ERR; - } =20 return ret; } @@ -602,9 +589,8 @@ s32 sxevf_cast_mode_set(struct sxevf_hw *hw, enum sxevf= _cast_mode mode) msg.cast_mode =3D mode; =20 ret =3D sxevf_send_and_rcv_msg(hw, (u32 *)&msg, SXEVF_MSG_NUM(sizeof(msg)= )); - if (ret || (msg.msg_type !=3D (SXEVF_CAST_MODE_SET | SXEVF_MSGTYPE_ACK)))= { + if (ret || (msg.msg_type !=3D (SXEVF_CAST_MODE_SET | SXEVF_MSGTYPE_ACK))) ret =3D ret ? ret : -SXEVF_ERR_MSG_HANDLE_ERR; - } =20 LOG_INFO_BDF("msg_type:0x%x mode:0x%x msg result:0x%x.(ret:%d)\n", msg.msg_type, mode, msg.msg_type, ret); @@ -624,16 +610,14 @@ s32 sxevf_uc_addr_add(struct sxevf_hw *hw, u32 index,= u8 *mac_addr) msg.index =3D index; check =3D *(u32 *)&msg; =20 - if (mac_addr) { + if (mac_addr) memcpy((u8 *)&msg.addr, mac_addr, SXEVF_MAC_ADDR_LEN); - } =20 ret =3D sxevf_send_and_rcv_msg(hw, (u32 *)&msg, SXEVF_MSG_NUM(sizeof(msg)= )); result =3D *(u32 *)&msg; =20 - if (ret || (result !=3D (check | SXEVF_MSGTYPE_ACK))) { + if (ret || (result !=3D (check | SXEVF_MSGTYPE_ACK))) ret =3D ret ? ret : -SXEVF_ERR_MSG_HANDLE_ERR; - } =20 LOG_INFO_BDF("msg_type:0x%x index:%d addr:%pM sync done " " result:0x%x msg.(ret:%d)\n", diff --git a/drivers/net/sxe/vf/sxevf_msg.h b/drivers/net/sxe/vf/sxevf_msg.h index c3e22d7785..aeca7b4bef 100644 --- a/drivers/net/sxe/vf/sxevf_msg.h +++ b/drivers/net/sxe/vf/sxevf_msg.h @@ -11,53 +11,53 @@ struct sxevf_adapter; #define SXEVF_UC_ENTRY_NUM_MAX 10 #define SXEVF_MC_ENTRY_NUM_MAX 30 =20 -#define SXEVF_MBX_MSG_NUM 16 +#define SXEVF_MBX_MSG_NUM 16 #define SXEVF_MBX_RETRY_INTERVAL 500 -#define SXEVF_MBX_RETRY_COUNT 2000 +#define SXEVF_MBX_RETRY_COUNT 2000 =20 -#define SXEVF_RST_CHECK_NUM 200 +#define SXEVF_RST_CHECK_NUM 200 =20 -#define SXEVF_DEFAULT_ADDR_LEN 4 -#define SXEVF_MC_FILTER_TYPE_WORD 3 +#define SXEVF_DEFAULT_ADDR_LEN 4 +#define SXEVF_MC_FILTER_TYPE_WORD 3 =20 -#define SXEVF_RESET 0x01=20 -#define SXEVF_DEV_MAC_ADDR_SET 0x02=20 -#define SXEVF_MC_ADDR_SYNC 0x03=20 -#define SXEVF_VLAN_SET 0x04=20 -#define SXEVF_LPE_SET 0x05=20=20 +#define SXEVF_RESET 0x01 +#define SXEVF_DEV_MAC_ADDR_SET 0x02 +#define SXEVF_MC_ADDR_SYNC 0x03 +#define SXEVF_VLAN_SET 0x04 +#define SXEVF_LPE_SET 0x05 =20 -#define SXEVF_UC_ADDR_SYNC 0x06=20=20 +#define SXEVF_UC_ADDR_SYNC 0x06 =20 -#define SXEVF_API_NEGOTIATE 0x08=20=20 +#define SXEVF_API_NEGOTIATE 0x08 =20 -#define SXEVF_RING_INFO_GET 0x09=20=20 +#define SXEVF_RING_INFO_GET 0x09 =20 -#define SXEVF_REDIR_TBL_GET 0x0a=20 -#define SXEVF_RSS_KEY_GET 0x0b=20 -#define SXEVF_CAST_MODE_SET 0x0c=20 -#define SXEVF_LINK_ENABLE_GET 0X0d=20=20 -#define SXEVF_IPSEC_ADD 0x0e=20 -#define SXEVF_IPSEC_DEL 0x0f=20 -#define SXEVF_RSS_CONF_GET 0x10=20 +#define SXEVF_REDIR_TBL_GET 0x0a +#define SXEVF_RSS_KEY_GET 0x0b +#define SXEVF_CAST_MODE_SET 0x0c +#define SXEVF_LINK_ENABLE_GET 0X0d +#define SXEVF_IPSEC_ADD 0x0e +#define SXEVF_IPSEC_DEL 0x0f +#define SXEVF_RSS_CONF_GET 0x10 =20 #define SXEVF_PF_CTRL_MSG_LINK_UPDATE 0x100 #define SXEVF_PF_CTRL_MSG_NETDEV_DOWN 0x200 =20 -#define SXEVF_PF_CTRL_MSG_REINIT 0x400 +#define SXEVF_PF_CTRL_MSG_REINIT 0x400 =20 -#define SXEVF_PF_CTRL_MSG_MASK 0x700 -#define SXEVF_PFREQ_MASK 0xFF00=20 +#define SXEVF_PF_CTRL_MSG_MASK 0x700 +#define SXEVF_PFREQ_MASK 0xFF00 =20 -#define SXEVF_RSS_HASH_KEY_SIZE (40)=20=20 -#define SXEVF_MAX_RETA_ENTRIES (128)=20 +#define SXEVF_RSS_HASH_KEY_SIZE (40) +#define SXEVF_MAX_RETA_ENTRIES (128) #define SXEVF_RETA_ENTRIES_DWORDS (SXEVF_MAX_RETA_ENTRIES / 16) =20 -#define SXEVF_TX_QUEUES 1=20 -#define SXEVF_RX_QUEUES 2=20 -#define SXEVF_TRANS_VLAN 3=20 -#define SXEVF_DEF_QUEUE 4=20 +#define SXEVF_TX_QUEUES 1 +#define SXEVF_RX_QUEUES 2 +#define SXEVF_TRANS_VLAN 3 +#define SXEVF_DEF_QUEUE 4 =20 -#define SXEVF_MSGTYPE_ACK 0x80000000 +#define SXEVF_MSGTYPE_ACK 0x80000000 #define SXEVF_MSGTYPE_NACK 0x40000000 =20 #define SXEVF_MSGINFO_SHIFT 16 @@ -69,17 +69,17 @@ enum sxevf_mbx_api_version { SXEVF_MBX_API_10 =3D 0, SXEVF_MBX_API_11, SXEVF_MBX_API_12, - SXEVF_MBX_API_13,=20 - SXEVF_MBX_API_14,=20 + SXEVF_MBX_API_13, + SXEVF_MBX_API_14, =20 - SXEVF_MBX_API_NR,=20 + SXEVF_MBX_API_NR, }; =20 enum sxevf_cast_mode { - SXEVF_CAST_MODE_NONE =3D 0,=20 - SXEVF_CAST_MODE_MULTI,=20=20=20=20 - SXEVF_CAST_MODE_ALLMULTI,=20 - SXEVF_CAST_MODE_PROMISC,=20=20 + SXEVF_CAST_MODE_NONE =3D 0, + SXEVF_CAST_MODE_MULTI, + SXEVF_CAST_MODE_ALLMULTI, + SXEVF_CAST_MODE_PROMISC, }; =20 struct sxevf_rst_msg { @@ -198,4 +198,4 @@ s32 sxevf_uc_addr_add(struct sxevf_hw *hw, u32 index, u= 8 *mac_addr); =20 s32 sxevf_ctrl_msg_rcv_and_clear(struct sxevf_hw *hw, u32 *msg, u16 msg_le= n); =20 -#endif=20 +#endif diff --git a/drivers/net/sxe/vf/sxevf_queue.c b/drivers/net/sxe/vf/sxevf_qu= eue.c index 5e7d9ec17d..15a2461e5f 100644 --- a/drivers/net/sxe/vf/sxevf_queue.c +++ b/drivers/net/sxe/vf/sxevf_queue.c @@ -36,7 +36,7 @@ s32 __rte_cold sxevf_rx_queue_setup(struct rte_eth_dev *d= ev, struct rte_mempool *mp) { struct sxevf_adapter *adapter =3D dev->data->dev_private; - struct sxevf_hw *hw =3D &adapter->hw; + struct sxevf_hw *hw =3D &adapter->hw; struct rx_setup rx_setup =3D {}; s32 ret; =20 @@ -52,9 +52,8 @@ s32 __rte_cold sxevf_rx_queue_setup(struct rte_eth_dev *d= ev, rx_setup.rx_batch_alloc_allowed =3D &adapter->rx_batch_alloc_allowed; =20 ret =3D __sxe_rx_queue_setup(&rx_setup, true); - if (ret) { + if (ret) LOG_ERROR_BDF("rx queue setup fail.(err:%d)", ret); - } =20 return ret; } @@ -77,9 +76,8 @@ s32 __rte_cold sxevf_tx_queue_setup(struct rte_eth_dev *d= ev, tx_setup.tx_conf =3D tx_conf; =20 ret =3D __sxe_tx_queue_setup(&tx_setup, true); - if (ret) { + if (ret) PMD_LOG_ERR(DRV, "rx queue setup fail.(err:%d)", ret); - } =20 return ret; } @@ -93,7 +91,6 @@ void __rte_cold sxevf_rx_queue_release(void *rxq) void __rte_cold sxevf_tx_queue_release(void *txq) { __sxe_tx_queue_free(txq); - return; } =20 #else @@ -107,7 +104,6 @@ void __rte_cold sxevf_tx_queue_release(struct rte_eth_dev *dev, u16 queue_id) { __sxe_tx_queue_free(dev->data->tx_queues[queue_id]); - return; } #endif =20 @@ -116,7 +112,6 @@ void sxevf_rx_queue_info_get(struct rte_eth_dev *dev, u= 16 queue_id, { __sxe_rx_queue_info_get(dev, queue_id, qinfo); =20 - return; } =20 void sxevf_tx_queue_info_get(struct rte_eth_dev *dev, u16 queue_id, @@ -124,7 +119,6 @@ void sxevf_tx_queue_info_get(struct rte_eth_dev *dev, u= 16 queue_id, { __sxe_tx_queue_info_get(dev, queue_id, q_info); =20 - return; } =20 s32 sxevf_tx_done_cleanup(void *tx_queue, u32 free_cnt) @@ -133,9 +127,8 @@ s32 sxevf_tx_done_cleanup(void *tx_queue, u32 free_cnt) =20 /* Tx queue cleanup */ ret =3D __sxe_tx_done_cleanup(tx_queue, free_cnt); - if (ret) { + if (ret) PMD_LOG_ERR(DRV, "tx cleanup fail.(err:%d)", ret); - } =20 return ret; } @@ -183,7 +176,7 @@ s32 sxevf_rss_reta_query(struct rte_eth_dev *dev, } =20 s32 sxevf_rss_hash_conf_get(struct rte_eth_dev *dev, - struct rte_eth_rss_conf *rss_conf) + struct rte_eth_rss_conf *rss_conf) { s32 ret =3D 0; struct sxevf_adapter *adapter =3D dev->data->dev_private; @@ -217,20 +210,17 @@ void sxevf_secondary_proc_init(struct rte_eth_dev *et= h_dev) bool rx_vec_allowed =3D 0; =20 __sxe_secondary_proc_init(eth_dev, adapter->rx_batch_alloc_allowed, &rx_v= ec_allowed); - return; } =20 void __rte_cold sxevf_txrx_queues_clear(struct rte_eth_dev *dev, bool rx_b= atch_alloc_allowed) { __sxe_txrx_queues_clear(dev, rx_batch_alloc_allowed); - return; } =20 void sxevf_queues_free(struct rte_eth_dev *dev) { __sxe_queues_free(dev); =20 - return; } =20 #endif diff --git a/drivers/net/sxe/vf/sxevf_queue.h b/drivers/net/sxe/vf/sxevf_qu= eue.h index 1a061231a5..f22bdb6768 100644 --- a/drivers/net/sxe/vf/sxevf_queue.h +++ b/drivers/net/sxe/vf/sxevf_queue.h @@ -12,8 +12,8 @@ typedef union sxe_tx_data_desc sxevf_tx_data_desc_u; typedef struct sxe_rx_buffer sxevf_rx_buffer_s; typedef union sxe_rx_data_desc sxevf_rx_data_desc_u; -typedef struct sxe_tx_queue sxevf_tx_queue_s; -typedef struct sxe_rx_queue sxevf_rx_queue_s; +typedef struct sxe_tx_queue sxevf_tx_queue_s; +typedef struct sxe_rx_queue sxevf_rx_queue_s; =20 s32 __rte_cold sxevf_rx_queue_mbufs_alloc(sxevf_rx_queue_s *rxq); =20 @@ -56,7 +56,7 @@ s32 sxevf_rss_reta_query(struct rte_eth_dev *dev, u16 reta_size); =20 s32 sxevf_rss_hash_conf_get(struct rte_eth_dev *dev, - struct rte_eth_rss_conf *rss_conf); + struct rte_eth_rss_conf *rss_conf); =20 s32 sxevf_rss_hash_update(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_conf); @@ -69,7 +69,7 @@ s32 sxevf_rx_descriptor_done(void *rx_queue, u16 offset); =20 s32 sxevf_rx_descriptor_status(void *rx_queue, u16 offset); =20 -u16 sxevf_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts,u16 num_pkts= ); +u16 sxevf_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts, u16 num_pkt= s); =20 u16 sxevf_pkts_xmit_with_offload(void *tx_queue, struct rte_mbuf **tx_pkts= , u16 pkts_num); s32 sxevf_tx_descriptor_status(void *tx_queue, u16 offset); diff --git a/drivers/net/sxe/vf/sxevf_rx.c b/drivers/net/sxe/vf/sxevf_rx.c index 53b9168345..85ed9bffcb 100644 --- a/drivers/net/sxe/vf/sxevf_rx.c +++ b/drivers/net/sxe/vf/sxevf_rx.c @@ -32,7 +32,6 @@ static void sxevf_rss_bit_num_configure(struct sxevf_hw *= hw, u16 rx_queues_num) =20 sxevf_rss_bit_num_set(hw, psrtype); =20 - return; } =20 static void sxevf_rxmode_offload_configure(struct rte_eth_dev *eth_dev, @@ -42,22 +41,20 @@ static void sxevf_rxmode_offload_configure(struct rte_e= th_dev *eth_dev, u32 frame_size =3D SXE_GET_FRAME_SIZE(eth_dev); =20 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_SCATTER || - ((frame_size + 2 * SXEVF_VLAN_TAG_SIZE) > buf_size)) { + ((frame_size + 2 * SXEVF_VLAN_TAG_SIZE) > buf_size)) { if (!eth_dev->data->scattered_rx) { PMD_LOG_WARN(DRV, "rxmode offload:0x%"SXE_PRIX64" max_rx_pkt_len:%u " - "buf_size:%u enable rx scatter", - rxmode->offloads, - frame_size, - buf_size); + "buf_size:%u enable rx scatter", + rxmode->offloads, + frame_size, + buf_size); } eth_dev->data->scattered_rx =3D 1; } =20 - if (queue_offload & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { + if (queue_offload & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) rxmode->offloads |=3D RTE_ETH_RX_OFFLOAD_VLAN_STRIP; - } =20 - return; } =20 static s32 sxevf_rx_queue_configure(struct rte_eth_dev *eth_dev) @@ -79,8 +76,8 @@ static s32 sxevf_rx_queue_configure(struct rte_eth_dev *e= th_dev) ret =3D sxevf_rx_queue_mbufs_alloc(rxq); if (ret) { LOG_ERROR_BDF("rx queue num:%u queue id:%u alloc " - "rx buffer fail.(err:%d)", - eth_dev->data->nb_rx_queues, i, ret); + "rx buffer fail.(err:%d)", + eth_dev->data->nb_rx_queues, i, ret); goto l_out; } =20 @@ -130,14 +127,14 @@ s32 sxevf_rx_configure(struct rte_eth_dev *eth_dev) ret =3D sxevf_rx_max_frame_set(hw, mtu); if (ret) { LOG_ERROR_BDF("max frame size:%u set fail.(err:%d)", - frame_size, ret); + frame_size, ret); goto l_out; } =20 ret =3D sxevf_rx_queue_configure(eth_dev); if (ret) { LOG_ERROR_BDF("rx queue num:%u configure fail.(err:%u)", - eth_dev->data->nb_rx_queues, ret); + eth_dev->data->nb_rx_queues, ret); } =20 l_out: @@ -154,13 +151,12 @@ void __rte_cold sxevf_rx_function_set(struct rte_eth_= dev *dev) __sxe_rx_function_set(dev, adapter->rx_batch_alloc_allowed, NULL); #endif =20 - return;=20 } =20 #if defined DPDK_20_11_5 || defined DPDK_19_11_6 s32 sxevf_rx_descriptor_done(void *rx_queue, u16 offset) { - return __sxe_rx_descriptor_done(rx_queue,offset); + return __sxe_rx_descriptor_done(rx_queue, offset); } #endif =20 @@ -169,7 +165,7 @@ s32 sxevf_rx_descriptor_status(void *rx_queue, u16 offs= et) return __sxe_rx_descriptor_status(rx_queue, offset); } =20 -u16 sxevf_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts,u16 num_pkts) +u16 sxevf_pkts_recv(void *rx_queue, struct rte_mbuf **rx_pkts, u16 num_pkt= s) { return __sxe_pkts_recv(rx_queue, rx_pkts, num_pkts); } diff --git a/drivers/net/sxe/vf/sxevf_stats.c b/drivers/net/sxe/vf/sxevf_st= ats.c index f82ccf1fd7..007bd02887 100644 --- a/drivers/net/sxe/vf/sxevf_stats.c +++ b/drivers/net/sxe/vf/sxevf_stats.c @@ -16,14 +16,14 @@ #endif =20 #define SXE_HW_XSTATS_CNT (sizeof(sxevf_xstats_field) / \ - sizeof(sxevf_xstats_field[0])) + sizeof(sxevf_xstats_field[0])) =20 static const struct sxevf_stats_field sxevf_xstats_field[] =3D { {"rx_multicast_packets", offsetof(struct sxevf_hw_stats, vfmprc)}, }; =20 #ifdef SXE_TEST -STATIC u32 sxevf_xstats_cnt_get(void) +static u32 sxevf_xstats_cnt_get(void) { return SXE_HW_XSTATS_CNT; } @@ -80,7 +80,7 @@ static s32 sxevf_hw_xstat_offset_get(u32 id, u32 *offset) } else { ret =3D -SXE_ERR_PARAM; PMD_LOG_ERR(DRV, "invalid id:%u exceed stats size cnt:%u.", - id, size); + id, size); } =20 return ret; @@ -100,13 +100,13 @@ s32 sxevf_xstats_get(struct rte_eth_dev *eth_dev, =20 cnt =3D SXE_HW_XSTATS_CNT; PMD_LOG_INFO(DRV, "xstat size:%u. hw xstat field cnt:%lu ", - cnt, - SXE_HW_XSTATS_CNT); + cnt, + SXE_HW_XSTATS_CNT); =20 if (usr_cnt < cnt) { ret =3D cnt; PMD_LOG_ERR(DRV, "user usr_cnt:%u less than stats cnt:%u.", - usr_cnt, cnt); + usr_cnt, cnt); goto l_out; } =20 @@ -115,7 +115,7 @@ s32 sxevf_xstats_get(struct rte_eth_dev *eth_dev, if (xstats =3D=3D NULL) { ret =3D 0; PMD_LOG_ERR(DRV, "usr_cnt:%u, input param xstats is null.", - usr_cnt); + usr_cnt); goto l_out; } =20 diff --git a/drivers/net/sxe/vf/sxevf_tx.c b/drivers/net/sxe/vf/sxevf_tx.c index 667a165c64..3d80deee78 100644 --- a/drivers/net/sxe/vf/sxevf_tx.c +++ b/drivers/net/sxe/vf/sxevf_tx.c @@ -32,7 +32,6 @@ void sxevf_tx_configure(struct rte_eth_dev *eth_dev) LOG_DEBUG_BDF("tx queue num:%u tx configure done.", eth_dev->data->nb_tx_queues); =20 - return; } =20 s32 sxevf_tx_descriptor_status(void *tx_queue, u16 offset) --=20 2.45.2.windows.1