From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9196545955; Tue, 10 Sep 2024 13:10:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4077842E91; Tue, 10 Sep 2024 13:09:48 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by mails.dpdk.org (Postfix) with ESMTP id ABB9D42E4F for ; Tue, 10 Sep 2024 13:09:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725966587; x=1757502587; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SStyhKfnZINlB5EniA9UNZNd0NlerT5J8vWuJaI7XAU=; b=ezrfV+1LBTnfSAhZSu6Terq7LMLEy9GP4a1ixm6jdflcLsQ/TI6/aWEV lr4gcPK/A1JpezPnMQ8aP6QYr8Mvk490hElvOZ9NrgrYKHBRtz5HJgW67 OtoDkOOqKbttM+pNUgH0k90dakoD7Mg25WfMVJ4VdO0J8y047W7YEAx/k vRE/dutLqpgZJkpFGo0Cychhr7faKWwCk/hK36krup851Dbqf8+sS4B6M oZFxanc4AKy++lsr+TmoH9dxr+i+AsPgm/4a4mhWHsYrbE8jVnhnIgRKi nwAHGcrglB/RiaRww2vjfamV0Rv/mhrGiT7PNMh4IBEGQ+xD7S75//oa1 g==; X-CSE-ConnectionGUID: 8yu4CgWwRqOzZ7iJelWf5Q== X-CSE-MsgGUID: t7cD1WRuQS+YbJT9k83D3g== X-IronPort-AV: E=McAfee;i="6700,10204,11190"; a="35276931" X-IronPort-AV: E=Sophos;i="6.10,217,1719903600"; d="scan'208";a="35276931" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2024 04:09:47 -0700 X-CSE-ConnectionGUID: CMkP9JOMRZ+xta8hDD4QpA== X-CSE-MsgGUID: 7FC1EhgRQJSHV2EqhjBGkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,217,1719903600"; d="scan'208";a="71969857" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa004.jf.intel.com with ESMTP; 10 Sep 2024 04:09:45 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com, Julian Grajkowski Subject: [PATCH v1 7/9] common/iavf: add RefSync support Date: Tue, 10 Sep 2024 10:12:22 +0000 Message-ID: <20240910101224.497044-8-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240910101224.497044-1-soumyadeep.hore@intel.com> References: <20240910101224.497044-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Julian Grajkowski Update virtchnl to reflect RefSync implementation. Reading and modifying DPLL input pin configuration, including Esync/RefSync option, is possible on VM using sysfs. The request is passed from the VM via virtchnl message to the host driver and results in an admin command being sent to FW. Before the change only Esync enable/disable option was supported and it used bit 6, but this change introduces support for RefSync option, so there are now 3 possible values - Esync disabled (0), Esync enabled (1) and RefSync enabled (2). The change updates description of relevant virtchnl messages, but leaves the previous description of bit 6 for backward compatibility, so that when RefSync is not supported this bit may still be used for Esync enable/disable only. Signed-off-by: Julian Grajkowski Signed-off-by: Soumyadeep Hore --- drivers/common/iavf/virtchnl.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index ae6770adaf..2d88b83932 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -2320,6 +2320,12 @@ struct virtchnl_synce_get_input_pin_cfg { u8 flags2; #define VIRTCHNL_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) #define VIRTCHNL_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) +#define VIRTCHNL_GET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN_SHIFT 6 +#define VIRTHCNL_GET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN \ + MAKEMASK(0x3, VIRTCHNL_GET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN_SHIFT) +#define VIRTCHNL_GET_CGU_IN_CFG_ESYNC_DIS 0 +#define VIRTCHNL_GET_CGU_IN_CFG_ESYNC_EN 1 +#define VIRTCHNL_GET_CGU_IN_CFG_REFSYNC_EN 2 u8 rsvd[3]; }; @@ -2335,6 +2341,12 @@ struct virtchnl_synce_set_input_pin_cfg { u8 flags2; #define VIRTCHNL_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) #define VIRTCHNL_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) +#define VIRTCHNL_SET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN_SHIFT 6 +#define VIRTCHNL_SET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN \ + MAKEMASK(0x3, ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_REFSYNC_EN_SHIFT) +#define VIRTCHNL_SET_CGU_IN_CFG_ESYNC_DIS 0 +#define VIRTCHNL_SET_CGU_IN_CFG_ESYNC_EN 1 +#define VIRTCHNL_SET_CGU_IN_CFG_REFSYNC_EN 2 u8 rsvd[5]; }; -- 2.34.1