From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0D78245955; Tue, 10 Sep 2024 13:10:29 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8581542ECE; Tue, 10 Sep 2024 13:09:50 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by mails.dpdk.org (Postfix) with ESMTP id BF14E42EBF for ; Tue, 10 Sep 2024 13:09:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725966589; x=1757502589; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=83DVW9D9Sg1QTnG+evSmYaXbVotgwPMYAYIsT2PUs7I=; b=bJwJ96oYOOUPqbrVeDF5STFUuGzo2TznjvOLDdQmJ05jfC4YdXCskJEL uKrmW+Z3uSCYF67xJPFg0jn66SY5KH1RVY3yJXtnJ4aZBYaGbH++u9f/t 79L4npzLioZchQIk0EUgy21YJdd2Yo1yQPahefrEa8Slfe6Yx+u1sNhJz Efyp8J/BS2fHY4sSFO9WxtzJbSoJDe/KonsIkzg6jJnFWCCaZcvLMGG4B 2D/mntm3ZaO+x+/YBqOYFUwsy5GQdYduTbsERv19YEiWwuYSWMZLj1cQk +Me7IcwCt1BtdPXlCPgAQfZsTcSXkbJyCPI2BncBbqPaK1ZZyQBNq1qOy A==; X-CSE-ConnectionGUID: piAlaecZRqK+9KzvVNoTUA== X-CSE-MsgGUID: EiHMggddS+eoj8D//J5xMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11190"; a="35276935" X-IronPort-AV: E=Sophos;i="6.10,217,1719903600"; d="scan'208";a="35276935" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2024 04:09:49 -0700 X-CSE-ConnectionGUID: ORpBhqm+RsSIIX3Sh4ZbhA== X-CSE-MsgGUID: VI1r04NZSzyv1HwOdQ9Czg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,217,1719903600"; d="scan'208";a="71969860" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa004.jf.intel.com with ESMTP; 10 Sep 2024 04:09:47 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, shaiq.wani@intel.com, Sudheer Mogilappagari Subject: [PATCH v1 8/9] common/iavf: introduce QGRP capabilities to replace ADQ caps Date: Tue, 10 Sep 2024 10:12:23 +0000 Message-ID: <20240910101224.497044-9-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240910101224.497044-1-soumyadeep.hore@intel.com> References: <20240910101224.497044-1-soumyadeep.hore@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sudheer Mogilappagari Currently VIRTCHNL_VF_OFFLOAD_ADQ cap is used for VF ADQ functionality with i40e PF and VIRTCHNL_VF_OFFLOAD_ADQ_V2 cap is used for functionality with ice PF. Above caps makes the IAVF code complicated with additional checks all around TC configuration and TC filter code. Also VF ADQ with i40e is not officially supported feature. The current ADQ and ADQ_V2 caps will be deprecated to simplify the code and QGRPS and FLOW_STEER_QGRP caps will be used to negotiate TC configuration and TC filter configuration capabilities. Also define VIRTCHNL_MAX_TC which will eventually replace VIRTCHNL_MAX_ADQ_V2_CHANNELS. Signed-off-by: Sudheer Mogilappagari Signed-off-by: Soumyadeep Hore --- drivers/common/iavf/virtchnl.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index 2d88b83932..92e323d741 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -479,6 +479,8 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource); #define VIRTCHNL_VF_OFFLOAD_INLINE_IPSEC_CRYPTO BIT(8) #define VIRTCHNL_VF_LARGE_NUM_QPAIRS BIT(9) #define VIRTCHNL_VF_OFFLOAD_CRC BIT(10) +#define VIRTCHNL_VF_OFFLOAD_QGRPS BIT(12) +#define VIRTCHNL_VF_OFFLOAD_FLOW_STEER_TO_QGRP BIT(13) #define VIRTCHNL_VF_OFFLOAD_FSUB_PF BIT(14) #define VIRTCHNL_VF_OFFLOAD_VLAN_V2 BIT(15) #define VIRTCHNL_VF_OFFLOAD_VLAN BIT(16) @@ -1303,6 +1305,8 @@ enum virtchnl_rss_algorithm { */ #define VIRTCHNL_MAX_ADQ_CHANNELS 4 #define VIRTCHNL_MAX_ADQ_V2_CHANNELS 16 +/* This is used by PF driver to enforce max supported channels */ +#define VIRTCHNL_MAX_QGRPS 16 /* VIRTCHNL_OP_ENABLE_CHANNELS * VIRTCHNL_OP_DISABLE_CHANNELS -- 2.34.1