From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 35FE6459BC; Tue, 17 Sep 2024 11:46:47 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AED5640BA2; Tue, 17 Sep 2024 11:46:16 +0200 (CEST) Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2043.outbound.protection.outlook.com [40.107.20.43]) by mails.dpdk.org (Postfix) with ESMTP id 26AF640A77 for ; Tue, 17 Sep 2024 11:46:14 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=rlExKWUNt7iLswy8Z23JpErlM1EoPuWmA/5PlYBQ2HDVelx+XNXMRpAkHkas4TrEMpqf54SgCAzdDuFxLBGY/Dh36WjHPzsXyhisf2tg3JAlStRB9CCSTEovcZOVT5hZtSR2lG2QT5LTq00ehFzIcvjfnTytt9cP4eLjL0VQROnRJSfag388T/PYCYYrbIHcq2pAkzjIZ/oIhnBeFCfwh1ij3URLZJAPOaHYPZl1jddMa73/GenouZFM9RqW3l2wP6V2wP4rNhcsFlB4Uz/LXjvL3gFMugdAqwqHIJU2OI9WFqng6qTmfm6KdRvHBkhoYGoaNrd4hXb6WA0n57eF7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5UKgQdVaciDeShGgGbM6oo5b5b9ozFm128R5ONKGWa0=; b=mugSFVbwOnvtgwCESZPFxCilCuVSc19ysWPQMde0npwQ3umFH34XYJgDR5f0gZ2//WsCPpfAlBhLyVIqsJGKTP9+Vd9okur8bPPVSLcOB/Wq46qTmgC06GJs5tCNG+0UgdWXd/wKsy72IbzMu+wfJfwuvs9iqoI5Ry0/F70pyS1JCLgLYFCYg9bL/O7diyqwS/UbchgBgFkyU6GeS55Fi6sBwtlApxRJNw8MjDgf0rMW3eEHn6TIlCPa0Cm6CvI5T56wjrNDCoTz4Hyca3ESdyjXDAjbM4M35Nc8LHCFqxmPkdyWpd0+VSyqz2YVV9C3nMDkaPgrykX/ok9W3Vfkjg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 192.176.1.74) smtp.rcpttodomain=dpdk.org smtp.mailfrom=ericsson.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=ericsson.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5UKgQdVaciDeShGgGbM6oo5b5b9ozFm128R5ONKGWa0=; b=jh5tEPTPPOA4oSbAfeEKd++dFk5NzhpkPyHEGdILpf85E3tCB/ApPWgCdgdPIaWOShOq+x2dD5Omw3usTJiJ9n2sQ6wD6GEk+3wmQZbbDMsB/0M1fx6QCHaSwFg3AwuX+Nei9jbepc63OQ+LNsS22P1P02oVpYxTMPKxCjpekj8I79hfqmZBjyAbQb7KmCeCX3ZU12FmKtSbAe3+U2OYRHJ1CSD1dNlhuOHPgIZwGOJSN57LuP4yTUAy6cxavaOskwYXKHya6egauLkiR+MXqkd6uqybNX10rle510MM50YjTQ3eWObz9Lfya8z2SBPAFLE9SAYnGZ4JnhNLMj/i8A== Received: from DUZPR01CA0074.eurprd01.prod.exchangelabs.com (2603:10a6:10:3c2::20) by PA4PR07MB7167.eurprd07.prod.outlook.com (2603:10a6:102:f7::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7962.22; Tue, 17 Sep 2024 09:46:12 +0000 Received: from DU6PEPF00009525.eurprd02.prod.outlook.com (2603:10a6:10:3c2:cafe::3) by DUZPR01CA0074.outlook.office365.com (2603:10a6:10:3c2::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.30 via Frontend Transport; Tue, 17 Sep 2024 09:46:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 192.176.1.74) smtp.mailfrom=ericsson.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=ericsson.com; Received-SPF: Pass (protection.outlook.com: domain of ericsson.com designates 192.176.1.74 as permitted sender) receiver=protection.outlook.com; client-ip=192.176.1.74; helo=oa.msg.ericsson.com; pr=C Received: from oa.msg.ericsson.com (192.176.1.74) by DU6PEPF00009525.mail.protection.outlook.com (10.167.8.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7918.13 via Frontend Transport; Tue, 17 Sep 2024 09:46:11 +0000 Received: from seliicinfr00050.seli.gic.ericsson.se (153.88.142.248) by smtp-central.internal.ericsson.com (100.87.178.62) with Microsoft SMTP Server id 15.2.1544.11; Tue, 17 Sep 2024 11:46:04 +0200 Received: from breslau.. (seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00050.seli.gic.ericsson.se (Postfix) with ESMTP id 6826B1C006A; Tue, 17 Sep 2024 11:46:04 +0200 (CEST) From: =?UTF-8?q?Mattias=20R=C3=B6nnblom?= To: CC: , Heng Wang , "Stephen Hemminger" , Tyler Retzlaff , =?UTF-8?q?Morten=20Br=C3=B8rup?= , Jack Bond-Preston , David Marchand , Chengwen Feng , =?UTF-8?q?Mattias=20R=C3=B6nnblom?= Subject: [PATCH v7 2/6] eal: extend bit manipulation functionality Date: Tue, 17 Sep 2024 11:36:42 +0200 Message-ID: <20240917093646.723777-3-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240917093646.723777-1-mattias.ronnblom@ericsson.com> References: <20240809201440.590464-1-mattias.ronnblom@ericsson.com> <20240917093646.723777-1-mattias.ronnblom@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU6PEPF00009525:EE_|PA4PR07MB7167:EE_ X-MS-Office365-Filtering-Correlation-Id: 8bf494e3-f82d-4d9d-2947-08dcd6fd908e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?U3l0NWFtcVdiU2NvZnhVWldEN1l1N2VweStyTFgxeDlobzBZbHJWbTYzQmVY?= =?utf-8?B?dGt0VGYyblRkMDBiZ1hpQmFESkFRYXhJd2Jzcit5UmtyR212RDFxRi85bGds?= =?utf-8?B?V1pTQ0JTOUdFQVZSQzg0bkkzM0pLSFpzeEdQUHh6T1MwL1FidTNXR2RKZDNm?= =?utf-8?B?SHZERjJCOHVFME9qbmV2RWliVHBEWVJDZVAxQUxReWpMU2JxekJaMTdpU2tO?= =?utf-8?B?Vnk4dVhmUDZDck1aa1krOUhFSlJRa1Z4Z3NaVmhaNVRmL2RoVFE4WFl5ZW1G?= =?utf-8?B?d2kydTBaQVV2L0ZnaXB4aXVpTEozL2I0WmI5S1BmUExybWoyOVZZNC9zekhl?= =?utf-8?B?UlBCQ1hMVWNIUmpHZzZtdXNMZDhYNWNpd0U1Y3NFSlhrWTRrVzA4RXVCZWxL?= =?utf-8?B?WWllbWpuYTBiR3QzVFUvSS84U1ZHb1laeXlad1ZwWUxDUFZJZHU3cUhjZm80?= =?utf-8?B?ZDBMVlZINUFoRGF6M3l1QTNYWUlXUkE2MzI1eEQydU5rN2liek5BNm1JVGxr?= =?utf-8?B?ait4WHNTbWk1UUpZTlhaSjRYNnB5bHA4WUtoYkx3c09xMGkyV2hMUzVHdFRS?= =?utf-8?B?T0gyOWVjQUZsb0o3WEIzV24rSHg3d1VoQkZBS3BIYTFpb0t6THQzWHNtR0Nw?= =?utf-8?B?YjlxQ2pZYXRRbkRYcStuekxpMFR1dURNcitTOVBQM0kyMHhrVlNpblJKb2x6?= =?utf-8?B?REVMVzg2Yno4V04zTXNlOVoycHVlN1I1dmhJSUVNR05CVWU2a21jZnJrTWV0?= =?utf-8?B?U0lQVDNDb00valZGZjFuSEpUM1p1Mng1MlVVRkEyamdSUEQxamR3SGRRNEhK?= =?utf-8?B?VXFnOUhaU2JSM0dLL1hlZ05lWGxyQWZpZHF0WUJQMjEyUTBhbnNuV3V1Wkdp?= =?utf-8?B?N2NFK1BzWVFOQWlTbCtBUktSUmJuNmw2UFowZXdOdlduMTRieEZzSGtRcTVC?= =?utf-8?B?bWlhdlVFbFNmZHpuSVFScmJuQmRQNkd5VTNBT2kydEFvampqR0NFVFU2cmxG?= =?utf-8?B?MWhWTmxEaUJxMFBxKzFZMmhvTlA4elg0TGcrWVhSVmlRUG1JbW93ZzFVVTA4?= =?utf-8?B?dWFXY2FyRzFlVlU0U1kyWUZBYWo5YXNxUExxVkVFQkhYSGg3R0MyTmlnRkNi?= =?utf-8?B?ZFpnUnVFaERwY1hydktTclYrenVZeFExRTlaSXp2eTRKaDlwUlVMbEk2RWYy?= =?utf-8?B?Zml2Mm1pRXBiYWhXZWVqZnRKUy9URjJYYThOamFKdkpSd2xmNS9TZkVac09D?= =?utf-8?B?OFIxdzFlU2F2dXV4NjFGWFpMRFk4cXUxOVpyVnlWUVNld2NiNWVibmtEdDRV?= =?utf-8?B?dkNDMk1QWitlSk1tNXBtUXNoUkVwUktkOFI2SmRiempqcHFXK2UwWEJpVXhO?= =?utf-8?B?a2djWDYxQ1BaQXNOeTgyMW16TnU0T0svVHN6NGJZYzFmTWk3RHIwNDlrTFhy?= =?utf-8?B?VjRycHZBcjZlY251ZmpYYWJhaDQyRENaR2hHUVU5a09MWDU4bVE1eHp5cDZp?= =?utf-8?B?R0tTdlpYMnFCUkxUQS9jeFdGVHUvNVRHajZWWUY3eEI4UnZmckw1dTJ6VFc0?= =?utf-8?B?Z3VTeDNnYXRhdWlHS2xUQW85WVZCaFZRWVVKTkR1UTYvTHFUYklVUGZSL0pk?= =?utf-8?B?NHQ0MFhtekRWakJwNTFLVTEzcndUOXZXMWZEVGNBbjlKZjVDRUx0aW5uN1VW?= =?utf-8?B?MTYwSTJpZ2t1SW9aRWVFU1JxS1ZIa1J6d1UwMzZUSkhJSWo5Qk05MW90aitw?= =?utf-8?B?RHI3Zmk5Rzc2OCtvWTZXZDJXWXQvK2d0QTdRMHY1T2dqWURIUHgzdndtd2I0?= =?utf-8?B?eVMwd2o5bDhnUXMrSmVkTWRrYTNaM053dDJPWTJ2azRpUHJjRmlZaldHNmdt?= =?utf-8?Q?SObowMdiARD1f?= X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2024 09:46:11.9292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8bf494e3-f82d-4d9d-2947-08dcd6fd908e X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF00009525.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR07MB7167 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add functionality to test and modify the value of individual bits in 32-bit or 64-bit words. These functions have no implications on memory ordering, atomicity and does not use volatile and thus does not prevent any compiler optimizations. Signed-off-by: Mattias Rönnblom Acked-by: Morten Brørup Acked-by: Tyler Retzlaff Acked-by: Jack Bond-Preston -- PATCH v3: * Remove unnecessary include. * Remove redundant 'fun' parameter from the __RTE_GEN_BIT_*() macros (Jack Bond-Preston). * Introduce __RTE_BIT_BIT_OPS() macro, consistent with how things are done when generating the atomic bit operations. * Refer to volatile bit op functions as variants instead of families (macro parameter naming). RFC v6: * Have rte_bit_test() accept const-marked bitsets. RFC v4: * Add rte_bit_flip() which, believe it or not, flips the value of a bit. * Mark macro-generated private functions as experimental. * Use macros to generate *assign*() functions. RFC v3: * Work around lack of C++ support for _Generic (Tyler Retzlaff). * Fix ','-related checkpatch warnings. --- lib/eal/include/rte_bitops.h | 260 ++++++++++++++++++++++++++++++++++- 1 file changed, 258 insertions(+), 2 deletions(-) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 449565eeae..6915b945ba 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -2,6 +2,7 @@ * Copyright(c) 2020 Arm Limited * Copyright(c) 2010-2019 Intel Corporation * Copyright(c) 2023 Microsoft Corporation + * Copyright(c) 2024 Ericsson AB */ #ifndef _RTE_BITOPS_H_ @@ -11,12 +12,14 @@ * @file * Bit Operations * - * This file defines a family of APIs for bit operations - * without enforcing memory ordering. + * This file provides functionality for low-level, single-word + * arithmetic and bit-level operations, such as counting or + * setting individual bits. */ #include +#include #include #ifdef __cplusplus @@ -105,6 +108,197 @@ extern "C" { #define RTE_FIELD_GET64(mask, reg) \ ((typeof(mask))(((reg) & (mask)) >> rte_ctz64(mask))) +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Test bit in word. + * + * Generic selection macro to test the value of a bit in a 32-bit or + * 64-bit word. The type of operation depends on the type of the @c + * addr parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_test(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_test32, \ + const uint32_t *: __rte_bit_test32, \ + uint64_t *: __rte_bit_test64, \ + const uint64_t *: __rte_bit_test64)(addr, nr) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Set bit in word. + * + * Generic selection macro to set a bit in a 32-bit or 64-bit + * word. The type of operation depends on the type of the @c addr + * parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_set(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_set32, \ + uint64_t *: __rte_bit_set64)(addr, nr) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Clear bit in word. + * + * Generic selection macro to clear a bit in a 32-bit or 64-bit + * word. The type of operation depends on the type of the @c addr + * parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_clear(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_clear32, \ + uint64_t *: __rte_bit_clear64)(addr, nr) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Assign a value to a bit in word. + * + * Generic selection macro to assign a value to a bit in a 32-bit or 64-bit + * word. The type of operation depends on the type of the @c addr parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + * @param value + * The new value of the bit - true for '1', or false for '0'. + */ +#define rte_bit_assign(addr, nr, value) \ + _Generic((addr), \ + uint32_t *: __rte_bit_assign32, \ + uint64_t *: __rte_bit_assign64)(addr, nr, value) + +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Flip a bit in word. + * + * Generic selection macro to change the value of a bit to '0' if '1' + * or '1' if '0' in a 32-bit or 64-bit word. The type of operation + * depends on the type of the @c addr parameter. + * + * This macro does not give any guarantees in regards to memory + * ordering or atomicity. + * + * @param addr + * A pointer to the word to modify. + * @param nr + * The index of the bit. + */ +#define rte_bit_flip(addr, nr) \ + _Generic((addr), \ + uint32_t *: __rte_bit_flip32, \ + uint64_t *: __rte_bit_flip64)(addr, nr) + +#define __RTE_GEN_BIT_TEST(variant, qualifier, size) \ + __rte_experimental \ + static inline bool \ + __rte_bit_ ## variant ## test ## size(const qualifier uint ## size ## _t *addr, \ + unsigned int nr) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + return *addr & mask; \ + } + +#define __RTE_GEN_BIT_SET(variant, qualifier, size) \ + __rte_experimental \ + static inline void \ + __rte_bit_ ## variant ## set ## size(qualifier uint ## size ## _t *addr, \ + unsigned int nr) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = (uint ## size ## _t)1 << nr; \ + *addr |= mask; \ + } \ + +#define __RTE_GEN_BIT_CLEAR(variant, qualifier, size) \ + __rte_experimental \ + static inline void \ + __rte_bit_ ## variant ## clear ## size(qualifier uint ## size ## _t *addr, \ + unsigned int nr) \ + { \ + RTE_ASSERT(nr < size); \ + \ + uint ## size ## _t mask = ~((uint ## size ## _t)1 << nr); \ + (*addr) &= mask; \ + } \ + +#define __RTE_GEN_BIT_ASSIGN(variant, qualifier, size) \ + __rte_experimental \ + static inline void \ + __rte_bit_ ## variant ## assign ## size(qualifier uint ## size ## _t *addr, \ + unsigned int nr, bool value) \ + { \ + if (value) \ + __rte_bit_ ## variant ## set ## size(addr, nr); \ + else \ + __rte_bit_ ## variant ## clear ## size(addr, nr); \ + } + +#define __RTE_GEN_BIT_FLIP(variant, qualifier, size) \ + __rte_experimental \ + static inline void \ + __rte_bit_ ## variant ## flip ## size(qualifier uint ## size ## _t *addr, \ + unsigned int nr) \ + { \ + bool value; \ + \ + value = __rte_bit_ ## variant ## test ## size(addr, nr); \ + __rte_bit_ ## variant ## assign ## size(addr, nr, !value); \ + } + +#define __RTE_GEN_BIT_OPS(v, qualifier, size) \ + __RTE_GEN_BIT_TEST(v, qualifier, size) \ + __RTE_GEN_BIT_SET(v, qualifier, size) \ + __RTE_GEN_BIT_CLEAR(v, qualifier, size) \ + __RTE_GEN_BIT_ASSIGN(v, qualifier, size) \ + __RTE_GEN_BIT_FLIP(v, qualifier, size) + +#define __RTE_GEN_BIT_OPS_SIZE(size) \ + __RTE_GEN_BIT_OPS(,, size) + +__RTE_GEN_BIT_OPS_SIZE(32) +__RTE_GEN_BIT_OPS_SIZE(64) + /*------------------------ 32-bit relaxed operations ------------------------*/ /** @@ -787,6 +981,68 @@ rte_log2_u64(uint64_t v) #ifdef __cplusplus } + +/* + * Since C++ doesn't support generic selection (i.e., _Generic), + * function overloading is used instead. Such functions must be + * defined outside 'extern "C"' to be accepted by the compiler. + */ + +#undef rte_bit_test +#undef rte_bit_set +#undef rte_bit_clear +#undef rte_bit_assign +#undef rte_bit_flip + +#define __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, size, arg1_type, arg1_name) \ + static inline void \ + rte_bit_ ## fun(qualifier uint ## size ## _t *addr, \ + arg1_type arg1_name) \ + { \ + __rte_bit_ ## fun ## size(addr, arg1_name); \ + } + +#define __RTE_BIT_OVERLOAD_2(fun, qualifier, arg1_type, arg1_name) \ + __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, 32, arg1_type, arg1_name) \ + __RTE_BIT_OVERLOAD_SZ_2(fun, qualifier, 64, arg1_type, arg1_name) + +#define __RTE_BIT_OVERLOAD_SZ_2R(fun, qualifier, size, ret_type, arg1_type, \ + arg1_name) \ + static inline ret_type \ + rte_bit_ ## fun(qualifier uint ## size ## _t *addr, \ + arg1_type arg1_name) \ + { \ + return __rte_bit_ ## fun ## size(addr, arg1_name); \ + } + +#define __RTE_BIT_OVERLOAD_2R(fun, qualifier, ret_type, arg1_type, arg1_name) \ + __RTE_BIT_OVERLOAD_SZ_2R(fun, qualifier, 32, ret_type, arg1_type, \ + arg1_name) \ + __RTE_BIT_OVERLOAD_SZ_2R(fun, qualifier, 64, ret_type, arg1_type, \ + arg1_name) + +#define __RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, size, arg1_type, arg1_name, \ + arg2_type, arg2_name) \ + static inline void \ + rte_bit_ ## fun(uint ## size ## _t *addr, arg1_type arg1_name, \ + arg2_type arg2_name) \ + { \ + __rte_bit_ ## fun ## size(addr, arg1_name, arg2_name); \ + } + +#define __RTE_BIT_OVERLOAD_3(fun, qualifier, arg1_type, arg1_name, arg2_type, \ + arg2_name) \ + __RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, 32, arg1_type, arg1_name, \ + arg2_type, arg2_name) \ + __RTE_BIT_OVERLOAD_SZ_3(fun, qualifier, 64, arg1_type, arg1_name, \ + arg2_type, arg2_name) + +__RTE_BIT_OVERLOAD_2R(test, const, bool, unsigned int, nr) +__RTE_BIT_OVERLOAD_2(set,, unsigned int, nr) +__RTE_BIT_OVERLOAD_2(clear,, unsigned int, nr) +__RTE_BIT_OVERLOAD_3(assign,, unsigned int, nr, bool, value) +__RTE_BIT_OVERLOAD_2(flip,, unsigned int, nr) + #endif #endif /* _RTE_BITOPS_H_ */ -- 2.34.1