From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7B634459CC; Wed, 18 Sep 2024 15:48:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AB5D1432B0; Wed, 18 Sep 2024 15:47:31 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2084.outbound.protection.outlook.com [40.107.94.84]) by mails.dpdk.org (Postfix) with ESMTP id 18D90432B0; Wed, 18 Sep 2024 15:47:30 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=EQ8jrPOFMfMVfVa/UWyf4+Dg8Q75dWWCcAnzFFb1hBDFcNQW5x+uZy7krZ1yGVWXhWjUD9gGTLL3vNSpxS8wgo8HD7U8ZpmHHbz525JJQpfjtpOHTenOJzOfbOEHO/morvAEKgJwRZV51TdO6XmsGvG4/1tFbmaPKEGl0bqd3Nr8LATaZzXBE/uJyI8G5koWV59rUhAcdgk0MFReY9aoe1DnuoGAwYF5chvsavp3ab1S9geVPyFjCrcZYxWUBMx1hkCoNm+qmgJrfi7YxFhKj2MNUoP6yB/sWonlISH49zPYmeRs0eFqrRmXzvp1I4CdqGDkTHg3OBWKxhobktC/Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Om94qSh5KjPCvYJlVWdyGfmtYpnq+GxiH4HKerrp1qE=; b=h2GhGbd9i7JqZ1J9tYTP02VF4RRpjzg6rdcnNLT945Ry2Frzn1P3rRyi9e11FSfl1imLlhVWcZnnhGlbQlo1DoDOZe2MkEpNaSHkyQkEAgxP0MwONhUba8jtTeJVvMO9l3/iNmrQK/26VhKOhfpzixnqxZH+1/V77S7JOhpkaW3GXxMwLJcu/tGROh/1tVXFVP+i7jT8V2zB3yCmvSr4oBBzO242gmnhVaz9J7TPvhSVtWiaLCBVEB+/U03Ev0x69nX+nHyMcvi2QBfMpE1Dnn0ZqjBJxRn3HkLMhDTA3Zu6G92wBdk9pMaXTI/9koUvriM4jKs1CvbhPFFOvEc2mw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Om94qSh5KjPCvYJlVWdyGfmtYpnq+GxiH4HKerrp1qE=; b=Hw5NHDo5SpZ61Z4HB5o+uwt+sLUZwkP4YEIr9f6lZPfim7jUOHFdVGjPDtWraySUa+j3QZYRzhkt4yjqpPNhtC35bctFrb1E0zryL7kZ8oiOzK/w6PCMg9Y3322kFxvmlvZ3nmMkwGJQdSrG7InTgsMuaP5fv/oW8eIXOaF18cKsrA2twSML8voE04dndQOimyt6btChdj0NP8s7xUI2XMkPzaAXxa/VcBVG0rPOnK53WOELQp/UIHoq98QXk0mux6M9DEp4Hm6DvX6JuXZiVVWMfsfrV5IXMGlhSJFLw8kPnuNs3bQ44e2uubISx0C7WFDNT5fUDexQdWSDFshsWg== Received: from CH0PR08CA0021.namprd08.prod.outlook.com (2603:10b6:610:33::26) by CH3PR12MB9430.namprd12.prod.outlook.com (2603:10b6:610:1cd::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7962.26; Wed, 18 Sep 2024 13:47:24 +0000 Received: from DS2PEPF00003447.namprd04.prod.outlook.com (2603:10b6:610:33:cafe::bd) by CH0PR08CA0021.outlook.office365.com (2603:10b6:610:33::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.30 via Frontend Transport; Wed, 18 Sep 2024 13:47:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS2PEPF00003447.mail.protection.outlook.com (10.167.17.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7918.13 via Frontend Transport; Wed, 18 Sep 2024 13:47:24 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 18 Sep 2024 06:47:09 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 18 Sep 2024 06:47:07 -0700 From: Viacheslav Ovsiienko To: CC: , , , , Subject: [PATCH v2 9/9] net/mlx5: fix flex item header length field translation Date: Wed, 18 Sep 2024 16:46:23 +0300 Message-ID: <20240918134623.8441-10-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918134623.8441-1-viacheslavo@nvidia.com> References: <20240911160458.524732-1-viacheslavo@nvidia.com> <20240918134623.8441-1-viacheslavo@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003447:EE_|CH3PR12MB9430:EE_ X-MS-Office365-Filtering-Correlation-Id: fd453bb9-134b-4aa5-d147-08dcd7e86d4c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GYFWh+p7RAxH3fD71j85+j7wSYISWa8MLBa6NDRFyXxmGcgsdsArTN4v1ZTt?= =?us-ascii?Q?PBGk9utweaiMW2tKozY69hu2aHD4h9j6FpCozpAYiSUqLO9xKCVctOySMMIp?= =?us-ascii?Q?IyUPqIaQQdQdYoQyowJue6NT8YcSI6nzYmxdtlEHyuHdvJ55L/dqCAIXQmSp?= =?us-ascii?Q?im1EPZLAa04E2xv1sZw5dn3vPVX753D2P1rc4BgIR+PIgofLfN7SjwPMjAcH?= =?us-ascii?Q?AB+aSp6SPSBCxaSyKGfLOnqLE1iLB5q3xK2dq09jWqjGEE33r3BpRg3EAqfs?= =?us-ascii?Q?yU6tCPf8BRMAang+l8wBzoKR3ot1NREWzk29fDW2fsm8jdRT0uGXxI8T+dkY?= =?us-ascii?Q?Ct9ORS5C4rJPNXY+SuoLAIGlUqwBqKpKGrryGcyVVd9T2Ft3eCoH+3rNqjdt?= =?us-ascii?Q?QVPC84+3zB6UNh/ER7YilT2fFpt4XJpRbG7J0sfB6hdQicwztC1BfnkVk2eB?= =?us-ascii?Q?PjAlaGVMoWzSvLqzrjDFbf4NkpMxfSMwtDVjqOZB5fciZCtZOaFikQPqJ59H?= =?us-ascii?Q?MRjm1ns3/aUORg+wdB2E5izcwaCOQLKI68FMTq/c1W27e56//NHJbhWsg00c?= =?us-ascii?Q?YVRQXV5kbPh0napbECQNbUMLtqBgXmWn65UbhgcckrcCqUQxvCwr+MIJttBR?= =?us-ascii?Q?8WgVlNWWVPDCJluiaKs26OsTTBAs8wR4K1V6wzmePQ5CLT8eHjxlHhGiGanJ?= =?us-ascii?Q?i8anLitxY97yVqnnVAmpy7+3tpkZNRJqfVWuYdOQqmxkGQK4JGQJgSk8Gn/r?= =?us-ascii?Q?McSqYQEnaRMyBj93GGeIcYrY/tQnyeXdkDSC43njVoMJurVXW5+8A9iYePv/?= =?us-ascii?Q?9Nvi7y2b1hhq0BcQdGHDBs2o7KcdCmV3AVONQoHPXwRZRTP4V+hRpmtIP7/Y?= =?us-ascii?Q?ZUeyauRQtsdkVJnVpvbttwjU/NrVefQ4DW3A+STqJk7RkHiZxbDJaK+A/UpZ?= =?us-ascii?Q?pObv37+MmR1amm8+w49avAuKvdEZvapO8TCsh4APG7p9e/rc6NecJp1tnq0Y?= =?us-ascii?Q?+bbpkWyoDNcZPpQ92jx5+DsjTF2hIrBzgg+aMZIBpMvZ9Jl5l02rfWcXQBDC?= =?us-ascii?Q?uSZrO6DHsxa2NdfKbuzr7+eatHTOubE7kED9DfqKNXtJz9GKwxXwexqvzd/O?= =?us-ascii?Q?KwhQ5pByMt+tOVjzz561B/m1zJ3GHfn06/0vbRfu0pRmuEFJkMn9EFWyFXbN?= =?us-ascii?Q?n3QGppsUpHBr8hvIRsmeomXG/UVR6Ys79q3pN4wx/68E/vrX/3LC22X+Hxsk?= =?us-ascii?Q?RHHDnFbxLefQ70VHbFV+QA+LBj6unqrHDWrvkqFJuiCS7YXXHajbh6fOdbVS?= =?us-ascii?Q?18A2br/aDS0ogJyOrkcXK1Xdijx1Z6hXA9FnKRucWJyNQsUihDyElNUcl6DO?= =?us-ascii?Q?Qy9R0y8Y35yTUk0zfjffXN8BlhHe?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 13:47:24.4496 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fd453bb9-134b-4aa5-d147-08dcd7e86d4c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003447.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9430 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org There are hardware imposed limitations on the header length field description for the mask and shift combinations in the FIELD_MODE_OFFSET mode. The patch updates: - parameter check for FIELD_MODE_OFFSET for the header length field - check whether length field crosses dword boundaries in header - correct mask extension to the hardware required width 6-bits - correct adjusting the mask left margin offset, preventing dword offset Fixes: b293e8e49d78 ("net/mlx5: translate flex item configuration") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_flex.c | 120 ++++++++++++++++-------------- 1 file changed, 66 insertions(+), 54 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_flex.c b/drivers/net/mlx5/mlx5_flow_flex.c index bf38643a23..afed16985a 100644 --- a/drivers/net/mlx5/mlx5_flow_flex.c +++ b/drivers/net/mlx5/mlx5_flow_flex.c @@ -449,12 +449,14 @@ mlx5_flex_release_index(struct rte_eth_dev *dev, * * shift mask * ------- --------------- - * 0 b111100 0x3C - * 1 b111110 0x3E - * 2 b111111 0x3F - * 3 b011111 0x1F - * 4 b001111 0x0F - * 5 b000111 0x07 + * 0 b11111100 0x3C + * 1 b01111110 0x3E + * 2 b00111111 0x3F + * 3 b00011111 0x1F + * 4 b00001111 0x0F + * 5 b00000111 0x07 + * 6 b00000011 0x03 + * 7 b00000001 0x01 */ static uint8_t mlx5_flex_hdr_len_mask(uint8_t shift, @@ -464,8 +466,7 @@ mlx5_flex_hdr_len_mask(uint8_t shift, int diff = shift - MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD; base_mask = mlx5_hca_parse_graph_node_base_hdr_len_mask(attr); - return diff == 0 ? base_mask : - diff < 0 ? (base_mask << -diff) & base_mask : base_mask >> diff; + return diff < 0 ? base_mask << -diff : base_mask >> diff; } static int @@ -476,7 +477,6 @@ mlx5_flex_translate_length(struct mlx5_hca_flex_attr *attr, { const struct rte_flow_item_flex_field *field = &conf->next_header; struct mlx5_devx_graph_node_attr *node = &devx->devx_conf; - uint32_t len_width, mask; if (field->field_base % CHAR_BIT) return rte_flow_error_set @@ -504,7 +504,14 @@ mlx5_flex_translate_length(struct mlx5_hca_flex_attr *attr, "negative header length field base (FIXED)"); node->header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED; break; - case FIELD_MODE_OFFSET: + case FIELD_MODE_OFFSET: { + uint32_t msb, lsb; + int32_t shift = field->offset_shift; + uint32_t offset = field->offset_base; + uint32_t mask = field->offset_mask; + uint32_t wmax = attr->header_length_mask_width + + MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD; + if (!(attr->header_length_mode & RTE_BIT32(MLX5_GRAPH_NODE_LEN_FIELD))) return rte_flow_error_set @@ -514,47 +521,73 @@ mlx5_flex_translate_length(struct mlx5_hca_flex_attr *attr, return rte_flow_error_set (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, "field size is a must for offset mode"); - if (field->field_size + field->offset_base < attr->header_length_mask_width) + if ((offset ^ (field->field_size + offset)) >> 5) return rte_flow_error_set (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, - "field size plus offset_base is too small"); - node->header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; - if (field->offset_mask == 0 || - !rte_is_power_of_2(field->offset_mask + 1)) + "field crosses the 32-bit word boundary"); + /* Hardware counts in dwords, all shifts done by offset within mask */ + if (shift < 0 || (uint32_t)shift >= wmax) + return rte_flow_error_set + (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "header length field shift exceeds limits (OFFSET)"); + if (!mask) + return rte_flow_error_set + (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "zero length field offset mask (OFFSET)"); + msb = rte_fls_u32(mask) - 1; + lsb = rte_bsf32(mask); + if (!rte_is_power_of_2((mask >> lsb) + 1)) return rte_flow_error_set (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, - "invalid length field offset mask (OFFSET)"); - len_width = rte_fls_u32(field->offset_mask); - if (len_width > attr->header_length_mask_width) + "length field offset mask not contiguous (OFFSET)"); + if (msb >= field->field_size) return rte_flow_error_set (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, - "length field offset mask too wide (OFFSET)"); - mask = mlx5_flex_hdr_len_mask(field->offset_shift, attr); - if (mask < field->offset_mask) + "length field offset mask exceeds field size (OFFSET)"); + if (msb >= wmax) return rte_flow_error_set (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, - "length field shift too big (OFFSET)"); - node->header_length_field_mask = RTE_MIN(mask, - field->offset_mask); + "length field offset mask exceeds supported width (OFFSET)"); + if (mask & ~mlx5_flex_hdr_len_mask(shift, attr)) + return rte_flow_error_set + (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "mask and shift combination not supported (OFFSET)"); + msb++; + offset += field->field_size - msb; + if (msb < attr->header_length_mask_width) { + if (attr->header_length_mask_width - msb > offset) + return rte_flow_error_set + (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "field size plus offset_base is too small"); + offset += msb; + /* + * Here we can move to preceding dword. Hardware does + * cyclic left shift so we should avoid this and stay + * at current dword offset. + */ + offset = (offset & ~0x1Fu) | + ((offset - attr->header_length_mask_width) & 0x1F); + } + node->header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; + node->header_length_field_mask = mask; + node->header_length_field_shift = shift; + node->header_length_field_offset = offset; break; + } case FIELD_MODE_BITMASK: if (!(attr->header_length_mode & RTE_BIT32(MLX5_GRAPH_NODE_LEN_BITMASK))) return rte_flow_error_set (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, "unsupported header length field mode (BITMASK)"); - if (attr->header_length_mask_width < field->field_size) + if (field->offset_shift > 15 || field->offset_shift < 0) return rte_flow_error_set (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, - "header length field width exceeds limit"); + "header length field shift exceeds limit (BITMASK)"); node->header_length_mode = MLX5_GRAPH_NODE_LEN_BITMASK; - mask = mlx5_flex_hdr_len_mask(field->offset_shift, attr); - if (mask < field->offset_mask) - return rte_flow_error_set - (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, - "length field shift too big (BITMASK)"); - node->header_length_field_mask = RTE_MIN(mask, - field->offset_mask); + node->header_length_field_mask = field->offset_mask; + node->header_length_field_shift = field->offset_shift; + node->header_length_field_offset = field->offset_base; break; default: return rte_flow_error_set @@ -567,27 +600,6 @@ mlx5_flex_translate_length(struct mlx5_hca_flex_attr *attr, (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, "header length field base exceeds limit"); node->header_length_base_value = field->field_base / CHAR_BIT; - if (field->field_mode == FIELD_MODE_OFFSET || - field->field_mode == FIELD_MODE_BITMASK) { - if (field->offset_shift > 15 || field->offset_shift < 0) - return rte_flow_error_set - (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, - "header length field shift exceeds limit"); - node->header_length_field_shift = field->offset_shift; - node->header_length_field_offset = field->offset_base; - } - if (field->field_mode == FIELD_MODE_OFFSET) { - if (field->field_size > attr->header_length_mask_width) { - node->header_length_field_offset += - field->field_size - attr->header_length_mask_width; - } else if (field->field_size < attr->header_length_mask_width) { - node->header_length_field_offset -= - attr->header_length_mask_width - field->field_size; - node->header_length_field_mask = - RTE_MIN(node->header_length_field_mask, - (1u << field->field_size) - 1); - } - } return 0; } -- 2.34.1