From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1CDA045AAF; Fri, 4 Oct 2024 17:13:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 12AD942E54; Fri, 4 Oct 2024 17:08:53 +0200 (CEST) Received: from egress-ip42a.ess.de.barracuda.com (egress-ip42a.ess.de.barracuda.com [18.185.115.201]) by mails.dpdk.org (Postfix) with ESMTP id 51BA842D7B for ; Fri, 4 Oct 2024 17:08:31 +0200 (CEST) Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05lp2111.outbound.protection.outlook.com [104.47.18.111]) by mx-outbound8-201.eu-central-1a.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 04 Oct 2024 15:08:30 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=EsYpwHvzY+qAWBXvc2hNbe+hV0Ph288U+TnX4A2EPwnDJjH7muzfJ/CYXdXHq2bwMDQShLazt+jRkGLyhnxm0VEtvQNRwTV8fKzDpIn9RWwlaNUgODlMVh5TRjF52b0DUOk42a4j7R7/ruF02OyAN49kuLmdDJ5zVo5Vucy3kuh7+iAwiQLEgV6ZeFpHxDu58UGF/4Ou8kM+CxxuwmBawJW9KN8rEoxp84s/PJhLz8MU8QC5SNntauqPntx0YVw8KpyJFjHG1HAsmr/Vp/VjlHL+xW2JgpJQ6okPJsO8whaBoAqYEdHwovpttbuj00MhUA/jMTShqbvjir29izhnRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=B8u/DwR1WhibYc5POCYyGm2FQ55vYKNswWFMUXYm5Ew=; b=DK5PAk5YWzJsjkry7cZ6shGQQoOhtYvf1QaQvAw+zVMU4KWleip2p3GkYqG2gHPM3lyTwTf3dCv13C67mRdinrLqHUR1tAt9AEInJhnreKZr5sKhznpF/RLvLPWrHRolx1izz1rkmHrOSx0Wtgiraqh1CzQToy0jN5JpROe6gqCRxUAUxB7bX2shGFpdrSBFEGSPHUhHkNKECBaRfx/EQhCzo/xvvwnU/FvlCT2bfiSxkD7QOUgrZcwlsbXTEaR7B3WMko/SwwK+IcxSme7z2BPp03kDb3BPtwwF85zCej8IwnV/QeFX6cCU2XTHIdSF6uDM9N87O+ttNFBgLCuIUA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 178.72.21.4) smtp.rcpttodomain=dpdk.org smtp.mailfrom=napatech.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=napatech.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=napatech.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=B8u/DwR1WhibYc5POCYyGm2FQ55vYKNswWFMUXYm5Ew=; b=F5Fve8oqImfz2q70XQoHmIG2oy89Bqsog5M3+IJSizgy602Tcx2yTRIwPz63geAqMZVFqbhhgp3M7uLIQS+bJTvkEggsLswZTh9ub3He3yHH6hrFdiHugv5JpaSo+06a+oZQxmT6uUuayLH8JYVVCak7BZ8q6Ov3swmpvRRWMuI= Received: from AM0PR02CA0020.eurprd02.prod.outlook.com (2603:10a6:208:3e::33) by AM9P190MB1107.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:271::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8005.22; Fri, 4 Oct 2024 15:08:28 +0000 Received: from AMS0EPF000001AC.eurprd05.prod.outlook.com (2603:10a6:208:3e:cafe::e9) by AM0PR02CA0020.outlook.office365.com (2603:10a6:208:3e::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8026.17 via Frontend Transport; Fri, 4 Oct 2024 15:08:28 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 178.72.21.4) smtp.mailfrom=napatech.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=napatech.com; Received-SPF: Fail (protection.outlook.com: domain of napatech.com does not designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com; client-ip=178.72.21.4; helo=localhost.localdomain; Received: from localhost.localdomain (178.72.21.4) by AMS0EPF000001AC.mail.protection.outlook.com (10.167.16.152) with Microsoft SMTP Server id 15.20.7918.13 via Frontend Transport; Fri, 4 Oct 2024 15:08:28 +0000 From: Serhii Iliushyk To: dev@dpdk.org Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com, andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com, Oleksandr Kolomeiets Subject: [PATCH v1 27/31] net/ntnic: add queue select (QSL) FPGA module Date: Fri, 4 Oct 2024 17:07:20 +0200 Message-ID: <20241004150749.261020-34-sil-plv@napatech.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241004150749.261020-1-sil-plv@napatech.com> References: <20241004150749.261020-1-sil-plv@napatech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS0EPF000001AC:EE_|AM9P190MB1107:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 7ded38d4-052e-4e91-cb66-08dce4866706 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?UgirR5FZQGACH0OtB8cwennLZy6Vy3sOYIXOrrA3zWfEOam3pNOx71Z8Xwlh?= =?us-ascii?Q?OvRZC4NjVGtyEpL+eLYf8Q0OAUbkD1+OebL98/340Iqh7dF+u9ObE83qU8hO?= =?us-ascii?Q?iWRt6DewBrlmOhfItPuRPsLBUOmvbN4f0mz/dGBARSaroelomCi0qIxf2jfB?= =?us-ascii?Q?bnGE+BQ2qiV7nMbEK/3xCD6AUOoILTW/5b7V18dszsbhQyqftQnUU+nkaHOJ?= =?us-ascii?Q?SZRPc3ooPuECM+S5aEyzhTDxM/u0uQQsZBpjQKkRFLy3uk7aYxUm8PLY1Kic?= =?us-ascii?Q?tNYO6oixozEvwuP9Y4Rd+ihu48JTuyR3olPjn+uFFKkg8WaC/TdXj3q2kHz0?= =?us-ascii?Q?ncLyKs4Hrc3LUvoxjmuBHfqM3IEnVeJypcuhJXNBOZ24gmXjF5Qf6bxip9Al?= =?us-ascii?Q?rTmv3GxxaWHkIEMi7hZQ9Z5TjLWuoqGaoKFlQoSZ23n6bYoPaMU40C68vJxo?= =?us-ascii?Q?NwFl5bHj1etk0mr3Z+45EB/ccXyNCFtBQg7HCjpWvJzTvJg7aPJrmuM3lNvS?= =?us-ascii?Q?Bb+X65EVV1uf78xGoDckzG5giJ6H+xdvrQK4mmnuJYqmRmzE8GK4wZcU8KDd?= =?us-ascii?Q?2qGIqAnWcDnfeneATVAUR/vJKWNOLql5iZqurKlUVHoYr/SH7snZHj1hNjIu?= =?us-ascii?Q?25vAUzwG3n1WJaxgiluqZ8TJGR80faQTB681gE2DipL8gVHpus/JyterxzVi?= =?us-ascii?Q?HAoLHVnP01798grqWJ2Ojtx0tlXz/5cwsWZT0FjCQxBfmXTOn6oKgTO7tksZ?= =?us-ascii?Q?aXtBLjWDwEtgrJdCEOATVJixl28ZuxkZEtoXgbnV97XGypjPSXEFddj0lMk3?= =?us-ascii?Q?axu8PFLFvLqdYP5xMygXyHv5/iDtC4irMLXm7AknqJackVDl3542iiLkK0TF?= =?us-ascii?Q?8hW1Jy412+OrzavM6PsoOCqxOtiRoxRVsDJm4bqWKQ19/u6J5PV5/ZuxVR3k?= =?us-ascii?Q?lc05bYucHAW0/SLdTHCXnNl+jK1rIjFBdFZeEC0kaGXZr5ujuRb5hYBglvoZ?= =?us-ascii?Q?U0+gN85cQi4eKzaZeLbsEd5gcC/i7lD45FASSLzZau5Hql2liLCU5Q7eraAc?= =?us-ascii?Q?wcI8Awll8JjHFsi2MXRA8bcepJ3v6kV2ye7MA9/1nZ1G2oE/hhjraVWcM/mT?= =?us-ascii?Q?tt7sdqaUiIpXtaa6ypb5VEAXOTTp0e6PkZ7Doc0P5qtewxEQ8GK+ek09iDS4?= =?us-ascii?Q?4b1hQ19PUNkcnqNfBYUO9CrhRt9Tqh8yIrvoWWiYlmkzZQi0c67PPZfKTg14?= =?us-ascii?Q?3PnEbutRwBs3noGp1dYyWiq/U+hLSXrGP9LJ3MyGXDT3W1Rs/0cuDl9fzOuo?= =?us-ascii?Q?Qw3XB1Zsl7+U1dXRHh9G0iHv7ZaDfOhWlqG7XsPP5ihUwGuRLOJ+cSRtbF0Z?= =?us-ascii?Q?psffimqaU6YQR9ecA+aepfAtlRlE?= X-Forefront-Antispam-Report: CIP:178.72.21.4; CTRY:DK; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:localhost.localdomain; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: kvub3u7lf/ZpW2PPUAAhLfYDLsZ2hAQs2JsM9zkHnjeyiOsY52Fg4iRdvOvZrYC2DkWFV8sHd7IDnLLbvRV8k+zyp5Mj7x+KN1BAyCk8x/UM9uS5a+MkEsenK4HOHNeeW5mtr+sPqvopPsPxTIpL+ajvUq276+aJDS1dCTcbCyDiBXSpoEb5Kha/lftddPaL17P5CTVO8Xb/VzAL3w5Sl0kBFzcA7a3wiTCTJ+WB/iLHoUSRGzgVnnCxWQd3MegEL69IhhXBiZDNYSTD9HJ3hYjH3zTdnHgcO20rNR+Ut3yJLi6M/zlrOFSxleJ23Z8P2VT6dawQzgzPrMqo2x6Df2TU/erOZSkW1HQcLhrmR98p1Z6puthV8rhj7bP/B9zzFLF/tTSqu3gTmlRI6DOHhZie1e2KFsP4ISzJpFLUnKAEK+OKBPGFMDxKwR9zMnFp1p4wLkOlJTiqZ2hYnrCDISp6+9wY1oIK5NVoansODuHJKRRev5m4tx3iOWQvChobr1pcWqRbU7jFqlmM2F07/gjw5aR3AwKy5r1atTnExgfGMYiSWZp4EeHpwI1K7NoQhYv5rO8jaznbGnDxWV7yFcEiQHYF1gBuP1j5yaoJRd3KtQD/rY9wfYWiU4fi65Rpdk2O95tEB7W8u03xAZFJJQ== X-OriginatorOrg: napatech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2024 15:08:28.3141 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ded38d4-052e-4e91-cb66-08dce4866706 X-MS-Exchange-CrossTenant-Id: c4540d0b-728a-4233-9da5-9ea30c7ec3ed X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=c4540d0b-728a-4233-9da5-9ea30c7ec3ed; Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001AC.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P190MB1107 X-BESS-ID: 1728054510-302249-12642-31682-1 X-BESS-VER: 2019.1_20240924.1654 X-BESS-Apparent-Source-IP: 104.47.18.111 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVoZGlibmQGYGUDTR3MDEJNE8JS 051cAyLc3IwMjcyMLcAIQTLS0tLZRqYwHDpJ8aQgAAAA== X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.259494 [from cloudscan20-7.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Oleksandr Kolomeiets The Queue Selector module directs packets to a given destination which includes host queues, physical ports, exceptions paths, and discard. Signed-off-by: Oleksandr Kolomeiets --- drivers/net/ntnic/include/hw_mod_backend.h | 37 ++++ drivers/net/ntnic/meson.build | 1 + drivers/net/ntnic/nthw/flow_api/flow_api.c | 14 ++ .../nthw/flow_api/hw_mod/hw_mod_backend.c | 1 + .../ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c | 170 ++++++++++++++++++ .../supported/nthw_fpga_9563_055_049_0000.c | 57 +++++- 6 files changed, 279 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h index 6bf651272f..13e0d1731e 100644 --- a/drivers/net/ntnic/include/hw_mod_backend.h +++ b/drivers/net/ntnic/include/hw_mod_backend.h @@ -537,6 +537,42 @@ struct qsl_func_s { struct hw_mod_qsl_v7_s v7; }; }; +enum hw_qsl_e { + /* functions */ + HW_QSL_RCP_PRESET_ALL = 0, + HW_QSL_RCP_COMPARE, + HW_QSL_RCP_FIND, + HW_QSL_QST_PRESET_ALL, + /* fields */ + HW_QSL_RCP_DISCARD = FIELD_START_INDEX, + HW_QSL_RCP_DROP, + HW_QSL_RCP_TBL_LO, + HW_QSL_RCP_TBL_HI, + HW_QSL_RCP_TBL_IDX, + HW_QSL_RCP_TBL_MSK, + HW_QSL_RCP_LR, + HW_QSL_RCP_TSA, + HW_QSL_RCP_VLI, + HW_QSL_QST_QUEUE, + HW_QSL_QST_EN, /* Alias: HW_QSL_QST_QEN */ + HW_QSL_QST_TX_PORT, + HW_QSL_QST_LRE, + HW_QSL_QST_TCI, + HW_QSL_QST_VEN, + HW_QSL_QEN_EN, + HW_QSL_UNMQ_DEST_QUEUE, + HW_QSL_UNMQ_EN, +}; +bool hw_mod_qsl_present(struct flow_api_backend_s *be); +int hw_mod_qsl_alloc(struct flow_api_backend_s *be); +void hw_mod_qsl_free(struct flow_api_backend_s *be); +int hw_mod_qsl_reset(struct flow_api_backend_s *be); +int hw_mod_qsl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count); +int hw_mod_qsl_qst_flush(struct flow_api_backend_s *be, int start_idx, int count); +int hw_mod_qsl_qen_flush(struct flow_api_backend_s *be, int start_idx, int count); +int hw_mod_qsl_unmq_flush(struct flow_api_backend_s *be, int start_idx, int count); +int hw_mod_qsl_unmq_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, + uint32_t value); struct slc_lr_func_s { COMMON_FUNC_INFO_S; @@ -721,6 +757,7 @@ struct flow_api_backend_s { struct km_func_s km; struct flm_func_s flm; struct hsh_func_s hsh; + struct qsl_func_s qsl; /* NIC attributes */ unsigned int num_phy_ports; diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 18aafc57f0..02981ef987 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -53,6 +53,7 @@ sources = files( 'nthw/flow_api/hw_mod/hw_mod_flm.c', 'nthw/flow_api/hw_mod/hw_mod_hsh.c', 'nthw/flow_api/hw_mod/hw_mod_km.c', + 'nthw/flow_api/hw_mod/hw_mod_qsl.c', 'nthw/flow_filter/flow_nthw_cat.c', 'nthw/flow_filter/flow_nthw_csu.c', 'nthw/flow_filter/flow_nthw_flm.c', diff --git a/drivers/net/ntnic/nthw/flow_api/flow_api.c b/drivers/net/ntnic/nthw/flow_api/flow_api.c index b43c8fef1a..5d6571310c 100644 --- a/drivers/net/ntnic/nthw/flow_api/flow_api.c +++ b/drivers/net/ntnic/nthw/flow_api/flow_api.c @@ -144,6 +144,14 @@ int flow_delete_eth_dev(struct flow_eth_dev *eth_dev) /* delete all created flows from this device */ pthread_mutex_lock(&ndev->mtx); + /* + * remove unmatched queue if setup in QSL + * remove exception queue setting in QSL UNM + */ + hw_mod_qsl_unmq_set(&ndev->be, HW_QSL_UNMQ_DEST_QUEUE, eth_dev->port, 0); + hw_mod_qsl_unmq_set(&ndev->be, HW_QSL_UNMQ_EN, eth_dev->port, 0); + hw_mod_qsl_unmq_flush(&ndev->be, eth_dev->port, 1); + #ifdef FLOW_DEBUG ndev->be.iface->set_debug_mode(ndev->be.be_dev, FLOW_BACKEND_DEBUG_MODE_NONE); #endif @@ -293,6 +301,12 @@ struct flow_nic_dev *flow_api_create(uint8_t adapter_no, const struct flow_api_b if (init_resource_elements(ndev, RES_HSH_RCP, ndev->be.hsh.nb_rcp)) goto err_exit; + if (init_resource_elements(ndev, RES_QSL_RCP, ndev->be.qsl.nb_rcp_categories)) + goto err_exit; + + if (init_resource_elements(ndev, RES_QSL_QST, ndev->be.qsl.nb_qst_entries)) + goto err_exit; + if (init_resource_elements(ndev, RES_SLC_LR_RCP, ndev->be.max_categories)) goto err_exit; diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c index 3ccc14c4ce..4f16235a67 100644 --- a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c +++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c @@ -21,6 +21,7 @@ static const struct { { "KM", hw_mod_km_alloc, hw_mod_km_free, hw_mod_km_reset, hw_mod_km_present }, { "FLM", hw_mod_flm_alloc, hw_mod_flm_free, hw_mod_flm_reset, hw_mod_flm_present }, { "HSH", hw_mod_hsh_alloc, hw_mod_hsh_free, hw_mod_hsh_reset, hw_mod_hsh_present }, + { "QSL", hw_mod_qsl_alloc, hw_mod_qsl_free, hw_mod_qsl_reset, hw_mod_qsl_present }, }; #define MOD_COUNT (ARRAY_SIZE(module)) diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c new file mode 100644 index 0000000000..f69717cf84 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_qsl.c @@ -0,0 +1,170 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include +#include + +#include "hw_mod_backend.h" + +#define _MOD_ "QSL" +#define _VER_ be->qsl.ver + +#define QSL_QEN_ENTRIES 32 +#define QSL_QNMQ_ENTRIES 256 + +bool hw_mod_qsl_present(struct flow_api_backend_s *be) +{ + return be->iface->get_qsl_present(be->be_dev); +} + +int hw_mod_qsl_alloc(struct flow_api_backend_s *be) +{ + int nb; + _VER_ = be->iface->get_qsl_version(be->be_dev); + NT_LOG(DBG, FILTER, "QSL MODULE VERSION %i.%i\n", VER_MAJOR(_VER_), VER_MINOR(_VER_)); + + nb = be->iface->get_nb_qsl_categories(be->be_dev); + + if (nb <= 0) + return COUNT_ERROR(qsl_categories); + + be->qsl.nb_rcp_categories = (uint32_t)nb; + + nb = be->iface->get_nb_qsl_qst_entries(be->be_dev); + + if (nb <= 0) + return COUNT_ERROR(qsl_qst_entries); + + be->qsl.nb_qst_entries = (uint32_t)nb; + + switch (_VER_) { + case 7: + if (!callocate_mod((struct common_func_s *)&be->qsl, 4, &be->qsl.v7.rcp, + be->qsl.nb_rcp_categories, sizeof(struct qsl_v7_rcp_s), + &be->qsl.v7.qst, be->qsl.nb_qst_entries, + sizeof(struct qsl_v7_qst_s), &be->qsl.v7.qen, QSL_QEN_ENTRIES, + sizeof(struct qsl_v7_qen_s), &be->qsl.v7.unmq, QSL_QNMQ_ENTRIES, + sizeof(struct qsl_v7_unmq_s))) + return -1; + + break; + + /* end case 7 */ + default: + return UNSUP_VER; + } + + return 0; +} + +void hw_mod_qsl_free(struct flow_api_backend_s *be) +{ + if (be->qsl.base) { + free(be->qsl.base); + be->qsl.base = NULL; + } +} + +int hw_mod_qsl_reset(struct flow_api_backend_s *be) +{ + /* Zero entire cache area */ + zero_module_cache((struct common_func_s *)(&be->qsl)); + + NT_LOG(DBG, FILTER, "INIT QSL RCP\n"); + hw_mod_qsl_rcp_flush(be, 0, ALL_ENTRIES); + + NT_LOG(DBG, FILTER, "INIT QSL QST\n"); + hw_mod_qsl_qst_flush(be, 0, ALL_ENTRIES); + + NT_LOG(DBG, FILTER, "INIT QSL QEN\n"); + hw_mod_qsl_qen_flush(be, 0, ALL_ENTRIES); + + NT_LOG(DBG, FILTER, "INIT QSL UNMQ\n"); + be->iface->qsl_unmq_flush(be->be_dev, &be->qsl, 0, 256); + + return 0; +} + +int hw_mod_qsl_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count) +{ + if (count == ALL_ENTRIES) + count = be->qsl.nb_rcp_categories; + + if ((unsigned int)(start_idx + count) > be->qsl.nb_rcp_categories) + return INDEX_TOO_LARGE; + + return be->iface->qsl_rcp_flush(be->be_dev, &be->qsl, start_idx, count); +} + +int hw_mod_qsl_qst_flush(struct flow_api_backend_s *be, int start_idx, int count) +{ + if (count == ALL_ENTRIES) + count = be->qsl.nb_qst_entries; + + if ((unsigned int)(start_idx + count) > be->qsl.nb_qst_entries) + return INDEX_TOO_LARGE; + + return be->iface->qsl_qst_flush(be->be_dev, &be->qsl, start_idx, count); +} + +int hw_mod_qsl_qen_flush(struct flow_api_backend_s *be, int start_idx, int count) +{ + if (count == ALL_ENTRIES) + count = QSL_QEN_ENTRIES; + + if ((start_idx + count) > QSL_QEN_ENTRIES) + return INDEX_TOO_LARGE; + + return be->iface->qsl_qen_flush(be->be_dev, &be->qsl, start_idx, count); +} + +int hw_mod_qsl_unmq_flush(struct flow_api_backend_s *be, int start_idx, int count) +{ + if (count == ALL_ENTRIES) + count = QSL_QNMQ_ENTRIES; + + if ((start_idx + count) > QSL_QNMQ_ENTRIES) + return INDEX_TOO_LARGE; + + return be->iface->qsl_unmq_flush(be->be_dev, &be->qsl, start_idx, count); +} + +static int hw_mod_qsl_unmq_mod(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, + uint32_t *value, int get) +{ + if (index >= QSL_QNMQ_ENTRIES) + return INDEX_TOO_LARGE; + + switch (_VER_) { + case 7: + switch (field) { + case HW_QSL_UNMQ_DEST_QUEUE: + GET_SET(be->qsl.v7.unmq[index].dest_queue, value); + break; + + case HW_QSL_UNMQ_EN: + GET_SET(be->qsl.v7.unmq[index].en, value); + break; + + default: + return UNSUP_FIELD; + } + + break; + + /* end case 7 */ + default: + return UNSUP_VER; + } + + return 0; +} + +int hw_mod_qsl_unmq_set(struct flow_api_backend_s *be, enum hw_qsl_e field, uint32_t index, + uint32_t value) +{ + return hw_mod_qsl_unmq_mod(be, field, index, &value, 0); +} diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c index 4317da8094..7eeb210b80 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c @@ -1297,6 +1297,60 @@ static nthw_fpga_register_init_s pci_wr_tg_registers[] = { { PCI_WR_TG_TG_WR_RUN, 4, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wr_run_fields }, }; +static nthw_fpga_field_init_s qsl_qen_ctrl_fields[] = { + { QSL_QEN_CTRL_ADR, 5, 0, 0x0000 }, + { QSL_QEN_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_qen_data_fields[] = { + { QSL_QEN_DATA_EN, 4, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_qst_ctrl_fields[] = { + { QSL_QST_CTRL_ADR, 12, 0, 0x0000 }, + { QSL_QST_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_qst_data_fields[] = { + { QSL_QST_DATA_LRE, 1, 9, 0x0000 }, { QSL_QST_DATA_QEN, 1, 7, 0x0000 }, + { QSL_QST_DATA_QUEUE, 7, 0, 0x0000 }, { QSL_QST_DATA_TCI, 16, 10, 0x0000 }, + { QSL_QST_DATA_TX_PORT, 1, 8, 0x0000 }, { QSL_QST_DATA_VEN, 1, 26, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_rcp_ctrl_fields[] = { + { QSL_RCP_CTRL_ADR, 5, 0, 0x0000 }, + { QSL_RCP_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_rcp_data_fields[] = { + { QSL_RCP_DATA_DISCARD, 1, 0, 0x0000 }, { QSL_RCP_DATA_DROP, 2, 1, 0x0000 }, + { QSL_RCP_DATA_LR, 2, 51, 0x0000 }, { QSL_RCP_DATA_TBL_HI, 12, 15, 0x0000 }, + { QSL_RCP_DATA_TBL_IDX, 12, 27, 0x0000 }, { QSL_RCP_DATA_TBL_LO, 12, 3, 0x0000 }, + { QSL_RCP_DATA_TBL_MSK, 12, 39, 0x0000 }, { QSL_RCP_DATA_TSA, 1, 53, 0x0000 }, + { QSL_RCP_DATA_VLI, 2, 54, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_unmq_ctrl_fields[] = { + { QSL_UNMQ_CTRL_ADR, 1, 0, 0x0000 }, + { QSL_UNMQ_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s qsl_unmq_data_fields[] = { + { QSL_UNMQ_DATA_DEST_QUEUE, 7, 0, 0x0000 }, + { QSL_UNMQ_DATA_EN, 1, 7, 0x0000 }, +}; + +static nthw_fpga_register_init_s qsl_registers[] = { + { QSL_QEN_CTRL, 4, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_qen_ctrl_fields }, + { QSL_QEN_DATA, 5, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, qsl_qen_data_fields }, + { QSL_QST_CTRL, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_qst_ctrl_fields }, + { QSL_QST_DATA, 3, 27, NTHW_FPGA_REG_TYPE_WO, 0, 6, qsl_qst_data_fields }, + { QSL_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_rcp_ctrl_fields }, + { QSL_RCP_DATA, 1, 56, NTHW_FPGA_REG_TYPE_WO, 0, 9, qsl_rcp_data_fields }, + { QSL_UNMQ_CTRL, 6, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_unmq_ctrl_fields }, + { QSL_UNMQ_DATA, 7, 8, NTHW_FPGA_REG_TYPE_WO, 0, 2, qsl_unmq_data_fields }, +}; + static nthw_fpga_field_init_s rac_dbg_ctrl_fields[] = { { RAC_DBG_CTRL_C, 32, 0, 0x0000 }, }; @@ -1456,6 +1510,7 @@ static nthw_fpga_module_init_s fpga_modules[] = { MOD_PCI_WR_TG, 0, MOD_PCI_WR_TG, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 2304, 7, pci_wr_tg_registers }, + { MOD_QSL, 0, MOD_QSL, 0, 7, NTHW_FPGA_BUS_TYPE_RAB1, 1792, 8, qsl_registers }, { MOD_RAC, 0, MOD_RAC, 3, 0, NTHW_FPGA_BUS_TYPE_PCI, 8192, 14, rac_registers }, { MOD_RST9563, 0, MOD_RST9563, 0, 5, NTHW_FPGA_BUS_TYPE_RAB0, 1024, 5, rst9563_registers }, }; @@ -1617,5 +1672,5 @@ static nthw_fpga_prod_param_s product_parameters[] = { }; nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = { - 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 18, fpga_modules, + 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 19, fpga_modules, }; -- 2.45.0