[PATCH v1 22/50] net/ntnic: add checksum update (CSU) flow module

[Serhii Iliushyk <sil-plv@napatech.com>]

From: Oleksandr Kolomeiets <okl-plv@napatech.com>

The Checksum Update module updates the checksums of packets
that has been modified in any way.

Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
 drivers/net/ntnic/meson.build                 |  1 +
 .../nthw/flow_api/flow_backend/flow_backend.c | 13 ++++
 .../ntnic/nthw/flow_filter/flow_nthw_csu.c    | 62 +++++++++++++++++++
 .../ntnic/nthw/flow_filter/flow_nthw_csu.h    | 35 +++++++++++
 .../ntnic/nthw/supported/nthw_fpga_mod_defs.h |  1 +
 .../ntnic/nthw/supported/nthw_fpga_reg_defs.h |  1 +
 .../nthw/supported/nthw_fpga_reg_defs_csu.h   | 31 ++++++++++
 7 files changed, 144 insertions(+)
 create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_csu.c
 create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_csu.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h

diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 3c00203e34..cc5e6fe100 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -47,6 +47,7 @@ sources = files(
         'nthw/flow_api/flow_backend/flow_backend.c',
         'nthw/flow_api/flow_filter.c',
         'nthw/flow_filter/flow_nthw_cat.c',
+        'nthw/flow_filter/flow_nthw_csu.c',
         'nthw/flow_filter/flow_nthw_flm.c',
         'nthw/flow_filter/flow_nthw_hfu.c',
         'nthw/flow_filter/flow_nthw_hsh.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
index af1e8ce3a4..c12a3204bc 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
@@ -8,6 +8,7 @@
 #include "flow_nthw_info.h"
 #include "flow_nthw_ifr.h"
 #include "flow_nthw_cat.h"
+#include "flow_nthw_csu.h"
 #include "flow_nthw_km.h"
 #include "flow_nthw_flm.h"
 #include "flow_nthw_hfu.h"
@@ -42,6 +43,7 @@ static struct backend_dev_s {
 	struct hfu_nthw *p_hfu_nthw;    /* TPE module */
 	struct rpp_lr_nthw *p_rpp_lr_nthw;      /* TPE module */
 	struct tx_cpy_nthw *p_tx_cpy_nthw;      /* TPE module */
+	struct csu_nthw *p_csu_nthw;    /* TPE module */
 	struct ifr_nthw *p_ifr_nthw;    /* TPE module */
 } be_devs[MAX_PHYS_ADAPTERS];
 
@@ -1819,6 +1821,16 @@ const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, vo
 		be_devs[physical_adapter_no].p_tx_cpy_nthw = NULL;
 	}
 
+	/* Init nthw CSU */
+	if (csu_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) {
+		struct csu_nthw *ptr = csu_nthw_new();
+		csu_nthw_init(ptr, p_fpga, physical_adapter_no);
+		be_devs[physical_adapter_no].p_csu_nthw = ptr;
+
+	} else {
+		be_devs[physical_adapter_no].p_csu_nthw = NULL;
+	}
+
 	be_devs[physical_adapter_no].adapter_no = physical_adapter_no;
 	*dev = (void *)&be_devs[physical_adapter_no];
 
@@ -1836,6 +1848,7 @@ static void bin_flow_backend_done(void *dev)
 	qsl_nthw_delete(be_dev->p_qsl_nthw);
 	slc_lr_nthw_delete(be_dev->p_slc_lr_nthw);
 	pdb_nthw_delete(be_dev->p_pdb_nthw);
+	csu_nthw_delete(be_dev->p_csu_nthw);
 	hfu_nthw_delete(be_dev->p_hfu_nthw);
 	rpp_lr_nthw_delete(be_dev->p_rpp_lr_nthw);
 	tx_cpy_nthw_delete(be_dev->p_tx_cpy_nthw);
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_csu.c b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_csu.c
new file mode 100644
index 0000000000..21efc62eda
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_csu.c
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "ntlog.h"
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "flow_nthw_csu.h"
+
+struct csu_nthw *csu_nthw_new(void)
+{
+	struct csu_nthw *p = malloc(sizeof(struct csu_nthw));
+
+	if (p)
+		(void)memset(p, 0, sizeof(*p));
+
+	return p;
+}
+
+void csu_nthw_delete(struct csu_nthw *p)
+{
+	if (p) {
+		(void)memset(p, 0, sizeof(*p));
+		free(p);
+	}
+}
+
+int csu_nthw_init(struct csu_nthw *p, nthw_fpga_t *p_fpga, int n_instance)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_CSU, n_instance);
+
+	assert(n_instance >= 0 && n_instance < 256);
+
+	if (p == NULL)
+		return p_mod == NULL ? -1 : 0;
+
+	if (p_mod == NULL) {
+		NT_LOG(ERR, NTHW, "%s: Csu %d: no such instance\n", p_adapter_id_str, n_instance);
+		return -1;
+	}
+
+	p->mp_fpga = p_fpga;
+	p->m_physical_adapter_no = (uint8_t)n_instance;
+	p->m_csu = p_mod;
+
+	p->mp_rcp_ctrl = nthw_module_get_register(p->m_csu, CSU_RCP_CTRL);
+	p->mp_rcp_ctrl_adr = nthw_register_get_field(p->mp_rcp_ctrl, CSU_RCP_CTRL_ADR);
+	p->mp_rcp_ctrl_cnt = nthw_register_get_field(p->mp_rcp_ctrl, CSU_RCP_CTRL_CNT);
+	p->mp_rcp_data = nthw_module_get_register(p->m_csu, CSU_RCP_DATA);
+	p->mp_rcp_data_ol3_cmd = nthw_register_get_field(p->mp_rcp_data, CSU_RCP_DATA_OL3_CMD);
+	p->mp_rcp_data_ol4_cmd = nthw_register_get_field(p->mp_rcp_data, CSU_RCP_DATA_OL4_CMD);
+	p->mp_rcp_data_il3_cmd = nthw_register_get_field(p->mp_rcp_data, CSU_RCP_DATA_IL3_CMD);
+	p->mp_rcp_data_il4_cmd = nthw_register_get_field(p->mp_rcp_data, CSU_RCP_DATA_IL4_CMD);
+
+	return 0;
+}
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_csu.h b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_csu.h
new file mode 100644
index 0000000000..e5986a1a9b
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_csu.h
@@ -0,0 +1,35 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _FLOW_NTHW_CSU_H_
+#define _FLOW_NTHW_CSU_H_
+
+#include <stdint.h>
+
+#include "nthw_fpga_model.h"
+
+struct csu_nthw {
+	uint8_t m_physical_adapter_no;
+	nthw_fpga_t *mp_fpga;
+
+	nthw_module_t *m_csu;
+
+	nthw_register_t *mp_rcp_ctrl;
+	nthw_field_t *mp_rcp_ctrl_adr;
+	nthw_field_t *mp_rcp_ctrl_cnt;
+	nthw_register_t *mp_rcp_data;
+	nthw_field_t *mp_rcp_data_ol3_cmd;
+	nthw_field_t *mp_rcp_data_ol4_cmd;
+	nthw_field_t *mp_rcp_data_il3_cmd;
+	nthw_field_t *mp_rcp_data_il4_cmd;
+};
+
+struct csu_nthw *csu_nthw_new(void);
+void csu_nthw_delete(struct csu_nthw *p);
+int csu_nthw_init(struct csu_nthw *p, nthw_fpga_t *p_fpga, int n_instance);
+
+int csu_nthw_setup(struct csu_nthw *p, int n_idx, int n_idx_cnt);
+
+#endif	/* _FLOW_NTHW_CSU_H_ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
index d93d9d3816..14e031dc69 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
@@ -15,6 +15,7 @@
 
 #define MOD_UNKNOWN (0L)/* Unknown/uninitialized - keep this as the first element */
 #define MOD_CAT (0x30b447c2UL)
+#define MOD_CSU (0x3f470787UL)
 #define MOD_FLM (0xe7ba53a4UL)
 #define MOD_GFG (0xfc423807UL)
 #define MOD_GMF (0x68b1d15aUL)
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
index d58d10c438..6eebab65a2 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
@@ -15,6 +15,7 @@
 
 #include "nthw_fpga_reg_defs_cat.h"
 #include "nthw_fpga_reg_defs_cpy.h"
+#include "nthw_fpga_reg_defs_csu.h"
 #include "nthw_fpga_reg_defs_flm.h"
 #include "nthw_fpga_reg_defs_gfg.h"
 #include "nthw_fpga_reg_defs_gmf.h"
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h
new file mode 100644
index 0000000000..a67f1c392e
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_csu.h
@@ -0,0 +1,31 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+/*
+ * nthw_fpga_reg_defs_csu.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_CSU_
+#define _NTHW_FPGA_REG_DEFS_CSU_
+
+/* CSU */
+#define NTHW_MOD_CSU (0x3f470787UL)
+#define CSU_RCP_CTRL (0x11955fefUL)
+#define CSU_RCP_CTRL_ADR (0x8efb3c71UL)
+#define CSU_RCP_CTRL_CNT (0x9ef3a5a0UL)
+#define CSU_RCP_DATA (0xbe44ddf6UL)
+#define CSU_RCP_DATA_IL3_CMD (0xdbac8e0dUL)
+#define CSU_RCP_DATA_IL4_CMD (0x698c521dUL)
+#define CSU_RCP_DATA_OL3_CMD (0xb87cbb37UL)
+#define CSU_RCP_DATA_OL4_CMD (0xa5c6727UL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_CSU_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
-- 
2.45.0