* [PATCH] raw/ntb: refactor to support NTB on 5th Gen Intel Xeon
@ 2023-12-06 3:00 Junfeng Guo
2024-10-07 20:12 ` Stephen Hemminger
0 siblings, 1 reply; 2+ messages in thread
From: Junfeng Guo @ 2023-12-06 3:00 UTC (permalink / raw)
To: jingjing.wu; +Cc: dev, omkar.maslekar, Junfeng Guo
Refactor to support for 5th Gen Intel Xeon Scalable processors. Note that
NTB devices within the 3rd, 4th and 5th Gen Intel Xeon Scalable processors
share the same device id, and compliant to PCIe 4.0 spec.
It is more reasonable to distinguish NTB devices by their PCIe generation.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
---
doc/guides/rawdevs/ntb.rst | 7 +-
doc/guides/rel_notes/release_24_03.rst | 4 +
drivers/raw/ntb/ntb.c | 8 +-
drivers/raw/ntb/ntb.h | 5 +-
drivers/raw/ntb/ntb_hw_intel.c | 182 +++++++++++--------------
drivers/raw/ntb/ntb_hw_intel.h | 90 ++++++------
usertools/dpdk-devbind.py | 8 +-
7 files changed, 149 insertions(+), 155 deletions(-)
diff --git a/doc/guides/rawdevs/ntb.rst b/doc/guides/rawdevs/ntb.rst
index f8befc6594..ee452af4fd 100644
--- a/doc/guides/rawdevs/ntb.rst
+++ b/doc/guides/rawdevs/ntb.rst
@@ -153,6 +153,7 @@ Limitation
This PMD is only supported on Intel Xeon Platforms:
-- 4th Generation Intel® Xeon® Scalable Processors.
-- 3rd Generation Intel® Xeon® Scalable Processors.
-- 2nd Generation Intel® Xeon® Scalable Processors.
+- 5th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E)
+- 4th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E)
+- 3rd Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E)
+- 2nd Generation Intel® Xeon® Scalable Processors. (NTB GEN3 device id: 0x201C)
diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst
index bd84875d4f..a43f64b199 100644
--- a/doc/guides/rel_notes/release_24_03.rst
+++ b/doc/guides/rel_notes/release_24_03.rst
@@ -55,6 +55,10 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Added support for Intel NTB with 5th Gen Intel Xeon Scalable processors..**
+
+Added NTB device (4th generation) support for the 5th Gen Intel Xeon Platforms.
+
* **Improved support of RSS hash algorithm.**
* Added new function ``rte_eth_find_rss_algo`` to get RSS hash
diff --git a/drivers/raw/ntb/ntb.c b/drivers/raw/ntb/ntb.c
index 0ed4c14592..2a163eff60 100644
--- a/drivers/raw/ntb/ntb.c
+++ b/drivers/raw/ntb/ntb.c
@@ -24,8 +24,8 @@
#include "ntb.h"
static const struct rte_pci_id pci_id_ntb_map[] = {
- { RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_SKX) },
- { RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_ICX) },
+ { RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_GEN3) },
+ { RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_GEN4) },
{ .vendor_id = 0, /* sentinel */ },
};
@@ -1378,8 +1378,8 @@ ntb_init_hw(struct rte_rawdev *dev, struct rte_pci_device *pci_dev)
hw->link_width = NTB_WIDTH_NONE;
switch (pci_dev->id.device_id) {
- case NTB_INTEL_DEV_ID_B2B_SKX:
- case NTB_INTEL_DEV_ID_B2B_ICX:
+ case NTB_INTEL_DEV_ID_B2B_GEN3:
+ case NTB_INTEL_DEV_ID_B2B_GEN4:
hw->ntb_ops = &intel_ntb_ops;
break;
default:
diff --git a/drivers/raw/ntb/ntb.h b/drivers/raw/ntb/ntb.h
index a30a6b60c9..d2e6d566ed 100644
--- a/drivers/raw/ntb/ntb.h
+++ b/drivers/raw/ntb/ntb.h
@@ -17,9 +17,8 @@ extern int ntb_logtype;
#define NTB_INTEL_VENDOR_ID 0x8086
/* Device IDs */
-#define NTB_INTEL_DEV_ID_B2B_SKX 0x201C
-#define NTB_INTEL_DEV_ID_B2B_ICX 0x347E
-#define NTB_INTEL_DEV_ID_B2B_SPR 0x347E
+#define NTB_INTEL_DEV_ID_B2B_GEN3 0x201C
+#define NTB_INTEL_DEV_ID_B2B_GEN4 0x347E
/* Reserved to app to use. */
#define NTB_SPAD_USER "spad_user_"
diff --git a/drivers/raw/ntb/ntb_hw_intel.c b/drivers/raw/ntb/ntb_hw_intel.c
index 9b4465176a..3e2094437f 100644
--- a/drivers/raw/ntb/ntb_hw_intel.c
+++ b/drivers/raw/ntb/ntb_hw_intel.c
@@ -25,25 +25,6 @@ static enum xeon_ntb_bar intel_ntb_bar[] = {
XEON_NTB_BAR45,
};
-static inline int
-is_gen3_ntb(const struct ntb_hw *hw)
-{
- if (hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_SKX)
- return 1;
-
- return 0;
-}
-
-static inline int
-is_gen4_ntb(const struct ntb_hw *hw)
-{
- if (hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_ICX ||
- hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_SPR)
- return 1;
-
- return 0;
-}
-
static int
intel_ntb3_check_ppd(struct ntb_hw *hw)
{
@@ -51,35 +32,36 @@ intel_ntb3_check_ppd(struct ntb_hw *hw)
int ret;
ret = rte_pci_read_config(hw->pci_dev, ®_val,
- sizeof(reg_val), XEON_PPD_OFFSET);
+ sizeof(reg_val), XEON_NTB3_PPD_OFFSET);
if (ret < 0) {
NTB_LOG(ERR, "Cannot get NTB PPD (PCIe port definition).");
return -EIO;
}
/* Check connection topo type. Only support B2B. */
- switch (reg_val & XEON_PPD_CONN_MASK) {
- case XEON_PPD_CONN_B2B:
+ switch (reg_val & XEON_NTB3_PPD_CONN_MASK) {
+ case XEON_NTB3_PPD_CONN_B2B:
NTB_LOG(INFO, "Topo B2B (back to back) is using.");
break;
- case XEON_PPD_CONN_TRANSPARENT:
- case XEON_PPD_CONN_RP:
default:
NTB_LOG(ERR, "Not supported conn topo. Please use B2B.");
return -EINVAL;
}
- /* Check device type. */
- if (reg_val & XEON_PPD_DEV_DSD) {
+ /* Check device config status. */
+ switch (reg_val & XEON_NTB3_PPD_DEV_MASK) {
+ case XEON_NTB3_PPD_DEV_DSD:
NTB_LOG(INFO, "DSD, Downstream Device.");
hw->topo = NTB_TOPO_B2B_DSD;
- } else {
+ break;
+ case XEON_NTB3_PPD_DEV_USD:
NTB_LOG(INFO, "USD, Upstream device.");
hw->topo = NTB_TOPO_B2B_USD;
+ break;
}
/* Check if bar4 is split. Do not support split bar. */
- if (reg_val & XEON_PPD_SPLIT_BAR_MASK) {
+ if (reg_val & XEON_NTB3_PPD_SPLIT_BAR_MASK) {
NTB_LOG(ERR, "Do not support split bar.");
return -EINVAL;
}
@@ -91,8 +73,8 @@ static int
intel_ntb4_check_ppd_for_ICX(struct ntb_hw *hw, uint32_t reg_val)
{
/* Check connection topo type. Only support B2B. */
- switch (reg_val & XEON_GEN4_PPD_CONN_MASK) {
- case XEON_GEN4_PPD_CONN_B2B:
+ switch (reg_val & XEON_GEN3_NTB4_PPD_CONN_MASK) {
+ case XEON_GEN3_NTB4_PPD_CONN_B2B:
NTB_LOG(INFO, "Topo B2B (back to back) is using.");
break;
default:
@@ -100,38 +82,16 @@ intel_ntb4_check_ppd_for_ICX(struct ntb_hw *hw, uint32_t reg_val)
return -EINVAL;
}
- /* Check device type. */
- if (reg_val & XEON_GEN4_PPD_DEV_DSD) {
+ /* Check device config status. */
+ switch (reg_val & XEON_GEN3_NTB4_PPD_DEV_MASK) {
+ case XEON_GEN3_NTB4_PPD_DEV_DSD:
NTB_LOG(INFO, "DSD, Downstream Device.");
hw->topo = NTB_TOPO_B2B_DSD;
- } else {
- NTB_LOG(INFO, "USD, Upstream device.");
- hw->topo = NTB_TOPO_B2B_USD;
- }
-
- return 0;
-}
-
-static int
-intel_ntb4_check_ppd_for_SPR(struct ntb_hw *hw, uint32_t reg_val)
-{
- /* Check connection topo type. Only support B2B. */
- switch (reg_val & XEON_SPR_PPD_CONN_MASK) {
- case XEON_SPR_PPD_CONN_B2B:
- NTB_LOG(INFO, "Topo B2B (back to back) is using.");
break;
- default:
- NTB_LOG(ERR, "Not supported conn topo. Please use B2B.");
- return -EINVAL;
- }
-
- /* Check device type. */
- if (reg_val & XEON_SPR_PPD_DEV_DSD) {
- NTB_LOG(INFO, "DSD, Downstream Device.");
- hw->topo = NTB_TOPO_B2B_DSD;
- } else {
+ case XEON_GEN3_NTB4_PPD_DEV_USD:
NTB_LOG(INFO, "USD, Upstream device.");
hw->topo = NTB_TOPO_B2B_USD;
+ break;
}
return 0;
@@ -152,19 +112,36 @@ intel_ntb4_check_ppd(struct ntb_hw *hw)
return -EIO;
}
- reg_val = rte_read32(hw->hw_addr + XEON_GEN4_PPD1_OFFSET);
+ reg_val = rte_read32(hw->hw_addr + XEON_NTB4_PPD1_OFFSET);
- /* Distinguish HW platform (ICX/SPR) via PCI Revision ID */
- if (revision_id > NTB_PCI_DEV_REVISION_ICX_MAX)
- ret = intel_ntb4_check_ppd_for_SPR(hw, reg_val);
- else if (revision_id >= NTB_PCI_DEV_REVISION_ICX_MIN)
- ret = intel_ntb4_check_ppd_for_ICX(hw, reg_val);
- else {
- NTB_LOG(ERR, "Invalid NTB PCI Device Revision ID.");
- return -EIO;
+ /* Distinguish HW platform (3rd Gen Xeon) via PCI Revision ID */
+ if (revision_id <= NTB_PCI_DEV_REVISION_ICX_MAX &&
+ is_gen4_ntb(hw->pci_dev))
+ return intel_ntb4_check_ppd_for_ICX(hw, reg_val);
+
+ /* Check connection topo type. Only support B2B. */
+ switch (reg_val & XEON_NTB4_PPD_CONN_MASK) {
+ case XEON_NTB4_PPD_CONN_B2B:
+ NTB_LOG(INFO, "Topo B2B (back to back) is using.");
+ break;
+ default:
+ NTB_LOG(ERR, "Not supported conn topo. Please use B2B.");
+ return -EINVAL;
}
- return ret;
+ /* Check device config status. */
+ switch (reg_val & XEON_NTB4_PPD_DEV_MASK) {
+ case XEON_NTB4_PPD_DEV_DSD:
+ NTB_LOG(INFO, "DSD, Downstream Device.");
+ hw->topo = NTB_TOPO_B2B_DSD;
+ break;
+ case XEON_NTB4_PPD_DEV_USD:
+ NTB_LOG(INFO, "USD, Upstream device.");
+ hw->topo = NTB_TOPO_B2B_USD;
+ break;
+ }
+
+ return 0;
}
static int
@@ -181,10 +158,11 @@ intel_ntb_dev_init(const struct rte_rawdev *dev)
hw->hw_addr = (char *)hw->pci_dev->mem_resource[0].addr;
- if (is_gen3_ntb(hw))
+ if (is_gen3_ntb(hw->pci_dev))
+ /* PPD is in config space for NTB Gen3 */
ret = intel_ntb3_check_ppd(hw);
- else if (is_gen4_ntb(hw))
- /* PPD is in MMIO but not config space for NTB Gen4 */
+ else if (is_gen4_ntb(hw->pci_dev))
+ /* PPD is in MMIO for NTB Gen4 */
ret = intel_ntb4_check_ppd(hw);
else {
NTB_LOG(ERR, "Cannot init device for unsupported device.");
@@ -275,7 +253,7 @@ intel_ntb_mw_set_trans(const struct rte_rawdev *dev, int mw_idx,
rte_write64(base, xlat_addr);
rte_write64(limit, limit_addr);
- if (is_gen3_ntb(hw)) {
+ if (is_gen3_ntb(hw->pci_dev)) {
/* Setup the external point so that remote can access. */
xlat_off = XEON_EMBAR1_OFFSET + 8 * mw_idx;
xlat_addr = hw->hw_addr + xlat_off;
@@ -286,10 +264,10 @@ intel_ntb_mw_set_trans(const struct rte_rawdev *dev, int mw_idx,
base &= ~0xf;
limit = base + size;
rte_write64(limit, limit_addr);
- } else if (is_gen4_ntb(hw)) {
+ } else if (is_gen4_ntb(hw->pci_dev)) {
/* Set translate base address index register */
- xlat_off = XEON_GEN4_IM1XBASEIDX_OFFSET +
- mw_idx * XEON_GEN4_XBASEIDX_INTERVAL;
+ xlat_off = XEON_NTB4_IM1XBASEIDX_OFFSET +
+ mw_idx * XEON_XBASEIDX_INTERVAL;
xlat_addr = hw->hw_addr + xlat_off;
rte_write16(rte_log2_u64(size), xlat_addr);
} else {
@@ -335,16 +313,16 @@ intel_ntb_get_link_status(const struct rte_rawdev *dev)
return -EINVAL;
}
- if (is_gen3_ntb(hw)) {
- reg_off = XEON_GEN3_LINK_STATUS_OFFSET;
+ if (is_gen3_ntb(hw->pci_dev)) {
+ reg_off = XEON_NTB3_LINK_STATUS_OFFSET;
ret = rte_pci_read_config(hw->pci_dev, ®_val,
sizeof(reg_val), reg_off);
if (ret < 0) {
NTB_LOG(ERR, "Unable to get link status.");
return -EIO;
}
- } else if (is_gen4_ntb(hw)) {
- reg_off = XEON_GEN4_LINK_STATUS_OFFSET;
+ } else if (is_gen4_ntb(hw->pci_dev)) {
+ reg_off = XEON_NTB4_LINK_STATUS_OFFSET;
reg_val = rte_read16(hw->hw_addr + reg_off);
} else {
NTB_LOG(ERR, "Cannot get link status for unsupported device.");
@@ -402,20 +380,20 @@ intel_ntb_gen4_set_link(const struct ntb_hw *hw, bool up)
ntb_ctrl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP;
rte_write32(ntb_ctrl, reg_addr);
- reg_addr = hw->hw_addr + XEON_GEN4_LINK_CTRL_OFFSET;
+ reg_addr = hw->hw_addr + XEON_NTB4_LINK_CTRL_OFFSET;
link_ctrl = rte_read16(reg_addr);
- link_ctrl &= ~XEON_GEN4_LINK_CTRL_LINK_DIS;
+ link_ctrl &= ~XEON_NTB4_LINK_CTRL_LINK_DIS;
rte_write16(link_ctrl, reg_addr);
/* start link training */
- reg_addr = hw->hw_addr + XEON_GEN4_PPD0_OFFSET;
+ reg_addr = hw->hw_addr + XEON_NTB4_PPD0_OFFSET;
ppd0 = rte_read32(reg_addr);
- ppd0 |= XEON_GEN4_PPD_LINKTRN;
+ ppd0 |= XEON_NTB4_PPD_LINKTRN;
rte_write32(ppd0, reg_addr);
/* make sure link training has started */
ppd0 = rte_read32(reg_addr);
- if (!(ppd0 & XEON_GEN4_PPD_LINKTRN)) {
+ if (!(ppd0 & XEON_NTB4_PPD_LINKTRN)) {
NTB_LOG(ERR, "Link is not training.");
return -EINVAL;
}
@@ -426,9 +404,9 @@ intel_ntb_gen4_set_link(const struct ntb_hw *hw, bool up)
ntb_ctrl &= ~(NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP);
rte_write32(ntb_ctrl, reg_addr);
- reg_addr = hw->hw_addr + XEON_GEN4_LINK_CTRL_OFFSET;
+ reg_addr = hw->hw_addr + XEON_NTB4_LINK_CTRL_OFFSET;
link_ctrl = rte_read16(reg_addr);
- link_ctrl |= XEON_GEN4_LINK_CTRL_LINK_DIS;
+ link_ctrl |= XEON_NTB4_LINK_CTRL_LINK_DIS;
rte_write16(link_ctrl, reg_addr);
}
@@ -441,9 +419,9 @@ intel_ntb_set_link(const struct rte_rawdev *dev, bool up)
struct ntb_hw *hw = dev->dev_private;
int ret = 0;
- if (is_gen3_ntb(hw))
+ if (is_gen3_ntb(hw->pci_dev))
ret = intel_ntb_gen3_set_link(hw, up);
- else if (is_gen4_ntb(hw))
+ else if (is_gen4_ntb(hw->pci_dev))
ret = intel_ntb_gen4_set_link(hw, up);
else {
NTB_LOG(ERR, "Cannot set link for unsupported device.");
@@ -466,11 +444,11 @@ intel_ntb_spad_read(const struct rte_rawdev *dev, int spad, bool peer)
}
/* When peer is true, read peer spad reg */
- if (is_gen3_ntb(hw))
- reg_off = peer ? XEON_GEN3_B2B_SPAD_OFFSET :
+ if (is_gen3_ntb(hw->pci_dev))
+ reg_off = peer ? XEON_NTB3_B2B_SPAD_OFFSET :
XEON_IM_SPAD_OFFSET;
- else if (is_gen4_ntb(hw))
- reg_off = peer ? XEON_GEN4_B2B_SPAD_OFFSET :
+ else if (is_gen4_ntb(hw->pci_dev))
+ reg_off = peer ? XEON_NTB4_B2B_SPAD_OFFSET :
XEON_IM_SPAD_OFFSET;
else {
NTB_LOG(ERR, "Cannot read spad for unsupported device.");
@@ -496,11 +474,11 @@ intel_ntb_spad_write(const struct rte_rawdev *dev, int spad,
}
/* When peer is true, write peer spad reg */
- if (is_gen3_ntb(hw))
- reg_off = peer ? XEON_GEN3_B2B_SPAD_OFFSET :
+ if (is_gen3_ntb(hw->pci_dev))
+ reg_off = peer ? XEON_NTB3_B2B_SPAD_OFFSET :
XEON_IM_SPAD_OFFSET;
- else if (is_gen4_ntb(hw))
- reg_off = peer ? XEON_GEN4_B2B_SPAD_OFFSET :
+ else if (is_gen4_ntb(hw->pci_dev))
+ reg_off = peer ? XEON_NTB4_B2B_SPAD_OFFSET :
XEON_IM_SPAD_OFFSET;
else {
NTB_LOG(ERR, "Cannot write spad for unsupported device.");
@@ -538,9 +516,9 @@ intel_ntb_db_clear(const struct rte_rawdev *dev, uint64_t db_bits)
db_off = XEON_IM_INT_STATUS_OFFSET;
db_addr = hw->hw_addr + db_off;
- if (is_gen4_ntb(hw))
- rte_write16(XEON_GEN4_SLOTSTS_DLLSCS,
- hw->hw_addr + XEON_GEN4_SLOTSTS);
+ if (is_gen4_ntb(hw->pci_dev))
+ rte_write16(XEON_NTB4_SLOTSTS_DLLSCS,
+ hw->hw_addr + XEON_NTB4_SLOTSTS);
rte_write64(db_bits, db_addr);
return 0;
@@ -598,10 +576,10 @@ intel_ntb_vector_bind(const struct rte_rawdev *dev, uint8_t intr, uint8_t msix)
}
/* Bind intr source to msix vector */
- if (is_gen3_ntb(hw))
- reg_off = XEON_GEN3_INTVEC_OFFSET;
- else if (is_gen4_ntb(hw))
- reg_off = XEON_GEN4_INTVEC_OFFSET;
+ if (is_gen3_ntb(hw->pci_dev))
+ reg_off = XEON_NTB3_INTVEC_OFFSET;
+ else if (is_gen4_ntb(hw->pci_dev))
+ reg_off = XEON_NTB4_INTVEC_OFFSET;
else {
NTB_LOG(ERR, "Cannot bind vectors for unsupported device.");
return -ENOTSUP;
diff --git a/drivers/raw/ntb/ntb_hw_intel.h b/drivers/raw/ntb/ntb_hw_intel.h
index 9587104f80..5a45785b57 100644
--- a/drivers/raw/ntb/ntb_hw_intel.h
+++ b/drivers/raw/ntb/ntb_hw_intel.h
@@ -5,6 +5,8 @@
#ifndef _NTB_HW_INTEL_H_
#define _NTB_HW_INTEL_H_
+#include "ntb.h"
+
/* Supported PCI device revision ID range for ICX */
#define NTB_PCI_DEV_REVISION_ICX_MIN 0x02
#define NTB_PCI_DEV_REVISION_ICX_MAX 0x0F
@@ -38,13 +40,14 @@
#define XEON_DEVSTS_OFFSET 0x009a
#define XEON_UNCERRSTS_OFFSET 0x014c
#define XEON_CORERRSTS_OFFSET 0x0158
-#define XEON_GEN3_LINK_STATUS_OFFSET 0x01a2
-/* Link status and PPD are in MMIO but not config space for Gen4 NTB */
-#define XEON_GEN4_PPD0_OFFSET 0xb0d4
-#define XEON_GEN4_PPD1_OFFSET 0xb4c0
-#define XEON_GEN4_LINK_CTRL_OFFSET 0xb050
-#define XEON_GEN4_LINK_STATUS_OFFSET 0xb052
-#define XEON_GEN4_LINK_CTRL_LINK_DIS 0x0010
+#define XEON_NTB3_LINK_STATUS_OFFSET 0x01a2
+/* Link status and PPD are in MMIO but not config space for Gen4/5 NTB */
+#define XEON_NTB4_PPD0_OFFSET 0xb0d4
+#define XEON_NTB4_PPD1_OFFSET 0xb4c0
+#define XEON_NTB4_LINK_CTRL_OFFSET 0xb050
+#define XEON_NTB4_LINK_STATUS_OFFSET 0xb052
+#define XEON_NTB4_LINK_CTRL_LINK_DIS 0x0010
+
#define XEON_NTBCNTL_OFFSET 0x0000
#define XEON_BAR_INTERVAL_OFFSET 0x0010
@@ -52,17 +55,17 @@
#define XEON_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
#define XEON_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
#define XEON_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
-#define XEON_GEN4_XBASEIDX_INTERVAL 0x0002
-#define XEON_GEN4_IM1XBASEIDX_OFFSET 0x0074
-#define XEON_GEN4_IM2XBASEIDX_OFFSET 0x0076
+#define XEON_XBASEIDX_INTERVAL 0x0002
+#define XEON_NTB4_IM1XBASEIDX_OFFSET 0x0074
+#define XEON_NTB4_IM2XBASEIDX_OFFSET 0x0076
#define XEON_IM_INT_STATUS_OFFSET 0x0040
#define XEON_IM_INT_DISABLE_OFFSET 0x0048
#define XEON_IM_SPAD_OFFSET 0x0080 /* SPAD */
-#define XEON_GEN3_B2B_SPAD_OFFSET 0x0180 /* GEN3 B2B SPAD */
-#define XEON_GEN4_B2B_SPAD_OFFSET 0x8080 /* GEN4 B2B SPAD */
+#define XEON_NTB3_B2B_SPAD_OFFSET 0x0180 /* NTB GEN3 B2B SPAD */
+#define XEON_NTB4_B2B_SPAD_OFFSET 0x8080 /* NTB GEN4/5 B2B SPAD */
#define XEON_USMEMMISS_OFFSET 0x0070
-#define XEON_GEN3_INTVEC_OFFSET 0x00d0
-#define XEON_GEN4_INTVEC_OFFSET 0x0050
+#define XEON_NTB3_INTVEC_OFFSET 0x00d0
+#define XEON_NTB4_INTVEC_OFFSET 0x0050
#define XEON_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
#define XEON_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
#define XEON_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
@@ -78,30 +81,29 @@
#define XEON_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
#define XEON_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
-#define XEON_PPD_OFFSET 0x00d4
-#define XEON_PPD_CONN_MASK 0x03
-#define XEON_PPD_CONN_TRANSPARENT 0x00
-#define XEON_PPD_CONN_B2B 0x01
-#define XEON_PPD_CONN_RP 0x02
-#define XEON_PPD_DEV_MASK 0x10
-#define XEON_PPD_DEV_USD 0x00
-#define XEON_PPD_DEV_DSD 0x10
-#define XEON_PPD_SPLIT_BAR_MASK 0x40
-
-#define XEON_GEN4_PPD_CONN_MASK 0x0300
-#define XEON_GEN4_PPD_CONN_B2B 0x0200
-#define XEON_GEN4_PPD_DEV_MASK 0x1000
-#define XEON_GEN4_PPD_DEV_DSD 0x1000
-#define XEON_GEN4_PPD_DEV_USD 0x0000
-#define XEON_GEN4_PPD_LINKTRN 0x0008
-#define XEON_GEN4_SLOTSTS 0xb05a
-#define XEON_GEN4_SLOTSTS_DLLSCS 0x100
-
-#define XEON_SPR_PPD_CONN_MASK 0x0700
-#define XEON_SPR_PPD_CONN_B2B 0x0200
-#define XEON_SPR_PPD_DEV_MASK 0x4000
-#define XEON_SPR_PPD_DEV_DSD 0x4000
-#define XEON_SPR_PPD_DEV_USD 0x0000
+#define XEON_NTB3_PPD_OFFSET 0x00d4
+#define XEON_NTB3_PPD_CONN_MASK 0x03
+#define XEON_NTB3_PPD_CONN_B2B 0x01
+#define XEON_NTB3_PPD_DEV_MASK 0x10
+#define XEON_NTB3_PPD_DEV_USD 0x00
+#define XEON_NTB3_PPD_DEV_DSD 0x10
+#define XEON_NTB3_PPD_SPLIT_BAR_MASK 0x40
+
+#define XEON_GEN3_NTB4_PPD_CONN_MASK 0x0300
+#define XEON_GEN3_NTB4_PPD_CONN_B2B 0x0200
+#define XEON_GEN3_NTB4_PPD_DEV_MASK 0x1000
+#define XEON_GEN3_NTB4_PPD_DEV_DSD 0x1000
+#define XEON_GEN3_NTB4_PPD_DEV_USD 0x0000
+
+#define XEON_NTB4_PPD_CONN_MASK 0x0700
+#define XEON_NTB4_PPD_CONN_B2B 0x0200
+#define XEON_NTB4_PPD_DEV_MASK 0x4000
+#define XEON_NTB4_PPD_DEV_DSD 0x4000
+#define XEON_NTB4_PPD_DEV_USD 0x0000
+
+#define XEON_NTB4_PPD_LINKTRN 0x0008
+#define XEON_NTB4_SLOTSTS 0xb05a
+#define XEON_NTB4_SLOTSTS_DLLSCS 0x100
#define XEON_MW_COUNT 2
@@ -115,4 +117,16 @@
extern const struct ntb_dev_ops intel_ntb_ops;
+static inline bool
+is_gen3_ntb(const struct rte_pci_device *pci_dev)
+{
+ return pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_GEN3;
+}
+
+static inline bool
+is_gen4_ntb(const struct rte_pci_device *pci_dev)
+{
+ return pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_GEN4;
+}
+
#endif /* _NTB_HW_INTEL_H_ */
diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index a278f5e7f3..230c81c5f3 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -60,10 +60,8 @@
'SVendor': None, 'SDevice': None}
intel_idxd_spr = {'Class': '08', 'Vendor': '8086', 'Device': '0b25',
'SVendor': None, 'SDevice': None}
-intel_ntb_skx = {'Class': '06', 'Vendor': '8086', 'Device': '201c',
- 'SVendor': None, 'SDevice': None}
-intel_ntb_icx = {'Class': '06', 'Vendor': '8086', 'Device': '347e',
- 'SVendor': None, 'SDevice': None}
+intel_ntb = {'Class': '06', 'Vendor': '8086', 'Device': '201c,347e',
+ 'SVendor': None, 'SDevice': None}
cnxk_sso = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f9,a0fa',
'SVendor': None, 'SDevice': None}
@@ -89,7 +87,7 @@
regex_devices = [cn9k_ree]
ml_devices = [cnxk_ml]
misc_devices = [cnxk_bphy, cnxk_bphy_cgx, cnxk_inl_dev,
- intel_ntb_skx, intel_ntb_icx,
+ intel_ntb,
virtio_blk]
# global dict ethernet devices present. Dictionary indexed by PCI address.
--
2.34.1
^ permalink raw reply [flat|nested] 2+ messages in thread* Re: [PATCH] raw/ntb: refactor to support NTB on 5th Gen Intel Xeon
2023-12-06 3:00 [PATCH] raw/ntb: refactor to support NTB on 5th Gen Intel Xeon Junfeng Guo
@ 2024-10-07 20:12 ` Stephen Hemminger
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Hemminger @ 2024-10-07 20:12 UTC (permalink / raw)
To: Junfeng Guo; +Cc: jingjing.wu, dev, omkar.maslekar
On Wed, 6 Dec 2023 11:00:25 +0800
Junfeng Guo <junfeng.guo@intel.com> wrote:
> Refactor to support for 5th Gen Intel Xeon Scalable processors. Note that
> NTB devices within the 3rd, 4th and 5th Gen Intel Xeon Scalable processors
> share the same device id, and compliant to PCIe 4.0 spec.
> It is more reasonable to distinguish NTB devices by their PCIe generation.
>
> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
> ---
> doc/guides/rawdevs/ntb.rst | 7 +-
> doc/guides/rel_notes/release_24_03.rst | 4 +
Needs to be rebased to target the correct release note.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-12-06 3:00 [PATCH] raw/ntb: refactor to support NTB on 5th Gen Intel Xeon Junfeng Guo
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