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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509EC.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8P190MB1173 X-BESS-ID: 1728329716-311201-2749-3510-1 X-BESS-VER: 2019.1_20241004.2057 X-BESS-Apparent-Source-IP: 104.47.30.107 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVkYmxoYWQGYGUDTFONEkNdHCID kx1cjMMM3cyCLJIjHF0NQixdgsKTHVXKk2FgBAMPPlQgAAAA== X-BESS-Outbound-Spam-Score: 1.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.259566 [from cloudscan16-140.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.50 BSF_RULE_7582B META: Custom Rule 7582B X-BESS-Outbound-Spam-Status: SCORE=1.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND, BSF_RULE_7582B X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Oleksandr Kolomeiets The Hasher module calculates a configurable hash value to be used internally by the FPGA. The module support both Toeplitz and NT-hash. Signed-off-by: Oleksandr Kolomeiets --- drivers/net/ntnic/include/hw_mod_backend.h | 16 ++ drivers/net/ntnic/include/hw_mod_hsh_v5.h | 46 ++++ drivers/net/ntnic/meson.build | 1 + .../nthw/flow_api/flow_backend/flow_backend.c | 80 ++++++ .../ntnic/nthw/flow_filter/flow_nthw_hsh.c | 260 ++++++++++++++++++ .../ntnic/nthw/flow_filter/flow_nthw_hsh.h | 87 ++++++ .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 + .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 + .../nthw/supported/nthw_fpga_reg_defs_hsh.h | 50 ++++ 9 files changed, 542 insertions(+) create mode 100644 drivers/net/ntnic/include/hw_mod_hsh_v5.h create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_hsh.c create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_hsh.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h index 133a61fe9c..a4c3336e13 100644 --- a/drivers/net/ntnic/include/hw_mod_backend.h +++ b/drivers/net/ntnic/include/hw_mod_backend.h @@ -12,6 +12,7 @@ #include "hw_mod_cat_v21.h" #include "hw_mod_flm_v25.h" #include "hw_mod_km_v7.h" +#include "hw_mod_hsh_v5.h" #define MAX_PHYS_ADAPTERS 8 @@ -75,6 +76,16 @@ struct flm_func_s { }; }; +struct hsh_func_s { + COMMON_FUNC_INFO_S; + uint32_t nb_rcp;/* number of HSH recipes supported by FPGA */ + /* indication if Toeplitz is supported by FPGA, i.e. 0 - unsupported, 1 - supported */ + uint32_t toeplitz; + union { + struct hw_mod_hsh_v5_s v5; + }; +}; + enum debug_mode_e { FLOW_BACKEND_DEBUG_MODE_NONE = 0x0000, FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001 @@ -180,6 +191,11 @@ struct flow_api_backend_ops { uint32_t *inf_data, uint32_t inf_size, uint32_t *inf_word_cnt, uint32_t *sta_data, uint32_t sta_size, uint32_t *sta_word_cnt); + + /* HSH */ + bool (*get_hsh_present)(void *dev); + uint32_t (*get_hsh_version)(void *dev); + int (*hsh_rcp_flush)(void *dev, const struct hsh_func_s *hsh, int category, int cnt); }; struct flow_api_backend_s { diff --git a/drivers/net/ntnic/include/hw_mod_hsh_v5.h b/drivers/net/ntnic/include/hw_mod_hsh_v5.h new file mode 100644 index 0000000000..cdab15e6c2 --- /dev/null +++ b/drivers/net/ntnic/include/hw_mod_hsh_v5.h @@ -0,0 +1,46 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _HW_MOD_HSH_V5_H_ +#define _HW_MOD_HSH_V5_H_ + +#include + +#define HSH_RCP_MAC_PORT_MASK_SIZE 4 +#define HSH_RCP_WORD_MASK_SIZE 10 +/* Toeplitz hash key size in 32-bit words, e.g. 10 words means 320 bits, i.e. 40 Bytes */ +#define HSH_RCP_KEY_SIZE 10 + +struct hsh_v5_rcp_s { + uint32_t load_dist_type; + uint32_t mac_port_mask[HSH_RCP_MAC_PORT_MASK_SIZE]; + uint32_t sort; + uint32_t qw0_pe; + int32_t qw0_ofs; + uint32_t qw4_pe; + int32_t qw4_ofs; + uint32_t w8_pe; + int32_t w8_ofs; + uint32_t w8_sort; + uint32_t w9_pe; + int32_t w9_ofs; + uint32_t w9_sort; + uint32_t w9_p; + uint32_t p_mask; + uint32_t word_mask[HSH_RCP_WORD_MASK_SIZE]; + uint32_t seed; + uint32_t tnl_p; + uint32_t hsh_valid; + uint32_t hsh_type; + uint32_t toeplitz; /* Toeplitz enabled / disabled */ + uint32_t k[HSH_RCP_KEY_SIZE]; /* Toeplitz hash key */ + uint32_t auto_ipv4_mask; +}; + +struct hw_mod_hsh_v5_s { + struct hsh_v5_rcp_s *rcp; +}; + +#endif /* _HW_MOD_HSH_V5_H_ */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 1ca34d8b47..de6777f4d3 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -48,6 +48,7 @@ sources = files( 'nthw/flow_api/flow_filter.c', 'nthw/flow_filter/flow_nthw_cat.c', 'nthw/flow_filter/flow_nthw_flm.c', + 'nthw/flow_filter/flow_nthw_hsh.c', 'nthw/flow_filter/flow_nthw_ifr.c', 'nthw/flow_filter/flow_nthw_info.c', 'nthw/flow_filter/flow_nthw_km.c', diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c index 5d2c09d52a..86a7da2334 100644 --- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c +++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c @@ -10,6 +10,7 @@ #include "flow_nthw_cat.h" #include "flow_nthw_km.h" #include "flow_nthw_flm.h" +#include "flow_nthw_hsh.h" #include "ntnic_mod_reg.h" #include "nthw_fpga_model.h" #include "hw_mod_backend.h" @@ -28,6 +29,7 @@ static struct backend_dev_s { struct cat_nthw *p_cat_nthw; struct km_nthw *p_km_nthw; struct flm_nthw *p_flm_nthw; + struct hsh_nthw *p_hsh_nthw; struct ifr_nthw *p_ifr_nthw; /* TPE module */ } be_devs[MAX_PHYS_ADAPTERS]; @@ -1260,6 +1262,69 @@ static int flm_inf_sta_data_update(void *be_dev, const struct flm_func_s *flm, u return ret; } +/* + * HSH + */ + +static bool hsh_get_present(void *be_dev) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + return be->p_hsh_nthw != NULL; +} + +static uint32_t hsh_get_version(void *be_dev) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + return (uint32_t)((nthw_module_get_major_version(be->p_hsh_nthw->m_hsh) << 16) | + (nthw_module_get_minor_version(be->p_hsh_nthw->m_hsh) & 0xffff)); +} + +static int hsh_rcp_flush(void *be_dev, const struct hsh_func_s *hsh, int category, int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, hsh, be->p_hsh_nthw); + + if (hsh->ver == 5) { + hsh_nthw_rcp_cnt(be->p_hsh_nthw, 1); + + for (int i = 0; i < cnt; i++) { + hsh_nthw_rcp_select(be->p_hsh_nthw, category + i); + hsh_nthw_rcp_load_dist_type(be->p_hsh_nthw, + hsh->v5.rcp[category + i].load_dist_type); + hsh_nthw_rcp_mac_port_mask(be->p_hsh_nthw, + hsh->v5.rcp[category + i].mac_port_mask); + hsh_nthw_rcp_sort(be->p_hsh_nthw, hsh->v5.rcp[category + i].sort); + hsh_nthw_rcp_qw0_pe(be->p_hsh_nthw, hsh->v5.rcp[category + i].qw0_pe); + hsh_nthw_rcp_qw0_ofs(be->p_hsh_nthw, hsh->v5.rcp[category + i].qw0_ofs); + hsh_nthw_rcp_qw4_pe(be->p_hsh_nthw, hsh->v5.rcp[category + i].qw4_pe); + hsh_nthw_rcp_qw4_ofs(be->p_hsh_nthw, hsh->v5.rcp[category + i].qw4_ofs); + hsh_nthw_rcp_w8_pe(be->p_hsh_nthw, hsh->v5.rcp[category + i].w8_pe); + hsh_nthw_rcp_w8_ofs(be->p_hsh_nthw, hsh->v5.rcp[category + i].w8_ofs); + hsh_nthw_rcp_w8_sort(be->p_hsh_nthw, hsh->v5.rcp[category + i].w8_sort); + hsh_nthw_rcp_w9_pe(be->p_hsh_nthw, hsh->v5.rcp[category + i].w9_pe); + hsh_nthw_rcp_w9_ofs(be->p_hsh_nthw, hsh->v5.rcp[category + i].w9_ofs); + hsh_nthw_rcp_w9_sort(be->p_hsh_nthw, hsh->v5.rcp[category + i].w9_sort); + hsh_nthw_rcp_w9_p(be->p_hsh_nthw, hsh->v5.rcp[category + i].w9_p); + hsh_nthw_rcp_p_mask(be->p_hsh_nthw, hsh->v5.rcp[category + i].p_mask); + hsh_nthw_rcp_word_mask(be->p_hsh_nthw, + hsh->v5.rcp[category + i].word_mask); + hsh_nthw_rcp_seed(be->p_hsh_nthw, hsh->v5.rcp[category + i].seed); + hsh_nthw_rcp_tnl_p(be->p_hsh_nthw, hsh->v5.rcp[category + i].tnl_p); + hsh_nthw_rcp_hsh_valid(be->p_hsh_nthw, + hsh->v5.rcp[category + i].hsh_valid); + hsh_nthw_rcp_hsh_type(be->p_hsh_nthw, hsh->v5.rcp[category + i].hsh_type); + hsh_nthw_rcp_toeplitz(be->p_hsh_nthw, hsh->v5.rcp[category + i].toeplitz); + hsh_nthw_rcp_k(be->p_hsh_nthw, hsh->v5.rcp[category + i].k); + hsh_nthw_rcp_auto_ipv4_mask(be->p_hsh_nthw, + hsh->v5.rcp[category + i].auto_ipv4_mask); + hsh_nthw_rcp_flush(be->p_hsh_nthw); + } + } + + CHECK_DEBUG_OFF(hsh, be->p_hsh_nthw); + return 0; +} + /* * DBS */ @@ -1369,6 +1434,10 @@ const struct flow_api_backend_ops flow_be_iface = { flm_stat_update, flm_lrn_data_flush, flm_inf_sta_data_update, + + hsh_get_present, + hsh_get_version, + hsh_rcp_flush, }; const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, void **dev) @@ -1419,6 +1488,16 @@ const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, vo be_devs[physical_adapter_no].p_ifr_nthw = NULL; } + /* Init nthw HSH */ + if (hsh_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) { + struct hsh_nthw *phshnthw = hsh_nthw_new(); + hsh_nthw_init(phshnthw, p_fpga, physical_adapter_no); + be_devs[physical_adapter_no].p_hsh_nthw = phshnthw; + + } else { + be_devs[physical_adapter_no].p_hsh_nthw = NULL; + } + be_devs[physical_adapter_no].adapter_no = physical_adapter_no; *dev = (void *)&be_devs[physical_adapter_no]; @@ -1432,6 +1511,7 @@ static void bin_flow_backend_done(void *dev) cat_nthw_delete(be_dev->p_cat_nthw); km_nthw_delete(be_dev->p_km_nthw); flm_nthw_delete(be_dev->p_flm_nthw); + hsh_nthw_delete(be_dev->p_hsh_nthw); } static const struct flow_backend_ops ops = { diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hsh.c b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hsh.c new file mode 100644 index 0000000000..c878c4e54b --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hsh.c @@ -0,0 +1,260 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "flow_nthw_hsh.h" + +void hsh_nthw_set_debug_mode(struct hsh_nthw *p, unsigned int n_debug_mode) +{ + nthw_module_set_debug_mode(p->m_hsh, n_debug_mode); +} + +struct hsh_nthw *hsh_nthw_new(void) +{ + struct hsh_nthw *p = malloc(sizeof(struct hsh_nthw)); + + if (p) + (void)memset(p, 0, sizeof(*p)); + + return p; +} + +void hsh_nthw_delete(struct hsh_nthw *p) +{ + if (p) { + (void)memset(p, 0, sizeof(*p)); + free(p); + } +} + +int hsh_nthw_init(struct hsh_nthw *p, nthw_fpga_t *p_fpga, int n_instance) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_HSH, n_instance); + assert(n_instance >= 0 && n_instance < 256); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: Hsh %d: no such instance\n", p_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->m_physical_adapter_no = (uint8_t)n_instance; + p->m_hsh = p_mod; + + /* RCP */ + p->mp_rcp_ctrl = nthw_module_get_register(p->m_hsh, HSH_RCP_CTRL); + p->mp_rcp_addr = nthw_register_get_field(p->mp_rcp_ctrl, HSH_RCP_CTRL_ADR); + p->mp_rcp_cnt = nthw_register_get_field(p->mp_rcp_ctrl, HSH_RCP_CTRL_CNT); + p->mp_rcp_data = nthw_module_get_register(p->m_hsh, HSH_RCP_DATA); + p->mp_rcp_data_load_dist_type = + nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_LOAD_DIST_TYPE); + p->mp_rcp_data_mac_port_mask = + nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_MAC_PORT_MASK); + p->mp_rcp_data_sort = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_SORT); + p->mp_rcp_data_qw0_pe = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_QW0_PE); + p->mp_rcp_data_qw0_ofs = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_QW0_OFS); + p->mp_rcp_data_qw4_pe = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_QW4_PE); + p->mp_rcp_data_qw4_ofs = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_QW4_OFS); + p->mp_rcp_data_w8_pe = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_W8_PE); + p->mp_rcp_data_w8_ofs = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_W8_OFS); + p->mp_rcp_data_w8_sort = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_W8_SORT); + p->mp_rcp_data_w9_pe = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_W9_PE); + p->mp_rcp_data_w9_ofs = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_W9_OFS); + p->mp_rcp_data_w9_sort = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_W9_SORT); + p->mp_rcp_data_w9_p = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_W9_P); + p->mp_rcp_data_p_mask = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_P_MASK); + p->mp_rcp_data_word_mask = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_WORD_MASK); + p->mp_rcp_data_seed = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_SEED); + p->mp_rcp_data_tnl_p = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_TNL_P); + p->mp_rcp_data_hsh_valid = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_HSH_VALID); + p->mp_rcp_data_hsh_type = nthw_register_get_field(p->mp_rcp_data, HSH_RCP_DATA_HSH_TYPE); + p->mp_rcp_data_toeplitz = nthw_register_query_field(p->mp_rcp_data, HSH_RCP_DATA_TOEPLITZ); + p->mp_rcp_data_k = nthw_register_query_field(p->mp_rcp_data, HSH_RCP_DATA_K); + p->mp_rcp_data_auto_ipv4_mask = + nthw_register_query_field(p->mp_rcp_data, HSH_RCP_DATA_AUTO_IPV4_MASK); + + /* Init */ + uint32_t val[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + nthw_field_set_val32(p->mp_rcp_addr, 0); + nthw_field_set_val32(p->mp_rcp_cnt, 1); + + nthw_field_set_val32(p->mp_rcp_data_load_dist_type, 0); + nthw_field_set_val(p->mp_rcp_data_mac_port_mask, val, + p->mp_rcp_data_mac_port_mask->mn_words); + nthw_field_set_val32(p->mp_rcp_data_sort, 0); + nthw_field_set_val32(p->mp_rcp_data_qw0_pe, 0); + nthw_field_set_val32(p->mp_rcp_data_qw0_ofs, 0); + nthw_field_set_val32(p->mp_rcp_data_qw4_pe, 0); + nthw_field_set_val32(p->mp_rcp_data_qw4_ofs, 0); + nthw_field_set_val32(p->mp_rcp_data_w8_pe, 0); + nthw_field_set_val32(p->mp_rcp_data_w8_ofs, 0); + nthw_field_set_val32(p->mp_rcp_data_w8_sort, 0); + nthw_field_set_val32(p->mp_rcp_data_w9_pe, 0); + nthw_field_set_val32(p->mp_rcp_data_w9_ofs, 0); + nthw_field_set_val32(p->mp_rcp_data_w9_sort, 0); + nthw_field_set_val32(p->mp_rcp_data_w9_p, 0); + nthw_field_set_val(p->mp_rcp_data_word_mask, val, 10); + nthw_field_set_val32(p->mp_rcp_data_seed, 0); + nthw_field_set_val32(p->mp_rcp_data_tnl_p, 0); + nthw_field_set_val32(p->mp_rcp_data_hsh_valid, 0); + nthw_field_set_val32(p->mp_rcp_data_hsh_type, 31); + + if (p->mp_rcp_data_toeplitz) + nthw_field_set_val32(p->mp_rcp_data_toeplitz, 0); + + if (p->mp_rcp_data_k) + nthw_field_set_val(p->mp_rcp_data_k, val, 10); + + nthw_register_flush(p->mp_rcp_ctrl, 1); + nthw_register_flush(p->mp_rcp_data, 1); + + return 0; +} + +void hsh_nthw_rcp_select(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_addr, val); +} + +void hsh_nthw_rcp_cnt(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_cnt, val); +} + +void hsh_nthw_rcp_load_dist_type(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_load_dist_type, val); +} + +void hsh_nthw_rcp_mac_port_mask(const struct hsh_nthw *p, uint32_t *val) +{ + nthw_field_set_val(p->mp_rcp_data_mac_port_mask, val, + p->mp_rcp_data_mac_port_mask->mn_words); +} + +void hsh_nthw_rcp_sort(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_sort, val); +} + +void hsh_nthw_rcp_qw0_pe(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw0_pe, val); +} + +void hsh_nthw_rcp_qw0_ofs(const struct hsh_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw0_ofs, val); +} + +void hsh_nthw_rcp_qw4_pe(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw4_pe, val); +} + +void hsh_nthw_rcp_qw4_ofs(const struct hsh_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_qw4_ofs, val); +} + +void hsh_nthw_rcp_w8_pe(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_w8_pe, val); +} + +void hsh_nthw_rcp_w8_ofs(const struct hsh_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_w8_ofs, val); +} + +void hsh_nthw_rcp_w8_sort(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_w8_sort, val); +} + +void hsh_nthw_rcp_w9_pe(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_w9_pe, val); +} + +void hsh_nthw_rcp_w9_ofs(const struct hsh_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_w9_ofs, val); +} + +void hsh_nthw_rcp_w9_sort(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_w9_sort, val); +} + +void hsh_nthw_rcp_w9_p(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_w9_p, val); +} + +void hsh_nthw_rcp_p_mask(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_p_mask, val); +} + +void hsh_nthw_rcp_word_mask(const struct hsh_nthw *p, uint32_t *val) +{ + nthw_field_set_val(p->mp_rcp_data_word_mask, val, 10); +} + +void hsh_nthw_rcp_seed(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_seed, val); +} + +void hsh_nthw_rcp_tnl_p(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tnl_p, val); +} + +void hsh_nthw_rcp_hsh_valid(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_hsh_valid, val); +} + +void hsh_nthw_rcp_hsh_type(const struct hsh_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_hsh_type, val); +} + +void hsh_nthw_rcp_toeplitz(const struct hsh_nthw *p, uint32_t val) +{ + if (p->mp_rcp_data_toeplitz) + nthw_field_set_val32(p->mp_rcp_data_toeplitz, val); +} + +void hsh_nthw_rcp_k(const struct hsh_nthw *p, uint32_t *val) +{ + if (p->mp_rcp_data_k) + nthw_field_set_val(p->mp_rcp_data_k, val, 10); +} + +void hsh_nthw_rcp_auto_ipv4_mask(const struct hsh_nthw *p, uint32_t val) +{ + if (p->mp_rcp_data_auto_ipv4_mask) + nthw_field_set_val32(p->mp_rcp_data_auto_ipv4_mask, val); +} + +void hsh_nthw_rcp_flush(const struct hsh_nthw *p) +{ + nthw_register_flush(p->mp_rcp_ctrl, 1); + nthw_register_flush(p->mp_rcp_data, 1); +} diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hsh.h b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hsh.h new file mode 100644 index 0000000000..70626122e3 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_hsh.h @@ -0,0 +1,87 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __FLOW_NTHW_HSH_H__ +#define __FLOW_NTHW_HSH_H__ + +#include + +#include "nthw_fpga_model.h" + +struct hsh_nthw; + +typedef struct hsh_nthw hsh_nthw_t; + +struct hsh_nthw *hsh_nthw_new(void); +void hsh_nthw_delete(struct hsh_nthw *p); +int hsh_nthw_init(struct hsh_nthw *p, nthw_fpga_t *p_fpga, int n_instance); + +int hsh_nthw_setup(struct hsh_nthw *p, int n_idx, int n_idx_cnt); +void hsh_nthw_set_debug_mode(struct hsh_nthw *p, unsigned int n_debug_mode); + +/* RCP */ +void hsh_nthw_rcp_select(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_cnt(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_load_dist_type(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_mac_port_mask(const struct hsh_nthw *p, uint32_t *val); +void hsh_nthw_rcp_sort(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_qw0_pe(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_qw0_ofs(const struct hsh_nthw *p, int32_t val); +void hsh_nthw_rcp_qw4_pe(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_qw4_ofs(const struct hsh_nthw *p, int32_t val); +void hsh_nthw_rcp_w8_pe(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_w8_ofs(const struct hsh_nthw *p, int32_t val); +void hsh_nthw_rcp_w8_sort(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_w9_pe(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_w9_ofs(const struct hsh_nthw *p, int32_t val); +void hsh_nthw_rcp_w9_sort(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_w9_p(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_p_mask(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_word_mask(const struct hsh_nthw *p, uint32_t *val); +void hsh_nthw_rcp_seed(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_tnl_p(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_hsh_valid(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_hsh_type(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_toeplitz(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_k(const struct hsh_nthw *p, uint32_t *val); +void hsh_nthw_rcp_auto_ipv4_mask(const struct hsh_nthw *p, uint32_t val); +void hsh_nthw_rcp_flush(const struct hsh_nthw *p); + +struct hsh_nthw { + uint8_t m_physical_adapter_no; + nthw_fpga_t *mp_fpga; + + nthw_module_t *m_hsh; + + nthw_register_t *mp_rcp_ctrl; + nthw_field_t *mp_rcp_addr; + nthw_field_t *mp_rcp_cnt; + nthw_register_t *mp_rcp_data; + nthw_field_t *mp_rcp_data_load_dist_type; + nthw_field_t *mp_rcp_data_mac_port_mask; + nthw_field_t *mp_rcp_data_sort; + nthw_field_t *mp_rcp_data_qw0_pe; + nthw_field_t *mp_rcp_data_qw0_ofs; + nthw_field_t *mp_rcp_data_qw4_pe; + nthw_field_t *mp_rcp_data_qw4_ofs; + nthw_field_t *mp_rcp_data_w8_pe; + nthw_field_t *mp_rcp_data_w8_ofs; + nthw_field_t *mp_rcp_data_w8_sort; + nthw_field_t *mp_rcp_data_w9_pe; + nthw_field_t *mp_rcp_data_w9_ofs; + nthw_field_t *mp_rcp_data_w9_sort; + nthw_field_t *mp_rcp_data_w9_p; + nthw_field_t *mp_rcp_data_p_mask; + nthw_field_t *mp_rcp_data_word_mask; + nthw_field_t *mp_rcp_data_seed; + nthw_field_t *mp_rcp_data_tnl_p; + nthw_field_t *mp_rcp_data_hsh_valid; + nthw_field_t *mp_rcp_data_hsh_type; + nthw_field_t *mp_rcp_data_toeplitz; + nthw_field_t *mp_rcp_data_k; + nthw_field_t *mp_rcp_data_auto_ipv4_mask; +}; + +#endif /* __FLOW_NTHW_HSH_H__ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h index 6b2b5334da..a929a98b52 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -20,6 +20,7 @@ #define MOD_GMF (0x68b1d15aUL) #define MOD_GPIO_PHY (0xbbe81659UL) #define MOD_HIF (0x7815363UL) +#define MOD_HSH (0x501484bfUL) #define MOD_I2CM (0x93bc7780UL) #define MOD_IFR (0x9b01f1e6UL) #define MOD_IIC (0x7629cddbUL) diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h index 38b222363e..9155cc4435 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h @@ -19,6 +19,7 @@ #include "nthw_fpga_reg_defs_gmf.h" #include "nthw_fpga_reg_defs_gpio_phy.h" #include "nthw_fpga_reg_defs_hif.h" +#include "nthw_fpga_reg_defs_hsh.h" #include "nthw_fpga_reg_defs_i2cm.h" #include "nthw_fpga_reg_defs_ifr.h" #include "nthw_fpga_reg_defs_iic.h" diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h new file mode 100644 index 0000000000..fb95a514de --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hsh.h @@ -0,0 +1,50 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +/* + * nthw_fpga_reg_defs_hsh.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_HSH_ +#define _NTHW_FPGA_REG_DEFS_HSH_ + +/* HSH */ +#define NTHW_MOD_HSH (0x501484bfUL) +#define HSH_RCP_CTRL (0xb257f1b9UL) +#define HSH_RCP_CTRL_ADR (0x5685bfbUL) +#define HSH_RCP_CTRL_CNT (0x1560c22aUL) +#define HSH_RCP_DATA (0x1d8673a0UL) +#define HSH_RCP_DATA_AUTO_IPV4_MASK (0xa0d4de3bUL) +#define HSH_RCP_DATA_HSH_TYPE (0x14cd0865UL) +#define HSH_RCP_DATA_HSH_VALID (0xc89b0bd3UL) +#define HSH_RCP_DATA_K (0xccdb0222UL) +#define HSH_RCP_DATA_LOAD_DIST_TYPE (0x152a0a87UL) +#define HSH_RCP_DATA_MAC_PORT_MASK (0x5160b288UL) +#define HSH_RCP_DATA_P_MASK (0x8a555abbUL) +#define HSH_RCP_DATA_QW0_OFS (0x276b79cfUL) +#define HSH_RCP_DATA_QW0_PE (0x32014a20UL) +#define HSH_RCP_DATA_QW4_OFS (0xd2ebdf0fUL) +#define HSH_RCP_DATA_QW4_PE (0xbd63dd77UL) +#define HSH_RCP_DATA_SEED (0xf8fc2c1cUL) +#define HSH_RCP_DATA_SORT (0xed5f3d38UL) +#define HSH_RCP_DATA_TNL_P (0x6e56b51eUL) +#define HSH_RCP_DATA_TOEPLITZ (0xc1864a45UL) +#define HSH_RCP_DATA_W8_OFS (0x68150d02UL) +#define HSH_RCP_DATA_W8_PE (0x9387d583UL) +#define HSH_RCP_DATA_W8_SORT (0x5c67eca8UL) +#define HSH_RCP_DATA_W9_OFS (0x557524b2UL) +#define HSH_RCP_DATA_W9_P (0x808204d9UL) +#define HSH_RCP_DATA_W9_PE (0x2b3bb2e6UL) +#define HSH_RCP_DATA_W9_SORT (0x973b3f0dUL) +#define HSH_RCP_DATA_WORD_MASK (0x55c53a1fUL) + +#endif /* _NTHW_FPGA_REG_DEFS_HSH_ */ + +/* + * Auto-generated file - do *NOT* edit + */ -- 2.45.0