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From: Serhii Iliushyk <sil-plv@napatech.com>
To: dev@dpdk.org
Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com,
andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com,
Oleksandr Kolomeiets <okl-plv@napatech.com>
Subject: [PATCH v2 31/50] net/ntnic: add hasher (HSH) FPGA module
Date: Mon, 7 Oct 2024 21:34:07 +0200
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From: Oleksandr Kolomeiets <okl-plv@napatech.com>
The Hasher module calculates a configurable hash value
to be used internally by the FPGA.
The module support both Toeplitz and NT-hash.
Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
drivers/net/ntnic/include/hw_mod_backend.h | 36 ++++++++
drivers/net/ntnic/meson.build | 1 +
drivers/net/ntnic/nthw/flow_api/flow_api.c | 3 +
.../nthw/flow_api/hw_mod/hw_mod_backend.c | 1 +
.../ntnic/nthw/flow_api/hw_mod/hw_mod_hsh.c | 84 +++++++++++++++++++
.../supported/nthw_fpga_9563_055_049_0000.c | 39 ++++++++-
6 files changed, 163 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_hsh.c
diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h
index 3933d4bf53..6bf651272f 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -493,6 +493,41 @@ struct hsh_func_s {
struct hw_mod_hsh_v5_s v5;
};
};
+enum hw_hsh_e {
+ /* functions */
+ HW_HSH_RCP_PRESET_ALL = 0,
+ HW_HSH_RCP_COMPARE,
+ HW_HSH_RCP_FIND,
+ /* fields */
+ HW_HSH_RCP_LOAD_DIST_TYPE = FIELD_START_INDEX,
+ HW_HSH_RCP_MAC_PORT_MASK,
+ HW_HSH_RCP_SORT,
+ HW_HSH_RCP_QW0_PE,
+ HW_HSH_RCP_QW0_OFS,
+ HW_HSH_RCP_QW4_PE,
+ HW_HSH_RCP_QW4_OFS,
+ HW_HSH_RCP_W8_PE,
+ HW_HSH_RCP_W8_OFS,
+ HW_HSH_RCP_W8_SORT,
+ HW_HSH_RCP_W9_PE,
+ HW_HSH_RCP_W9_OFS,
+ HW_HSH_RCP_W9_SORT,
+ HW_HSH_RCP_W9_P,
+ HW_HSH_RCP_P_MASK,
+ HW_HSH_RCP_WORD_MASK,
+ HW_HSH_RCP_SEED,
+ HW_HSH_RCP_TNL_P,
+ HW_HSH_RCP_HSH_VALID,
+ HW_HSH_RCP_HSH_TYPE,
+ HW_HSH_RCP_TOEPLITZ,
+ HW_HSH_RCP_K,
+ HW_HSH_RCP_AUTO_IPV4_MASK
+};
+bool hw_mod_hsh_present(struct flow_api_backend_s *be);
+int hw_mod_hsh_alloc(struct flow_api_backend_s *be);
+void hw_mod_hsh_free(struct flow_api_backend_s *be);
+int hw_mod_hsh_reset(struct flow_api_backend_s *be);
+int hw_mod_hsh_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count);
struct qsl_func_s {
COMMON_FUNC_INFO_S;
@@ -685,6 +720,7 @@ struct flow_api_backend_s {
struct cat_func_s cat;
struct km_func_s km;
struct flm_func_s flm;
+ struct hsh_func_s hsh;
/* NIC attributes */
unsigned int num_phy_ports;
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index 9af7e3d813..18aafc57f0 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -51,6 +51,7 @@ sources = files(
'nthw/flow_api/hw_mod/hw_mod_backend.c',
'nthw/flow_api/hw_mod/hw_mod_cat.c',
'nthw/flow_api/hw_mod/hw_mod_flm.c',
+ 'nthw/flow_api/hw_mod/hw_mod_hsh.c',
'nthw/flow_api/hw_mod/hw_mod_km.c',
'nthw/flow_filter/flow_nthw_cat.c',
'nthw/flow_filter/flow_nthw_csu.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_api.c b/drivers/net/ntnic/nthw/flow_api/flow_api.c
index d39bdc9936..b43c8fef1a 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_api.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_api.c
@@ -290,6 +290,9 @@ struct flow_nic_dev *flow_api_create(uint8_t adapter_no, const struct flow_api_b
if (init_resource_elements(ndev, RES_KM_CATEGORY, ndev->be.km.nb_categories))
goto err_exit;
+ if (init_resource_elements(ndev, RES_HSH_RCP, ndev->be.hsh.nb_rcp))
+ goto err_exit;
+
if (init_resource_elements(ndev, RES_SLC_LR_RCP, ndev->be.max_categories))
goto err_exit;
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
index fe66493336..3ccc14c4ce 100644
--- a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_backend.c
@@ -20,6 +20,7 @@ static const struct {
{ "CAT", hw_mod_cat_alloc, hw_mod_cat_free, hw_mod_cat_reset, hw_mod_cat_present },
{ "KM", hw_mod_km_alloc, hw_mod_km_free, hw_mod_km_reset, hw_mod_km_present },
{ "FLM", hw_mod_flm_alloc, hw_mod_flm_free, hw_mod_flm_reset, hw_mod_flm_present },
+ { "HSH", hw_mod_hsh_alloc, hw_mod_hsh_free, hw_mod_hsh_reset, hw_mod_hsh_present },
};
#define MOD_COUNT (ARRAY_SIZE(module))
diff --git a/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_hsh.c b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_hsh.c
new file mode 100644
index 0000000000..77dfbb5374
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_api/hw_mod/hw_mod_hsh.c
@@ -0,0 +1,84 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "hw_mod_backend.h"
+
+#define _MOD_ "HSH"
+#define _VER_ be->hsh.ver
+
+bool hw_mod_hsh_present(struct flow_api_backend_s *be)
+{
+ return be->iface->get_hsh_present(be->be_dev);
+}
+
+int hw_mod_hsh_alloc(struct flow_api_backend_s *be)
+{
+ int nb;
+ _VER_ = be->iface->get_hsh_version(be->be_dev);
+ NT_LOG(DBG, FILTER, "HSH MODULE VERSION %i.%i\n", VER_MAJOR(_VER_), VER_MINOR(_VER_));
+
+ /* detect number of HSH categories supported by FPGA */
+ nb = be->iface->get_nb_hsh_categories(be->be_dev);
+
+ if (nb <= 0)
+ return COUNT_ERROR(hsh_categories);
+
+ be->hsh.nb_rcp = (uint32_t)nb;
+
+ /* detect if Toeplitz hashing function is supported by FPGA */
+ nb = be->iface->get_nb_hsh_toeplitz(be->be_dev);
+
+ if (nb < 0)
+ return COUNT_ERROR(hsh_toeplitz);
+
+ be->hsh.toeplitz = (uint32_t)nb;
+
+ switch (_VER_) {
+ case 5:
+ if (!callocate_mod((struct common_func_s *)&be->hsh, 1, &be->hsh.v5.rcp,
+ be->hsh.nb_rcp, sizeof(struct hsh_v5_rcp_s)))
+ return -1;
+
+ break;
+
+ /* end case 5 */
+ default:
+ return UNSUP_VER;
+ }
+
+ return 0;
+}
+
+void hw_mod_hsh_free(struct flow_api_backend_s *be)
+{
+ if (be->hsh.base) {
+ free(be->hsh.base);
+ be->hsh.base = NULL;
+ }
+}
+
+int hw_mod_hsh_reset(struct flow_api_backend_s *be)
+{
+ /* Zero entire cache area */
+ zero_module_cache((struct common_func_s *)(&be->hsh));
+
+ NT_LOG(DBG, FILTER, "INIT HSH RCP\n");
+ return hw_mod_hsh_rcp_flush(be, 0, be->hsh.nb_rcp);
+}
+
+int hw_mod_hsh_rcp_flush(struct flow_api_backend_s *be, int start_idx, int count)
+{
+ if (count == ALL_ENTRIES)
+ count = be->hsh.nb_rcp;
+
+ if ((start_idx + count) > (int)be->hsh.nb_rcp)
+ return INDEX_TOO_LARGE;
+
+ return be->iface->hsh_rcp_flush(be->be_dev, &be->hsh, start_idx, count);
+}
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
index a003334a23..4317da8094 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
@@ -544,6 +544,42 @@ static nthw_fpga_register_init_s hif_registers[] = {
{ HIF_UUID3, 176, 32, NTHW_FPGA_REG_TYPE_RO, 462142918, 1, hif_uuid3_fields },
};
+static nthw_fpga_field_init_s hsh_rcp_ctrl_fields[] = {
+ { HSH_RCP_CTRL_ADR, 4, 0, 0x0000 },
+ { HSH_RCP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s hsh_rcp_data_fields[] = {
+ { HSH_RCP_DATA_AUTO_IPV4_MASK, 1, 742, 0x0000 },
+ { HSH_RCP_DATA_HSH_TYPE, 5, 416, 0x0000 },
+ { HSH_RCP_DATA_HSH_VALID, 1, 415, 0x0000 },
+ { HSH_RCP_DATA_K, 320, 422, 0x0000 },
+ { HSH_RCP_DATA_LOAD_DIST_TYPE, 2, 0, 0x0000 },
+ { HSH_RCP_DATA_MAC_PORT_MASK, 2, 2, 0x0000 },
+ { HSH_RCP_DATA_P_MASK, 1, 61, 0x0000 },
+ { HSH_RCP_DATA_QW0_OFS, 8, 11, 0x0000 },
+ { HSH_RCP_DATA_QW0_PE, 5, 6, 0x0000 },
+ { HSH_RCP_DATA_QW4_OFS, 8, 24, 0x0000 },
+ { HSH_RCP_DATA_QW4_PE, 5, 19, 0x0000 },
+ { HSH_RCP_DATA_SEED, 32, 382, 0x0000 },
+ { HSH_RCP_DATA_SORT, 2, 4, 0x0000 },
+ { HSH_RCP_DATA_TNL_P, 1, 414, 0x0000 },
+ { HSH_RCP_DATA_TOEPLITZ, 1, 421, 0x0000 },
+ { HSH_RCP_DATA_W8_OFS, 8, 37, 0x0000 },
+ { HSH_RCP_DATA_W8_PE, 5, 32, 0x0000 },
+ { HSH_RCP_DATA_W8_SORT, 1, 45, 0x0000 },
+ { HSH_RCP_DATA_W9_OFS, 8, 51, 0x0000 },
+ { HSH_RCP_DATA_W9_P, 1, 60, 0x0000 },
+ { HSH_RCP_DATA_W9_PE, 5, 46, 0x0000 },
+ { HSH_RCP_DATA_W9_SORT, 1, 59, 0x0000 },
+ { HSH_RCP_DATA_WORD_MASK, 320, 62, 0x0000 },
+};
+
+static nthw_fpga_register_init_s hsh_registers[] = {
+ { HSH_RCP_CTRL, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, hsh_rcp_ctrl_fields },
+ { HSH_RCP_DATA, 1, 743, NTHW_FPGA_REG_TYPE_WO, 0, 23, hsh_rcp_data_fields },
+};
+
static nthw_fpga_field_init_s iic_adr_fields[] = {
{ IIC_ADR_SLV_ADR, 7, 1, 0 },
};
@@ -1398,6 +1434,7 @@ static nthw_fpga_module_init_s fpga_modules[] = {
gpio_phy_registers
},
{ MOD_HIF, 0, MOD_HIF, 0, 0, NTHW_FPGA_BUS_TYPE_PCI, 0, 18, hif_registers },
+ { MOD_HSH, 0, MOD_HSH, 0, 5, NTHW_FPGA_BUS_TYPE_RAB1, 1536, 2, hsh_registers },
{ MOD_IIC, 0, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 768, 22, iic_registers },
{ MOD_IIC, 1, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 896, 22, iic_registers },
{ MOD_IIC, 2, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24832, 22, iic_registers },
@@ -1580,5 +1617,5 @@ static nthw_fpga_prod_param_s product_parameters[] = {
};
nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = {
- 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 17, fpga_modules,
+ 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 18, fpga_modules,
};
--
2.45.0