From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C74545AE7; Tue, 8 Oct 2024 20:49:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8A72E4068E; Tue, 8 Oct 2024 20:49:31 +0200 (CEST) Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 5002C4025D for ; Tue, 8 Oct 2024 20:49:28 +0200 (CEST) Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 498DOpp8015500; Tue, 8 Oct 2024 11:49:27 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=j RHXqxQGI0DJPIl/uNqpNPxOV9MKnCK/c/UfySkqYqE=; b=IxaM2MmQy5F7lDoyR 4PjZWgamrsIxEDGcFk6brNCmzJ8SqaGnEQgNv6SoZZVBkWn3P7f/n6tXikGmUMhU DU1l979TraGVa3hZfrhtNCN2T4Wvg9qzRKzMB7yuz8j4IwRkSnzTx8aJ9VP9UMA0 TVVDaFbH25jK6YHZsfEKAHZuSTwtF7dP1ObM1boJ8lN4SnFihV0GXl6i++cr6LyD Jegm8YOtZkHDhHjuGPP2Um5TgfyMYwITwcr1HwDSPKNJwz3/5eQ66Pt24Py/DIV0 jVmo/ElIV6Q9SigHsf4h8fuspYCsD73Pjb51AC/r8vMpWfT19QJt0xUqHeoeWRm1 ToBew== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 4255kb8s0s-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 08 Oct 2024 11:49:27 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 8 Oct 2024 11:49:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 8 Oct 2024 11:49:25 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 6B1653F7043; Tue, 8 Oct 2024 11:49:23 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , "Akhil Goyal" Subject: [PATCH v3 2/9] raw/cnxk_rvu_lf: add PMD API to get npa/sso pffunc Date: Wed, 9 Oct 2024 00:19:08 +0530 Message-ID: <20241008184915.1356089-3-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241008184915.1356089-1-gakhil@marvell.com> References: <20241008105415.1026962-1-gakhil@marvell.com> <20241008184915.1356089-1-gakhil@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: _sFbwmAJtQojRk4mo4HIHRQdkc3LS4eh X-Proofpoint-ORIG-GUID: _sFbwmAJtQojRk4mo4HIHRQdkc3LS4eh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added rte_pmd_rvu_lf_npa_pf_func_get and rte_pmd_rvu_lf_sso_pf_func_get APIs to get NPA and SSO pffunc for the application use. Signed-off-by: Akhil Goyal --- doc/api/doxy-api-index.md | 1 + doc/guides/rawdevs/cnxk_rvu_lf.rst | 7 +++ drivers/common/cnxk/roc_npa.c | 6 +++ drivers/common/cnxk/roc_npa.h | 3 ++ drivers/common/cnxk/roc_sso.c | 6 +++ drivers/common/cnxk/roc_sso.h | 3 ++ drivers/common/cnxk/version.map | 2 + drivers/raw/cnxk_rvu_lf/cnxk_rvu_lf.c | 13 +++++ drivers/raw/cnxk_rvu_lf/meson.build | 1 + drivers/raw/cnxk_rvu_lf/rte_pmd_cnxk_rvu_lf.h | 51 +++++++++++++++++++ 10 files changed, 93 insertions(+) create mode 100644 drivers/raw/cnxk_rvu_lf/rte_pmd_cnxk_rvu_lf.h diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md index f9f0300126..b4dbe51727 100644 --- a/doc/api/doxy-api-index.md +++ b/doc/api/doxy-api-index.md @@ -52,6 +52,7 @@ The public API headers are grouped by topics: [cnxk_crypto](@ref rte_pmd_cnxk_crypto.h), [cnxk_eventdev](@ref rte_pmd_cnxk_eventdev.h), [cnxk_mempool](@ref rte_pmd_cnxk_mempool.h), + [cnxk_rvu_lf](@ref rte_pmd_cnxk_rvu_lf.h), [dpaa](@ref rte_pmd_dpaa.h), [dpaa2](@ref rte_pmd_dpaa2.h), [mlx5](@ref rte_pmd_mlx5.h), diff --git a/doc/guides/rawdevs/cnxk_rvu_lf.rst b/doc/guides/rawdevs/cnxk_rvu_lf.rst index 8a0bc22dd5..13184ad4dc 100644 --- a/doc/guides/rawdevs/cnxk_rvu_lf.rst +++ b/doc/guides/rawdevs/cnxk_rvu_lf.rst @@ -38,3 +38,10 @@ kernel driver. When querying the status of the devices, they will appear under the category of "Misc (rawdev) devices", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be used to see the state of those devices alone. + +Get NPA and SSO PF FUNC +----------------------- + +APIs ``rte_pmd_rvu_lf_npa_pf_func_get()`` and ``rte_pmd_rvu_lf_sso_pf_func_get()`` +can be used to get the cnxk NPA PF func and SSO PF func which application +can use for NPA/SSO specific configuration. diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index 934d7361a9..a33f9a8499 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -17,6 +17,12 @@ roc_npa_lf_init_cb_register(roc_npa_lf_init_cb_t cb) return 0; } +uint16_t +roc_npa_pf_func_get(void) +{ + return idev_npa_pffunc_get(); +} + void roc_npa_pool_op_range_set(uint64_t aura_handle, uint64_t start_iova, uint64_t end_iova) diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index fbf75b2fca..f7cb4460e7 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -820,6 +820,9 @@ int __roc_api roc_npa_aura_bp_configure(uint64_t aura_id, uint16_t bpid, uint8_t typedef int (*roc_npa_lf_init_cb_t)(struct plt_pci_device *pci_dev); int __roc_api roc_npa_lf_init_cb_register(roc_npa_lf_init_cb_t cb); +/* Utility functions */ +uint16_t __roc_api roc_npa_pf_func_get(void); + /* Debug */ int __roc_api roc_npa_ctx_dump(void); int __roc_api roc_npa_dump(void); diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 2e3b134bfc..aed8819a1b 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -319,6 +319,12 @@ roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, uint16_t hwgrp) return dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | hwgrp << 12); } +uint16_t +roc_sso_pf_func_get(void) +{ + return idev_sso_pffunc_get(); +} + uint64_t roc_sso_ns_to_gw(uint64_t base, uint64_t ns) { diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index 4ac901762e..3e293a0a69 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -103,6 +103,9 @@ int __roc_api roc_sso_hwgrp_stash_config(struct roc_sso *roc_sso, void __roc_api roc_sso_hws_gwc_invalidate(struct roc_sso *roc_sso, uint8_t *hws, uint8_t nb_hws); +/* Utility function */ +uint16_t __roc_api roc_sso_pf_func_get(void); + /* Debug */ void __roc_api roc_sso_dump(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t hwgrp, FILE *f); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 9f7c804542..dd56caef16 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -451,6 +451,7 @@ INTERNAL { roc_npa_dev_unlock; roc_npa_dump; roc_npa_lf_init_cb_register; + roc_npa_pf_func_get; roc_npa_pool_create; roc_npa_pool_destroy; roc_npa_pool_op_pc_reset; @@ -518,6 +519,7 @@ INTERNAL { roc_sso_hws_gwc_invalidate; roc_sso_hws_unlink; roc_sso_ns_to_gw; + roc_sso_pf_func_get; roc_sso_rsrc_fini; roc_sso_rsrc_init; roc_tim_fini; diff --git a/drivers/raw/cnxk_rvu_lf/cnxk_rvu_lf.c b/drivers/raw/cnxk_rvu_lf/cnxk_rvu_lf.c index 36067909be..43d3a6fa87 100644 --- a/drivers/raw/cnxk_rvu_lf/cnxk_rvu_lf.c +++ b/drivers/raw/cnxk_rvu_lf/cnxk_rvu_lf.c @@ -14,6 +14,19 @@ #include #include "cnxk_rvu_lf.h" +#include "rte_pmd_cnxk_rvu_lf.h" + +uint16_t +rte_pmd_rvu_lf_npa_pf_func_get(void) +{ + return roc_npa_pf_func_get(); +} + +uint16_t +rte_pmd_rvu_lf_sso_pf_func_get(void) +{ + return roc_sso_pf_func_get(); +} static const struct rte_rawdev_ops rvu_lf_rawdev_ops = { .dev_selftest = NULL, diff --git a/drivers/raw/cnxk_rvu_lf/meson.build b/drivers/raw/cnxk_rvu_lf/meson.build index 32081e147f..a1a010319b 100644 --- a/drivers/raw/cnxk_rvu_lf/meson.build +++ b/drivers/raw/cnxk_rvu_lf/meson.build @@ -6,4 +6,5 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev'] sources = files( 'cnxk_rvu_lf.c', ) +headers = files('rte_pmd_cnxk_rvu_lf.h') require_iova_in_mbuf = false diff --git a/drivers/raw/cnxk_rvu_lf/rte_pmd_cnxk_rvu_lf.h b/drivers/raw/cnxk_rvu_lf/rte_pmd_cnxk_rvu_lf.h new file mode 100644 index 0000000000..ea03e7ac8c --- /dev/null +++ b/drivers/raw/cnxk_rvu_lf/rte_pmd_cnxk_rvu_lf.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2024 Marvell. + */ + +#ifndef _RTE_PMD_CNXK_RVU_LF_H_ +#define _RTE_PMD_CNXK_RVU_LF_H_ + +#include + +#include +#include +#include +#include +#include + +/** + * @file rte_pmd_cnxk_rvu_lf.h + * + * Marvell RVU LF raw PMD specific structures and interface + * + * This API allows applications to manage RVU LF device in user space along with + * installing interrupt handlers for low latency signal processing. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Obtain NPA PF func + * + * @return + * Returns NPA pf_func on success, 0 in case of invalid pf_func. + */ +__rte_experimental +uint16_t rte_pmd_rvu_lf_npa_pf_func_get(void); + +/** + * Obtain SSO PF func + * + * @return + * Returns SSO pf_func on success, 0 in case of invalid pf_func. + */ +__rte_experimental +uint16_t rte_pmd_rvu_lf_sso_pf_func_get(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _RTE_PMD_CNXK_RVU_LF_H_ */ -- 2.25.1