From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41F2645AF8; Wed, 9 Oct 2024 23:18:21 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 16B9B40658; Wed, 9 Oct 2024 23:17:53 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mails.dpdk.org (Postfix) with ESMTP id 18487402E4 for ; Wed, 9 Oct 2024 23:17:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728508664; x=1760044664; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ei+7U2Rl6KGe01jHZKAvbhyLFjxJFXcwJC03zQSnyMs=; b=EcRfOFFKjkxJCaU+sc9imKp9Nra85UmIClkIZbny28caBPtZCNdliRPK EbsMIYYYadGZ0eIQS2mL5JjiGp/0VOBMLx88QILhXrCynnunhZ724qDE2 mpohVoUbUtGDWivIoXiqta6kcxvAyaZIBFeU+DfIzCBq810RN0R2cCJQ4 Jt2rrfOmZ+7e5M7oFrI2aiakX97NqVLGiZ/ApwW+7ADAf3T407BgHAFU3 dzOBg1t0nqb8R/9JQqrvhOU6x6aOnVXSTmf5hVT63fe7dgNybAVF6s2SC K3rfdtYBnl1sPG5ymcPrW1to5E0gGHTTCyK2wlFfptFOivEUDz147o32w w==; X-CSE-ConnectionGUID: TF8wUBRXQWq9qQa0Qf/R0g== X-CSE-MsgGUID: nFg1zlwbR/ic+CboUbF+ZQ== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="39202237" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="39202237" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 14:17:43 -0700 X-CSE-ConnectionGUID: SdmNJLGNQgGi/68CPIvkmw== X-CSE-MsgGUID: e6VMZ+2pRf6+6bRgNKzHoA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76480605" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa008.fm.intel.com with ESMTP; 09 Oct 2024 14:17:42 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v3 06/12] baseband/acc: enhance SW ring alignment Date: Wed, 9 Oct 2024 14:12:56 -0700 Message-Id: <20241009211302.177471-7-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241009211302.177471-1-hernan.vargas@intel.com> References: <20241009211302.177471-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Calculate the aligned total size required for queue rings, ensuring that the size is a power of two for proper memory allocation. Signed-off-by: Hernan Vargas --- drivers/baseband/acc/acc_common.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 1d8fd24ba008..0c249d5b93fd 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -767,6 +767,7 @@ alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc_device *d, int i = 0; uint32_t q_sw_ring_size = ACC_MAX_QUEUE_DEPTH * get_desc_len(); uint32_t dev_sw_ring_size = q_sw_ring_size * num_queues; + uint32_t alignment = q_sw_ring_size * rte_align32pow2(num_queues); /* Free first in case this is a reconfiguration */ rte_free(d->sw_rings_base); @@ -774,12 +775,12 @@ alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc_device *d, while (i < ACC_SW_RING_MEM_ALLOC_ATTEMPTS) { /* * sw_ring allocated memory is guaranteed to be aligned to - * q_sw_ring_size at the condition that the requested size is - * less than the page size + * the variable 'alignment' at the condition that the requested + * size is less than the page size */ sw_rings_base = rte_zmalloc_socket( dev->device->driver->name, - dev_sw_ring_size, q_sw_ring_size, socket); + dev_sw_ring_size, alignment, socket); if (sw_rings_base == NULL) { rte_acc_log(ERR, -- 2.37.1