From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A06245B04; Thu, 10 Oct 2024 16:16:46 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 87A7540DD7; Thu, 10 Oct 2024 16:14:59 +0200 (CEST) Received: from egress-ip42b.ess.de.barracuda.com (egress-ip42b.ess.de.barracuda.com [18.185.115.246]) by mails.dpdk.org (Postfix) with ESMTP id 61A3240A80 for ; Thu, 10 Oct 2024 16:14:47 +0200 (CEST) Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05lp2107.outbound.protection.outlook.com [104.47.18.107]) by mx-outbound20-48.eu-central-1b.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 10 Oct 2024 14:14:45 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wmvcRQst92Dza5OMXbHSTvFt//S1aMzmLi9wFHv45OVAcgzoNxf0ZMQXL2yNnSY2hH/ARVIobjS/59p3sIguuRf3HHIC+06XZ5S/9y9xK6FD2vqcxTGJweYRc7iLZQyH0tkNeLF08l0bzifdxB/OqvfTCl3fEhM7/fncye/hcsbNPHB76vJJvdzLOBXXpOjI0+uAtID+qggPayFjfzc4RJuWRZC8O4VMZ/NVs7qauBSgH/Hus0ipy5g/KyqCa8A4LK8WDSY/GSSCYnNa8P5K1qrSoAOv2Ab4zP0mxNXxV5c6Z+UF3PRHdqB2AGUlrM2mb4WNPzT9Wjqr7qTmsKZegg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BfTM5pabktmHZBohqzdLPKX9Ko5XAg2lHphxEvb2L10=; b=DdQrTRUpNFUqnmOQqFxPcJ2j38Hgz+MpdF1fey15uDjaf2yW6LGigl0lIsCddtYYObmZV8NyHTu7Teydap239HrNtk1AsdmpGH4oC5QkAp7tMaj7KTLgyDQaiq8hREeMk5L6faOIXsVPQSyZwktvEYGTYmn9GybMenYUPEgzVevWM1xhJ1mxyv7ERJAIBNhxvsO3vbGVeUQf0tvhxpJDWZb6b9IISClC32OZVrpoinQFilQjqbd88DKnt0G9Jaysx8OwW92u5Xo+9b6+YeB8i2gNQFLEGMRqFn9nIrlzx0Hvn4owzMcWe3qqqkxLiN19Y0a20YGyC1DASkB1udePCQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 178.72.21.4) smtp.rcpttodomain=dpdk.org smtp.mailfrom=napatech.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=napatech.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=napatech.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BfTM5pabktmHZBohqzdLPKX9Ko5XAg2lHphxEvb2L10=; b=mGPmXX9KLvaQTFQpC5BV4qP1l8eUG2pXgGMMBY5voqH8OOUqxwmT2HgBt/OABmZr06WFDD/lynM1rfGCOmAeQ7/nxIAxfG10T4U6Y6INPe4HNxJjnBCPTU5Sr4NKTjpsM7dLQ/YAC1Fun587CY5mlhdiMplK2jZkaTnvSqt6Mao= Received: from DU2PR04CA0070.eurprd04.prod.outlook.com (2603:10a6:10:232::15) by VE1P190MB1008.EURP190.PROD.OUTLOOK.COM (2603:10a6:800:1a0::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.18; Thu, 10 Oct 2024 14:14:38 +0000 Received: from DU6PEPF0000B61B.eurprd02.prod.outlook.com (2603:10a6:10:232:cafe::26) by DU2PR04CA0070.outlook.office365.com (2603:10a6:10:232::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.17 via Frontend Transport; Thu, 10 Oct 2024 14:14:38 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 178.72.21.4) smtp.mailfrom=napatech.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=napatech.com; Received-SPF: Fail (protection.outlook.com: domain of napatech.com does not designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com; client-ip=178.72.21.4; helo=localhost.localdomain; Received: from localhost.localdomain (178.72.21.4) by DU6PEPF0000B61B.mail.protection.outlook.com (10.167.8.132) with Microsoft SMTP Server id 15.20.8048.13 via Frontend Transport; Thu, 10 Oct 2024 14:14:38 +0000 From: Serhii Iliushyk To: dev@dpdk.org Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com, andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com, Oleksandr Kolomeiets Subject: [PATCH v3 16/50] net/ntnic: add queue select (QSL) flow module Date: Thu, 10 Oct 2024 16:13:31 +0200 Message-ID: <20241010141416.4063591-17-sil-plv@napatech.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241010141416.4063591-1-sil-plv@napatech.com> References: <20241006203728.330792-2-sil-plv@napatech.com> <20241010141416.4063591-1-sil-plv@napatech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU6PEPF0000B61B:EE_|VE1P190MB1008:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: a2e98029-9a1d-4752-3836-08dce935e073 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?uzXKU7GnygHzmuoFmUnAFwiTt/hhg5bU4iTrPQuXuhg/XAeSvpmLITsBgwwp?= =?us-ascii?Q?zfYhgo2LdvNnuqOop/G8tkGwIjgxjuFZm25F56ZhTWhp4/8y/8EMy0Qi9CCM?= =?us-ascii?Q?MO0GuMOhyP3V8I3+8NUMHmh+neZs28ASIWuy4yUJATuPg3c120xHFPm1U6kw?= =?us-ascii?Q?eXlQqKsnuJsNrebjqIA2ImZNgjYIn5Fxz0am8kQiM9FFNhupL7baOTFBqYQm?= =?us-ascii?Q?c334M9Rq0xJ8nMO2Ab7QRrp+AGjNx8Cb/iugwGbpSeJMWX8WjRyPHRTVggJm?= =?us-ascii?Q?EvIoymtsvzufJTPVCsa4OdaAXQTeRawAMwrqgdmilwEUfMi8+WQT/Vq8hU0F?= =?us-ascii?Q?9i6JXnZWukPrmV58VSOa6hZ1e2mhAV+s6BCgTOI0yOs44B/JfpWKddObc64u?= =?us-ascii?Q?bmKz4ghjkRBZpHpiuFAWivK2Z35MKMDKbREUHjpRdssi64SSA9MvbfoGyBta?= =?us-ascii?Q?fIeHblpU3XPedtbcg1sx1ZyCRJvVcmiSXTp5bxR5R+cWWwpF20nceSKpIwH0?= =?us-ascii?Q?4a75DNRBUHNxidW4qtNMQptOKUm6ZDecSJvxWcRMCZGoBUrKqXWD2JPkHzZz?= =?us-ascii?Q?FQe+Bs3dLV9p+zUOajRVz0GRfb8E2JVu3O+hTxkM/kKjnrG5V23dzRWfb9tU?= =?us-ascii?Q?y0ngJMouBUfdZdW6ZiKMErgsN9fSJjNh4tGenzyf4VQk+OdUZpP2y9XGVo2q?= =?us-ascii?Q?ImC/PU8xhsEArb+Ozb1nI5r0LCUd+N0u3gf7N2vjr3XXFF22e+llOfz+dzGP?= =?us-ascii?Q?qhOkFk+y9SBAer44cvlj3NCnOdSWysO+TDDLLi6UulFANl0Sew7VrUUrJqXf?= =?us-ascii?Q?XrUP5Vc2DeBNq6pILcCFI4fPZg4wy8kHPqduNttr8UBbUD8AjrLfx//79+ZE?= =?us-ascii?Q?F3ofO2lU4a+9bwyFa4zmiLw4FujNU381R04Nu00c/xT4kzOMnTIWmJPyW1P4?= =?us-ascii?Q?+UUsy59NjIpocG0MkfWHfBK8SML5lSrmI0RWAJh6YM6peqTe1xKdsUPAuS+c?= =?us-ascii?Q?4sGhnSsrRE9uWFwrU+6waSmuwWPKjCwb4dVW7qehFEbmL6T9Xmmz7qHgGOsI?= =?us-ascii?Q?FjnNfSKeZ8PUMPTbmVdikk1mmg2lVg92oFLQzBko3McxYz4jOHQTq0/husfs?= =?us-ascii?Q?t0dIU+2MlwXWM50qirWt0PRHLqo8VvaLSo19R5Riz6uQxjDLXZXNbZm3OPEp?= =?us-ascii?Q?52HbQ6EeK83Ys1c/Bh7Agcy/VHKm/BjloydAqz3QIEISkYrlHUHkt8iihRd4?= =?us-ascii?Q?tzwIUckYZYySGbYQZg+InGyfOKPxvtTcTI+AYOF23MWq3SXWgjNjzH0OwVHT?= =?us-ascii?Q?L2HwTPDd1oa8U/PU74yT/rRYuXc58GMaq3SvAyE91K2R7WLrRdmkfgJvLgLk?= =?us-ascii?Q?Vg8bunk30SISa6s2M/K2A0WGQX1i?= X-Forefront-Antispam-Report: CIP:178.72.21.4; CTRY:DK; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:localhost.localdomain; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: fR38bwqF7tp4J+WwxwU7vI1ofUzaSNrV2AnyzjImEnL1H4L4ib1nPo/f5FCUMXHfESDx+qDpEEGJ2UaJffrrv3qMK11HXCuzKkYe10wv1GjTF/jIzlmSX5ytXoYJVUJkbqAn3o+dkrQ5ilOJGDcVQaIyvxbRArt/Qlg3QTeAUOctCvXkTeivE8ekJCuYkZi0QJbhSzsjc4LROdTMH6WppW7S5IWdHH3WI0+nfkOWJzGl59I1cyE6vxulqh9KZ/z47oFJCRPz/XMhIuZwEV+WHjL4B91fCKtDMnGgqbN7iOql9osHe1muRHZreTmo0qioFAv2T+Z+Z4l7pgqMtKD0ElknYJuelMMwGfL2UTMuQUdaEWBV3zHxPBK8BfXecK1/Et6FQI8FEH7WJO5AflC+09RcvA9tbatJarPAlyHppXFxr8IWiJ1VPBeK2JPEFcLO4u+8LQofddgCu0HE2D8wgVK7oMGoS9ubHuPGUzrgt09imgllM+CgJ/ARRWz5n5X+cxiOfWc5nSqXaTZ+ge+fO08k6ySQbyj6XsbdHAu8zmkvIU1TDv9xQFPkazVr2B75CLdaT482tHhbVWGGAFPKT5A6y/LoCvd8JaqOqvKl2fMguB5tsEH2g83lfswvtINUg1Wltz/So6MchPkVFuarPipHs6aqktL3HA0jrvdsD/4= X-OriginatorOrg: napatech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 14:14:38.5141 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2e98029-9a1d-4752-3836-08dce935e073 X-MS-Exchange-CrossTenant-Id: c4540d0b-728a-4233-9da5-9ea30c7ec3ed X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=c4540d0b-728a-4233-9da5-9ea30c7ec3ed; Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000B61B.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1P190MB1008 X-BESS-ID: 1728569682-305168-12632-25869-2 X-BESS-VER: 2019.1_20241004.2057 X-BESS-Apparent-Source-IP: 104.47.18.107 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVkZmFiamQGYGUDTRIC3N3NzExD DNIgUobmRqkphsnGxonGJoZppsYpKqVBsLALjdV5lCAAAA X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.259630 [from cloudscan22-68.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Oleksandr Kolomeiets The Queue Selector module directs packets to a given destination which includes host queues, physical ports, exceptions paths, and discard. Signed-off-by: Oleksandr Kolomeiets --- v3 * Remove newline characters from logs. --- drivers/net/ntnic/include/hw_mod_backend.h | 18 ++ drivers/net/ntnic/include/hw_mod_qsl_v7.h | 48 +++ drivers/net/ntnic/meson.build | 1 + .../nthw/flow_api/flow_backend/flow_backend.c | 129 ++++++++ .../ntnic/nthw/flow_filter/flow_nthw_qsl.c | 295 ++++++++++++++++++ .../ntnic/nthw/flow_filter/flow_nthw_qsl.h | 113 +++++++ .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 + .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 + .../nthw/supported/nthw_fpga_reg_defs_qsl.h | 66 ++++ 9 files changed, 672 insertions(+) create mode 100644 drivers/net/ntnic/include/hw_mod_qsl_v7.h create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_qsl.c create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_qsl.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h index a4c3336e13..84f2ed6c6a 100644 --- a/drivers/net/ntnic/include/hw_mod_backend.h +++ b/drivers/net/ntnic/include/hw_mod_backend.h @@ -12,6 +12,7 @@ #include "hw_mod_cat_v21.h" #include "hw_mod_flm_v25.h" #include "hw_mod_km_v7.h" +#include "hw_mod_qsl_v7.h" #include "hw_mod_hsh_v5.h" #define MAX_PHYS_ADAPTERS 8 @@ -86,6 +87,15 @@ struct hsh_func_s { }; }; +struct qsl_func_s { + COMMON_FUNC_INFO_S; + uint32_t nb_rcp_categories; + uint32_t nb_qst_entries; + union { + struct hw_mod_qsl_v7_s v7; + }; +}; + enum debug_mode_e { FLOW_BACKEND_DEBUG_MODE_NONE = 0x0000, FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001 @@ -196,6 +206,14 @@ struct flow_api_backend_ops { bool (*get_hsh_present)(void *dev); uint32_t (*get_hsh_version)(void *dev); int (*hsh_rcp_flush)(void *dev, const struct hsh_func_s *hsh, int category, int cnt); + + /* QSL */ + bool (*get_qsl_present)(void *dev); + uint32_t (*get_qsl_version)(void *dev); + int (*qsl_rcp_flush)(void *dev, const struct qsl_func_s *qsl, int category, int cnt); + int (*qsl_qst_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); + int (*qsl_qen_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); + int (*qsl_unmq_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt); }; struct flow_api_backend_s { diff --git a/drivers/net/ntnic/include/hw_mod_qsl_v7.h b/drivers/net/ntnic/include/hw_mod_qsl_v7.h new file mode 100644 index 0000000000..6f6f230638 --- /dev/null +++ b/drivers/net/ntnic/include/hw_mod_qsl_v7.h @@ -0,0 +1,48 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _HW_MOD_QSL_V7_H_ +#define _HW_MOD_QSL_V7_H_ + +#include + +struct qsl_v7_rcp_s { + uint32_t discard; + uint32_t drop; + uint32_t tbl_lo; + uint32_t tbl_hi; + uint32_t tbl_idx; + uint32_t tbl_msk; + uint32_t lr; + uint32_t tsa; + uint32_t vli; +}; + +struct qsl_v7_qst_s { + uint32_t queue; + uint32_t en; + uint32_t tx_port; + uint32_t lre; + uint32_t tci; + uint32_t ven; +}; + +struct qsl_v7_qen_s { + uint32_t en; +}; + +struct qsl_v7_unmq_s { + uint32_t dest_queue; + uint32_t en; +}; + +struct hw_mod_qsl_v7_s { + struct qsl_v7_rcp_s *rcp; + struct qsl_v7_qst_s *qst; + struct qsl_v7_qen_s *qen; + struct qsl_v7_unmq_s *unmq; +}; + +#endif /* _HW_MOD_QSL_V7_H_ */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index de6777f4d3..c7c5cd997f 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -52,6 +52,7 @@ sources = files( 'nthw/flow_filter/flow_nthw_ifr.c', 'nthw/flow_filter/flow_nthw_info.c', 'nthw/flow_filter/flow_nthw_km.c', + 'nthw/flow_filter/flow_nthw_qsl.c', 'nthw/model/nthw_fpga_model.c', 'nthw/nthw_platform.c', 'nthw/nthw_rac.c', diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c index de72c63b2f..d1c2e3ab44 100644 --- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c +++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c @@ -11,6 +11,7 @@ #include "flow_nthw_km.h" #include "flow_nthw_flm.h" #include "flow_nthw_hsh.h" +#include "flow_nthw_qsl.h" #include "ntnic_mod_reg.h" #include "nthw_fpga_model.h" #include "hw_mod_backend.h" @@ -30,6 +31,7 @@ static struct backend_dev_s { struct km_nthw *p_km_nthw; struct flm_nthw *p_flm_nthw; struct hsh_nthw *p_hsh_nthw; + struct qsl_nthw *p_qsl_nthw; struct ifr_nthw *p_ifr_nthw; /* TPE module */ } be_devs[MAX_PHYS_ADAPTERS]; @@ -1325,6 +1327,115 @@ static int hsh_rcp_flush(void *be_dev, const struct hsh_func_s *hsh, int categor return 0; } +/* + * QSL + */ + +static bool qsl_get_present(void *be_dev) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + return be->p_qsl_nthw != NULL; +} + +static uint32_t qsl_get_version(void *be_dev) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + return (uint32_t)((nthw_module_get_major_version(be->p_qsl_nthw->m_qsl) << 16) | + (nthw_module_get_minor_version(be->p_qsl_nthw->m_qsl) & 0xffff)); +} + +static int qsl_rcp_flush(void *be_dev, const struct qsl_func_s *qsl, int category, int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, qsl, be->p_qsl_nthw); + + if (qsl->ver == 7) { + qsl_nthw_rcp_cnt(be->p_qsl_nthw, 1); + + for (int i = 0; i < cnt; i++) { + qsl_nthw_rcp_select(be->p_qsl_nthw, category + i); + qsl_nthw_rcp_discard(be->p_qsl_nthw, qsl->v7.rcp[category + i].discard); + qsl_nthw_rcp_drop(be->p_qsl_nthw, qsl->v7.rcp[category + i].drop); + qsl_nthw_rcp_tbl_lo(be->p_qsl_nthw, qsl->v7.rcp[category + i].tbl_lo); + qsl_nthw_rcp_tbl_hi(be->p_qsl_nthw, qsl->v7.rcp[category + i].tbl_hi); + qsl_nthw_rcp_tbl_idx(be->p_qsl_nthw, qsl->v7.rcp[category + i].tbl_idx); + qsl_nthw_rcp_tbl_msk(be->p_qsl_nthw, qsl->v7.rcp[category + i].tbl_msk); + qsl_nthw_rcp_lr(be->p_qsl_nthw, qsl->v7.rcp[category + i].lr); + qsl_nthw_rcp_tsa(be->p_qsl_nthw, qsl->v7.rcp[category + i].tsa); + qsl_nthw_rcp_vli(be->p_qsl_nthw, qsl->v7.rcp[category + i].vli); + qsl_nthw_rcp_flush(be->p_qsl_nthw); + } + } + + CHECK_DEBUG_OFF(qsl, be->p_qsl_nthw); + return 0; +} + +static int qsl_qst_flush(void *be_dev, const struct qsl_func_s *qsl, int entry, int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, qsl, be->p_qsl_nthw); + + if (qsl->ver == 7) { + qsl_nthw_qst_cnt(be->p_qsl_nthw, 1); + + for (int i = 0; i < cnt; i++) { + qsl_nthw_qst_select(be->p_qsl_nthw, entry + i); + qsl_nthw_qst_queue(be->p_qsl_nthw, qsl->v7.qst[entry + i].queue); + qsl_nthw_qst_en(be->p_qsl_nthw, qsl->v7.qst[entry + i].en); + + qsl_nthw_qst_tx_port(be->p_qsl_nthw, qsl->v7.qst[entry + i].tx_port); + qsl_nthw_qst_lre(be->p_qsl_nthw, qsl->v7.qst[entry + i].lre); + qsl_nthw_qst_tci(be->p_qsl_nthw, qsl->v7.qst[entry + i].tci); + qsl_nthw_qst_ven(be->p_qsl_nthw, qsl->v7.qst[entry + i].ven); + qsl_nthw_qst_flush(be->p_qsl_nthw); + } + } + + CHECK_DEBUG_OFF(qsl, be->p_qsl_nthw); + return 0; +} + +static int qsl_qen_flush(void *be_dev, const struct qsl_func_s *qsl, int entry, int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, qsl, be->p_qsl_nthw); + + if (qsl->ver == 7) { + qsl_nthw_qen_cnt(be->p_qsl_nthw, 1); + + for (int i = 0; i < cnt; i++) { + qsl_nthw_qen_select(be->p_qsl_nthw, entry + i); + qsl_nthw_qen_en(be->p_qsl_nthw, qsl->v7.qen[entry + i].en); + qsl_nthw_qen_flush(be->p_qsl_nthw); + } + } + + CHECK_DEBUG_OFF(qsl, be->p_qsl_nthw); + return 0; +} + +static int qsl_unmq_flush(void *be_dev, const struct qsl_func_s *qsl, int entry, int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, qsl, be->p_qsl_nthw); + + if (qsl->ver == 7) { + qsl_nthw_unmq_cnt(be->p_qsl_nthw, 1); + + for (int i = 0; i < cnt; i++) { + qsl_nthw_unmq_select(be->p_qsl_nthw, entry + i); + qsl_nthw_unmq_dest_queue(be->p_qsl_nthw, + qsl->v7.unmq[entry + i].dest_queue); + qsl_nthw_unmq_en(be->p_qsl_nthw, qsl->v7.unmq[entry + i].en); + qsl_nthw_unmq_flush(be->p_qsl_nthw); + } + } + + CHECK_DEBUG_OFF(qsl, be->p_qsl_nthw); + return 0; +} + /* * DBS */ @@ -1438,6 +1549,13 @@ const struct flow_api_backend_ops flow_be_iface = { hsh_get_present, hsh_get_version, hsh_rcp_flush, + + qsl_get_present, + qsl_get_version, + qsl_rcp_flush, + qsl_qst_flush, + qsl_qen_flush, + qsl_unmq_flush, }; const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, void **dev) @@ -1498,6 +1616,16 @@ const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, vo be_devs[physical_adapter_no].p_hsh_nthw = NULL; } + /* Init nthw QSL */ + if (qsl_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) { + struct qsl_nthw *pqslnthw = qsl_nthw_new(); + qsl_nthw_init(pqslnthw, p_fpga, physical_adapter_no); + be_devs[physical_adapter_no].p_qsl_nthw = pqslnthw; + + } else { + be_devs[physical_adapter_no].p_qsl_nthw = NULL; + } + be_devs[physical_adapter_no].adapter_no = physical_adapter_no; *dev = (void *)&be_devs[physical_adapter_no]; @@ -1512,6 +1640,7 @@ static void bin_flow_backend_done(void *dev) km_nthw_delete(be_dev->p_km_nthw); flm_nthw_delete(be_dev->p_flm_nthw); hsh_nthw_delete(be_dev->p_hsh_nthw); + qsl_nthw_delete(be_dev->p_qsl_nthw); } static const struct flow_backend_ops ops = { diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_qsl.c b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_qsl.c new file mode 100644 index 0000000000..c887fe25e2 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_qsl.c @@ -0,0 +1,295 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "flow_nthw_qsl.h" + +void qsl_nthw_set_debug_mode(struct qsl_nthw *p, unsigned int n_debug_mode) +{ + nthw_module_set_debug_mode(p->m_qsl, n_debug_mode); +} + +struct qsl_nthw *qsl_nthw_new(void) +{ + struct qsl_nthw *p = malloc(sizeof(struct qsl_nthw)); + + if (p) + (void)memset(p, 0, sizeof(*p)); + + return p; +} + +void qsl_nthw_delete(struct qsl_nthw *p) +{ + if (p) { + (void)memset(p, 0, sizeof(*p)); + free(p); + } +} + +int qsl_nthw_init(struct qsl_nthw *p, nthw_fpga_t *p_fpga, int n_instance) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_QSL, n_instance); + + assert(n_instance >= 0 && n_instance < 256); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: QSL %d: no such instance", p_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->m_physical_adapter_no = (uint8_t)n_instance; + p->m_qsl = p_mod; + + /* RCP */ + p->mp_rcp_ctrl = nthw_module_get_register(p->m_qsl, QSL_RCP_CTRL); + p->mp_rcp_addr = nthw_register_get_field(p->mp_rcp_ctrl, QSL_RCP_CTRL_ADR); + p->mp_rcp_cnt = nthw_register_get_field(p->mp_rcp_ctrl, QSL_RCP_CTRL_CNT); + p->mp_rcp_data = nthw_module_get_register(p->m_qsl, QSL_RCP_DATA); + p->mp_rcp_data_discard = nthw_register_get_field(p->mp_rcp_data, QSL_RCP_DATA_DISCARD); + p->mp_rcp_data_drop = nthw_register_get_field(p->mp_rcp_data, QSL_RCP_DATA_DROP); + p->mp_rcp_data_tbl_lo = nthw_register_get_field(p->mp_rcp_data, QSL_RCP_DATA_TBL_LO); + p->mp_rcp_data_tbl_hi = nthw_register_get_field(p->mp_rcp_data, QSL_RCP_DATA_TBL_HI); + p->mp_rcp_data_tbl_idx = nthw_register_get_field(p->mp_rcp_data, QSL_RCP_DATA_TBL_IDX); + p->mp_rcp_data_tbl_msk = nthw_register_get_field(p->mp_rcp_data, QSL_RCP_DATA_TBL_MSK); + p->mp_rcp_data_cao = nthw_register_query_field(p->mp_rcp_data, QSL_RCP_DATA_CAO); + p->mp_rcp_data_lr = nthw_register_query_field(p->mp_rcp_data, QSL_RCP_DATA_LR); + p->mp_rcp_data_tsa = nthw_register_query_field(p->mp_rcp_data, QSL_RCP_DATA_TSA); + p->mp_rcp_data_vli = nthw_register_query_field(p->mp_rcp_data, QSL_RCP_DATA_VLI); + + /* QST */ + p->mp_qst_ctrl = nthw_module_get_register(p->m_qsl, QSL_QST_CTRL); + p->mp_qst_addr = nthw_register_get_field(p->mp_qst_ctrl, QSL_QST_CTRL_ADR); + p->mp_qst_cnt = nthw_register_get_field(p->mp_qst_ctrl, QSL_QST_CTRL_CNT); + p->mp_qst_data = nthw_module_get_register(p->m_qsl, QSL_QST_DATA); + p->mp_qst_data_queue = nthw_register_get_field(p->mp_qst_data, QSL_QST_DATA_QUEUE); + p->mp_qst_data_en = nthw_register_query_field(p->mp_qst_data, QSL_QST_DATA_EN); + p->mp_qst_data_tx_port = nthw_register_query_field(p->mp_qst_data, QSL_QST_DATA_TX_PORT); + p->mp_qst_data_lre = nthw_register_query_field(p->mp_qst_data, QSL_QST_DATA_LRE); + p->mp_qst_data_tci = nthw_register_query_field(p->mp_qst_data, QSL_QST_DATA_TCI); + p->mp_qst_data_ven = nthw_register_query_field(p->mp_qst_data, QSL_QST_DATA_VEN); + /* QEN */ + p->mp_qen_ctrl = nthw_module_get_register(p->m_qsl, QSL_QEN_CTRL); + p->mp_qen_addr = nthw_register_get_field(p->mp_qen_ctrl, QSL_QEN_CTRL_ADR); + p->mp_qen_cnt = nthw_register_get_field(p->mp_qen_ctrl, QSL_QEN_CTRL_CNT); + p->mp_qen_data = nthw_module_get_register(p->m_qsl, QSL_QEN_DATA); + p->mp_qen_data_en = nthw_register_get_field(p->mp_qen_data, QSL_QEN_DATA_EN); + /* UNMQ */ + p->mp_unmq_ctrl = nthw_module_get_register(p->m_qsl, QSL_UNMQ_CTRL); + p->mp_unmq_addr = nthw_register_get_field(p->mp_unmq_ctrl, QSL_UNMQ_CTRL_ADR); + p->mp_unmq_cnt = nthw_register_get_field(p->mp_unmq_ctrl, QSL_UNMQ_CTRL_CNT); + p->mp_unmq_data = nthw_module_get_register(p->m_qsl, QSL_UNMQ_DATA); + p->mp_unmq_data_dest_queue = + nthw_register_get_field(p->mp_unmq_data, QSL_UNMQ_DATA_DEST_QUEUE); + p->mp_unmq_data_en = nthw_register_get_field(p->mp_unmq_data, QSL_UNMQ_DATA_EN); + + if (!p->mp_qst_data_en) { + /* changed name from EN to QEN in v0.7 */ + p->mp_qst_data_en = nthw_register_get_field(p->mp_qst_data, QSL_QST_DATA_QEN); + } + + /* LTX - not there anymore from v0.7+ */ + p->mp_ltx_ctrl = nthw_module_query_register(p->m_qsl, QSL_LTX_CTRL); + + if (p->mp_ltx_ctrl) { + p->mp_ltx_addr = nthw_register_get_field(p->mp_ltx_ctrl, QSL_LTX_CTRL_ADR); + p->mp_ltx_cnt = nthw_register_get_field(p->mp_ltx_ctrl, QSL_LTX_CTRL_CNT); + + } else { + p->mp_ltx_addr = NULL; + p->mp_ltx_cnt = NULL; + } + + p->mp_ltx_data = nthw_module_query_register(p->m_qsl, QSL_LTX_DATA); + + if (p->mp_ltx_data) { + p->mp_ltx_data_lr = nthw_register_get_field(p->mp_ltx_data, QSL_LTX_DATA_LR); + p->mp_ltx_data_tx_port = + nthw_register_get_field(p->mp_ltx_data, QSL_LTX_DATA_TX_PORT); + p->mp_ltx_data_tsa = nthw_register_get_field(p->mp_ltx_data, QSL_LTX_DATA_TSA); + + } else { + p->mp_ltx_data_lr = NULL; + p->mp_ltx_data_tx_port = NULL; + p->mp_ltx_data_tsa = NULL; + } + + return 0; +} + +/* RCP */ +void qsl_nthw_rcp_select(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_addr, val); +}; + +void qsl_nthw_rcp_cnt(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_cnt, val); +} + +void qsl_nthw_rcp_discard(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_discard, val); +} + +void qsl_nthw_rcp_drop(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_drop, val); +} + +void qsl_nthw_rcp_tbl_lo(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tbl_lo, val); +} +void qsl_nthw_rcp_tbl_hi(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tbl_hi, val); +} +void qsl_nthw_rcp_tbl_idx(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tbl_idx, val); +} + +void qsl_nthw_rcp_tbl_msk(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tbl_msk, val); +} + +void qsl_nthw_rcp_lr(const struct qsl_nthw *p, uint32_t val) +{ + if (p->mp_rcp_data_lr) + nthw_field_set_val32(p->mp_rcp_data_lr, val); +} + +void qsl_nthw_rcp_tsa(const struct qsl_nthw *p, uint32_t val) +{ + if (p->mp_rcp_data_tsa) + nthw_field_set_val32(p->mp_rcp_data_tsa, val); +} + +void qsl_nthw_rcp_vli(const struct qsl_nthw *p, uint32_t val) +{ + if (p->mp_rcp_data_vli) + nthw_field_set_val32(p->mp_rcp_data_vli, val); +} + +void qsl_nthw_rcp_flush(const struct qsl_nthw *p) +{ + nthw_register_flush(p->mp_rcp_ctrl, 1); + nthw_register_flush(p->mp_rcp_data, 1); +} + +/* QST */ +void qsl_nthw_qst_select(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_qst_addr, val); +} + +void qsl_nthw_qst_cnt(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_qst_cnt, val); +} + +void qsl_nthw_qst_queue(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_qst_data_queue, val); +} + +void qsl_nthw_qst_en(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_qst_data_en, val); +} + +void qsl_nthw_qst_tx_port(const struct qsl_nthw *p, uint32_t val) +{ + if (p->mp_qst_data_tx_port) + nthw_field_set_val32(p->mp_qst_data_tx_port, val); +} + +void qsl_nthw_qst_lre(const struct qsl_nthw *p, uint32_t val) +{ + if (p->mp_qst_data_lre) + nthw_field_set_val32(p->mp_qst_data_lre, val); +} + +void qsl_nthw_qst_tci(const struct qsl_nthw *p, uint32_t val) +{ + if (p->mp_qst_data_tci) + nthw_field_set_val32(p->mp_qst_data_tci, val); +} + +void qsl_nthw_qst_ven(const struct qsl_nthw *p, uint32_t val) +{ + if (p->mp_qst_data_ven) + nthw_field_set_val32(p->mp_qst_data_ven, val); +} + +void qsl_nthw_qst_flush(const struct qsl_nthw *p) +{ + nthw_register_flush(p->mp_qst_ctrl, 1); + nthw_register_flush(p->mp_qst_data, 1); +} + +/* QEN */ +void qsl_nthw_qen_select(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_qen_addr, val); +} + +void qsl_nthw_qen_cnt(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_qen_cnt, val); +} + +void qsl_nthw_qen_en(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_qen_data_en, val); +} + +void qsl_nthw_qen_flush(const struct qsl_nthw *p) +{ + nthw_register_flush(p->mp_qen_ctrl, 1); + nthw_register_flush(p->mp_qen_data, 1); +} + +/* UNMQ */ +void qsl_nthw_unmq_select(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_unmq_addr, val); +} + +void qsl_nthw_unmq_cnt(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_unmq_cnt, val); +} + +void qsl_nthw_unmq_dest_queue(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_unmq_data_dest_queue, val); +} + +void qsl_nthw_unmq_en(const struct qsl_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_unmq_data_en, val); +} + +void qsl_nthw_unmq_flush(const struct qsl_nthw *p) +{ + nthw_register_flush(p->mp_unmq_ctrl, 1); + nthw_register_flush(p->mp_unmq_data, 1); +} diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_qsl.h b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_qsl.h new file mode 100644 index 0000000000..1bbcd1cea6 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_qsl.h @@ -0,0 +1,113 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __FLOW_NTHW_QSL_H__ +#define __FLOW_NTHW_QSL_H__ + +#include + +#include "nthw_fpga_model.h" + +struct qsl_nthw { + uint8_t m_physical_adapter_no; + nthw_fpga_t *mp_fpga; + + nthw_module_t *m_qsl; + + nthw_register_t *mp_rcp_ctrl; + nthw_field_t *mp_rcp_addr; + nthw_field_t *mp_rcp_cnt; + nthw_register_t *mp_rcp_data; + nthw_field_t *mp_rcp_data_discard; + nthw_field_t *mp_rcp_data_drop; + nthw_field_t *mp_rcp_data_tbl_lo; + nthw_field_t *mp_rcp_data_tbl_hi; + nthw_field_t *mp_rcp_data_tbl_idx; + nthw_field_t *mp_rcp_data_tbl_msk; + nthw_field_t *mp_rcp_data_cao; + nthw_field_t *mp_rcp_data_lr; + nthw_field_t *mp_rcp_data_tsa; + nthw_field_t *mp_rcp_data_vli; + + nthw_register_t *mp_ltx_ctrl; + nthw_field_t *mp_ltx_addr; + nthw_field_t *mp_ltx_cnt; + nthw_register_t *mp_ltx_data; + nthw_field_t *mp_ltx_data_lr; + nthw_field_t *mp_ltx_data_tx_port; + nthw_field_t *mp_ltx_data_tsa; + + nthw_register_t *mp_qst_ctrl; + nthw_field_t *mp_qst_addr; + nthw_field_t *mp_qst_cnt; + nthw_register_t *mp_qst_data; + nthw_field_t *mp_qst_data_queue; + nthw_field_t *mp_qst_data_en; + nthw_field_t *mp_qst_data_tx_port; + nthw_field_t *mp_qst_data_lre; + nthw_field_t *mp_qst_data_tci; + nthw_field_t *mp_qst_data_ven; + + nthw_register_t *mp_qen_ctrl; + nthw_field_t *mp_qen_addr; + nthw_field_t *mp_qen_cnt; + nthw_register_t *mp_qen_data; + nthw_field_t *mp_qen_data_en; + + nthw_register_t *mp_unmq_ctrl; + nthw_field_t *mp_unmq_addr; + nthw_field_t *mp_unmq_cnt; + nthw_register_t *mp_unmq_data; + nthw_field_t *mp_unmq_data_dest_queue; + nthw_field_t *mp_unmq_data_en; +}; + +typedef struct qsl_nthw qsl_nthw_t; + +struct qsl_nthw *qsl_nthw_new(void); +void qsl_nthw_delete(struct qsl_nthw *p); +int qsl_nthw_init(struct qsl_nthw *p, nthw_fpga_t *p_fpga, int n_instance); + +void qsl_nthw_set_debug_mode(struct qsl_nthw *p, unsigned int n_debug_mode); + +/* RCP */ +void qsl_nthw_rcp_select(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_cnt(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_discard(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_drop(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_tbl_lo(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_tbl_hi(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_tbl_idx(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_tbl_msk(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_lr(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_tsa(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_vli(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_rcp_flush(const struct qsl_nthw *p); + +/* QST */ +void qsl_nthw_qst_select(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qst_cnt(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qst_queue(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qst_en(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qst_tx_port(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qst_lre(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qst_tci(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qst_ven(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qst_flush(const struct qsl_nthw *p); + +/* QEN */ +void qsl_nthw_qen_select(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qen_cnt(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qen_en(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_qen_flush(const struct qsl_nthw *p); + +/* UNMQ */ +void qsl_nthw_unmq_select(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_unmq_cnt(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_unmq_dest_queue(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_unmq_en(const struct qsl_nthw *p, uint32_t val); +void qsl_nthw_unmq_flush(const struct qsl_nthw *p); + +#endif /* __FLOW_NTHW_QSL_H__ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h index a929a98b52..b159da7597 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -29,6 +29,7 @@ #define MOD_PCIE3 (0xfbc48c18UL) #define MOD_PCI_RD_TG (0x9ad9eed2UL) #define MOD_PCI_WR_TG (0x274b69e1UL) +#define MOD_QSL (0x448ed859UL) #define MOD_RAC (0xae830b42UL) #define MOD_RST9563 (0x385d6d1dUL) #define MOD_SDC (0xd2369530UL) diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h index 9155cc4435..7b99a7fbdb 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h @@ -28,6 +28,7 @@ #include "nthw_fpga_reg_defs_pcie3.h" #include "nthw_fpga_reg_defs_pci_rd_tg.h" #include "nthw_fpga_reg_defs_pci_wr_tg.h" +#include "nthw_fpga_reg_defs_qsl.h" #include "nthw_fpga_reg_defs_rac.h" #include "nthw_fpga_reg_defs_rst9563.h" #include "nthw_fpga_reg_defs_sdc.h" diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h new file mode 100644 index 0000000000..6a15ddc00e --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_qsl.h @@ -0,0 +1,66 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +/* + * nthw_fpga_reg_defs_qsl.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_QSL_ +#define _NTHW_FPGA_REG_DEFS_QSL_ + +/* QSL */ +#define NTHW_MOD_QSL (0x448ed859UL) +#define QSL_LTX_CTRL (0xd16859aUL) +#define QSL_LTX_CTRL_ADR (0x56ab4bfeUL) +#define QSL_LTX_CTRL_CNT (0x46a3d22fUL) +#define QSL_LTX_DATA (0xa2c70783UL) +#define QSL_LTX_DATA_LR (0xbd09e686UL) +#define QSL_LTX_DATA_TSA (0xdc9172f1UL) +#define QSL_LTX_DATA_TX_PORT (0x4e838100UL) +#define QSL_QEN_CTRL (0xfe8ed79cUL) +#define QSL_QEN_CTRL_ADR (0x81d44d48UL) +#define QSL_QEN_CTRL_CNT (0x91dcd499UL) +#define QSL_QEN_DATA (0x515f5585UL) +#define QSL_QEN_DATA_EN (0xa1e5961UL) +#define QSL_QST_CTRL (0x58cd5f95UL) +#define QSL_QST_CTRL_ADR (0xf71b52e1UL) +#define QSL_QST_CTRL_CNT (0xe713cb30UL) +#define QSL_QST_DATA (0xf71cdd8cUL) +#define QSL_QST_DATA_EN (0x19406021UL) +#define QSL_QST_DATA_LRE (0x71626c7eUL) +#define QSL_QST_DATA_QEN (0xf7cd0143UL) +#define QSL_QST_DATA_QUEUE (0x70bc6d12UL) +#define QSL_QST_DATA_TCI (0x3938f18dUL) +#define QSL_QST_DATA_TX_PORT (0x101a63f0UL) +#define QSL_QST_DATA_VEN (0xf28217c6UL) +#define QSL_RCP_CTRL (0x2a0d86aeUL) +#define QSL_RCP_CTRL_ADR (0x2798e4a0UL) +#define QSL_RCP_CTRL_CNT (0x37907d71UL) +#define QSL_RCP_DATA (0x85dc04b7UL) +#define QSL_RCP_DATA_CAO (0x2b87358eUL) +#define QSL_RCP_DATA_DISCARD (0x5b3da2b8UL) +#define QSL_RCP_DATA_DROP (0x30f5b2fbUL) +#define QSL_RCP_DATA_LR (0x3f2331c2UL) +#define QSL_RCP_DATA_TBL_HI (0xde81892fUL) +#define QSL_RCP_DATA_TBL_IDX (0xa8d19ee1UL) +#define QSL_RCP_DATA_TBL_LO (0x538ee91eUL) +#define QSL_RCP_DATA_TBL_MSK (0x2ee5f375UL) +#define QSL_RCP_DATA_TSA (0xada2ddafUL) +#define QSL_RCP_DATA_VLI (0x6da78f6dUL) +#define QSL_UNMQ_CTRL (0xe759d3f1UL) +#define QSL_UNMQ_CTRL_ADR (0xe5833152UL) +#define QSL_UNMQ_CTRL_CNT (0xf58ba883UL) +#define QSL_UNMQ_DATA (0x488851e8UL) +#define QSL_UNMQ_DATA_DEST_QUEUE (0xef8ce959UL) +#define QSL_UNMQ_DATA_EN (0x36ca8378UL) + +#endif /* _NTHW_FPGA_REG_DEFS_QSL_ */ + +/* + * Auto-generated file - do *NOT* edit + */ -- 2.45.0