[PATCH v3 17/50] net/ntnic: add slicer (SLC LR) flow module

[Serhii Iliushyk <sil-plv@napatech.com>]

From: Oleksandr Kolomeiets <okl-plv@napatech.com>

The Slicer for Local Retransmit module can cut of the head a packet
before the packet leaves the FPGA RX pipeline.
This is used when the TX pipeline is configured
to add a new head in the packet.

Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
v3
* Remove newline characters from logs.
---
 drivers/net/ntnic/include/hw_mod_backend.h    |  14 ++
 drivers/net/ntnic/include/hw_mod_slc_lr_v2.h  |  25 ++++
 drivers/net/ntnic/meson.build                 |   1 +
 .../nthw/flow_api/flow_backend/flow_backend.c |  66 +++++++++
 .../ntnic/nthw/flow_filter/flow_nthw_slc_lr.c | 126 ++++++++++++++++++
 .../ntnic/nthw/flow_filter/flow_nthw_slc_lr.h |  54 ++++++++
 .../ntnic/nthw/supported/nthw_fpga_mod_defs.h |   1 +
 .../ntnic/nthw/supported/nthw_fpga_reg_defs.h |   2 +
 .../nthw/supported/nthw_fpga_reg_defs_slc.h   |  34 +++++
 .../supported/nthw_fpga_reg_defs_slc_lr.h     |  23 ++++
 10 files changed, 346 insertions(+)
 create mode 100644 drivers/net/ntnic/include/hw_mod_slc_lr_v2.h
 create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.c
 create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h
 create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h

diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h
index 84f2ed6c6a..309365f30d 100644
--- a/drivers/net/ntnic/include/hw_mod_backend.h
+++ b/drivers/net/ntnic/include/hw_mod_backend.h
@@ -13,6 +13,7 @@
 #include "hw_mod_flm_v25.h"
 #include "hw_mod_km_v7.h"
 #include "hw_mod_qsl_v7.h"
+#include "hw_mod_slc_lr_v2.h"
 #include "hw_mod_hsh_v5.h"
 
 #define MAX_PHYS_ADAPTERS 8
@@ -96,6 +97,13 @@ struct qsl_func_s {
 	};
 };
 
+struct slc_lr_func_s {
+	COMMON_FUNC_INFO_S;
+	union {
+		struct hw_mod_slc_lr_v2_s v2;
+	};
+};
+
 enum debug_mode_e {
 	FLOW_BACKEND_DEBUG_MODE_NONE = 0x0000,
 	FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001
@@ -214,6 +222,12 @@ struct flow_api_backend_ops {
 	int (*qsl_qst_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt);
 	int (*qsl_qen_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt);
 	int (*qsl_unmq_flush)(void *dev, const struct qsl_func_s *qsl, int entry, int cnt);
+
+	/* SLC LR */
+	bool (*get_slc_lr_present)(void *dev);
+	uint32_t (*get_slc_lr_version)(void *dev);
+	int (*slc_lr_rcp_flush)(void *dev, const struct slc_lr_func_s *slc_lr, int category,
+		int cnt);
 };
 
 struct flow_api_backend_s {
diff --git a/drivers/net/ntnic/include/hw_mod_slc_lr_v2.h b/drivers/net/ntnic/include/hw_mod_slc_lr_v2.h
new file mode 100644
index 0000000000..718a3cff27
--- /dev/null
+++ b/drivers/net/ntnic/include/hw_mod_slc_lr_v2.h
@@ -0,0 +1,25 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef _HW_MOD_SLC_LR_V2_H_
+#define _HW_MOD_SLC_LR_V2_H_
+
+#include <stdint.h>
+
+struct slc_lr_v2_rcp_s {
+	uint32_t head_slc_en;
+	uint32_t head_dyn;
+	int32_t head_ofs;
+	uint32_t tail_slc_en;
+	uint32_t tail_dyn;
+	int32_t tail_ofs;
+	uint32_t pcap;
+};
+
+struct hw_mod_slc_lr_v2_s {
+	struct slc_lr_v2_rcp_s *rcp;
+};
+
+#endif	/* _HW_MOD_SLC_V2_H_ */
diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build
index c7c5cd997f..2c303f6980 100644
--- a/drivers/net/ntnic/meson.build
+++ b/drivers/net/ntnic/meson.build
@@ -53,6 +53,7 @@ sources = files(
         'nthw/flow_filter/flow_nthw_info.c',
         'nthw/flow_filter/flow_nthw_km.c',
         'nthw/flow_filter/flow_nthw_qsl.c',
+        'nthw/flow_filter/flow_nthw_slc_lr.c',
         'nthw/model/nthw_fpga_model.c',
         'nthw/nthw_platform.c',
         'nthw/nthw_rac.c',
diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
index d1c2e3ab44..c7a6ff0e97 100644
--- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
+++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c
@@ -12,6 +12,7 @@
 #include "flow_nthw_flm.h"
 #include "flow_nthw_hsh.h"
 #include "flow_nthw_qsl.h"
+#include "flow_nthw_slc_lr.h"
 #include "ntnic_mod_reg.h"
 #include "nthw_fpga_model.h"
 #include "hw_mod_backend.h"
@@ -32,6 +33,7 @@ static struct backend_dev_s {
 	struct flm_nthw *p_flm_nthw;
 	struct hsh_nthw *p_hsh_nthw;
 	struct qsl_nthw *p_qsl_nthw;
+	struct slc_lr_nthw *p_slc_lr_nthw;
 	struct ifr_nthw *p_ifr_nthw;    /* TPE module */
 } be_devs[MAX_PHYS_ADAPTERS];
 
@@ -1436,6 +1438,55 @@ static int qsl_unmq_flush(void *be_dev, const struct qsl_func_s *qsl, int entry,
 	return 0;
 }
 
+/*
+ * SLC LR
+ */
+
+static bool slc_lr_get_present(void *be_dev)
+{
+	struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+	return be->p_slc_lr_nthw != NULL;
+}
+
+static uint32_t slc_lr_get_version(void *be_dev)
+{
+	struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+	return (uint32_t)((nthw_module_get_major_version(be->p_slc_lr_nthw->m_slc_lr) << 16) |
+			(nthw_module_get_minor_version(be->p_slc_lr_nthw->m_slc_lr) & 0xffff));
+}
+
+static int slc_lr_rcp_flush(void *be_dev, const struct slc_lr_func_s *slc_lr, int category,
+	int cnt)
+{
+	struct backend_dev_s *be = (struct backend_dev_s *)be_dev;
+	CHECK_DEBUG_ON(be, slc_lr, be->p_slc_lr_nthw);
+
+	if (slc_lr->ver == 2) {
+		slc_lr_nthw_rcp_cnt(be->p_slc_lr_nthw, 1);
+
+		for (int i = 0; i < cnt; i++) {
+			slc_lr_nthw_rcp_select(be->p_slc_lr_nthw, category + i);
+			slc_lr_nthw_rcp_head_slc_en(be->p_slc_lr_nthw,
+				slc_lr->v2.rcp[category + i].head_slc_en);
+			slc_lr_nthw_rcp_head_dyn(be->p_slc_lr_nthw,
+				slc_lr->v2.rcp[category + i].head_dyn);
+			slc_lr_nthw_rcp_head_ofs(be->p_slc_lr_nthw,
+				slc_lr->v2.rcp[category + i].head_ofs);
+			slc_lr_nthw_rcp_tail_slc_en(be->p_slc_lr_nthw,
+				slc_lr->v2.rcp[category + i].tail_slc_en);
+			slc_lr_nthw_rcp_tail_dyn(be->p_slc_lr_nthw,
+				slc_lr->v2.rcp[category + i].tail_dyn);
+			slc_lr_nthw_rcp_tail_ofs(be->p_slc_lr_nthw,
+				slc_lr->v2.rcp[category + i].tail_ofs);
+			slc_lr_nthw_rcp_pcap(be->p_slc_lr_nthw, slc_lr->v2.rcp[category + i].pcap);
+			slc_lr_nthw_rcp_flush(be->p_slc_lr_nthw);
+		}
+	}
+
+	CHECK_DEBUG_OFF(slc_lr, be->p_slc_lr_nthw);
+	return 0;
+}
+
 /*
  * DBS
  */
@@ -1556,6 +1607,10 @@ const struct flow_api_backend_ops flow_be_iface = {
 	qsl_qst_flush,
 	qsl_qen_flush,
 	qsl_unmq_flush,
+
+	slc_lr_get_present,
+	slc_lr_get_version,
+	slc_lr_rcp_flush,
 };
 
 const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, void **dev)
@@ -1626,6 +1681,16 @@ const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, vo
 		be_devs[physical_adapter_no].p_qsl_nthw = NULL;
 	}
 
+	/* Init nthw SLC LR */
+	if (slc_lr_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) {
+		struct slc_lr_nthw *pslclrnthw = slc_lr_nthw_new();
+		slc_lr_nthw_init(pslclrnthw, p_fpga, physical_adapter_no);
+		be_devs[physical_adapter_no].p_slc_lr_nthw = pslclrnthw;
+
+	} else {
+		be_devs[physical_adapter_no].p_slc_lr_nthw = NULL;
+	}
+
 	be_devs[physical_adapter_no].adapter_no = physical_adapter_no;
 	*dev = (void *)&be_devs[physical_adapter_no];
 
@@ -1641,6 +1706,7 @@ static void bin_flow_backend_done(void *dev)
 	flm_nthw_delete(be_dev->p_flm_nthw);
 	hsh_nthw_delete(be_dev->p_hsh_nthw);
 	qsl_nthw_delete(be_dev->p_qsl_nthw);
+	slc_lr_nthw_delete(be_dev->p_slc_lr_nthw);
 }
 
 static const struct flow_backend_ops ops = {
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.c b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.c
new file mode 100644
index 0000000000..e062a700eb
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.c
@@ -0,0 +1,126 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "ntlog.h"
+
+#include "nthw_drv.h"
+#include "nthw_register.h"
+
+#include "flow_nthw_slc_lr.h"
+
+void slc_lr_nthw_set_debug_mode(struct slc_lr_nthw *p, unsigned int n_debug_mode)
+{
+	nthw_module_set_debug_mode(p->m_slc_lr, n_debug_mode);
+}
+
+struct slc_lr_nthw *slc_lr_nthw_new(void)
+{
+	struct slc_lr_nthw *p = malloc(sizeof(struct slc_lr_nthw));
+
+	if (p)
+		(void)memset(p, 0, sizeof(*p));
+
+	return p;
+}
+
+void slc_lr_nthw_delete(struct slc_lr_nthw *p)
+{
+	if (p) {
+		(void)memset(p, 0, sizeof(*p));
+		free(p);
+	}
+}
+
+int slc_lr_nthw_init(struct slc_lr_nthw *p, nthw_fpga_t *p_fpga, int n_instance)
+{
+	const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str;
+	nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_SLC_LR, n_instance);
+
+	assert(n_instance >= 0 && n_instance < 256);
+
+	if (p == NULL)
+		return p_mod == NULL ? -1 : 0;
+
+	if (p_mod == NULL) {
+		NT_LOG(ERR, NTHW, "%s: Slc %d: no such instance", p_adapter_id_str, n_instance);
+		return -1;
+	}
+
+	p->mp_fpga = p_fpga;
+	p->m_physical_adapter_no = (uint8_t)n_instance;
+	p->m_slc_lr = nthw_fpga_query_module(p_fpga, MOD_SLC_LR, n_instance);
+
+	/* RCP */
+	p->mp_rcp_ctrl = nthw_module_get_register(p->m_slc_lr, SLC_RCP_CTRL);
+	p->mp_rcp_addr = nthw_register_get_field(p->mp_rcp_ctrl, SLC_RCP_CTRL_ADR);
+	p->mp_rcp_cnt = nthw_register_get_field(p->mp_rcp_ctrl, SLC_RCP_CTRL_CNT);
+	p->mp_rcp_data = nthw_module_get_register(p->m_slc_lr, SLC_RCP_DATA);
+	p->mp_rcp_data_head_slc_en =
+		nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_HEAD_SLC_EN);
+	p->mp_rcp_data_head_dyn = nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_HEAD_DYN);
+	p->mp_rcp_data_head_ofs = nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_HEAD_OFS);
+	p->mp_rcp_data_tail_slc_en =
+		nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_TAIL_SLC_EN);
+	p->mp_rcp_data_tail_dyn = nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_TAIL_DYN);
+	p->mp_rcp_data_tail_ofs = nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_TAIL_OFS);
+	p->mp_rcp_data_pcap = nthw_register_get_field(p->mp_rcp_data, SLC_RCP_DATA_PCAP);
+
+	return 0;
+}
+
+/* RCP */
+void slc_lr_nthw_rcp_select(const struct slc_lr_nthw *p, uint32_t val)
+{
+	nthw_field_set_val32(p->mp_rcp_addr, val);
+}
+
+void slc_lr_nthw_rcp_cnt(const struct slc_lr_nthw *p, uint32_t val)
+{
+	nthw_field_set_val32(p->mp_rcp_cnt, val);
+}
+
+void slc_lr_nthw_rcp_head_slc_en(const struct slc_lr_nthw *p, uint32_t val)
+{
+	nthw_field_set_val32(p->mp_rcp_data_head_slc_en, val);
+}
+
+void slc_lr_nthw_rcp_head_dyn(const struct slc_lr_nthw *p, uint32_t val)
+{
+	nthw_field_set_val32(p->mp_rcp_data_head_dyn, val);
+}
+
+void slc_lr_nthw_rcp_head_ofs(const struct slc_lr_nthw *p, int32_t val)
+{
+	nthw_field_set_val32(p->mp_rcp_data_head_ofs, val);
+}
+
+void slc_lr_nthw_rcp_tail_slc_en(const struct slc_lr_nthw *p, uint32_t val)
+{
+	nthw_field_set_val32(p->mp_rcp_data_tail_slc_en, val);
+}
+
+void slc_lr_nthw_rcp_tail_dyn(const struct slc_lr_nthw *p, uint32_t val)
+{
+	nthw_field_set_val32(p->mp_rcp_data_tail_dyn, val);
+}
+
+void slc_lr_nthw_rcp_tail_ofs(const struct slc_lr_nthw *p, int32_t val)
+{
+	nthw_field_set_val32(p->mp_rcp_data_tail_ofs, val);
+}
+
+void slc_lr_nthw_rcp_pcap(const struct slc_lr_nthw *p, uint32_t val)
+{
+	nthw_field_set_val32(p->mp_rcp_data_pcap, val);
+}
+
+void slc_lr_nthw_rcp_flush(const struct slc_lr_nthw *p)
+{
+	nthw_register_flush(p->mp_rcp_ctrl, 1);
+	nthw_register_flush(p->mp_rcp_data, 1);
+}
diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.h b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.h
new file mode 100644
index 0000000000..2eed32c022
--- /dev/null
+++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_slc_lr.h
@@ -0,0 +1,54 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2023 Napatech A/S
+ */
+
+#ifndef __FLOW_NTHW_SLC_LR_H__
+#define __FLOW_NTHW_SLC_LR_H__
+
+#include <stdint.h>
+
+#include "nthw_fpga_model.h"
+
+struct slc_lr_nthw {
+	uint8_t m_physical_adapter_no;
+	nthw_fpga_t *mp_fpga;
+
+	nthw_module_t *m_slc_lr;
+
+	nthw_register_t *mp_rcp_ctrl;
+	nthw_field_t *mp_rcp_addr;
+	nthw_field_t *mp_rcp_cnt;
+	nthw_register_t *mp_rcp_data;
+
+	nthw_field_t *mp_rcp_data_head_slc_en;
+	nthw_field_t *mp_rcp_data_head_dyn;
+	nthw_field_t *mp_rcp_data_head_ofs;
+	nthw_field_t *mp_rcp_data_tail_slc_en;
+	nthw_field_t *mp_rcp_data_tail_dyn;
+	nthw_field_t *mp_rcp_data_tail_ofs;
+	nthw_field_t *mp_rcp_data_pcap;
+};
+
+typedef struct slc_lr_nthw slc_lr_nthw_t;
+
+struct slc_lr_nthw *slc_lr_nthw_new(void);
+void slc_lr_nthw_delete(struct slc_lr_nthw *p);
+int slc_lr_nthw_init(struct slc_lr_nthw *p, nthw_fpga_t *p_fpga, int n_instance);
+
+int slc_lr_nthw_setup(struct slc_lr_nthw *p, int n_idx, int n_idx_cnt);
+void slc_lr_nthw_set_debug_mode(struct slc_lr_nthw *p, unsigned int n_debug_mode);
+
+/* RCP */
+void slc_lr_nthw_rcp_select(const struct slc_lr_nthw *p, uint32_t val);
+void slc_lr_nthw_rcp_cnt(const struct slc_lr_nthw *p, uint32_t val);
+void slc_lr_nthw_rcp_head_slc_en(const struct slc_lr_nthw *p, uint32_t val);
+void slc_lr_nthw_rcp_head_dyn(const struct slc_lr_nthw *p, uint32_t val);
+void slc_lr_nthw_rcp_head_ofs(const struct slc_lr_nthw *p, int32_t val);
+void slc_lr_nthw_rcp_tail_slc_en(const struct slc_lr_nthw *p, uint32_t val);
+void slc_lr_nthw_rcp_tail_dyn(const struct slc_lr_nthw *p, uint32_t val);
+void slc_lr_nthw_rcp_tail_ofs(const struct slc_lr_nthw *p, int32_t val);
+void slc_lr_nthw_rcp_pcap(const struct slc_lr_nthw *p, uint32_t val);
+void slc_lr_nthw_rcp_flush(const struct slc_lr_nthw *p);
+
+#endif	/* __FLOW_NTHW_SLC_LR_H__ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
index b159da7597..22682b6a5f 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h
@@ -33,6 +33,7 @@
 #define MOD_RAC (0xae830b42UL)
 #define MOD_RST9563 (0x385d6d1dUL)
 #define MOD_SDC (0xd2369530UL)
+#define MOD_SLC_LR (0x969fc50bUL)
 #define MOD_IDX_COUNT (14)
 
 /* aliases - only aliases go below this point */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
index 7b99a7fbdb..f775a4b33a 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h
@@ -32,6 +32,8 @@
 #include "nthw_fpga_reg_defs_rac.h"
 #include "nthw_fpga_reg_defs_rst9563.h"
 #include "nthw_fpga_reg_defs_sdc.h"
+#include "nthw_fpga_reg_defs_slc.h"
+#include "nthw_fpga_reg_defs_slc_lr.h"
 
 /* aliases */
 
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h
new file mode 100644
index 0000000000..11a8ef79a1
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc.h
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+/*
+ * nthw_fpga_reg_defs_slc.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_SLC_
+#define _NTHW_FPGA_REG_DEFS_SLC_
+
+/* SLC */
+#define NTHW_MOD_SLC (0x1aef1f38UL)
+#define SLC_RCP_CTRL (0xa3373b1UL)
+#define SLC_RCP_CTRL_ADR (0xe64629e7UL)
+#define SLC_RCP_CTRL_CNT (0xf64eb036UL)
+#define SLC_RCP_DATA (0xa5e2f1a8UL)
+#define SLC_RCP_DATA_HEAD_DYN (0x86b55a78UL)
+#define SLC_RCP_DATA_HEAD_OFS (0x24bcd7deUL)
+#define SLC_RCP_DATA_HEAD_SLC_EN (0x61cf5ef7UL)
+#define SLC_RCP_DATA_PCAP (0x84909c04UL)
+#define SLC_RCP_DATA_TAIL_DYN (0x85cd93a3UL)
+#define SLC_RCP_DATA_TAIL_OFS (0x27c41e05UL)
+#define SLC_RCP_DATA_TAIL_SLC_EN (0xa4f5112cUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_SLC_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h
new file mode 100644
index 0000000000..ef1f358cb3
--- /dev/null
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_slc_lr.h
@@ -0,0 +1,23 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2024 Napatech A/S
+ */
+
+/*
+ * nthw_fpga_reg_defs_slc_lr.h
+ *
+ * Auto-generated file - do *NOT* edit
+ *
+ */
+
+#ifndef _NTHW_FPGA_REG_DEFS_SLC_LR_
+#define _NTHW_FPGA_REG_DEFS_SLC_LR_
+
+/* SLC_LR */
+#define NTHW_MOD_SLC_LR (0x969fc50bUL)
+
+#endif	/* _NTHW_FPGA_REG_DEFS_SLC_LR_ */
+
+/*
+ * Auto-generated file - do *NOT* edit
+ */
-- 
2.45.0