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Signed-off-by: Oleksandr Kolomeiets --- v3 * Remove newline characters from logs. --- drivers/net/ntnic/include/hw_mod_backend.h | 16 ++ drivers/net/ntnic/include/hw_mod_pdb_v9.h | 42 ++++ drivers/net/ntnic/meson.build | 1 + .../nthw/flow_api/flow_backend/flow_backend.c | 93 ++++++++ .../ntnic/nthw/flow_filter/flow_nthw_pdb.c | 210 ++++++++++++++++++ .../ntnic/nthw/flow_filter/flow_nthw_pdb.h | 85 +++++++ .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 + .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 + .../nthw/supported/nthw_fpga_reg_defs_pdb.h | 48 ++++ 9 files changed, 497 insertions(+) create mode 100644 drivers/net/ntnic/include/hw_mod_pdb_v9.h create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_pdb.c create mode 100644 drivers/net/ntnic/nthw/flow_filter/flow_nthw_pdb.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h diff --git a/drivers/net/ntnic/include/hw_mod_backend.h b/drivers/net/ntnic/include/hw_mod_backend.h index 309365f30d..3ea2fefc53 100644 --- a/drivers/net/ntnic/include/hw_mod_backend.h +++ b/drivers/net/ntnic/include/hw_mod_backend.h @@ -13,6 +13,7 @@ #include "hw_mod_flm_v25.h" #include "hw_mod_km_v7.h" #include "hw_mod_qsl_v7.h" +#include "hw_mod_pdb_v9.h" #include "hw_mod_slc_lr_v2.h" #include "hw_mod_hsh_v5.h" @@ -104,6 +105,15 @@ struct slc_lr_func_s { }; }; +struct pdb_func_s { + COMMON_FUNC_INFO_S; + uint32_t nb_pdb_rcp_categories; + + union { + struct hw_mod_pdb_v9_s v9; + }; +}; + enum debug_mode_e { FLOW_BACKEND_DEBUG_MODE_NONE = 0x0000, FLOW_BACKEND_DEBUG_MODE_WRITE = 0x0001 @@ -228,6 +238,12 @@ struct flow_api_backend_ops { uint32_t (*get_slc_lr_version)(void *dev); int (*slc_lr_rcp_flush)(void *dev, const struct slc_lr_func_s *slc_lr, int category, int cnt); + + /* PDB */ + bool (*get_pdb_present)(void *dev); + uint32_t (*get_pdb_version)(void *dev); + int (*pdb_rcp_flush)(void *dev, const struct pdb_func_s *pdb, int category, int cnt); + int (*pdb_config_flush)(void *dev, const struct pdb_func_s *pdb); }; struct flow_api_backend_s { diff --git a/drivers/net/ntnic/include/hw_mod_pdb_v9.h b/drivers/net/ntnic/include/hw_mod_pdb_v9.h new file mode 100644 index 0000000000..b155ee6d1e --- /dev/null +++ b/drivers/net/ntnic/include/hw_mod_pdb_v9.h @@ -0,0 +1,42 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _HW_MOD_PDB_V9_H_ +#define _HW_MOD_PDB_V9_H_ + +#include + +struct pdb_v9_rcp_s { + uint32_t descriptor; + uint32_t desc_len; + uint32_t tx_port; + uint32_t tx_ignore; + uint32_t tx_now; + uint32_t crc_overwrite; + uint32_t align; + uint32_t ofs0_dyn; + int32_t ofs0_rel; + uint32_t ofs1_dyn; + int32_t ofs1_rel; + uint32_t ofs2_dyn; + int32_t ofs2_rel; + uint32_t ip_prot_tnl; + uint32_t ppc_hsh; + uint32_t duplicate_en; + uint32_t duplicate_bit; + uint32_t pcap_keep_fcs; /* only field added to v9 cmp to v7/8 */ +}; + +struct pdb_v9_config_s { + uint32_t ts_format; + uint32_t port_ofs; +}; + +struct hw_mod_pdb_v9_s { + struct pdb_v9_rcp_s *rcp; + struct pdb_v9_config_s *config; +}; + +#endif /* _HW_MOD_PDB_V9_H_ */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 2c303f6980..35f7feb7be 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -52,6 +52,7 @@ sources = files( 'nthw/flow_filter/flow_nthw_ifr.c', 'nthw/flow_filter/flow_nthw_info.c', 'nthw/flow_filter/flow_nthw_km.c', + 'nthw/flow_filter/flow_nthw_pdb.c', 'nthw/flow_filter/flow_nthw_qsl.c', 'nthw/flow_filter/flow_nthw_slc_lr.c', 'nthw/model/nthw_fpga_model.c', diff --git a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c index c7a6ff0e97..13bc9f479a 100644 --- a/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c +++ b/drivers/net/ntnic/nthw/flow_api/flow_backend/flow_backend.c @@ -13,6 +13,7 @@ #include "flow_nthw_hsh.h" #include "flow_nthw_qsl.h" #include "flow_nthw_slc_lr.h" +#include "flow_nthw_pdb.h" #include "ntnic_mod_reg.h" #include "nthw_fpga_model.h" #include "hw_mod_backend.h" @@ -34,6 +35,7 @@ static struct backend_dev_s { struct hsh_nthw *p_hsh_nthw; struct qsl_nthw *p_qsl_nthw; struct slc_lr_nthw *p_slc_lr_nthw; + struct pdb_nthw *p_pdb_nthw; struct ifr_nthw *p_ifr_nthw; /* TPE module */ } be_devs[MAX_PHYS_ADAPTERS]; @@ -1487,6 +1489,81 @@ static int slc_lr_rcp_flush(void *be_dev, const struct slc_lr_func_s *slc_lr, in return 0; } +/* + * PDB + */ + +static bool pdb_get_present(void *be_dev) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + return be->p_pdb_nthw != NULL; +} + +static uint32_t pdb_get_version(void *be_dev) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + return (uint32_t)((nthw_module_get_major_version(be->p_pdb_nthw->m_pdb) << 16) | + (nthw_module_get_minor_version(be->p_pdb_nthw->m_pdb) & 0xffff)); +} + +static int pdb_rcp_flush(void *be_dev, const struct pdb_func_s *pdb, int category, int cnt) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, pdb, be->p_pdb_nthw); + + if (pdb->ver == 9) { + pdb_nthw_rcp_cnt(be->p_pdb_nthw, 1); + + for (int i = 0; i < cnt; i++) { + pdb_nthw_rcp_select(be->p_pdb_nthw, category + i); + pdb_nthw_rcp_descriptor(be->p_pdb_nthw, + pdb->v9.rcp[category + i].descriptor); + pdb_nthw_rcp_desc_len(be->p_pdb_nthw, pdb->v9.rcp[category + i].desc_len); + pdb_nthw_rcp_tx_port(be->p_pdb_nthw, pdb->v9.rcp[category + i].tx_port); + pdb_nthw_rcp_tx_ignore(be->p_pdb_nthw, + pdb->v9.rcp[category + i].tx_ignore); + pdb_nthw_rcp_tx_now(be->p_pdb_nthw, pdb->v9.rcp[category + i].tx_now); + pdb_nthw_rcp_crc_overwrite(be->p_pdb_nthw, + pdb->v9.rcp[category + i].crc_overwrite); + pdb_nthw_rcp_align(be->p_pdb_nthw, pdb->v9.rcp[category + i].align); + pdb_nthw_rcp_ofs0_dyn(be->p_pdb_nthw, pdb->v9.rcp[category + i].ofs0_dyn); + pdb_nthw_rcp_ofs0_rel(be->p_pdb_nthw, pdb->v9.rcp[category + i].ofs0_rel); + pdb_nthw_rcp_ofs1_dyn(be->p_pdb_nthw, pdb->v9.rcp[category + i].ofs1_dyn); + pdb_nthw_rcp_ofs1_rel(be->p_pdb_nthw, pdb->v9.rcp[category + i].ofs1_rel); + pdb_nthw_rcp_ofs2_dyn(be->p_pdb_nthw, pdb->v9.rcp[category + i].ofs2_dyn); + pdb_nthw_rcp_ofs2_rel(be->p_pdb_nthw, pdb->v9.rcp[category + i].ofs2_rel); + pdb_nthw_rcp_ip_prot_tnl(be->p_pdb_nthw, + pdb->v9.rcp[category + i].ip_prot_tnl); + pdb_nthw_rcp_ppc_hsh(be->p_pdb_nthw, pdb->v9.rcp[category + i].ppc_hsh); + pdb_nthw_rcp_duplicate_en(be->p_pdb_nthw, + pdb->v9.rcp[category + i].duplicate_en); + pdb_nthw_rcp_duplicate_bit(be->p_pdb_nthw, + pdb->v9.rcp[category + i].duplicate_bit); + pdb_nthw_rcp_duplicate_bit(be->p_pdb_nthw, + pdb->v9.rcp[category + i].pcap_keep_fcs); + pdb_nthw_rcp_flush(be->p_pdb_nthw); + } + } + + CHECK_DEBUG_OFF(pdb, be->p_pdb_nthw); + return 0; +} + +static int pdb_config_flush(void *be_dev, const struct pdb_func_s *pdb) +{ + struct backend_dev_s *be = (struct backend_dev_s *)be_dev; + CHECK_DEBUG_ON(be, pdb, be->p_pdb_nthw); + + if (pdb->ver == 9) { + pdb_nthw_config_ts_format(be->p_pdb_nthw, pdb->v9.config->ts_format); + pdb_nthw_config_port_ofs(be->p_pdb_nthw, pdb->v9.config->port_ofs); + pdb_nthw_config_flush(be->p_pdb_nthw); + } + + CHECK_DEBUG_OFF(pdb, be->p_pdb_nthw); + return 0; +} + /* * DBS */ @@ -1611,6 +1688,11 @@ const struct flow_api_backend_ops flow_be_iface = { slc_lr_get_present, slc_lr_get_version, slc_lr_rcp_flush, + + pdb_get_present, + pdb_get_version, + pdb_rcp_flush, + pdb_config_flush, }; const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, void **dev) @@ -1691,6 +1773,16 @@ const struct flow_api_backend_ops *bin_flow_backend_init(nthw_fpga_t *p_fpga, vo be_devs[physical_adapter_no].p_slc_lr_nthw = NULL; } + /* Init nthw PDB */ + if (pdb_nthw_init(NULL, p_fpga, physical_adapter_no) == 0) { + struct pdb_nthw *ppdbnthw = pdb_nthw_new(); + pdb_nthw_init(ppdbnthw, p_fpga, physical_adapter_no); + be_devs[physical_adapter_no].p_pdb_nthw = ppdbnthw; + + } else { + be_devs[physical_adapter_no].p_pdb_nthw = NULL; + } + be_devs[physical_adapter_no].adapter_no = physical_adapter_no; *dev = (void *)&be_devs[physical_adapter_no]; @@ -1707,6 +1799,7 @@ static void bin_flow_backend_done(void *dev) hsh_nthw_delete(be_dev->p_hsh_nthw); qsl_nthw_delete(be_dev->p_qsl_nthw); slc_lr_nthw_delete(be_dev->p_slc_lr_nthw); + pdb_nthw_delete(be_dev->p_pdb_nthw); } static const struct flow_backend_ops ops = { diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_pdb.c b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_pdb.c new file mode 100644 index 0000000000..4a9713965b --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_pdb.c @@ -0,0 +1,210 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "flow_nthw_pdb.h" + +void pdb_nthw_set_debug_mode(struct pdb_nthw *p, unsigned int n_debug_mode) +{ + nthw_module_set_debug_mode(p->m_pdb, n_debug_mode); +} + +struct pdb_nthw *pdb_nthw_new(void) +{ + struct pdb_nthw *p = malloc(sizeof(struct pdb_nthw)); + + if (p) + (void)memset(p, 0, sizeof(*p)); + + return p; +} + +void pdb_nthw_delete(struct pdb_nthw *p) +{ + if (p) { + (void)memset(p, 0, sizeof(*p)); + free(p); + } +} + +int pdb_nthw_init(struct pdb_nthw *p, nthw_fpga_t *p_fpga, int n_instance) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_PDB, n_instance); + assert(n_instance >= 0 && n_instance < 256); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: Pdb %d: no such instance", p_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->m_physical_adapter_no = (uint8_t)n_instance; + p->m_pdb = p_mod; + + /* RCP */ + p->mp_rcp_ctrl = nthw_module_get_register(p->m_pdb, PDB_RCP_CTRL); + p->mp_rcp_addr = nthw_register_get_field(p->mp_rcp_ctrl, PDB_RCP_CTRL_ADR); + p->mp_rcp_cnt = nthw_register_get_field(p->mp_rcp_ctrl, PDB_RCP_CTRL_CNT); + p->mp_rcp_data = nthw_module_get_register(p->m_pdb, PDB_RCP_DATA); + p->mp_rcp_data_descriptor = + nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_DESCRIPTOR); + p->mp_rcp_data_desc_len = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_DESC_LEN); + p->mp_rcp_data_tx_port = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_TX_PORT); + p->mp_rcp_data_tx_ignore = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_TX_IGNORE); + p->mp_rcp_data_tx_now = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_TX_NOW); + p->mp_rcp_data_crc_overwrite = + nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_CRC_OVERWRITE); + p->mp_rcp_data_align = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_ALIGN); + p->mp_rcp_data_ofs0_dyn = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_OFS0_DYN); + p->mp_rcp_data_ofs0_rel = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_OFS0_REL); + p->mp_rcp_data_ofs1_dyn = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_OFS1_DYN); + p->mp_rcp_data_ofs1_rel = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_OFS1_REL); + p->mp_rcp_data_ofs2_dyn = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_OFS2_DYN); + p->mp_rcp_data_ofs2_rel = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_OFS2_REL); + p->mp_rcp_data_ip_prot_tnl = + nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_IP_PROT_TNL); + p->mp_rcp_data_ppc_hsh = nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_PPC_HSH); + p->mp_rcp_data_duplicate_en = + nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_DUPLICATE_EN); + p->mp_rcp_data_duplicate_bit = + nthw_register_get_field(p->mp_rcp_data, PDB_RCP_DATA_DUPLICATE_BIT); + p->mp_rcp_data_pcap_keep_fcs = + nthw_register_query_field(p->mp_rcp_data, PDB_RCP_DATA_PCAP_KEEP_FCS); + /* CONFIG */ + p->mp_config = nthw_module_get_register(p->m_pdb, PDB_CONFIG); + p->mp_config_ts_format = nthw_register_get_field(p->mp_config, PDB_CONFIG_TS_FORMAT); + p->mp_config_port_ofs = nthw_register_get_field(p->mp_config, PDB_CONFIG_PORT_OFS); + + return 0; +} + +/* RCP */ +void pdb_nthw_rcp_select(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_addr, val); +} + +void pdb_nthw_rcp_cnt(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_cnt, val); +} + +void pdb_nthw_rcp_descriptor(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_descriptor, val); +} + +void pdb_nthw_rcp_desc_len(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_desc_len, val); +} + +void pdb_nthw_rcp_tx_port(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tx_port, val); +} + +void pdb_nthw_rcp_tx_ignore(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tx_ignore, val); +} + +void pdb_nthw_rcp_tx_now(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_tx_now, val); +} + +void pdb_nthw_rcp_crc_overwrite(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_crc_overwrite, val); +} + +void pdb_nthw_rcp_align(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_align, val); +} + +void pdb_nthw_rcp_ofs0_dyn(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_ofs0_dyn, val); +} + +void pdb_nthw_rcp_ofs0_rel(const struct pdb_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_ofs0_rel, val); +} + +void pdb_nthw_rcp_ofs1_dyn(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_ofs1_dyn, val); +} + +void pdb_nthw_rcp_ofs1_rel(const struct pdb_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_ofs1_rel, val); +} + +void pdb_nthw_rcp_ofs2_dyn(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_ofs2_dyn, val); +} + +void pdb_nthw_rcp_ofs2_rel(const struct pdb_nthw *p, int32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_ofs2_rel, val); +} + +void pdb_nthw_rcp_ip_prot_tnl(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_ip_prot_tnl, val); +} + +void pdb_nthw_rcp_ppc_hsh(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_ppc_hsh, val); +} + +void pdb_nthw_rcp_duplicate_en(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_duplicate_en, val); +} + +void pdb_nthw_rcp_duplicate_bit(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_rcp_data_duplicate_bit, val); +} + +void pdb_nthw_rcp_flush(const struct pdb_nthw *p) +{ + nthw_register_flush(p->mp_rcp_ctrl, 1); + nthw_register_flush(p->mp_rcp_data, 1); +} + +/* CONFIG */ +void pdb_nthw_config_ts_format(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_config_ts_format, val); +} + +void pdb_nthw_config_port_ofs(const struct pdb_nthw *p, uint32_t val) +{ + nthw_field_set_val32(p->mp_config_port_ofs, val); +} + +void pdb_nthw_config_flush(const struct pdb_nthw *p) +{ + nthw_register_flush(p->mp_config, 1); +} diff --git a/drivers/net/ntnic/nthw/flow_filter/flow_nthw_pdb.h b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_pdb.h new file mode 100644 index 0000000000..aafe12d3e0 --- /dev/null +++ b/drivers/net/ntnic/nthw/flow_filter/flow_nthw_pdb.h @@ -0,0 +1,85 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __FLOW_NTHW_PDB_H__ +#define __FLOW_NTHW_PDB_H__ + +#include + +#include "nthw_fpga_model.h" + +struct pdb_nthw { + uint8_t m_physical_adapter_no; + nthw_fpga_t *mp_fpga; + + nthw_module_t *m_pdb; + + nthw_register_t *mp_rcp_ctrl; + nthw_field_t *mp_rcp_addr; + nthw_field_t *mp_rcp_cnt; + nthw_register_t *mp_rcp_data; + nthw_field_t *mp_rcp_data_descriptor; + nthw_field_t *mp_rcp_data_desc_len; + nthw_field_t *mp_rcp_data_tx_port; + nthw_field_t *mp_rcp_data_tx_ignore; + nthw_field_t *mp_rcp_data_tx_now; + nthw_field_t *mp_rcp_data_crc_overwrite; + nthw_field_t *mp_rcp_data_align; + nthw_field_t *mp_rcp_data_ofs0_dyn; + nthw_field_t *mp_rcp_data_ofs0_rel; + nthw_field_t *mp_rcp_data_ofs1_dyn; + nthw_field_t *mp_rcp_data_ofs1_rel; + nthw_field_t *mp_rcp_data_ofs2_dyn; + nthw_field_t *mp_rcp_data_ofs2_rel; + nthw_field_t *mp_rcp_data_ip_prot_tnl; + nthw_field_t *mp_rcp_data_ppc_hsh; + nthw_field_t *mp_rcp_data_duplicate_en; + nthw_field_t *mp_rcp_data_duplicate_bit; + nthw_field_t *mp_rcp_data_pcap_keep_fcs; + + nthw_register_t *mp_config; + nthw_field_t *mp_config_ts_format; + nthw_field_t *mp_config_port_ofs; +}; + +typedef struct pdb_nthw pdb_nthw_t; + +struct pdb_nthw *pdb_nthw_new(void); +void pdb_nthw_delete(struct pdb_nthw *p); +int pdb_nthw_init(struct pdb_nthw *p, nthw_fpga_t *p_fpga, int n_instance); + +int pdb_nthw_setup(struct pdb_nthw *p, int n_idx, int n_idx_cnt); +void pdb_nthw_set_debug_mode(struct pdb_nthw *p, unsigned int n_debug_mode); + +/* RCP */ +void pdb_nthw_rcp_select(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_cnt(const struct pdb_nthw *p, uint32_t val); + +void pdb_nthw_rcp_descriptor(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_desc_len(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_tx_port(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_tx_ignore(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_tx_now(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_crc_overwrite(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_align(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_ofs0_dyn(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_ofs0_rel(const struct pdb_nthw *p, int32_t val); +void pdb_nthw_rcp_ofs1_dyn(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_ofs1_rel(const struct pdb_nthw *p, int32_t val); +void pdb_nthw_rcp_ofs2_dyn(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_ofs2_rel(const struct pdb_nthw *p, int32_t val); +void pdb_nthw_rcp_ip_prot_tnl(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_ppc_hsh(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_duplicate_en(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_duplicate_bit(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_rcp_flush(const struct pdb_nthw *p); + +/* CONFIG */ +void pdb_nthw_config_ts_format(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_config_port_ofs(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_config_port_ofs(const struct pdb_nthw *p, uint32_t val); +void pdb_nthw_config_flush(const struct pdb_nthw *p); + +#endif /* __FLOW_NTHW_PDB_H__ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h index 22682b6a5f..65c482f7c8 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -29,6 +29,7 @@ #define MOD_PCIE3 (0xfbc48c18UL) #define MOD_PCI_RD_TG (0x9ad9eed2UL) #define MOD_PCI_WR_TG (0x274b69e1UL) +#define MOD_PDB (0xa7771bffUL) #define MOD_QSL (0x448ed859UL) #define MOD_RAC (0xae830b42UL) #define MOD_RST9563 (0x385d6d1dUL) diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h index f775a4b33a..ccb57fdd47 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h @@ -28,6 +28,7 @@ #include "nthw_fpga_reg_defs_pcie3.h" #include "nthw_fpga_reg_defs_pci_rd_tg.h" #include "nthw_fpga_reg_defs_pci_wr_tg.h" +#include "nthw_fpga_reg_defs_pdb.h" #include "nthw_fpga_reg_defs_qsl.h" #include "nthw_fpga_reg_defs_rac.h" #include "nthw_fpga_reg_defs_rst9563.h" diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h new file mode 100644 index 0000000000..98887ffccb --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pdb.h @@ -0,0 +1,48 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +/* + * nthw_fpga_reg_defs_pdb.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_PDB_ +#define _NTHW_FPGA_REG_DEFS_PDB_ + +/* PDB */ +#define NTHW_MOD_PDB (0xa7771bffUL) +#define PDB_CONFIG (0xf73771edUL) +#define PDB_CONFIG_PORT_OFS (0xb5b30335UL) +#define PDB_CONFIG_TS_FORMAT (0x7013d8aUL) +#define PDB_RCP_CTRL (0x28ac2b3aUL) +#define PDB_RCP_CTRL_ADR (0x9d08b0e4UL) +#define PDB_RCP_CTRL_CNT (0x8d002935UL) +#define PDB_RCP_DATA (0x877da923UL) +#define PDB_RCP_DATA_ALIGN (0xe802afb8UL) +#define PDB_RCP_DATA_CRC_OVERWRITE (0x4847dc0aUL) +#define PDB_RCP_DATA_DESCRIPTOR (0x46cb76faUL) +#define PDB_RCP_DATA_DESC_LEN (0xf467e85bUL) +#define PDB_RCP_DATA_DUPLICATE_BIT (0xaeb59507UL) +#define PDB_RCP_DATA_DUPLICATE_EN (0xbab03efeUL) +#define PDB_RCP_DATA_IP_PROT_TNL (0xec892325UL) +#define PDB_RCP_DATA_OFS0_DYN (0xcef3786aUL) +#define PDB_RCP_DATA_OFS0_REL (0xde219bd9UL) +#define PDB_RCP_DATA_OFS1_DYN (0xf39351daUL) +#define PDB_RCP_DATA_OFS1_REL (0xe341b269UL) +#define PDB_RCP_DATA_OFS2_DYN (0xb4332b0aUL) +#define PDB_RCP_DATA_OFS2_REL (0xa4e1c8b9UL) +#define PDB_RCP_DATA_PCAP_KEEP_FCS (0x90bc735eUL) +#define PDB_RCP_DATA_PPC_HSH (0xac10e9f8UL) +#define PDB_RCP_DATA_TX_IGNORE (0x14c556dcUL) +#define PDB_RCP_DATA_TX_NOW (0x479cb22cUL) +#define PDB_RCP_DATA_TX_PORT (0x412a5ed8UL) + +#endif /* _NTHW_FPGA_REG_DEFS_PDB_ */ + +/* + * Auto-generated file - do *NOT* edit + */ -- 2.45.0