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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1PEPF000042A7.mail.protection.outlook.com (10.167.243.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.13 via Frontend Transport; Fri, 11 Oct 2024 09:34:40 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 11 Oct 2024 02:34:27 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 11 Oct 2024 02:34:25 -0700 From: Dariusz Sosnowski To: Viacheslav Ovsiienko , Bing Zhao , Ori Kam , Suanming Mou , Matan Azrad CC: , Konstantin Ananyev Subject: [PATCH v2 4/4] net/mlx5: disable config restore Date: Fri, 11 Oct 2024 11:33:51 +0200 Message-ID: <20241011093351.187191-5-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241011093351.187191-1-dsosnowski@nvidia.com> References: <20241011092103.181145-1-dsosnowski@nvidia.com> <20241011093351.187191-1-dsosnowski@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A7:EE_|DM4PR12MB6205:EE_ X-MS-Office365-Filtering-Correlation-Id: cd1a5125-6040-4609-930d-08dce9d7ee42 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2024 09:34:40.2942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd1a5125-6040-4609-930d-08dce9d7ee42 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6205 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org mlx5 PMD does not require configuration restore on rte_eth_dev_start(). Add implementation of get_restore_flags() indicating that. Signed-off-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5.c | 2 ++ drivers/net/mlx5/mlx5.h | 3 +++ drivers/net/mlx5/mlx5_ethdev.c | 19 +++++++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 8d266b0e64..9b6acaf7f1 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -2571,6 +2571,7 @@ const struct eth_dev_ops mlx5_dev_ops = { .count_aggr_ports = mlx5_count_aggr_ports, .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, .rx_metadata_negotiate = mlx5_flow_rx_metadata_negotiate, + .get_restore_flags = mlx5_get_restore_flags, }; /* Available operations from secondary process. */ @@ -2663,6 +2664,7 @@ const struct eth_dev_ops mlx5_dev_ops_isolate = { .get_monitor_addr = mlx5_get_monitor_addr, .count_aggr_ports = mlx5_count_aggr_ports, .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, + .get_restore_flags = mlx5_get_restore_flags, }; /** diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 869aac032b..a5829fb71a 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -2228,6 +2228,9 @@ eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); +void mlx5_get_restore_flags(struct rte_eth_dev *dev, + enum rte_eth_dev_operation op, + uint32_t *flags); /* mlx5_ethdev_os.c */ diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index 6a678d6dcc..8b78efc3fd 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -796,3 +796,22 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) cap->tx_cap.rte_memory = hca_attr->hairpin_sq_wq_in_host_mem; return 0; } + +/** + * Indicate to ethdev layer, what configuration must be restored. + * + * @param[in] dev + * Pointer to Ethernet device structure. + * @param[in] op + * Type of operation which might require. + * @param[out] flags + * Restore flags will be stored here. + */ +void +mlx5_get_restore_flags(__rte_unused struct rte_eth_dev *dev, + __rte_unused enum rte_eth_dev_operation op, + uint32_t *flags) +{ + /* mlx5 PMD does not require any configuration restore. */ + *flags = 0; +} -- 2.39.5