From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1934A45B12; Fri, 11 Oct 2024 15:33:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 04B3F40395; Fri, 11 Oct 2024 15:33:10 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by mails.dpdk.org (Postfix) with ESMTP id 4BB9D40395 for ; Fri, 11 Oct 2024 15:33:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728653589; x=1760189589; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Rs/1EEMXCRDnQUWyY5CZkCTdpOjTMOau6Bhm1f0BoI=; b=PYlXDFjMHxTsjzK+nJJFCeUto3Di4a02F0yv1R10MByco9dC2ZZKeTax 5bCXwuzznTKzkZ27c+yoCHT8ii5SFue8+glGE4IitXdLycu7CbnNzkQzG X5L3wb3hYOZGtX0RTZncmQWaQyXB0XEYRZBJarDWFGmrxKFzM/5cuWsxp uBRnVeS0Ycc8/5tzEnOZaIMhk6ixPDKmNm87PGLnvXKJwDUOqskLMkltq TNBFrmaUma2w/rHzzJffoJGOe4xVk1nMBjTYdRQE2jaGGq629ABlOGGj+ mxp3A/7piejbX0NzCOTm4CRSrYpeZ1R2SM+lIHE8rsSad4zJxBr2IPaQu Q==; X-CSE-ConnectionGUID: /3LkbMi/QyeaqmT3ZAGKLw== X-CSE-MsgGUID: +Nerj6/WTfCyhKsrUDdKJg== X-IronPort-AV: E=McAfee;i="6700,10204,11221"; a="28144069" X-IronPort-AV: E=Sophos;i="6.11,196,1725346800"; d="scan'208";a="28144069" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2024 06:33:08 -0700 X-CSE-ConnectionGUID: ocF3oreVShGAon9IAdSKqQ== X-CSE-MsgGUID: BgNOA/2+TGyEecpPQeJPYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,196,1725346800"; d="scan'208";a="107764834" Received: from unknown (HELO silpixa00401385.ir.intel.com) ([10.237.214.25]) by orviesa002.jf.intel.com with ESMTP; 11 Oct 2024 06:33:07 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: david.marchand@redhat.com, wathsala.vithanage@arm.com, konstantin.ananyev@huawei.com, Bruce Richardson Subject: [PATCH v2] eal/x86: cache queried CPU flags Date: Fri, 11 Oct 2024 14:33:03 +0100 Message-ID: <20241011133303.1496014-1-bruce.richardson@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241007110725.377550-1-bruce.richardson@intel.com> References: <20241007110725.377550-1-bruce.richardson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Rather than re-querying the HW each time a CPU flag is requested, we can just save the return value in the flags array. This should speed up repeated querying of CPU flags, and provides a workaround for a reported issue where errors are seen with constant querying of the AVX-512 CPU flag from a non-AVX VM. Bugzilla ID: 1501 Signed-off-by: Bruce Richardson --- V2: Add compiler barrier to prevent issues with multi-threaded calls --- lib/eal/x86/rte_cpuflags.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c index 26163ab746..90389c66fc 100644 --- a/lib/eal/x86/rte_cpuflags.c +++ b/lib/eal/x86/rte_cpuflags.c @@ -8,8 +8,10 @@ #include #include #include +#include #include "rte_cpuid.h" +#include "rte_atomic.h" /** * Struct to hold a processor feature entry @@ -21,12 +23,14 @@ struct feature_entry { uint32_t bit; /**< cpuid register bit */ #define CPU_FLAG_NAME_MAX_LEN 64 char name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */ + bool has_value; + bool value; }; #define FEAT_DEF(name, leaf, subleaf, reg, bit) \ [RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name }, -const struct feature_entry rte_cpu_feature_table[] = { +struct feature_entry rte_cpu_feature_table[] = { FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX, 0) FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX, 1) FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX, 2) @@ -147,7 +151,7 @@ const struct feature_entry rte_cpu_feature_table[] = { int rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) { - const struct feature_entry *feat; + struct feature_entry *feat; cpuid_registers_t regs; unsigned int maxleaf; @@ -156,6 +160,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) return -ENOENT; feat = &rte_cpu_feature_table[feature]; + if (feat->has_value) + return feat->value; if (!feat->leaf) /* This entry in the table wasn't filled out! */ @@ -163,8 +169,10 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) maxleaf = __get_cpuid_max(feat->leaf & 0x80000000, NULL); - if (maxleaf < feat->leaf) - return 0; + if (maxleaf < feat->leaf) { + feat->value = 0; + goto out; + } #ifdef RTE_TOOLCHAIN_MSVC __cpuidex(regs, feat->leaf, feat->subleaf); @@ -175,7 +183,11 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature) #endif /* check if the feature is enabled */ - return (regs[feat->reg] >> feat->bit) & 1; + feat->value = (regs[feat->reg] >> feat->bit) & 1; +out: + rte_compiler_barrier(); + feat->has_value = true; + return feat->value; } const char * -- 2.43.0