From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 75FFA45B36; Mon, 14 Oct 2024 11:37:51 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 94E6840678; Mon, 14 Oct 2024 11:37:16 +0200 (CEST) Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2088.outbound.protection.outlook.com [40.107.22.88]) by mails.dpdk.org (Postfix) with ESMTP id C725540653 for ; Mon, 14 Oct 2024 11:37:09 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wMMNQ82pe2w/+Euw1LJccM2CT5qVXbrj6L1Qs4Oez5hCyWdMeyr6r9OTXZ1JCtoKE/Jbx3A9lhPfRsvgQ5NshsSsa3x67KfVeVnE4eGnSyoFjxj3wsSHE1mUzEy585we1qmNxcXTXl7uUGpVjkwEs7ljtxZnBEbHLjIi9yNIFX4/MtSDT62FAHxC/NswS9QHfrEMkfkhb4uCy7MPJYBByJYLRw6KJ0qHa2U75SF22pwPb2aR5oa9PSHqAJxtniczimoyZET1UaUE8cDf2TuH2llLsDYzTc99/unGMV4+/88b/iAmDlS5n+2hEGIj9eVGh6f/IKYTng5oxNF8EXEodg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=egWayJvVjKYFtLClWbnq96gOzwn62TcTjy09wRpnRoQ=; b=THo7kmeJ0zs3iE44l6kcg/GeaxW8YX4EHdWfLUokXV4bCoGoVgDTeH2lwGaqacqbWhBZ3C9kPtNgHgwcdW8Gr2mLD/Cj/xQLyPklJGqhcVYt21acklK6eHppsHjMwIrCA1KCyGTI0v0uzb527WprX2cQOffjXKcYgYxDKv8WOCd+YJ0PYmSJ/6UlM9UgFE1DvoAqk/AxYZjH+sEkEVDHg/crcBtmSc9LmnOofU/BTw4OirUtmExTSfXH4lWLMoJKww48kh0GJQwyCUD9ak5EROcysj4o4j3bFmBFtW9Sc8RWKYvpWLpPXz8G9y+xuC5k146vKrsI6l+dkuD3vs2a6g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=egWayJvVjKYFtLClWbnq96gOzwn62TcTjy09wRpnRoQ=; b=npf/7S+WT/T5m24cK2PSlIVOYtiloSarBMuTsyoesLjbe8myjRsXewsOmA/UcfC3k3FpZD3GWzA5ZN7Z5Vkit8YymK43LAEMk7pNoKAmDenQZnxtRx4mMjh4alIqtR85Ozbyklb5Bw0RdiZ9oPz0eL1s/lPf9Nzi8M6tqCxePBBO1uHH6Vwy1iWhOE9+1aHgzsdxmxWB3UtyvFeq+bYJq6prdFHcHqYQ4aMu1WIfcK9Wvvnj1FmSLp89fLZO5k+3qaWHdUshNRXNsEII7+8f6VYjH7lSkQJmWx272OrOqH2XQDZEhtLLQmzncuGlYWv6gBCgEU6fscXE8Usnmnd40Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AS8PR04MB8198.eurprd04.prod.outlook.com (2603:10a6:20b:3b0::14) by PA1PR04MB10580.eurprd04.prod.outlook.com (2603:10a6:102:482::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.25; Mon, 14 Oct 2024 09:37:08 +0000 Received: from AS8PR04MB8198.eurprd04.prod.outlook.com ([fe80::2e32:1a4a:7d29:195]) by AS8PR04MB8198.eurprd04.prod.outlook.com ([fe80::2e32:1a4a:7d29:195%4]) with mapi id 15.20.8048.020; Mon, 14 Oct 2024 09:37:08 +0000 From: Gagandeep Singh To: dev@dpdk.org, Hemant Agrawal , Sachin Saxena Cc: Jun Yang Subject: [v6 07/15] dma/dpaa2: move the qdma header to common place Date: Mon, 14 Oct 2024 15:06:31 +0530 Message-Id: <20241014093639.553467-8-g.singh@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241014093639.553467-1-g.singh@nxp.com> References: <20241008105810.1454133-2-g.singh@nxp.com> <20241014093639.553467-1-g.singh@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SI2P153CA0033.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::21) To AS8PR04MB8198.eurprd04.prod.outlook.com (2603:10a6:20b:3b0::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB8198:EE_|PA1PR04MB10580:EE_ X-MS-Office365-Filtering-Correlation-Id: 1743c79d-7e79-44d0-c2c5-08dcec33c543 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|52116014|366016|1800799024|38350700014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Y1Yx4HwA1UjZBZc7k2RmD+nt2TIo6yp13Z1YoNY4M3eHu0f6fuNJGaEDbpS9?= =?us-ascii?Q?XnIDC08dPmniy18+ktEhdlcWM2dyWBvQ5OqDbnKb1KyTF8z/X8MZyakxa7D8?= =?us-ascii?Q?0KiweBxsIu2TyP8rr3aCa+hfvWYt40/WNO4v/LfuEk/Mh2h4LL62XTbLYBT6?= =?us-ascii?Q?R60MbQ3qyFQJrVsCpf+oJwD+F2l7TkTlJZzHMPare3d2mmzUoo0WDYhMpkJL?= =?us-ascii?Q?Vp2DvDuldR05rAOxNwZH+3+utiKRA15u5En2Es9ac9FHFS62eY4K7Ty7H+iU?= =?us-ascii?Q?PJd3DO7xAq997ZPn7udIvSCBgWq/7UvwOp5ULA4Km9VTRBNTuko2UREJhBoU?= =?us-ascii?Q?ssvcLyxW/QLGPlw2O3UpkxaT3oZ1hibuFoWbRrBh9NTBPUMvLRyZSfeiKN8g?= =?us-ascii?Q?tMNuBXqmJUZxiuX15QVdJ9JX9GpYEK+ORSF19ArZdROveG6yVUKxm5CdYCua?= =?us-ascii?Q?0xtQ1WTUayjhVMuxivDSfzOeK51beEbZW/0qiMMJ5oR0hrvs8mMcF44e49mf?= =?us-ascii?Q?zRMUWwHsNZkalsk4efvmpJkyKUH15wI32wLhPEh7iGC5G8DgIE+A/HfUFOmg?= =?us-ascii?Q?1xD6JpEJaXURpF0CtnysxWx9Fm17Dl3hXUFYX3a4p+FuA/Kze5Ohem0VQ5XE?= =?us-ascii?Q?WUV6in3LEZkQHQ0/SOdRX8Qr8iinWtqRj83PVNhBjH/EOxO8V/T1e+NeiBcg?= =?us-ascii?Q?EhymSK+5FHZD8TktI2xGJvtn0aXBN79Gy1n7Ti5mXiv/3wpDj0eJw072lLx5?= =?us-ascii?Q?Df1wNypdV3XfN4NqPrE4EQMVICjREa4VHlusMaLqPbln/oVD3KKq3W5BM7Mv?= =?us-ascii?Q?yFZKR77r61tDatabgBZiVECoTu+O5JBI2bNxa8nnwGSj4pjjCTfJ9b8NIlCP?= =?us-ascii?Q?G4zdX7iHNqIF2eZiHpAOkiDUra4Jgo4ohqaNBQA8ybMwhjaXRMheg/nR+Za2?= =?us-ascii?Q?rRcEkgJ2JDu4SDJj9GYou3pXuJs8y/xpklnElIl4V6qv3a+GNDnHl7In6hQv?= =?us-ascii?Q?bwhzjewySLNiDJ6bvSOKViuUGMVH5QTA7b2tg3hsU40Xj4T20HY9VFIPZKDO?= =?us-ascii?Q?ChoP5l8HjiAosOMY4aAA6A0iNzhwu0e5iHaE8WcawiUlJfbGj++WDuX2rNvL?= =?us-ascii?Q?hAtDE1rMDtvmHbioJ9A8m+guCi7VZ44f0qidc+Onbe8TNiFF76QAQD2iHVml?= =?us-ascii?Q?y++qJZlhvq90PjHx3PmhZ/IiSrvwX3Negclcm1mO02UvBBnzapnEMt3QhWOG?= =?us-ascii?Q?9TVqedgr2JQ2MWHjBT9nhUsBEIOAnVmXHTN9eWyoeI4DuUbD/EnLmN3KsPC0?= =?us-ascii?Q?2QRMYParnfQJc32+FnhsSF/HkwA2VQzX0NnolHQdgEN0Zg=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AS8PR04MB8198.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(376014)(52116014)(366016)(1800799024)(38350700014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?lbltT2Z+yr5RKYerG2qnopNeHGjSmXMzpaAkkEEpdL+vG7VIDcG8WQmgWk7V?= =?us-ascii?Q?Ue9qjFP0FEb/JY1qUYeROxcPld6D9/5sYZ1YaHjNvqvrRRYf5WLMaSMsHOnL?= =?us-ascii?Q?ykOz/EemUSAVYzvCo11EgZ5mEKxouZLLVVaMUQO20klgmBKmpO73NI04/SMt?= =?us-ascii?Q?53sHrSypaohUh5c88VsYT/GpHqU35hQPlFll0/l/vn4Acxh/UPA460nUfAKk?= =?us-ascii?Q?kYuZ4rVCsYw2kz1I/YFwhMek/a1TQH8VU17wg3lGa2VUxyAP/BbveueKiShf?= =?us-ascii?Q?2VkU55gOdhNUdQAmP00eZOsgZ/YuQoGzpYYfNwpevgJ9m29O0/mXzppKvb4C?= =?us-ascii?Q?LgfgGpcf+b6FbzjmajNptK/pPI0X+8ISTyspGh4V3nJkNDm/0eGm090VJ2RE?= =?us-ascii?Q?URU2NWl6a7r5nQ6M3aoYufUQOc4yP4P7tLPQ/6sBm5igzLY5Kr4dsfOzog05?= =?us-ascii?Q?HYktoniTEMBGH5NqWSGNla5JsEHCvBbfjPDseRH74pggoF71ThO9lGikHOXv?= =?us-ascii?Q?N00VWN06bhYQdaPc0ao2rF+hGLrU7o/N+eX+k2VUCJwWd6iDLeanqXQLMT2I?= =?us-ascii?Q?gzoFLzuGEfQLpn3e+VxLYlrz3EwGuYPSZj/ATPblHNfkbGQppBoTFz8Z4veK?= =?us-ascii?Q?3b1Jm4seDWYP8wabdxjhQZdKLjbo8csc9gpSzseuKNju6r+SXmy/eWyjx3Fx?= =?us-ascii?Q?Mt47gzNpI4ILqz55xPDji8K1DCzWdqhZpxq/FTiGzTOvqURpBUwQwy6i2bUe?= =?us-ascii?Q?TelPxFhp0O2ITMG0y8gH1FiiImCZJjg2T+NG4+7v9p8jLEiiXP9apfMFoLBs?= =?us-ascii?Q?JSHHs/VIuQfp8dcdnIp65GY3Rkp6UOuj65IKNpiBzMQfvq/bA0GtQghCLTHd?= =?us-ascii?Q?yLcoyMhz0I1OLq8N0JNogj4g5ZZu7rlaILJCKJfUg9Dp3B4kyFbPBHSe36oP?= =?us-ascii?Q?/3ThqPHNLO88KZ9oejty4lM6D9LRxW6Lx5mSi5ie38eHs5JqjtBe91yltmy/?= =?us-ascii?Q?7Wt/tdVa7i7Yk8f8txpS0gQzM7nF3niptOHjuiYaH1Cu7y3jf22deyQbimWx?= =?us-ascii?Q?zsTOTR1fMjSrBXmrZCZdBMwpYPnOvV23+pXJtglG8Mr4/KspdOXeeRbNpePY?= =?us-ascii?Q?uArdaYReDowMUccvPOwePe2DQ88MO7kYKlT+0bBfRKtEt4N75lkgnpBULP3h?= =?us-ascii?Q?r3prmEx0iwTvYw+RzrBQU7J9m53P0iU/OfHpMLbrlyMeTfVRd20Z4XV1uqrH?= =?us-ascii?Q?bHh8ROWHLA+qTJT6zjDCLcfml5i/CS61MPuiriff1LJc8gg74pyL3xLUqyes?= =?us-ascii?Q?kJ0obM6MkgoEdrr4u/MlabJjdqAffh4Kd2YA8JEcn0RyXJirnYfmWTvACun9?= =?us-ascii?Q?Thz2Ld+4zlGthna495fuufX1U4+SQQ2sOy3zy2dRU8wmZFPPqF7zCKRZMisV?= =?us-ascii?Q?rwOPymv1IhxFx+kUxbd6hVas+4ZwwVlkpyiKiADmAC+EVp4u80QRfDbtF90s?= =?us-ascii?Q?nLK6e+y528WOMOf3oFzXGz7NuYvjLTH6kA1hru1HgBHzDuMccmnkW06iHY82?= =?us-ascii?Q?2V9B/AdXAYKyqhTAOottEI+P+Y4b9T7G0w96PQKu?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1743c79d-7e79-44d0-c2c5-08dcec33c543 X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8198.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2024 09:37:08.0028 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OgOq5DKKQ4cI14iVT/pZkH35aqHBo+9xUBKBCm8gB7kDJ8+RBYZCKGYIOV6kaeYH X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1PR04MB10580 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jun Yang Include rte_pmd_dpaax_qdma.h instead of rte_pmd_dpaa2_qdma.h and change code accordingly. Signed-off-by: Jun Yang --- doc/api/doxy-api-index.md | 2 +- doc/api/doxy-api.conf.in | 2 +- drivers/common/dpaax/meson.build | 3 +- drivers/common/dpaax/rte_pmd_dpaax_qdma.h | 23 +++++++ drivers/dma/dpaa2/dpaa2_qdma.c | 84 +++++++++++------------ drivers/dma/dpaa2/dpaa2_qdma.h | 10 +-- drivers/dma/dpaa2/meson.build | 4 +- drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h | 23 ------- 8 files changed, 72 insertions(+), 79 deletions(-) create mode 100644 drivers/common/dpaax/rte_pmd_dpaax_qdma.h delete mode 100644 drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md index f9f0300126..5a4411eb4a 100644 --- a/doc/api/doxy-api-index.md +++ b/doc/api/doxy-api-index.md @@ -57,7 +57,7 @@ The public API headers are grouped by topics: [mlx5](@ref rte_pmd_mlx5.h), [dpaa2_mempool](@ref rte_dpaa2_mempool.h), [dpaa2_cmdif](@ref rte_pmd_dpaa2_cmdif.h), - [dpaa2_qdma](@ref rte_pmd_dpaa2_qdma.h), + [dpaax](@ref rte_pmd_dpaax_qdma.h), [crypto_scheduler](@ref rte_cryptodev_scheduler.h), [dlb2](@ref rte_pmd_dlb2.h), [ifpga](@ref rte_pmd_ifpga.h) diff --git a/doc/api/doxy-api.conf.in b/doc/api/doxy-api.conf.in index a8823c046f..33250d867c 100644 --- a/doc/api/doxy-api.conf.in +++ b/doc/api/doxy-api.conf.in @@ -8,7 +8,7 @@ INPUT = @TOPDIR@/doc/api/doxy-api-index.md \ @TOPDIR@/drivers/bus/vdev \ @TOPDIR@/drivers/crypto/cnxk \ @TOPDIR@/drivers/crypto/scheduler \ - @TOPDIR@/drivers/dma/dpaa2 \ + @TOPDIR@/drivers/common/dpaax \ @TOPDIR@/drivers/event/dlb2 \ @TOPDIR@/drivers/event/cnxk \ @TOPDIR@/drivers/mempool/cnxk \ diff --git a/drivers/common/dpaax/meson.build b/drivers/common/dpaax/meson.build index a162779116..db61b76ce3 100644 --- a/drivers/common/dpaax/meson.build +++ b/drivers/common/dpaax/meson.build @@ -1,5 +1,5 @@ # SPDX-License-Identifier: BSD-3-Clause -# Copyright(c) 2018 NXP +# Copyright 2018, 2024 NXP if not is_linux build = false @@ -16,3 +16,4 @@ endif if cc.has_argument('-Wno-pointer-arith') cflags += '-Wno-pointer-arith' endif +headers = files('rte_pmd_dpaax_qdma.h') diff --git a/drivers/common/dpaax/rte_pmd_dpaax_qdma.h b/drivers/common/dpaax/rte_pmd_dpaax_qdma.h new file mode 100644 index 0000000000..2552a4adfb --- /dev/null +++ b/drivers/common/dpaax/rte_pmd_dpaax_qdma.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2021-2024 NXP + */ + +#ifndef _RTE_PMD_DPAAX_QDMA_H_ +#define _RTE_PMD_DPAAX_QDMA_H_ + +#include + +#define RTE_DPAAX_QDMA_COPY_IDX_OFFSET 8 +#define RTE_DPAAX_QDMA_SG_IDX_ADDR_ALIGN \ + RTE_BIT64(RTE_DPAAX_QDMA_COPY_IDX_OFFSET) +#define RTE_DPAAX_QDMA_SG_IDX_ADDR_MASK \ + (RTE_DPAAX_QDMA_SG_IDX_ADDR_ALIGN - 1) +#define RTE_DPAAX_QDMA_SG_SUBMIT(idx_addr, flag) \ + (((uint64_t)idx_addr) | (flag)) + +#define RTE_DPAAX_QDMA_COPY_SUBMIT(idx, flag) \ + ((idx << RTE_DPAAX_QDMA_COPY_IDX_OFFSET) | (flag)) + +#define RTE_DPAAX_QDMA_JOB_SUBMIT_MAX 64 +#define RTE_DMA_CAPA_DPAAX_QDMA_FLAGS_INDEX RTE_BIT64(63) +#endif /* _RTE_PMD_DPAAX_QDMA_H_ */ diff --git a/drivers/dma/dpaa2/dpaa2_qdma.c b/drivers/dma/dpaa2/dpaa2_qdma.c index 5e7640ae08..71e9ffdfc1 100644 --- a/drivers/dma/dpaa2/dpaa2_qdma.c +++ b/drivers/dma/dpaa2/dpaa2_qdma.c @@ -10,7 +10,7 @@ #include -#include "rte_pmd_dpaa2_qdma.h" +#include #include "dpaa2_qdma.h" #include "dpaa2_qdma_logs.h" @@ -243,16 +243,16 @@ fle_sdd_pre_populate(struct qdma_cntx_fle_sdd *fle_sdd, } /* source frame list to source buffer */ DPAA2_SET_FLE_ADDR(&fle[DPAA2_QDMA_SRC_FLE], src); -#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA - DPAA2_SET_FLE_BMT(&fle[DPAA2_QDMA_SRC_FLE]); -#endif + /** IOMMU is always on for either VA or PA mode, + * so Bypass Memory Translation should be disabled. + * + * DPAA2_SET_FLE_BMT(&fle[DPAA2_QDMA_SRC_FLE]); + * DPAA2_SET_FLE_BMT(&fle[DPAA2_QDMA_DST_FLE]); + */ fle[DPAA2_QDMA_SRC_FLE].word4.fmt = fmt; /* destination frame list to destination buffer */ DPAA2_SET_FLE_ADDR(&fle[DPAA2_QDMA_DST_FLE], dest); -#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA - DPAA2_SET_FLE_BMT(&fle[DPAA2_QDMA_DST_FLE]); -#endif fle[DPAA2_QDMA_DST_FLE].word4.fmt = fmt; /* Final bit: 1, for last frame list */ @@ -266,23 +266,21 @@ sg_entry_pre_populate(struct qdma_cntx_sg *sg_cntx) struct qdma_sg_entry *src_sge = sg_cntx->sg_src_entry; struct qdma_sg_entry *dst_sge = sg_cntx->sg_dst_entry; - for (i = 0; i < RTE_DPAA2_QDMA_JOB_SUBMIT_MAX; i++) { + for (i = 0; i < RTE_DPAAX_QDMA_JOB_SUBMIT_MAX; i++) { /* source SG */ src_sge[i].ctrl.sl = QDMA_SG_SL_LONG; src_sge[i].ctrl.fmt = QDMA_SG_FMT_SDB; -#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA - src_sge[i].ctrl.bmt = QDMA_SG_BMT_ENABLE; -#else + /** IOMMU is always on for either VA or PA mode, + * so Bypass Memory Translation should be disabled. + */ src_sge[i].ctrl.bmt = QDMA_SG_BMT_DISABLE; -#endif /* destination SG */ dst_sge[i].ctrl.sl = QDMA_SG_SL_LONG; dst_sge[i].ctrl.fmt = QDMA_SG_FMT_SDB; -#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA - dst_sge[i].ctrl.bmt = QDMA_SG_BMT_ENABLE; -#else + /** IOMMU is always on for either VA or PA mode, + * so Bypass Memory Translation should be disabled. + */ dst_sge[i].ctrl.bmt = QDMA_SG_BMT_DISABLE; -#endif } } @@ -381,21 +379,19 @@ sg_entry_populate(const struct rte_dma_sge *src, src_sge->data_len.data_len_sl0 = src[i].length; src_sge->ctrl.sl = QDMA_SG_SL_LONG; src_sge->ctrl.fmt = QDMA_SG_FMT_SDB; -#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA - src_sge->ctrl.bmt = QDMA_SG_BMT_ENABLE; -#else + /** IOMMU is always on for either VA or PA mode, + * so Bypass Memory Translation should be disabled. + */ src_sge->ctrl.bmt = QDMA_SG_BMT_DISABLE; -#endif dst_sge->addr_lo = (uint32_t)dst[i].addr; dst_sge->addr_hi = (dst[i].addr >> 32); dst_sge->data_len.data_len_sl0 = dst[i].length; dst_sge->ctrl.sl = QDMA_SG_SL_LONG; dst_sge->ctrl.fmt = QDMA_SG_FMT_SDB; -#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA - dst_sge->ctrl.bmt = QDMA_SG_BMT_ENABLE; -#else + /** IOMMU is always on for either VA or PA mode, + * so Bypass Memory Translation should be disabled. + */ dst_sge->ctrl.bmt = QDMA_SG_BMT_DISABLE; -#endif total_len += src[i].length; if (i == (nb_sge - 1)) { @@ -475,17 +471,16 @@ fle_populate(struct qbman_fle fle[], } /* source frame list to source buffer */ DPAA2_SET_FLE_ADDR(&fle[DPAA2_QDMA_SRC_FLE], src_iova); -#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA - DPAA2_SET_FLE_BMT(&fle[DPAA2_QDMA_SRC_FLE]); -#endif + /** IOMMU is always on for either VA or PA mode, + * so Bypass Memory Translation should be disabled. + * DPAA2_SET_FLE_BMT(&fle[DPAA2_QDMA_SRC_FLE]); + * DPAA2_SET_FLE_BMT(&fle[DPAA2_QDMA_DST_FLE]); + */ fle[DPAA2_QDMA_SRC_FLE].word4.fmt = fmt; DPAA2_SET_FLE_LEN(&fle[DPAA2_QDMA_SRC_FLE], len); /* destination frame list to destination buffer */ DPAA2_SET_FLE_ADDR(&fle[DPAA2_QDMA_DST_FLE], dst_iova); -#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA - DPAA2_SET_FLE_BMT(&fle[DPAA2_QDMA_DST_FLE]); -#endif fle[DPAA2_QDMA_DST_FLE].word4.fmt = fmt; DPAA2_SET_FLE_LEN(&fle[DPAA2_QDMA_DST_FLE], len); @@ -591,7 +586,7 @@ dpaa2_qdma_long_fmt_dump(const struct qbman_fle *fle) DPAA2_QDMA_INFO("long format/SG format, job number:%d", cntx_sg->job_nb); if (!cntx_sg->job_nb || - cntx_sg->job_nb > RTE_DPAA2_QDMA_JOB_SUBMIT_MAX) { + cntx_sg->job_nb > RTE_DPAAX_QDMA_JOB_SUBMIT_MAX) { DPAA2_QDMA_ERR("Invalid SG job number:%d", cntx_sg->job_nb); return; @@ -641,9 +636,9 @@ dpaa2_qdma_copy_sg(void *dev_private, return -EINVAL; } - if (unlikely(nb_src > RTE_DPAA2_QDMA_JOB_SUBMIT_MAX)) { + if (unlikely(nb_src > RTE_DPAAX_QDMA_JOB_SUBMIT_MAX)) { DPAA2_QDMA_ERR("SG entry number(%d) > MAX(%d)", - nb_src, RTE_DPAA2_QDMA_JOB_SUBMIT_MAX); + nb_src, RTE_DPAAX_QDMA_JOB_SUBMIT_MAX); return -EINVAL; } @@ -662,11 +657,7 @@ dpaa2_qdma_copy_sg(void *dev_private, cntx_sg->cntx_idx[i] = idx_addr[i]; } -#ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA - cntx_iova = rte_mempool_virt2iova(cntx_sg); -#else - cntx_iova = DPAA2_VADDR_TO_IOVA(cntx_sg); -#endif + cntx_iova = (uint64_t)cntx_sg - qdma_vq->fle_iova2va_offset; fle = cntx_sg->fle_sdd.fle; fle_iova = cntx_iova + @@ -698,8 +689,7 @@ dpaa2_qdma_copy_sg(void *dev_private, offsetof(struct qdma_cntx_sg, sg_src_entry); dst_sge_iova = cntx_iova + offsetof(struct qdma_cntx_sg, sg_dst_entry); - len = sg_entry_populate(src, dst, - cntx_sg, nb_src); + len = sg_entry_populate(src, dst, cntx_sg, nb_src); fle_populate(fle, sdd, sdd_iova, &qdma_vq->rbp, src_sge_iova, dst_sge_iova, len, @@ -1042,7 +1032,7 @@ dpaa2_qdma_dequeue(void *dev_private, q_storage->last_num_pkts); qbman_pull_desc_set_fq(&pulldesc, fqid); qbman_pull_desc_set_storage(&pulldesc, dq_storage, - (size_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1); + DPAA2_VADDR_TO_IOVA(dq_storage), 1); if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) { while (!qbman_check_command_complete( get_swp_active_dqs( @@ -1077,7 +1067,7 @@ dpaa2_qdma_dequeue(void *dev_private, qbman_pull_desc_set_numframes(&pulldesc, pull_size); qbman_pull_desc_set_fq(&pulldesc, fqid); qbman_pull_desc_set_storage(&pulldesc, dq_storage1, - (size_t)(DPAA2_VADDR_TO_IOVA(dq_storage1)), 1); + DPAA2_VADDR_TO_IOVA(dq_storage1), 1); /* Check if the previous issued command is completed. * Also seems like the SWP is shared between the Ethernet Driver @@ -1109,7 +1099,7 @@ dpaa2_qdma_dequeue(void *dev_private, } fd = qbman_result_DQ_fd(dq_storage); ret = dpaa2_qdma_dq_fd(fd, qdma_vq, &free_space, &fle_elem_nb); - if (ret || free_space < RTE_DPAA2_QDMA_JOB_SUBMIT_MAX) + if (ret || free_space < RTE_DPAAX_QDMA_JOB_SUBMIT_MAX) pending = 0; dq_storage++; @@ -1162,11 +1152,11 @@ dpaa2_qdma_info_get(const struct rte_dma_dev *dev, RTE_DMA_CAPA_SILENT | RTE_DMA_CAPA_OPS_COPY | RTE_DMA_CAPA_OPS_COPY_SG; - dev_info->dev_capa |= RTE_DMA_CAPA_DPAA2_QDMA_FLAGS_INDEX; + dev_info->dev_capa |= RTE_DMA_CAPA_DPAAX_QDMA_FLAGS_INDEX; dev_info->max_vchans = dpdmai_dev->num_queues; dev_info->max_desc = DPAA2_QDMA_MAX_DESC; dev_info->min_desc = DPAA2_QDMA_MIN_DESC; - dev_info->max_sges = RTE_DPAA2_QDMA_JOB_SUBMIT_MAX; + dev_info->max_sges = RTE_DPAAX_QDMA_JOB_SUBMIT_MAX; dev_info->dev_name = dev->device->name; if (dpdmai_dev->qdma_dev) dev_info->nb_vchans = dpdmai_dev->qdma_dev->num_vqs; @@ -1347,6 +1337,7 @@ dpaa2_qdma_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, uint32_t pool_size; char pool_name[64]; int ret; + uint64_t iova, va; DPAA2_QDMA_FUNC_TRACE(); @@ -1382,6 +1373,9 @@ dpaa2_qdma_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, DPAA2_QDMA_ERR("%s create failed", pool_name); return -ENOMEM; } + iova = qdma_dev->vqs[vchan].fle_pool->mz->iova; + va = qdma_dev->vqs[vchan].fle_pool->mz->addr_64; + qdma_dev->vqs[vchan].fle_iova2va_offset = va - iova; if (qdma_dev->is_silent) { ret = rte_mempool_get_bulk(qdma_dev->vqs[vchan].fle_pool, diff --git a/drivers/dma/dpaa2/dpaa2_qdma.h b/drivers/dma/dpaa2/dpaa2_qdma.h index 250c83c83c..0fd1debaf8 100644 --- a/drivers/dma/dpaa2/dpaa2_qdma.h +++ b/drivers/dma/dpaa2/dpaa2_qdma.h @@ -220,18 +220,18 @@ struct qdma_cntx_fle_sdd { struct qdma_cntx_sg { struct qdma_cntx_fle_sdd fle_sdd; - struct qdma_sg_entry sg_src_entry[RTE_DPAA2_QDMA_JOB_SUBMIT_MAX]; - struct qdma_sg_entry sg_dst_entry[RTE_DPAA2_QDMA_JOB_SUBMIT_MAX]; - uint16_t cntx_idx[RTE_DPAA2_QDMA_JOB_SUBMIT_MAX]; + struct qdma_sg_entry sg_src_entry[RTE_DPAAX_QDMA_JOB_SUBMIT_MAX]; + struct qdma_sg_entry sg_dst_entry[RTE_DPAAX_QDMA_JOB_SUBMIT_MAX]; + uint16_t cntx_idx[RTE_DPAAX_QDMA_JOB_SUBMIT_MAX]; uint16_t job_nb; uint16_t rsv[3]; } __rte_packed; #define DPAA2_QDMA_IDXADDR_FROM_SG_FLAG(flag) \ - ((void *)(uintptr_t)((flag) - ((flag) & RTE_DPAA2_QDMA_SG_IDX_ADDR_MASK))) + ((void *)(uintptr_t)((flag) - ((flag) & RTE_DPAAX_QDMA_SG_IDX_ADDR_MASK))) #define DPAA2_QDMA_IDX_FROM_FLAG(flag) \ - ((flag) >> RTE_DPAA2_QDMA_COPY_IDX_OFFSET) + ((flag) >> RTE_DPAAX_QDMA_COPY_IDX_OFFSET) /** Represents a DPDMAI device */ struct dpaa2_dpdmai_dev { diff --git a/drivers/dma/dpaa2/meson.build b/drivers/dma/dpaa2/meson.build index a99151e2a5..a523f5edb4 100644 --- a/drivers/dma/dpaa2/meson.build +++ b/drivers/dma/dpaa2/meson.build @@ -1,5 +1,5 @@ # SPDX-License-Identifier: BSD-3-Clause -# Copyright 2021 NXP +# Copyright 2021, 2024 NXP if not is_linux build = false @@ -14,5 +14,3 @@ sources = files('dpaa2_qdma.c') if cc.has_argument('-Wno-pointer-arith') cflags += '-Wno-pointer-arith' endif - -headers = files('rte_pmd_dpaa2_qdma.h') diff --git a/drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h b/drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h deleted file mode 100644 index df21b39cae..0000000000 --- a/drivers/dma/dpaa2/rte_pmd_dpaa2_qdma.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2021-2023 NXP - */ - -#ifndef _RTE_PMD_DPAA2_QDMA_H_ -#define _RTE_PMD_DPAA2_QDMA_H_ - -#include - -#define RTE_DPAA2_QDMA_COPY_IDX_OFFSET 8 -#define RTE_DPAA2_QDMA_SG_IDX_ADDR_ALIGN \ - RTE_BIT64(RTE_DPAA2_QDMA_COPY_IDX_OFFSET) -#define RTE_DPAA2_QDMA_SG_IDX_ADDR_MASK \ - (RTE_DPAA2_QDMA_SG_IDX_ADDR_ALIGN - 1) -#define RTE_DPAA2_QDMA_SG_SUBMIT(idx_addr, flag) \ - (((uint64_t)idx_addr) | (flag)) - -#define RTE_DPAA2_QDMA_COPY_SUBMIT(idx, flag) \ - ((idx << RTE_DPAA2_QDMA_COPY_IDX_OFFSET) | (flag)) - -#define RTE_DPAA2_QDMA_JOB_SUBMIT_MAX (32 + 8) -#define RTE_DMA_CAPA_DPAA2_QDMA_FLAGS_INDEX RTE_BIT64(63) -#endif /* _RTE_PMD_DPAA2_QDMA_H_ */ -- 2.25.1