* [PATCH 0/9] net/ice: base code update for RC2
@ 2024-10-11 16:44 Bruce Richardson
2024-10-11 16:44 ` [PATCH 1/9] net/ice/base: re-enable bypass mode for E822 Bruce Richardson
` (9 more replies)
0 siblings, 10 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-11 16:44 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
A number of small fixes and other changes to enable Tx scheduler
enhancements to our DPDK driver have been added to the base code.
Upstream these changes for 24.11 RC2. Most have previously been
submitted as part of the scheduler changes [1]
[1] https://patches.dpdk.org/project/dpdk/list/?series=32758&state=*
Bruce Richardson (6):
net/ice/base: remove 255 limit on sched child nodes
net/ice/base: set VSI index on newly created nodes
net/ice/base: optimize subtree searches
net/ice/base: remove flag checks before topology upload
net/ice/base: allow init without TC class sched nodes
net/ice/base: read VSI layer info from VSI
Dave Ertman (1):
net/ice/base: fix VLAN replay after reset
Fabio Pricoco (1):
net/ice/base: add bounds check
Jacob Keller (1):
net/ice/base: re-enable bypass mode for E822
drivers/net/ice/base/ice_controlq.c | 23 +++++-
drivers/net/ice/base/ice_dcb.c | 3 +-
drivers/net/ice/base/ice_ddp.c | 33 --------
drivers/net/ice/base/ice_ptp_hw.c | 117 ++++++++++++++++++++++++++--
drivers/net/ice/base/ice_ptp_hw.h | 2 +-
drivers/net/ice/base/ice_sched.c | 59 +++++++-------
drivers/net/ice/base/ice_switch.c | 2 -
drivers/net/ice/base/ice_type.h | 3 +-
drivers/net/ice/ice_ethdev.c | 2 +-
9 files changed, 168 insertions(+), 76 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/9] net/ice/base: re-enable bypass mode for E822
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
@ 2024-10-11 16:44 ` Bruce Richardson
2024-10-11 16:44 ` [PATCH 2/9] net/ice/base: add bounds check Bruce Richardson
` (8 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-11 16:44 UTC (permalink / raw)
To: dev; +Cc: Jacob Keller, stable, Bruce Richardson
From: Jacob Keller <jacob.e.keller@intel.com>
When removing bypass mode, the code for E822 bypass was completely
removed in error. This code should be maintained in DPDK so re-add the
necessary functions.
Fixes: ce9ad8c5bc6d ("net/ice/base: remove PHY port timer bypass mode")
Cc: stable@dpdk.org
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 117 ++++++++++++++++++++++++++++--
drivers/net/ice/base/ice_ptp_hw.h | 2 +-
drivers/net/ice/ice_ethdev.c | 2 +-
3 files changed, 113 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 2a112fea12..1e92e5ff21 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -4468,18 +4468,103 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)
return 0;
}
+/**
+ * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to configure
+ *
+ * Calculate and program the fixed Tx offset, and indicate that the offset is
+ * ready. This can be used when operating in bypass mode.
+ */
+static int ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port)
+{
+ enum ice_ptp_link_spd link_spd;
+ enum ice_ptp_fec_mode fec_mode;
+ u64 total_offset;
+ int err;
+
+ err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (err)
+ return err;
+
+ total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
+
+ /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L
+ * register, then indicate that the Tx offset is ready. After this,
+ * timestamps will be enabled.
+ *
+ * Note that this skips including the more precise offsets generated
+ * by the Vernier calibration.
+ */
+
+ err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
+ total_offset);
+ if (err)
+ return err;
+
+ err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
+ if (err)
+ return err;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_phy_cfg_rx_offset_e822 - Configure fixed Rx offset for bypass mode
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to configure
+ *
+ * Calculate and program the fixed Rx offset, and indicate that the offset is
+ * ready. This can be used when operating in bypass mode.
+ */
+static int ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)
+{
+ enum ice_ptp_link_spd link_spd;
+ enum ice_ptp_fec_mode fec_mode;
+ u64 total_offset;
+ int err;
+
+ err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (err)
+ return err;
+
+ total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
+
+ /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L
+ * register, then indicate that the Rx offset is ready. After this,
+ * timestamps will be enabled.
+ *
+ * Note that this skips including the more precise offsets generated
+ * by Vernier calibration.
+ */
+ err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
+ total_offset);
+ if (err)
+ return err;
+
+ err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
+ if (err)
+ return err;
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_start_phy_timer_e822 - Start the PHY clock timer
* @hw: pointer to the HW struct
* @port: the PHY port to start
+ * @bypass: if true, start the PHY in bypass mode
*
* Start the clock of a PHY port. This must be done as part of the flow to
* re-calibrate Tx and Rx timestamping offsets whenever the clock time is
* initialized or when link speed changes.
*
- * Hardware will take Vernier measurements on Tx or Rx of packets.
+ * Bypass mode enables timestamps immediately without waiting for Vernier
+ * calibration to complete. Hardware will still continue taking Vernier
+ * measurements on Tx or Rx of packets, but they will not be applied to
+ * timestamps.
*/
-int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)
+int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
{
u32 lo, hi, val;
u64 incval;
@@ -4544,15 +4629,35 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)
ice_ptp_exec_tmr_cmd(hw);
+ if (bypass) {
+ /* Enter BYPASS mode, enabling timestamps immediately. */
+ val |= P_REG_PS_BYPASS_MODE_M;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
+ }
+
val |= P_REG_PS_ENA_CLK_M;
err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
if (err)
return err;
- val |= P_REG_PS_LOAD_OFFSET_M;
- err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (err)
- return err;
+ if (bypass) {
+ /* Program the fixed Tx offset */
+ err = ice_phy_cfg_fixed_tx_offset_e822(hw, port);
+ if (err)
+ return err;
+
+ /* Program the fixed Rx offset */
+ err = ice_phy_cfg_fixed_rx_offset_e822(hw, port);
+ if (err)
+ return err;
+ } else {
+ val |= P_REG_PS_LOAD_OFFSET_M;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
+ }
ice_ptp_exec_tmr_cmd(hw);
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index 5d6636c0d1..534e05a8dd 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -277,7 +277,7 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port);
int
ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
-int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port);
+int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);
int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
int
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 61bff016be..2f9bcbd3a5 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -2540,7 +2540,7 @@ ice_dev_init(struct rte_eth_dev *dev)
ice_ptp_init_phy_model(hw);
if (hw->phy_model == ICE_PHY_E822) {
- ret = ice_start_phy_timer_e822(hw, hw->pf_id);
+ ret = ice_start_phy_timer_e822(hw, hw->pf_id, true);
if (ret)
PMD_INIT_LOG(ERR, "Failed to start phy timer");
}
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 2/9] net/ice/base: add bounds check
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
2024-10-11 16:44 ` [PATCH 1/9] net/ice/base: re-enable bypass mode for E822 Bruce Richardson
@ 2024-10-11 16:44 ` Bruce Richardson
2024-10-11 16:44 ` [PATCH 3/9] net/ice/base: fix VLAN replay after reset Bruce Richardson
` (7 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-11 16:44 UTC (permalink / raw)
To: dev; +Cc: Fabio Pricoco, stable, Bruce Richardson
From: Fabio Pricoco <fabio.pricoco@intel.com>
Refactor while loop to add a check that the values read are in the
correct range.
Fixes: 6c1f26be50a2 ("net/ice/base: add control queue information")
Cc: stable@dpdk.org
Signed-off-by: Fabio Pricoco <fabio.pricoco@intel.com>
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_controlq.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index af27dc8542..b210495827 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -839,16 +839,35 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
struct ice_ctl_q_ring *sq = &cq->sq;
u16 ntc = sq->next_to_clean;
struct ice_aq_desc *desc;
+ u32 head;
desc = ICE_CTL_Q_DESC(*sq, ntc);
- while (rd32(hw, cq->sq.head) != ntc) {
- ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));
+ head = rd32(hw, sq->head);
+ if (head >= sq->count) {
+ ice_debug(hw, ICE_DBG_AQ_MSG,
+ "Read head value (%d) exceeds allowed range.\n",
+ head);
+ return 0;
+ }
+
+ while (head != ntc) {
+ ice_debug(hw, ICE_DBG_AQ_MSG,
+ "ntc %d head %d.\n",
+ ntc, head);
ice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);
ntc++;
if (ntc == sq->count)
ntc = 0;
desc = ICE_CTL_Q_DESC(*sq, ntc);
+
+ head = rd32(hw, sq->head);
+ if (head >= sq->count) {
+ ice_debug(hw, ICE_DBG_AQ_MSG,
+ "Read head value (%d) exceeds allowed range.\n",
+ head);
+ return 0;
+ }
}
sq->next_to_clean = ntc;
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 3/9] net/ice/base: fix VLAN replay after reset
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
2024-10-11 16:44 ` [PATCH 1/9] net/ice/base: re-enable bypass mode for E822 Bruce Richardson
2024-10-11 16:44 ` [PATCH 2/9] net/ice/base: add bounds check Bruce Richardson
@ 2024-10-11 16:44 ` Bruce Richardson
2024-10-11 16:44 ` [PATCH 4/9] net/ice/base: remove 255 limit on sched child nodes Bruce Richardson
` (6 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-11 16:44 UTC (permalink / raw)
To: dev; +Cc: Dave Ertman, stable, Jacob Keller, Bruce Richardson
From: Dave Ertman <david.m.ertman@intel.com>
If there is more than one VLAN defined when any reset that affects the
PF is initiated, after the reset rebuild, no traffic will pass on any
VLAN but the last one created.
This is caused by the iteration though the VLANs during replay each
clearing the vsi_map bitmap of the VSI that is being replayed. The
problem is that during the replay, the pointer to the vsi_map bitmap is
used by each successive vlan to determine if it should be replayed on
this VSI.
The logic was that the replay of the VLAN would replace the bit in the
map before the next VLAN would iterate through. But, since the replay
copies the old bitmap pointer to filt_replay_rules and creates a new one
for the recreated VLANS, it does not do this, and leaves the old bitmap
broken to be used to replay the remaining VLANs.
Since the old bitmap will be cleaned up in post replay cleanup, there is
no need to alter it and break following VLAN replay, so don't clear the
bit.
Fixes: c7dd15931183 ("net/ice/base: add virtual switch code")
Cc: stable@dpdk.org
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_switch.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 96ef26d535..a3786961e6 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -10110,8 +10110,6 @@ ice_replay_vsi_fltr(struct ice_hw *hw, struct ice_port_info *pi,
if (!itr->vsi_list_info ||
!ice_is_bit_set(itr->vsi_list_info->vsi_map, vsi_handle))
continue;
- /* Clearing it so that the logic can add it back */
- ice_clear_bit(vsi_handle, itr->vsi_list_info->vsi_map);
f_entry.fltr_info.vsi_handle = vsi_handle;
f_entry.fltr_info.fltr_act = ICE_FWD_TO_VSI;
/* update the src in case it is VSI num */
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 4/9] net/ice/base: remove 255 limit on sched child nodes
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
` (2 preceding siblings ...)
2024-10-11 16:44 ` [PATCH 3/9] net/ice/base: fix VLAN replay after reset Bruce Richardson
@ 2024-10-11 16:44 ` Bruce Richardson
2024-10-11 16:44 ` [PATCH 5/9] net/ice/base: set VSI index on newly created nodes Bruce Richardson
` (5 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-11 16:44 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
The Tx scheduler in the ice driver can be configured to have large
numbers of child nodes at a given layer, but the driver code implicitly
limited the number of nodes to 255 by using a u8 datatype for the number
of children. Increase this to a 16-bit value throughout the code.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_dcb.c | 3 ++-
drivers/net/ice/base/ice_sched.c | 23 +++++++++++++----------
drivers/net/ice/base/ice_type.h | 2 +-
3 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index 4ef54613b1..e97f35b4cf 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -1585,7 +1585,8 @@ ice_update_port_tc_tree_cfg(struct ice_port_info *pi,
struct ice_aqc_txsched_elem_data elem;
u32 teid1, teid2;
int status = 0;
- u8 i, j;
+ u16 i;
+ u8 j;
if (!pi)
return ICE_ERR_PARAM;
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 373c32a518..1d6dd2af82 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -288,7 +288,7 @@ ice_sched_get_first_node(struct ice_port_info *pi,
*/
struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc)
{
- u8 i;
+ u16 i;
if (!pi || !pi->root)
return NULL;
@@ -311,7 +311,7 @@ void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node)
{
struct ice_sched_node *parent;
struct ice_hw *hw = pi->hw;
- u8 i, j;
+ u16 i, j;
/* Free the children before freeing up the parent node
* The parent array is updated below and that shifts the nodes
@@ -1503,7 +1503,7 @@ ice_sched_get_free_qgrp(struct ice_port_info *pi,
struct ice_sched_node *qgrp_node, u8 owner)
{
struct ice_sched_node *min_qgrp;
- u8 min_children;
+ u16 min_children;
if (!qgrp_node)
return qgrp_node;
@@ -2063,7 +2063,7 @@ static void ice_sched_rm_agg_vsi_info(struct ice_port_info *pi, u16 vsi_handle)
*/
static bool ice_sched_is_leaf_node_present(struct ice_sched_node *node)
{
- u8 i;
+ u16 i;
for (i = 0; i < node->num_children; i++)
if (ice_sched_is_leaf_node_present(node->children[i]))
@@ -2098,7 +2098,7 @@ ice_sched_rm_vsi_cfg(struct ice_port_info *pi, u16 vsi_handle, u8 owner)
ice_for_each_traffic_class(i) {
struct ice_sched_node *vsi_node, *tc_node;
- u8 j = 0;
+ u16 j = 0;
tc_node = ice_sched_get_tc_node(pi, i);
if (!tc_node)
@@ -2166,7 +2166,7 @@ int ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle)
*/
bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node)
{
- u8 i;
+ u16 i;
/* start from the leaf node */
for (i = 0; i < node->num_children; i++)
@@ -2240,7 +2240,8 @@ ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node,
u16 *num_nodes)
{
u8 l = node->tx_sched_layer;
- u8 vsil, i;
+ u8 vsil;
+ u16 i;
vsil = ice_sched_get_vsi_layer(hw);
@@ -2282,7 +2283,7 @@ ice_sched_update_parent(struct ice_sched_node *new_parent,
struct ice_sched_node *node)
{
struct ice_sched_node *old_parent;
- u8 i, j;
+ u16 i, j;
old_parent = node->parent;
@@ -2382,8 +2383,9 @@ ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 vsi_handle, u32 agg_id,
u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };
u32 first_node_teid, vsi_teid;
u16 num_nodes_added;
- u8 aggl, vsil, i;
+ u8 aggl, vsil;
int status;
+ u16 i;
tc_node = ice_sched_get_tc_node(pi, tc);
if (!tc_node)
@@ -2498,7 +2500,8 @@ ice_move_all_vsi_to_dflt_agg(struct ice_port_info *pi,
static bool
ice_sched_is_agg_inuse(struct ice_port_info *pi, struct ice_sched_node *node)
{
- u8 vsil, i;
+ u8 vsil;
+ u16 i;
vsil = ice_sched_get_vsi_layer(pi->hw);
if (node->tx_sched_layer < vsil - 1) {
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 598a80155b..6177bf4e2a 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1030,9 +1030,9 @@ struct ice_sched_node {
struct ice_aqc_txsched_elem_data info;
u32 agg_id; /* aggregator group ID */
u16 vsi_handle;
+ u16 num_children;
u8 in_use; /* suspended or in use */
u8 tx_sched_layer; /* Logical Layer (1-9) */
- u8 num_children;
u8 tc_num;
u8 owner;
#define ICE_SCHED_NODE_OWNER_LAN 0
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 5/9] net/ice/base: set VSI index on newly created nodes
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
` (3 preceding siblings ...)
2024-10-11 16:44 ` [PATCH 4/9] net/ice/base: remove 255 limit on sched child nodes Bruce Richardson
@ 2024-10-11 16:44 ` Bruce Richardson
2024-10-11 16:44 ` [PATCH 6/9] net/ice/base: optimize subtree searches Bruce Richardson
` (4 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-11 16:44 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
The ice_sched_node type has got a field for the vsi to which the node
belongs. This field was not getting set in "ice_sched_add_node", so add
a line configuring this field for each node from its parent node.
Similarly, when searching for a qgroup node, we can check for each node
that the VSI information is correct.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_sched.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 1d6dd2af82..45934f9152 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -200,6 +200,7 @@ ice_sched_add_node(struct ice_port_info *pi, u8 layer,
node->in_use = true;
node->parent = parent;
node->tx_sched_layer = layer;
+ node->vsi_handle = parent->vsi_handle;
parent->children[parent->num_children++] = node;
node->info = elem;
return 0;
@@ -1575,7 +1576,7 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
/* make sure the qgroup node is part of the VSI subtree */
if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node))
if (qgrp_node->num_children < max_children &&
- qgrp_node->owner == owner)
+ qgrp_node->owner == owner && qgrp_node->vsi_handle == vsi_handle)
break;
qgrp_node = qgrp_node->sibling;
}
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 6/9] net/ice/base: optimize subtree searches
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
` (4 preceding siblings ...)
2024-10-11 16:44 ` [PATCH 5/9] net/ice/base: set VSI index on newly created nodes Bruce Richardson
@ 2024-10-11 16:44 ` Bruce Richardson
2024-10-11 16:44 ` [PATCH 7/9] net/ice/base: remove flag checks before topology upload Bruce Richardson
` (3 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-11 16:44 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
In a number of places throughout the driver code, we want to confirm
that a scheduler node is indeed a child of another node. Currently, this
is confirmed by searching down the tree from the base until the desired
node is hit, a search which may hit many irrelevant tree nodes when
recursing down wrong branches. By switching the direction of search, to
check upwards from the node to the parent, we can avoid any incorrect
paths, and so speed up processing.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_sched.c | 23 +++++++----------------
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 45934f9152..4c5c19daf3 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -1464,25 +1464,16 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw)
* subtree or not
*/
bool
-ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base,
+ice_sched_find_node_in_subtree(struct ice_hw __ALWAYS_UNUSED *hw,
+ struct ice_sched_node *base,
struct ice_sched_node *node)
{
- u8 i;
-
- for (i = 0; i < base->num_children; i++) {
- struct ice_sched_node *child = base->children[i];
-
- if (node == child)
- return true;
-
- if (child->tx_sched_layer > node->tx_sched_layer)
- return false;
-
- /* this recursion is intentional, and wouldn't
- * go more than 8 calls
- */
- if (ice_sched_find_node_in_subtree(hw, child, node))
+ if (base == node)
+ return true;
+ while (node->tx_sched_layer != 0 && node->parent != NULL) {
+ if (node->parent == base)
return true;
+ node = node->parent;
}
return false;
}
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 7/9] net/ice/base: remove flag checks before topology upload
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
` (5 preceding siblings ...)
2024-10-11 16:44 ` [PATCH 6/9] net/ice/base: optimize subtree searches Bruce Richardson
@ 2024-10-11 16:44 ` Bruce Richardson
2024-10-11 16:44 ` [PATCH 8/9] net/ice/base: allow init without TC class sched nodes Bruce Richardson
` (2 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-11 16:44 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
DPDK should support more than just 9-level or 5-level topologies, so
remove the checks for those particular settings.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_ddp.c | 33 ---------------------------------
1 file changed, 33 deletions(-)
diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c
index 90aaa6b331..c17a58eab8 100644
--- a/drivers/net/ice/base/ice_ddp.c
+++ b/drivers/net/ice/base/ice_ddp.c
@@ -2384,38 +2384,6 @@ int ice_cfg_tx_topo(struct ice_hw *hw, u8 *buf, u32 len)
return status;
}
- /* Is default topology already applied ? */
- if (!(flags & ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW) &&
- hw->num_tx_sched_layers == 9) {
- ice_debug(hw, ICE_DBG_INIT, "Loaded default topology\n");
- /* Already default topology is loaded */
- return ICE_ERR_ALREADY_EXISTS;
- }
-
- /* Is new topology already applied ? */
- if ((flags & ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW) &&
- hw->num_tx_sched_layers == 5) {
- ice_debug(hw, ICE_DBG_INIT, "Loaded new topology\n");
- /* Already new topology is loaded */
- return ICE_ERR_ALREADY_EXISTS;
- }
-
- /* Is set topology issued already ? */
- if (flags & ICE_AQC_TX_TOPO_FLAGS_ISSUED) {
- ice_debug(hw, ICE_DBG_INIT, "Update tx topology was done by another PF\n");
- /* add a small delay before exiting */
- for (i = 0; i < 20; i++)
- ice_msec_delay(100, true);
- return ICE_ERR_ALREADY_EXISTS;
- }
-
- /* Change the topology from new to default (5 to 9) */
- if (!(flags & ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW) &&
- hw->num_tx_sched_layers == 5) {
- ice_debug(hw, ICE_DBG_INIT, "Change topology from 5 to 9 layers\n");
- goto update_topo;
- }
-
pkg_hdr = (struct ice_pkg_hdr *)buf;
state = ice_verify_pkg(pkg_hdr, len);
if (state) {
@@ -2462,7 +2430,6 @@ int ice_cfg_tx_topo(struct ice_hw *hw, u8 *buf, u32 len)
/* Get the new topology buffer */
new_topo = ((u8 *)section) + offset;
-update_topo:
/* acquire global lock to make sure that set topology issued
* by one PF
*/
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 8/9] net/ice/base: allow init without TC class sched nodes
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
` (6 preceding siblings ...)
2024-10-11 16:44 ` [PATCH 7/9] net/ice/base: remove flag checks before topology upload Bruce Richardson
@ 2024-10-11 16:44 ` Bruce Richardson
2024-10-11 16:44 ` [PATCH 9/9] net/ice/base: read VSI layer info from VSI Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
9 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-11 16:44 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
If DCB support is disabled via DDP image, there will not be any traffic
class (TC) nodes in the scheduler tree immediately above the root level.
To allow the driver to work with this scenario, we allow use of the root
node as a dummy TC0 node in case where there are no TC nodes in the
tree. For use of any other TC other than 0 (used by default in the
driver), existing behaviour of returning NULL pointer is maintained.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_sched.c | 8 +++++++-
drivers/net/ice/base/ice_type.h | 1 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 4c5c19daf3..7e255c0337 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -293,6 +293,10 @@ struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc)
if (!pi || !pi->root)
return NULL;
+ /* if no TC nodes, use root as TC node 0 */
+ if (!pi->has_tc)
+ return tc == 0 ? pi->root : NULL;
+
for (i = 0; i < pi->root->num_children; i++)
if (pi->root->children[i]->tc_num == tc)
return pi->root->children[i];
@@ -1306,7 +1310,9 @@ int ice_sched_init_port(struct ice_port_info *pi)
if (buf[0].generic[j].data.elem_type ==
ICE_AQC_ELEM_TYPE_ENTRY_POINT)
hw->sw_entry_point_layer = j;
-
+ else if (buf[0].generic[j].data.elem_type ==
+ ICE_AQC_ELEM_TYPE_TC)
+ pi->has_tc = 1;
status = ice_sched_add_node(pi, j, &buf[i].generic[j], NULL);
if (status)
goto err_init_port;
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 6177bf4e2a..35f832eb9f 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1260,6 +1260,7 @@ struct ice_port_info {
struct ice_qos_cfg qos_cfg;
u8 is_vf:1;
u8 is_custom_tx_enabled:1;
+ u8 has_tc:1;
};
struct ice_switch_info {
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 9/9] net/ice/base: read VSI layer info from VSI
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
` (7 preceding siblings ...)
2024-10-11 16:44 ` [PATCH 8/9] net/ice/base: allow init without TC class sched nodes Bruce Richardson
@ 2024-10-11 16:44 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
9 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-11 16:44 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
Rather than computing from the number of HW layers the layer of the VSI,
we can instead just read that info from the VSI node itself. This allows
the layer to be changed at runtime.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_sched.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 7e255c0337..9608ac7c24 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -1550,7 +1550,6 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
u16 max_children;
qgrp_layer = ice_sched_get_qgrp_layer(pi->hw);
- vsi_layer = ice_sched_get_vsi_layer(pi->hw);
max_children = pi->hw->max_children[qgrp_layer];
vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
@@ -1560,6 +1559,7 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
/* validate invalid VSI ID */
if (!vsi_node)
return NULL;
+ vsi_layer = vsi_node->tx_sched_layer;
/* If the queue group and vsi layer are same then queues
* are all attached directly to VSI
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 00/10] net/ice: base code update for RC2
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
` (8 preceding siblings ...)
2024-10-11 16:44 ` [PATCH 9/9] net/ice/base: read VSI layer info from VSI Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 01/10] net/ice/base: re-enable bypass mode for E822 Bruce Richardson
` (10 more replies)
9 siblings, 11 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
A number of small fixes and other changes to enable Tx scheduler
enhancements to our DPDK driver have been added to the base code.
Upstream these changes for 24.11 RC2. Most have previously been
submitted as part of the scheduler changes [1]
[1] https://patches.dpdk.org/project/dpdk/list/?series=32758&state=*
v2: include README file update
Bruce Richardson (7):
net/ice/base: remove 255 limit on sched child nodes
net/ice/base: set VSI index on newly created nodes
net/ice/base: optimize subtree searches
net/ice/base: remove flag checks before topology upload
net/ice/base: allow init without TC class sched nodes
net/ice/base: read VSI layer info from VSI
net/ice/base: update README
Dave Ertman (1):
net/ice/base: fix VLAN replay after reset
Fabio Pricoco (1):
net/ice/base: add bounds check
Jacob Keller (1):
net/ice/base: re-enable bypass mode for E822
drivers/net/ice/base/README | 2 +-
drivers/net/ice/base/ice_controlq.c | 23 +++++-
drivers/net/ice/base/ice_dcb.c | 3 +-
drivers/net/ice/base/ice_ddp.c | 33 --------
drivers/net/ice/base/ice_ptp_hw.c | 117 ++++++++++++++++++++++++++--
drivers/net/ice/base/ice_ptp_hw.h | 2 +-
drivers/net/ice/base/ice_sched.c | 59 +++++++-------
drivers/net/ice/base/ice_switch.c | 2 -
drivers/net/ice/base/ice_type.h | 3 +-
drivers/net/ice/ice_ethdev.c | 2 +-
10 files changed, 169 insertions(+), 77 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 01/10] net/ice/base: re-enable bypass mode for E822
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 02/10] net/ice/base: add bounds check Bruce Richardson
` (9 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Jacob Keller, stable, Bruce Richardson
From: Jacob Keller <jacob.e.keller@intel.com>
When removing bypass mode, the code for E822 bypass was completely
removed in error. This code should be maintained in DPDK so re-add the
necessary functions.
Fixes: ce9ad8c5bc6d ("net/ice/base: remove PHY port timer bypass mode")
Cc: stable@dpdk.org
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 117 ++++++++++++++++++++++++++++--
drivers/net/ice/base/ice_ptp_hw.h | 2 +-
drivers/net/ice/ice_ethdev.c | 2 +-
3 files changed, 113 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 2a112fea12..1e92e5ff21 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -4468,18 +4468,103 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset)
return 0;
}
+/**
+ * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to configure
+ *
+ * Calculate and program the fixed Tx offset, and indicate that the offset is
+ * ready. This can be used when operating in bypass mode.
+ */
+static int ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port)
+{
+ enum ice_ptp_link_spd link_spd;
+ enum ice_ptp_fec_mode fec_mode;
+ u64 total_offset;
+ int err;
+
+ err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (err)
+ return err;
+
+ total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
+
+ /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L
+ * register, then indicate that the Tx offset is ready. After this,
+ * timestamps will be enabled.
+ *
+ * Note that this skips including the more precise offsets generated
+ * by the Vernier calibration.
+ */
+
+ err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
+ total_offset);
+ if (err)
+ return err;
+
+ err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
+ if (err)
+ return err;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_phy_cfg_rx_offset_e822 - Configure fixed Rx offset for bypass mode
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to configure
+ *
+ * Calculate and program the fixed Rx offset, and indicate that the offset is
+ * ready. This can be used when operating in bypass mode.
+ */
+static int ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)
+{
+ enum ice_ptp_link_spd link_spd;
+ enum ice_ptp_fec_mode fec_mode;
+ u64 total_offset;
+ int err;
+
+ err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
+ if (err)
+ return err;
+
+ total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
+
+ /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L
+ * register, then indicate that the Rx offset is ready. After this,
+ * timestamps will be enabled.
+ *
+ * Note that this skips including the more precise offsets generated
+ * by Vernier calibration.
+ */
+ err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
+ total_offset);
+ if (err)
+ return err;
+
+ err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
+ if (err)
+ return err;
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_start_phy_timer_e822 - Start the PHY clock timer
* @hw: pointer to the HW struct
* @port: the PHY port to start
+ * @bypass: if true, start the PHY in bypass mode
*
* Start the clock of a PHY port. This must be done as part of the flow to
* re-calibrate Tx and Rx timestamping offsets whenever the clock time is
* initialized or when link speed changes.
*
- * Hardware will take Vernier measurements on Tx or Rx of packets.
+ * Bypass mode enables timestamps immediately without waiting for Vernier
+ * calibration to complete. Hardware will still continue taking Vernier
+ * measurements on Tx or Rx of packets, but they will not be applied to
+ * timestamps.
*/
-int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)
+int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)
{
u32 lo, hi, val;
u64 incval;
@@ -4544,15 +4629,35 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port)
ice_ptp_exec_tmr_cmd(hw);
+ if (bypass) {
+ /* Enter BYPASS mode, enabling timestamps immediately. */
+ val |= P_REG_PS_BYPASS_MODE_M;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
+ }
+
val |= P_REG_PS_ENA_CLK_M;
err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
if (err)
return err;
- val |= P_REG_PS_LOAD_OFFSET_M;
- err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (err)
- return err;
+ if (bypass) {
+ /* Program the fixed Tx offset */
+ err = ice_phy_cfg_fixed_tx_offset_e822(hw, port);
+ if (err)
+ return err;
+
+ /* Program the fixed Rx offset */
+ err = ice_phy_cfg_fixed_rx_offset_e822(hw, port);
+ if (err)
+ return err;
+ } else {
+ val |= P_REG_PS_LOAD_OFFSET_M;
+ err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
+ if (err)
+ return err;
+ }
ice_ptp_exec_tmr_cmd(hw);
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index 5d6636c0d1..534e05a8dd 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -277,7 +277,7 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port,
void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port);
int
ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
-int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port);
+int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);
int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
int
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 61bff016be..2f9bcbd3a5 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -2540,7 +2540,7 @@ ice_dev_init(struct rte_eth_dev *dev)
ice_ptp_init_phy_model(hw);
if (hw->phy_model == ICE_PHY_E822) {
- ret = ice_start_phy_timer_e822(hw, hw->pf_id);
+ ret = ice_start_phy_timer_e822(hw, hw->pf_id, true);
if (ret)
PMD_INIT_LOG(ERR, "Failed to start phy timer");
}
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 02/10] net/ice/base: add bounds check
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 01/10] net/ice/base: re-enable bypass mode for E822 Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 03/10] net/ice/base: fix VLAN replay after reset Bruce Richardson
` (8 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Fabio Pricoco, stable, Bruce Richardson
From: Fabio Pricoco <fabio.pricoco@intel.com>
Refactor while loop to add a check that the values read are in the
correct range.
Fixes: 6c1f26be50a2 ("net/ice/base: add control queue information")
Cc: stable@dpdk.org
Signed-off-by: Fabio Pricoco <fabio.pricoco@intel.com>
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_controlq.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index af27dc8542..b210495827 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -839,16 +839,35 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
struct ice_ctl_q_ring *sq = &cq->sq;
u16 ntc = sq->next_to_clean;
struct ice_aq_desc *desc;
+ u32 head;
desc = ICE_CTL_Q_DESC(*sq, ntc);
- while (rd32(hw, cq->sq.head) != ntc) {
- ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));
+ head = rd32(hw, sq->head);
+ if (head >= sq->count) {
+ ice_debug(hw, ICE_DBG_AQ_MSG,
+ "Read head value (%d) exceeds allowed range.\n",
+ head);
+ return 0;
+ }
+
+ while (head != ntc) {
+ ice_debug(hw, ICE_DBG_AQ_MSG,
+ "ntc %d head %d.\n",
+ ntc, head);
ice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);
ntc++;
if (ntc == sq->count)
ntc = 0;
desc = ICE_CTL_Q_DESC(*sq, ntc);
+
+ head = rd32(hw, sq->head);
+ if (head >= sq->count) {
+ ice_debug(hw, ICE_DBG_AQ_MSG,
+ "Read head value (%d) exceeds allowed range.\n",
+ head);
+ return 0;
+ }
}
sq->next_to_clean = ntc;
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 03/10] net/ice/base: fix VLAN replay after reset
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 01/10] net/ice/base: re-enable bypass mode for E822 Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 02/10] net/ice/base: add bounds check Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 04/10] net/ice/base: remove 255 limit on sched child nodes Bruce Richardson
` (7 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Dave Ertman, stable, Jacob Keller, Bruce Richardson
From: Dave Ertman <david.m.ertman@intel.com>
If there is more than one VLAN defined when any reset that affects the
PF is initiated, after the reset rebuild, no traffic will pass on any
VLAN but the last one created.
This is caused by the iteration though the VLANs during replay each
clearing the vsi_map bitmap of the VSI that is being replayed. The
problem is that during the replay, the pointer to the vsi_map bitmap is
used by each successive vlan to determine if it should be replayed on
this VSI.
The logic was that the replay of the VLAN would replace the bit in the
map before the next VLAN would iterate through. But, since the replay
copies the old bitmap pointer to filt_replay_rules and creates a new one
for the recreated VLANS, it does not do this, and leaves the old bitmap
broken to be used to replay the remaining VLANs.
Since the old bitmap will be cleaned up in post replay cleanup, there is
no need to alter it and break following VLAN replay, so don't clear the
bit.
Fixes: c7dd15931183 ("net/ice/base: add virtual switch code")
Cc: stable@dpdk.org
Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_switch.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c
index 96ef26d535..a3786961e6 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -10110,8 +10110,6 @@ ice_replay_vsi_fltr(struct ice_hw *hw, struct ice_port_info *pi,
if (!itr->vsi_list_info ||
!ice_is_bit_set(itr->vsi_list_info->vsi_map, vsi_handle))
continue;
- /* Clearing it so that the logic can add it back */
- ice_clear_bit(vsi_handle, itr->vsi_list_info->vsi_map);
f_entry.fltr_info.vsi_handle = vsi_handle;
f_entry.fltr_info.fltr_act = ICE_FWD_TO_VSI;
/* update the src in case it is VSI num */
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 04/10] net/ice/base: remove 255 limit on sched child nodes
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
` (2 preceding siblings ...)
2024-10-14 11:02 ` [PATCH v2 03/10] net/ice/base: fix VLAN replay after reset Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 05/10] net/ice/base: set VSI index on newly created nodes Bruce Richardson
` (6 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
The Tx scheduler in the ice driver can be configured to have large
numbers of child nodes at a given layer, but the driver code implicitly
limited the number of nodes to 255 by using a u8 datatype for the number
of children. Increase this to a 16-bit value throughout the code.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_dcb.c | 3 ++-
drivers/net/ice/base/ice_sched.c | 23 +++++++++++++----------
drivers/net/ice/base/ice_type.h | 2 +-
3 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index 4ef54613b1..e97f35b4cf 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -1585,7 +1585,8 @@ ice_update_port_tc_tree_cfg(struct ice_port_info *pi,
struct ice_aqc_txsched_elem_data elem;
u32 teid1, teid2;
int status = 0;
- u8 i, j;
+ u16 i;
+ u8 j;
if (!pi)
return ICE_ERR_PARAM;
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 373c32a518..1d6dd2af82 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -288,7 +288,7 @@ ice_sched_get_first_node(struct ice_port_info *pi,
*/
struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc)
{
- u8 i;
+ u16 i;
if (!pi || !pi->root)
return NULL;
@@ -311,7 +311,7 @@ void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node)
{
struct ice_sched_node *parent;
struct ice_hw *hw = pi->hw;
- u8 i, j;
+ u16 i, j;
/* Free the children before freeing up the parent node
* The parent array is updated below and that shifts the nodes
@@ -1503,7 +1503,7 @@ ice_sched_get_free_qgrp(struct ice_port_info *pi,
struct ice_sched_node *qgrp_node, u8 owner)
{
struct ice_sched_node *min_qgrp;
- u8 min_children;
+ u16 min_children;
if (!qgrp_node)
return qgrp_node;
@@ -2063,7 +2063,7 @@ static void ice_sched_rm_agg_vsi_info(struct ice_port_info *pi, u16 vsi_handle)
*/
static bool ice_sched_is_leaf_node_present(struct ice_sched_node *node)
{
- u8 i;
+ u16 i;
for (i = 0; i < node->num_children; i++)
if (ice_sched_is_leaf_node_present(node->children[i]))
@@ -2098,7 +2098,7 @@ ice_sched_rm_vsi_cfg(struct ice_port_info *pi, u16 vsi_handle, u8 owner)
ice_for_each_traffic_class(i) {
struct ice_sched_node *vsi_node, *tc_node;
- u8 j = 0;
+ u16 j = 0;
tc_node = ice_sched_get_tc_node(pi, i);
if (!tc_node)
@@ -2166,7 +2166,7 @@ int ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle)
*/
bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node)
{
- u8 i;
+ u16 i;
/* start from the leaf node */
for (i = 0; i < node->num_children; i++)
@@ -2240,7 +2240,8 @@ ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node,
u16 *num_nodes)
{
u8 l = node->tx_sched_layer;
- u8 vsil, i;
+ u8 vsil;
+ u16 i;
vsil = ice_sched_get_vsi_layer(hw);
@@ -2282,7 +2283,7 @@ ice_sched_update_parent(struct ice_sched_node *new_parent,
struct ice_sched_node *node)
{
struct ice_sched_node *old_parent;
- u8 i, j;
+ u16 i, j;
old_parent = node->parent;
@@ -2382,8 +2383,9 @@ ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 vsi_handle, u32 agg_id,
u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };
u32 first_node_teid, vsi_teid;
u16 num_nodes_added;
- u8 aggl, vsil, i;
+ u8 aggl, vsil;
int status;
+ u16 i;
tc_node = ice_sched_get_tc_node(pi, tc);
if (!tc_node)
@@ -2498,7 +2500,8 @@ ice_move_all_vsi_to_dflt_agg(struct ice_port_info *pi,
static bool
ice_sched_is_agg_inuse(struct ice_port_info *pi, struct ice_sched_node *node)
{
- u8 vsil, i;
+ u8 vsil;
+ u16 i;
vsil = ice_sched_get_vsi_layer(pi->hw);
if (node->tx_sched_layer < vsil - 1) {
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 598a80155b..6177bf4e2a 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1030,9 +1030,9 @@ struct ice_sched_node {
struct ice_aqc_txsched_elem_data info;
u32 agg_id; /* aggregator group ID */
u16 vsi_handle;
+ u16 num_children;
u8 in_use; /* suspended or in use */
u8 tx_sched_layer; /* Logical Layer (1-9) */
- u8 num_children;
u8 tc_num;
u8 owner;
#define ICE_SCHED_NODE_OWNER_LAN 0
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 05/10] net/ice/base: set VSI index on newly created nodes
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
` (3 preceding siblings ...)
2024-10-14 11:02 ` [PATCH v2 04/10] net/ice/base: remove 255 limit on sched child nodes Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 06/10] net/ice/base: optimize subtree searches Bruce Richardson
` (5 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
The ice_sched_node type has got a field for the vsi to which the node
belongs. This field was not getting set in "ice_sched_add_node", so add
a line configuring this field for each node from its parent node.
Similarly, when searching for a qgroup node, we can check for each node
that the VSI information is correct.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_sched.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 1d6dd2af82..45934f9152 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -200,6 +200,7 @@ ice_sched_add_node(struct ice_port_info *pi, u8 layer,
node->in_use = true;
node->parent = parent;
node->tx_sched_layer = layer;
+ node->vsi_handle = parent->vsi_handle;
parent->children[parent->num_children++] = node;
node->info = elem;
return 0;
@@ -1575,7 +1576,7 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
/* make sure the qgroup node is part of the VSI subtree */
if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node))
if (qgrp_node->num_children < max_children &&
- qgrp_node->owner == owner)
+ qgrp_node->owner == owner && qgrp_node->vsi_handle == vsi_handle)
break;
qgrp_node = qgrp_node->sibling;
}
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 06/10] net/ice/base: optimize subtree searches
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
` (4 preceding siblings ...)
2024-10-14 11:02 ` [PATCH v2 05/10] net/ice/base: set VSI index on newly created nodes Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 07/10] net/ice/base: remove flag checks before topology upload Bruce Richardson
` (4 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
In a number of places throughout the driver code, we want to confirm
that a scheduler node is indeed a child of another node. Currently, this
is confirmed by searching down the tree from the base until the desired
node is hit, a search which may hit many irrelevant tree nodes when
recursing down wrong branches. By switching the direction of search, to
check upwards from the node to the parent, we can avoid any incorrect
paths, and so speed up processing.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_sched.c | 23 +++++++----------------
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 45934f9152..4c5c19daf3 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -1464,25 +1464,16 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw)
* subtree or not
*/
bool
-ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base,
+ice_sched_find_node_in_subtree(struct ice_hw __ALWAYS_UNUSED *hw,
+ struct ice_sched_node *base,
struct ice_sched_node *node)
{
- u8 i;
-
- for (i = 0; i < base->num_children; i++) {
- struct ice_sched_node *child = base->children[i];
-
- if (node == child)
- return true;
-
- if (child->tx_sched_layer > node->tx_sched_layer)
- return false;
-
- /* this recursion is intentional, and wouldn't
- * go more than 8 calls
- */
- if (ice_sched_find_node_in_subtree(hw, child, node))
+ if (base == node)
+ return true;
+ while (node->tx_sched_layer != 0 && node->parent != NULL) {
+ if (node->parent == base)
return true;
+ node = node->parent;
}
return false;
}
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 07/10] net/ice/base: remove flag checks before topology upload
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
` (5 preceding siblings ...)
2024-10-14 11:02 ` [PATCH v2 06/10] net/ice/base: optimize subtree searches Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 08/10] net/ice/base: allow init without TC class sched nodes Bruce Richardson
` (3 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
DPDK should support more than just 9-level or 5-level topologies, so
remove the checks for those particular settings.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_ddp.c | 33 ---------------------------------
1 file changed, 33 deletions(-)
diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c
index 90aaa6b331..c17a58eab8 100644
--- a/drivers/net/ice/base/ice_ddp.c
+++ b/drivers/net/ice/base/ice_ddp.c
@@ -2384,38 +2384,6 @@ int ice_cfg_tx_topo(struct ice_hw *hw, u8 *buf, u32 len)
return status;
}
- /* Is default topology already applied ? */
- if (!(flags & ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW) &&
- hw->num_tx_sched_layers == 9) {
- ice_debug(hw, ICE_DBG_INIT, "Loaded default topology\n");
- /* Already default topology is loaded */
- return ICE_ERR_ALREADY_EXISTS;
- }
-
- /* Is new topology already applied ? */
- if ((flags & ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW) &&
- hw->num_tx_sched_layers == 5) {
- ice_debug(hw, ICE_DBG_INIT, "Loaded new topology\n");
- /* Already new topology is loaded */
- return ICE_ERR_ALREADY_EXISTS;
- }
-
- /* Is set topology issued already ? */
- if (flags & ICE_AQC_TX_TOPO_FLAGS_ISSUED) {
- ice_debug(hw, ICE_DBG_INIT, "Update tx topology was done by another PF\n");
- /* add a small delay before exiting */
- for (i = 0; i < 20; i++)
- ice_msec_delay(100, true);
- return ICE_ERR_ALREADY_EXISTS;
- }
-
- /* Change the topology from new to default (5 to 9) */
- if (!(flags & ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW) &&
- hw->num_tx_sched_layers == 5) {
- ice_debug(hw, ICE_DBG_INIT, "Change topology from 5 to 9 layers\n");
- goto update_topo;
- }
-
pkg_hdr = (struct ice_pkg_hdr *)buf;
state = ice_verify_pkg(pkg_hdr, len);
if (state) {
@@ -2462,7 +2430,6 @@ int ice_cfg_tx_topo(struct ice_hw *hw, u8 *buf, u32 len)
/* Get the new topology buffer */
new_topo = ((u8 *)section) + offset;
-update_topo:
/* acquire global lock to make sure that set topology issued
* by one PF
*/
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 08/10] net/ice/base: allow init without TC class sched nodes
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
` (6 preceding siblings ...)
2024-10-14 11:02 ` [PATCH v2 07/10] net/ice/base: remove flag checks before topology upload Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 09/10] net/ice/base: read VSI layer info from VSI Bruce Richardson
` (2 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
If DCB support is disabled via DDP image, there will not be any traffic
class (TC) nodes in the scheduler tree immediately above the root level.
To allow the driver to work with this scenario, we allow use of the root
node as a dummy TC0 node in case where there are no TC nodes in the
tree. For use of any other TC other than 0 (used by default in the
driver), existing behaviour of returning NULL pointer is maintained.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_sched.c | 8 +++++++-
drivers/net/ice/base/ice_type.h | 1 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 4c5c19daf3..7e255c0337 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -293,6 +293,10 @@ struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc)
if (!pi || !pi->root)
return NULL;
+ /* if no TC nodes, use root as TC node 0 */
+ if (!pi->has_tc)
+ return tc == 0 ? pi->root : NULL;
+
for (i = 0; i < pi->root->num_children; i++)
if (pi->root->children[i]->tc_num == tc)
return pi->root->children[i];
@@ -1306,7 +1310,9 @@ int ice_sched_init_port(struct ice_port_info *pi)
if (buf[0].generic[j].data.elem_type ==
ICE_AQC_ELEM_TYPE_ENTRY_POINT)
hw->sw_entry_point_layer = j;
-
+ else if (buf[0].generic[j].data.elem_type ==
+ ICE_AQC_ELEM_TYPE_TC)
+ pi->has_tc = 1;
status = ice_sched_add_node(pi, j, &buf[i].generic[j], NULL);
if (status)
goto err_init_port;
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 6177bf4e2a..35f832eb9f 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1260,6 +1260,7 @@ struct ice_port_info {
struct ice_qos_cfg qos_cfg;
u8 is_vf:1;
u8 is_custom_tx_enabled:1;
+ u8 has_tc:1;
};
struct ice_switch_info {
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 09/10] net/ice/base: read VSI layer info from VSI
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
` (7 preceding siblings ...)
2024-10-14 11:02 ` [PATCH v2 08/10] net/ice/base: allow init without TC class sched nodes Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 10/10] net/ice/base: update README Bruce Richardson
2024-10-14 17:27 ` [PATCH v2 00/10] net/ice: base code update for RC2 Medvedkin, Vladimir
10 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
Rather than computing from the number of HW layers the layer of the VSI,
we can instead just read that info from the VSI node itself. This allows
the layer to be changed at runtime.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/ice_sched.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 7e255c0337..9608ac7c24 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -1550,7 +1550,6 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
u16 max_children;
qgrp_layer = ice_sched_get_qgrp_layer(pi->hw);
- vsi_layer = ice_sched_get_vsi_layer(pi->hw);
max_children = pi->hw->max_children[qgrp_layer];
vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
@@ -1560,6 +1559,7 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
/* validate invalid VSI ID */
if (!vsi_node)
return NULL;
+ vsi_layer = vsi_node->tx_sched_layer;
/* If the queue group and vsi layer are same then queues
* are all attached directly to VSI
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 10/10] net/ice/base: update README
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
` (8 preceding siblings ...)
2024-10-14 11:02 ` [PATCH v2 09/10] net/ice/base: read VSI layer info from VSI Bruce Richardson
@ 2024-10-14 11:02 ` Bruce Richardson
2024-10-14 17:27 ` [PATCH v2 00/10] net/ice: base code update for RC2 Medvedkin, Vladimir
10 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-14 11:02 UTC (permalink / raw)
To: dev; +Cc: Bruce Richardson
Update the README file with the date of that latest base code snapshot.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/net/ice/base/README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/README b/drivers/net/ice/base/README
index 3c2dc43856..c32e530789 100644
--- a/drivers/net/ice/base/README
+++ b/drivers/net/ice/base/README
@@ -6,7 +6,7 @@ Intel® ICE driver
==================
This directory contains source code of ice base driver generated on
-2024-08-19 released by the team which develops
+2024-10-11 released by the team which develops
basic drivers for any ice NIC. The directory of base/ contains the
original source package.
This driver is valid for the product(s) listed below
--
2.43.0
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 00/10] net/ice: base code update for RC2
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
` (9 preceding siblings ...)
2024-10-14 11:02 ` [PATCH v2 10/10] net/ice/base: update README Bruce Richardson
@ 2024-10-14 17:27 ` Medvedkin, Vladimir
2024-10-15 10:05 ` Bruce Richardson
10 siblings, 1 reply; 23+ messages in thread
From: Medvedkin, Vladimir @ 2024-10-14 17:27 UTC (permalink / raw)
To: Bruce Richardson, dev
Hi Bruce,
Series-acked-by: Vladimir Medvedkin <vladimir.medvedkin@intel.com>
On 14/10/2024 12:02, Bruce Richardson wrote:
> A number of small fixes and other changes to enable Tx scheduler
> enhancements to our DPDK driver have been added to the base code.
> Upstream these changes for 24.11 RC2. Most have previously been
> submitted as part of the scheduler changes [1]
>
> [1] https://patches.dpdk.org/project/dpdk/list/?series=32758&state=*
>
> v2: include README file update
>
> Bruce Richardson (7):
> net/ice/base: remove 255 limit on sched child nodes
> net/ice/base: set VSI index on newly created nodes
> net/ice/base: optimize subtree searches
> net/ice/base: remove flag checks before topology upload
> net/ice/base: allow init without TC class sched nodes
> net/ice/base: read VSI layer info from VSI
> net/ice/base: update README
>
> Dave Ertman (1):
> net/ice/base: fix VLAN replay after reset
>
> Fabio Pricoco (1):
> net/ice/base: add bounds check
>
> Jacob Keller (1):
> net/ice/base: re-enable bypass mode for E822
>
> drivers/net/ice/base/README | 2 +-
> drivers/net/ice/base/ice_controlq.c | 23 +++++-
> drivers/net/ice/base/ice_dcb.c | 3 +-
> drivers/net/ice/base/ice_ddp.c | 33 --------
> drivers/net/ice/base/ice_ptp_hw.c | 117 ++++++++++++++++++++++++++--
> drivers/net/ice/base/ice_ptp_hw.h | 2 +-
> drivers/net/ice/base/ice_sched.c | 59 +++++++-------
> drivers/net/ice/base/ice_switch.c | 2 -
> drivers/net/ice/base/ice_type.h | 3 +-
> drivers/net/ice/ice_ethdev.c | 2 +-
> 10 files changed, 169 insertions(+), 77 deletions(-)
>
> --
> 2.43.0
>
--
Regards,
Vladimir
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 00/10] net/ice: base code update for RC2
2024-10-14 17:27 ` [PATCH v2 00/10] net/ice: base code update for RC2 Medvedkin, Vladimir
@ 2024-10-15 10:05 ` Bruce Richardson
0 siblings, 0 replies; 23+ messages in thread
From: Bruce Richardson @ 2024-10-15 10:05 UTC (permalink / raw)
To: Medvedkin, Vladimir; +Cc: dev
On Mon, Oct 14, 2024 at 06:27:44PM +0100, Medvedkin, Vladimir wrote:
> Hi Bruce,
>
> Series-acked-by: Vladimir Medvedkin <vladimir.medvedkin@intel.com>
>
Applied to dpdk-next-net-intel
/Bruce
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2024-10-15 10:05 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-10-11 16:44 [PATCH 0/9] net/ice: base code update for RC2 Bruce Richardson
2024-10-11 16:44 ` [PATCH 1/9] net/ice/base: re-enable bypass mode for E822 Bruce Richardson
2024-10-11 16:44 ` [PATCH 2/9] net/ice/base: add bounds check Bruce Richardson
2024-10-11 16:44 ` [PATCH 3/9] net/ice/base: fix VLAN replay after reset Bruce Richardson
2024-10-11 16:44 ` [PATCH 4/9] net/ice/base: remove 255 limit on sched child nodes Bruce Richardson
2024-10-11 16:44 ` [PATCH 5/9] net/ice/base: set VSI index on newly created nodes Bruce Richardson
2024-10-11 16:44 ` [PATCH 6/9] net/ice/base: optimize subtree searches Bruce Richardson
2024-10-11 16:44 ` [PATCH 7/9] net/ice/base: remove flag checks before topology upload Bruce Richardson
2024-10-11 16:44 ` [PATCH 8/9] net/ice/base: allow init without TC class sched nodes Bruce Richardson
2024-10-11 16:44 ` [PATCH 9/9] net/ice/base: read VSI layer info from VSI Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 00/10] net/ice: base code update for RC2 Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 01/10] net/ice/base: re-enable bypass mode for E822 Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 02/10] net/ice/base: add bounds check Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 03/10] net/ice/base: fix VLAN replay after reset Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 04/10] net/ice/base: remove 255 limit on sched child nodes Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 05/10] net/ice/base: set VSI index on newly created nodes Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 06/10] net/ice/base: optimize subtree searches Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 07/10] net/ice/base: remove flag checks before topology upload Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 08/10] net/ice/base: allow init without TC class sched nodes Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 09/10] net/ice/base: read VSI layer info from VSI Bruce Richardson
2024-10-14 11:02 ` [PATCH v2 10/10] net/ice/base: update README Bruce Richardson
2024-10-14 17:27 ` [PATCH v2 00/10] net/ice: base code update for RC2 Medvedkin, Vladimir
2024-10-15 10:05 ` Bruce Richardson
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