From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ABCB445A6D; Tue, 15 Oct 2024 00:30:31 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 02E904065A; Tue, 15 Oct 2024 00:30:26 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) by mails.dpdk.org (Postfix) with ESMTP id C55CD4026C for ; Tue, 15 Oct 2024 00:30:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728945021; x=1760481021; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pnPzxVMifiJbFVlxtxotRHHGUCiXNbMmFVOVO0xh0KE=; b=EZfffM8PWPw3tN7Ms/ShgMsomu6tr58Zalzva2YoZLLSSqNIwOh2iuFP Q5JHevIjiQijiYhvWZg6ZS2RTl8qA/dYodGaGKX9+v0hooB6c5j29e8H4 TegdXOJ4vi9jQwmOMTXwr8MD2oDuIrmU+wt1P8sszyRf0SHCha/55sUuz UeTh8oTNRTB4IldYsW9vWZEkxknnJyEG/sCdHueQdg7zuouRUeKcdBdF9 +YNX5H+E0G7fNbfcAVH1Nj/g3qHHEBRoOcczy0Q39IM+p2vEXUmsQOy5Q TttIyDCwLOpNbycn/YUat5TcN37FJCorRRRxCTpoJm/NgHVonaxThb4/T Q==; X-CSE-ConnectionGUID: 57Laz/xVQQyrDlkG4IOMmQ== X-CSE-MsgGUID: W8XE1Q7hTTC8BnTHxGrRpg== X-IronPort-AV: E=McAfee;i="6700,10204,11225"; a="38892042" X-IronPort-AV: E=Sophos;i="6.11,203,1725346800"; d="scan'208";a="38892042" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2024 15:30:19 -0700 X-CSE-ConnectionGUID: n2MJ1voTTHGC3qbEZhBKUQ== X-CSE-MsgGUID: k3lxJU9QSxizcrc8+xQveA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,203,1725346800"; d="scan'208";a="77321689" Received: from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..) ([10.233.181.123]) by fmviesa006.fm.intel.com with ESMTP; 14 Oct 2024 15:30:19 -0700 From: Nicolas Chautru To: dev@dpdk.org, maxime.coquelin@redhat.com Cc: hemant.agrawal@nxp.com, hernan.vargas@intel.com, Nicolas Chautru Subject: [PATCH v1 2/2] baseband/acc: saturate input to 6 bits for VRB decoder Date: Mon, 14 Oct 2024 15:30:46 -0700 Message-Id: <20241014223046.544893-3-nicolas.chautru@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241014223046.544893-1-nicolas.chautru@intel.com> References: <20241014223046.544893-1-nicolas.chautru@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Making the decoder more robust by forcing a default 6 bits LLR saturation to LDPC Decoder input. Signed-off-by: Nicolas Chautru --- drivers/baseband/acc/rte_vrb_pmd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 5eb3e8dd48..eb9892ff31 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -1799,6 +1799,9 @@ vrb_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, fcw->hcout_offset = 0; } + /* Force saturation to 6 bits LLR. */ + fcw->saturate_input = 1; + fcw->tb_crc_select = 0; if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK)) fcw->tb_crc_select = 2; -- 2.34.1