From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5606C45B42; Tue, 15 Oct 2024 17:20:43 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C5D7C40672; Tue, 15 Oct 2024 17:20:18 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by mails.dpdk.org (Postfix) with ESMTP id 52FA940430 for ; Tue, 15 Oct 2024 17:20:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729005609; x=1760541609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TGsVBPP0lj7ygwO0K865OhEfHC6NR0DXeyWUFVN/YjA=; b=YYqESHsMNIUGDaMzIZfvY5nwJiaOe3SWC6fJfyHJAMy/iGl7bwpKwsLk tYP2gkdRTHUcETXIGaSwt+LI52SJS+mSRFD6jcxYFSGea/4RWcJJK3lTq cnrHyyuEWQbUH/vA8WIXm2nfT+IRM/BhmCF/S1pmt3dvObItoW6dxfh+Z F5PkT9DP4S9txd2bCPPQc4O4VJZZuWcQQcud9whMsi7CI/jX37mZB/Brc XbCR/asAUBYS+tu/hcYUy0gl4QVLbWvre2+JHpTWEku37dal4ogRUXsGw /E75U8A5ZTu989jY8T77wBB7cEvUThd8+NEPWaVaUTEp545DVB4ELe9Tf g==; X-CSE-ConnectionGUID: xdYFT8JITRG2fVu3aKz6Ww== X-CSE-MsgGUID: ANPfdVu+R4in2zZplKBd0Q== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="28549692" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="28549692" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2024 08:20:08 -0700 X-CSE-ConnectionGUID: yV72WQlxREqMCUN7QI/4vA== X-CSE-MsgGUID: RThlAKoIQgqvaMCe/lNl5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,205,1725346800"; d="scan'208";a="78393726" Received: from unknown (HELO silpixa00401385.ir.intel.com) ([10.237.214.25]) by orviesa007.jf.intel.com with ESMTP; 15 Oct 2024 08:20:08 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: Bruce Richardson , Stephen Hemminger Subject: [PATCH v2 5/5] net/ice: limit the number of queues to sched capabilities Date: Tue, 15 Oct 2024 16:19:57 +0100 Message-ID: <20241015151957.1413286-6-bruce.richardson@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241015151957.1413286-1-bruce.richardson@intel.com> References: <20241009170822.344716-1-bruce.richardson@intel.com> <20241015151957.1413286-1-bruce.richardson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Rather than assuming that each VSI can hold up to 256 queue pairs, or the reported device limit, query the available nodes in the scheduler tree to check that we are not overflowing the limit for number of child scheduling nodes at each level. Do this by multiplying max_children for each level beyond the VSI and using that as an additional cap on the number of queues. Signed-off-by: Bruce Richardson Acked-by: Stephen Hemminger --- drivers/net/ice/ice_ethdev.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 422f600e3c..190ec00571 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -917,7 +917,7 @@ ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info) } static int -ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, +ice_vsi_config_tc_queue_mapping(struct ice_hw *hw, struct ice_vsi *vsi, struct ice_aqc_vsi_props *info, uint8_t enabled_tcmap) { @@ -933,13 +933,28 @@ ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi, } /* vector 0 is reserved and 1 vector for ctrl vsi */ - if (vsi->adapter->hw.func_caps.common_cap.num_msix_vectors < 2) + if (vsi->adapter->hw.func_caps.common_cap.num_msix_vectors < 2) { vsi->nb_qps = 0; - else + } else { vsi->nb_qps = RTE_MIN ((uint16_t)vsi->adapter->hw.func_caps.common_cap.num_msix_vectors - 2, RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC)); + /* cap max QPs to what the HW reports as num-children for each layer. + * Multiply num_children for each layer from the entry_point layer to + * the qgroup, or second-last layer. + * Avoid any potential overflow by using uint32_t type and breaking loop + * once we have a number greater than the already configured max. + */ + uint32_t max_sched_vsi_nodes = 1; + for (uint8_t i = hw->sw_entry_point_layer; i < hw->num_tx_sched_layers - 1; i++) { + max_sched_vsi_nodes *= hw->max_children[i]; + if (max_sched_vsi_nodes >= vsi->nb_qps) + break; + } + vsi->nb_qps = RTE_MIN(vsi->nb_qps, max_sched_vsi_nodes); + } + /* nb_qps(hex) -> fls */ /* 0000 -> 0 */ /* 0001 -> 0 */ @@ -1711,7 +1726,7 @@ ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort); /* Enable VLAN/UP trip */ - ret = ice_vsi_config_tc_queue_mapping(vsi, + ret = ice_vsi_config_tc_queue_mapping(hw, vsi, &vsi_ctx.info, ICE_DEFAULT_TCMAP); if (ret) { @@ -1735,7 +1750,7 @@ ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type) vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg); vsi_ctx.info.sw_id = hw->port_info->sw_id; vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA; - ret = ice_vsi_config_tc_queue_mapping(vsi, + ret = ice_vsi_config_tc_queue_mapping(hw, vsi, &vsi_ctx.info, ICE_DEFAULT_TCMAP); if (ret) { -- 2.43.0