From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D6C9945B44; Tue, 15 Oct 2024 18:37:05 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E78AC40274; Tue, 15 Oct 2024 18:36:55 +0200 (CEST) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2069.outbound.protection.outlook.com [40.107.93.69]) by mails.dpdk.org (Postfix) with ESMTP id 02F424065F for ; Tue, 15 Oct 2024 18:36:53 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Iyew2awPGqj1sFQKWcqyiWHmR9zIF4z4Lp7pmNO+t+68GBx5087uYQ4WeE1mcLg7GPv15sd9R37ThdQUBovO8Oc2wzSE8o2252eQJ21oZnoW+h6K0YNIbDaUHWUOcWBDviMPNrggWStDf0EvYHJ6faMs0UbgUEFekapW3JZMu8JauBObbnc5UQcQC4VY0YTAghsyKjq/Ko7BqpJNN6M5UKZK3alUFl2XM7q8CvLskHVAnme7f3Z6smW55WHGWeHhAZyED2Oc9MYunZHIn8yBMFUxCqmxuL2jmmBCaL1bkqu6a1lCcUfoI4gf/5Gd1TEpBFUj4551fZ8wdLQSp9XQPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=smmGrjW3OJmVR6oWbJn9CuAp9z8c7K0O4FgOtdIV9Q4=; b=YTzl0z28N+L8QGynzw4XwLYk/6EKjXKKvNiFLmJ/L6Mi9U3hLn76gxsJIduXWBwcT12CXQg6KvRtyqEDEn34nMBUFnjQyrTbxESqeTAYn5v5hY80IFXYgDnbTYgwslWO0Htx8Kgo4yvsLkKlNo5G2YiN5DTX3AYyjJCSYqm4Q6PpBTAMpNSj2CWuNL+5UG+vTyQzOtuGBzOGEE6meICbn5t1QkIRdYhEVF2jfTcbXeigNtxk9/Mgu95KMnslRdaNsszUX9fZBuUoxi34wuXwIybWlex5p6ACShTkBIzWgqA9ngpwPb0jjU52H6SsS+25ud7cImG4BnPuBWcO9zCWCA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=smmGrjW3OJmVR6oWbJn9CuAp9z8c7K0O4FgOtdIV9Q4=; b=W4xBMPKt3M4KUI1wMr7vCWC18iox/YgX2KCkfSvgFRN44tgrWX89P+iBR3RMeb32NVTxu5yWyPyqrSw5EVFeI5YcP9FJkeGtF0bZXWm6ULg94VUT17nbEZrkMosfZXYUjgA6+aSWIz1pTgcz5zOlcn2I8BhRMzmT3S+PpqmNDORfgpjcV6ay5hJlja4Cw1x90TsNvCedF95mnNR4ypTvxVxT+szcOnFUybVniZbnvWYMrHvsYY2NCJc0xW30lwwBWnmwEeLDei7ncsxh3ltbjnCiVYaQ3AOjK32yKQElhSghFAPVKh4Zydv9y81FQCpOxF25f0+fPh3VIGEVM6Yc+g== Received: from PH8PR22CA0006.namprd22.prod.outlook.com (2603:10b6:510:2d1::10) by PH7PR12MB7139.namprd12.prod.outlook.com (2603:10b6:510:1ef::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8069.18; Tue, 15 Oct 2024 16:36:51 +0000 Received: from CY4PEPF0000EE37.namprd05.prod.outlook.com (2603:10b6:510:2d1:cafe::99) by PH8PR22CA0006.outlook.office365.com (2603:10b6:510:2d1::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.28 via Frontend Transport; Tue, 15 Oct 2024 16:36:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE37.mail.protection.outlook.com (10.167.242.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8069.17 via Frontend Transport; Tue, 15 Oct 2024 16:36:50 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 15 Oct 2024 09:36:35 -0700 Received: from pegasus01.mtr.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 15 Oct 2024 09:36:32 -0700 From: Alexander Kozyrev To: CC: , , , , , , , , Subject: [PATCH 4/5] net/mlx5: add flow rule insertion by index with pattern Date: Tue, 15 Oct 2024 19:35:56 +0300 Message-ID: <20241015163557.581447-4-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20241015163557.581447-1-akozyrev@nvidia.com> References: <20241015163557.581447-1-akozyrev@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|PH7PR12MB7139:EE_ X-MS-Office365-Filtering-Correlation-Id: eb2e6314-6eaf-41d7-ddc6-08dced3791f1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?RRxtX3TD9eXcewDA68cT7WlsPJVWq4qMiJYcRiWgQxUP5TYIi+wqkMQJrxiN?= =?us-ascii?Q?YRuOw58d7RQrhH6hO+o0avhFkBqhhJsX+7F0HoQTsZu4WcdxzDKtweZtfvFm?= =?us-ascii?Q?DwQb31PM6BNehwuhP6jSiOjBQaF5aumcsl5IfojMLYMmpojv5u9VNTHcikSA?= =?us-ascii?Q?1PUHv7GgUPuAExYUu8wdCWDYv4YNvfRfKDjgELFFEnKVmhn1Ks1xVUa2cH/s?= =?us-ascii?Q?+FEmTrsmun2kBX5uiP2RrAntMz8MlociBg50yEF595lAFIncO1Q42OgbGWXi?= =?us-ascii?Q?bcC5aNyvmFmLsFZHJDKbzjIF4eOXzS+7GQmVzrQ6t1wloCcaHSgxqklw481G?= =?us-ascii?Q?KdfcPgbqU3LcS7RQNEznzDENSKnzXrQ1NnQe9GEzS82VLwvEW+UbSU2hdoK0?= =?us-ascii?Q?8EHSh1wLBr1+h0yEN53xqJdWt4ypSjiy2htyD30AX+bREEheqA+sm3sYgRiR?= =?us-ascii?Q?9WJgZV8xCMCBHWBRGH3ojapAbmEHuhTdQNwEzGQdnhqeY57lNmIP30Ty7RyQ?= =?us-ascii?Q?0gMsrBC1XiJGVKGvk2Y0+XxCWokjuFGNu71BwE2A9f3uq8sLVBfCMFSWE4b9?= =?us-ascii?Q?0bVLhHx0NXwKGQxfqRxT0nvR7OHuCNAJcwGBfhxcyRwOWDOGFS3w96ZyHcv/?= =?us-ascii?Q?VHuSINp13IXer57jOsAyKN1zdmnMWKSis/XkpGnFCBOR0Gja6PMakUkwdp1G?= =?us-ascii?Q?5Z8g84nrECT4RCfLLa7CVVpLeYY7qaz9wd6Xtpb+MHFYLvNe865gBQwanbe3?= =?us-ascii?Q?WH/au+d9mpFn6jyHqyo5iOSfXT8xxQhqlCUeD5R0BaF/hY1q8STVfr1FQBQ6?= =?us-ascii?Q?IingDA7KXn7h2NECj0FZLYQYCspfxE2GDChoUzeMxTJukYlBgD0zmuJ0Gpya?= =?us-ascii?Q?vBiRgdApOS/dyRd/Ybw/CI6q4wmzRe8KfYpejEiT98x1Sv7ymZT0aNaRW3mH?= =?us-ascii?Q?kSzA0GHE2y0sIiW3mHXFEmxuOcdvgiAk2EORrkzkNhbW8ohwoydvKcW0G0IW?= =?us-ascii?Q?+cM6vVtAa6c6q8JgZLXoJoYdpz+3wHgAaEmLEM5zs7eWrp5DahDtYaP1nm2e?= =?us-ascii?Q?R/VFigs01mX3DtAcEgRw865OCXnzAlQZlwf5RzSfCDSVSlfzHRm0i7nAy6Cd?= =?us-ascii?Q?Rdvkfv4kjALX765ZtkjUWm6AZTQENC2WKX7JtfqICci++6kJ8YCBpTow1vYD?= =?us-ascii?Q?V82dTsby+/dJZqI7qsYOxt0AL7g4hleg8sei2gv4YkAOI19YoFOjE0ivYUOJ?= =?us-ascii?Q?TJSfyMulPPOrBperB7UVir7CyYjo732R4kUuzBm+5gu9A/cJh58J9rV8M26Y?= =?us-ascii?Q?2fS0IIDOcx7mKE+9hDDcaWSRsoS2mPrP2LKw19ciYeLp6rmDAejWyXIliXnB?= =?us-ascii?Q?xDwDfqEcIgz9CqX+oCK2izCiyLP/?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2024 16:36:50.6205 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb2e6314-6eaf-41d7-ddc6-08dced3791f1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7139 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement rte_flow_async_create_by_index_with_pattern() function. Rework the driver implementaion to reduce the code duplication by providing a signle flow insertion routine, that can be called with different parameters depending on the insertion type. Signed-off-by: Alexander Kozyrev --- drivers/net/mlx5/mlx5_flow_hw.c | 281 +++++++++----------------------- 1 file changed, 81 insertions(+), 200 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 6434937562..6c8404ee2c 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -335,18 +335,13 @@ static __rte_always_inline uint32_t flow_hw_tx_tag_regc_value(struct rte_eth_dev static int flow_hw_async_create_validate(struct rte_eth_dev *dev, const uint32_t queue, const struct rte_flow_template_table *table, + enum rte_flow_table_insertion_type insertion_type, + const uint32_t rule_index, const struct rte_flow_item items[], const uint8_t pattern_template_index, const struct rte_flow_action actions[], const uint8_t action_template_index, struct rte_flow_error *error); -static int flow_hw_async_create_by_index_validate(struct rte_eth_dev *dev, - const uint32_t queue, - const struct rte_flow_template_table *table, - const uint32_t rule_index, - const struct rte_flow_action actions[], - const uint8_t action_template_index, - struct rte_flow_error *error); static int flow_hw_async_update_validate(struct rte_eth_dev *dev, const uint32_t queue, const struct rte_flow_hw *flow, @@ -3884,6 +3879,12 @@ flow_hw_get_rule_items(struct rte_eth_dev *dev, * The queue to create the flow. * @param[in] attr * Pointer to the flow operation attributes. + * @param[in] table + * Pointer to the template table. + * @param[in] insertion_type + * Insertion type for flow rules. + * @param[in] rule_index + * The item pattern flow follows from the table. * @param[in] items * Items with flow spec value. * @param[in] pattern_template_index @@ -3900,17 +3901,19 @@ flow_hw_get_rule_items(struct rte_eth_dev *dev, * @return * Flow pointer on success, NULL otherwise and rte_errno is set. */ -static struct rte_flow * -flow_hw_async_flow_create(struct rte_eth_dev *dev, - uint32_t queue, - const struct rte_flow_op_attr *attr, - struct rte_flow_template_table *table, - const struct rte_flow_item items[], - uint8_t pattern_template_index, - const struct rte_flow_action actions[], - uint8_t action_template_index, - void *user_data, - struct rte_flow_error *error) +static __rte_always_inline struct rte_flow * +flow_hw_async_flow_create_generic(struct rte_eth_dev *dev, + uint32_t queue, + const struct rte_flow_op_attr *attr, + struct rte_flow_template_table *table, + enum rte_flow_table_insertion_type insertion_type, + uint32_t rule_index, + const struct rte_flow_item items[], + uint8_t pattern_template_index, + const struct rte_flow_action actions[], + uint8_t action_template_index, + void *user_data, + struct rte_flow_error *error) { struct mlx5_priv *priv = dev->data->dev_private; struct mlx5dr_rule_attr rule_attr = { @@ -3928,8 +3931,8 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev, int ret; if (mlx5_fp_debug_enabled()) { - if (flow_hw_async_create_validate(dev, queue, table, items, pattern_template_index, - actions, action_template_index, error)) + if (flow_hw_async_create_validate(dev, queue, table, insertion_type, rule_index, + items, pattern_template_index, actions, action_template_index, error)) return NULL; } flow = mlx5_ipool_malloc(table->flow, &flow_idx); @@ -3967,7 +3970,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev, * Indexed pool returns 1-based indices, but mlx5dr expects 0-based indices * for rule insertion hints. */ - flow->rule_idx = flow->res_idx - 1; + flow->rule_idx = (rule_index == UINT32_MAX) ? flow->res_idx - 1 : rule_index; rule_attr.rule_idx = flow->rule_idx; /* * Construct the flow actions based on the input actions. @@ -4023,33 +4026,26 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev, return NULL; } -/** - * Enqueue HW steering flow creation by index. - * - * The flow will be applied to the HW only if the postpone bit is not set or - * the extra push function is called. - * The flow creation status should be checked from dequeue result. - * - * @param[in] dev - * Pointer to the rte_eth_dev structure. - * @param[in] queue - * The queue to create the flow. - * @param[in] attr - * Pointer to the flow operation attributes. - * @param[in] rule_index - * The item pattern flow follows from the table. - * @param[in] actions - * Action with flow spec value. - * @param[in] action_template_index - * The action pattern flow follows from the table. - * @param[in] user_data - * Pointer to the user_data. - * @param[out] error - * Pointer to error structure. - * - * @return - * Flow pointer on success, NULL otherwise and rte_errno is set. - */ +static struct rte_flow * +flow_hw_async_flow_create(struct rte_eth_dev *dev, + uint32_t queue, + const struct rte_flow_op_attr *attr, + struct rte_flow_template_table *table, + const struct rte_flow_item items[], + uint8_t pattern_template_index, + const struct rte_flow_action actions[], + uint8_t action_template_index, + void *user_data, + struct rte_flow_error *error) +{ + uint32_t rule_index = UINT32_MAX; + + return flow_hw_async_flow_create_generic(dev, queue, attr, table, + RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN, rule_index, + items, pattern_template_index, actions, action_template_index, + user_data, error); +} + static struct rte_flow * flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev, uint32_t queue, @@ -4062,105 +4058,31 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev, struct rte_flow_error *error) { struct rte_flow_item items[] = {{.type = RTE_FLOW_ITEM_TYPE_END,}}; - struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5dr_rule_attr rule_attr = { - .queue_id = queue, - .user_data = user_data, - .burst = attr->postpone, - }; - struct mlx5dr_rule_action *rule_acts; - struct mlx5_flow_hw_action_params ap; - struct rte_flow_hw *flow = NULL; - uint32_t flow_idx = 0; - uint32_t res_idx = 0; - int ret; + uint8_t pattern_template_index = 0; - if (mlx5_fp_debug_enabled()) { - if (flow_hw_async_create_by_index_validate(dev, queue, table, rule_index, - actions, action_template_index, error)) - return NULL; - } - flow = mlx5_ipool_malloc(table->flow, &flow_idx); - if (!flow) { - rte_errno = ENOMEM; - goto error; - } - rule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue); - /* - * Set the table here in order to know the destination table - * when free the flow afterwards. - */ - flow->table = table; - flow->mt_idx = 0; - flow->idx = flow_idx; - if (table->resource) { - mlx5_ipool_malloc(table->resource, &res_idx); - if (!res_idx) { - rte_errno = ENOMEM; - goto error; - } - flow->res_idx = res_idx; - } else { - flow->res_idx = flow_idx; - } - flow->flags = 0; - /* - * Set the flow operation type here in order to know if the flow memory - * should be freed or not when get the result from dequeue. - */ - flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE; - flow->user_data = user_data; - rule_attr.user_data = flow; - /* Set the rule index. */ - flow->rule_idx = rule_index; - rule_attr.rule_idx = flow->rule_idx; - /* - * Construct the flow actions based on the input actions. - * The implicitly appended action is always fixed, like metadata - * copy action from FDB to NIC Rx. - * No need to copy and contrust a new "actions" list based on the - * user's input, in order to save the cost. - */ - if (flow_hw_actions_construct(dev, flow, &ap, - &table->ats[action_template_index], - table->its[0]->item_flags, table, - actions, rule_acts, queue, error)) { - rte_errno = EINVAL; - goto error; - } - if (likely(!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))) { - ret = mlx5dr_rule_create(table->matcher_info[0].matcher, - 0, items, action_template_index, - rule_acts, &rule_attr, - (struct mlx5dr_rule *)flow->rule); - } else { - struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow); - uint32_t selector; + return flow_hw_async_flow_create_generic(dev, queue, attr, table, + RTE_FLOW_TABLE_INSERTION_TYPE_INDEX, rule_index, + items, pattern_template_index, actions, action_template_index, + user_data, error); +} - flow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE; - rte_rwlock_read_lock(&table->matcher_replace_rwlk); - selector = table->matcher_selector; - ret = mlx5dr_rule_create(table->matcher_info[selector].matcher, - 0, items, action_template_index, - rule_acts, &rule_attr, - (struct mlx5dr_rule *)flow->rule); - rte_rwlock_read_unlock(&table->matcher_replace_rwlk); - aux->matcher_selector = selector; - flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR; - } - if (likely(!ret)) { - flow_hw_q_inc_flow_ops(priv, queue); - return (struct rte_flow *)flow; - } -error: - if (table->resource && res_idx) - mlx5_ipool_free(table->resource, res_idx); - if (flow_idx) - mlx5_ipool_free(table->flow, flow_idx); - rte_flow_error_set(error, rte_errno, - RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, - "fail to create rte flow"); - return NULL; +static struct rte_flow * +flow_hw_async_flow_create_by_index_with_pattern(struct rte_eth_dev *dev, + uint32_t queue, + const struct rte_flow_op_attr *attr, + struct rte_flow_template_table *table, + uint32_t rule_index, + const struct rte_flow_item items[], + uint8_t pattern_template_index, + const struct rte_flow_action actions[], + uint8_t action_template_index, + void *user_data, + struct rte_flow_error *error) +{ + return flow_hw_async_flow_create_generic(dev, queue, attr, table, + RTE_FLOW_TABLE_INSERTION_TYPE_INDEX_WITH_PATTERN, rule_index, + items, pattern_template_index, actions, action_template_index, + user_data, error); } /** @@ -16579,6 +16501,8 @@ flow_hw_async_op_validate(struct rte_eth_dev *dev, * The queue to create the flow. * @param[in] table * Pointer to template table. + * @param[in] rule_index + * The item pattern flow follows from the table. * @param[in] items * Items with flow spec value. * @param[in] pattern_template_index @@ -16598,6 +16522,8 @@ static int flow_hw_async_create_validate(struct rte_eth_dev *dev, const uint32_t queue, const struct rte_flow_template_table *table, + enum rte_flow_table_insertion_type insertion_type, + uint32_t rule_index, const struct rte_flow_item items[], const uint8_t pattern_template_index, const struct rte_flow_action actions[], @@ -16607,63 +16533,18 @@ flow_hw_async_create_validate(struct rte_eth_dev *dev, if (flow_hw_async_op_validate(dev, queue, table, error)) return -rte_errno; - if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN) - return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, - "Only pattern insertion is allowed on this table"); - - if (flow_hw_validate_rule_pattern(dev, table, pattern_template_index, items, error)) - return -rte_errno; - - if (flow_hw_validate_rule_actions(dev, table, action_template_index, actions, error)) - return -rte_errno; - - return 0; -} + if (insertion_type != table->cfg.attr.insertion_type) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, "Flow rule insertion type mismatch with table configuration"); -/** - * Validate user input for rte_flow_async_create_by_index() implementation. - * - * If RTE_LIBRTE_MLX5_DEBUG macro is not defined, this function is a no-op. - * - * @param[in] dev - * Pointer to the rte_eth_dev structure. - * @param[in] queue - * The queue to create the flow. - * @param[in] table - * Pointer to template table. - * @param[in] rule_index - * Rule index in the table. - * Inserting a rule to already occupied index results in undefined behavior. - * @param[in] actions - * Action with flow spec value. - * @param[in] action_template_index - * The action pattern flow follows from the table. - * @param[out] error - * Pointer to error structure. - * - * @return - * 0 if user input is valid. - * Negative errno otherwise, rte_errno and error struct is set. - */ -static int -flow_hw_async_create_by_index_validate(struct rte_eth_dev *dev, - const uint32_t queue, - const struct rte_flow_template_table *table, - const uint32_t rule_index, - const struct rte_flow_action actions[], - const uint8_t action_template_index, - struct rte_flow_error *error) -{ - if (flow_hw_async_op_validate(dev, queue, table, error)) - return -rte_errno; + if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_PATTERN) + if (rule_index >= table->cfg.attr.nb_flows) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, "Flow rule index exceeds table size"); if (table->cfg.attr.insertion_type != RTE_FLOW_TABLE_INSERTION_TYPE_INDEX) - return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, - "Only index insertion is allowed on this table"); - - if (rule_index >= table->cfg.attr.nb_flows) - return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, - "Flow rule index exceeds table size"); + if (flow_hw_validate_rule_pattern(dev, table, pattern_template_index, items, error)) + return -rte_errno; if (flow_hw_validate_rule_actions(dev, table, action_template_index, actions, error)) return -rte_errno; @@ -16671,7 +16552,6 @@ flow_hw_async_create_by_index_validate(struct rte_eth_dev *dev, return 0; } - /** * Validate user input for rte_flow_async_update() implementation. * @@ -16744,6 +16624,7 @@ flow_hw_async_destroy_validate(struct rte_eth_dev *dev, static struct rte_flow_fp_ops mlx5_flow_hw_fp_ops = { .async_create = flow_hw_async_flow_create, .async_create_by_index = flow_hw_async_flow_create_by_index, + .async_create_by_index_with_pattern = flow_hw_async_flow_create_by_index_with_pattern, .async_actions_update = flow_hw_async_flow_update, .async_destroy = flow_hw_async_flow_destroy, .push = flow_hw_push, -- 2.18.2