From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EDF5045B5A; Thu, 17 Oct 2024 09:59:13 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 799AA406B8; Thu, 17 Oct 2024 09:58:40 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2044.outbound.protection.outlook.com [40.107.236.44]) by mails.dpdk.org (Postfix) with ESMTP id 2E581406B4 for ; Thu, 17 Oct 2024 09:58:38 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wrB4qDIqGSEdxPyniOpSXaG0lHBwuEequgpGS4gjsMlxC7s5ti9LnnqJgZl4ucsCk7uJq2PUY9r7sLRjfERLQXndN/XW8r341FtF1XGaDTcaBs9VZfGl1UY4TZHAoiku0naRsuLDPyDy+KzYOLZuJ365GuexQdhsCSccOuvRJSUrPlRGgYg3p9gWhUKD1ha8CidkdOKpXDiiDgKgmNFnn1F5ZY5w+Lx04YKYBgWBBPmcTAz1/S3j+j3Ns+ACjlCWZ5i+1IN/QwlveR8smeqeiEYEALbO9qsXHwY3MVvG6yNJ8lXMFLxIdijAYtT0NLqD5LyZx+qusizT0z+8P3Y8nw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+Fi8W9f+qq3Gha1oY1bleUGMoKK3lo3DQzkkqJxx3Vo=; b=k8BV90EJV6qWbNerRqdS1r/DwyZAn/hqtxfK9puESHWBJoZYWzsOm3/o5i1e9Mv5Nc8ol03xifgGJClwsjC/ATsPCJ0rw28KH2UpCCnDPvtMQk8n8Yljp8qiq7mgWN+b0y4mvZVFSrNgj17i4dl590026NWHTx6iGdPa73j5dDIlWGLiTy7h98kB+UqefsVYkmHvINaq5THe8kFn7IIOD3t977pxEZfC9ZQt/8F5cDR0hXvCNZt2XhfNzEk0CLqUY5/5Zh3wLPF8Y35uEG5rrAmXd0IH224JcpISCIYkNQezVNlbgA68I5lqNL3wgq6Um/upud0YTQ780jVIhEn6uQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+Fi8W9f+qq3Gha1oY1bleUGMoKK3lo3DQzkkqJxx3Vo=; b=SLhAAW/CJo9bcc7qWICToc/Z8+esDLNAQfkcFamrDC1hsxSMo8+VKfFK2a8Zk9Kxf6GklLW3eP3QRYrIfiL5obJlKaJlX3Zbq9eZiUB+sBdgJMfTNEoIEJmSAo89sR1MwWaetokDGw3YArDBq4SwiOwJG7VeBKCwMJLMIywoNO6gcbPDDkz4DAHkPNdl5nXlakYpA6oQf5HZtAHLiH/lHMuWegKiayBXdYq+33I2z/ovaVteG9w94xhkZ+eqPo63gBMKE+2zI6op6cYizC8yXheXo+0gfpJt5DCHlsOXJjcUpaXJn2bLexQNklPTquxQmboYzTQQCjfGYRd6dg4PRA== Received: from SA1PR05CA0007.namprd05.prod.outlook.com (2603:10b6:806:2d2::9) by MW4PR12MB6801.namprd12.prod.outlook.com (2603:10b6:303:1e8::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.27; Thu, 17 Oct 2024 07:58:33 +0000 Received: from SA2PEPF000015CC.namprd03.prod.outlook.com (2603:10b6:806:2d2:cafe::81) by SA1PR05CA0007.outlook.office365.com (2603:10b6:806:2d2::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.7 via Frontend Transport; Thu, 17 Oct 2024 07:58:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SA2PEPF000015CC.mail.protection.outlook.com (10.167.241.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8069.17 via Frontend Transport; Thu, 17 Oct 2024 07:58:32 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 17 Oct 2024 00:58:20 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 17 Oct 2024 00:58:18 -0700 From: Dariusz Sosnowski To: Viacheslav Ovsiienko , Bing Zhao , Ori Kam , Suanming Mou , Matan Azrad CC: Subject: [PATCH 09/10] net/mlx5: add dynamic unicast flow rule management Date: Thu, 17 Oct 2024 09:57:37 +0200 Message-ID: <20241017075738.190064-10-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241017075738.190064-1-dsosnowski@nvidia.com> References: <20241017075738.190064-1-dsosnowski@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CC:EE_|MW4PR12MB6801:EE_ X-MS-Office365-Filtering-Correlation-Id: ccb904a5-f23a-41ad-82b5-08dcee817f17 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?wnXUbiW6j5WnYnWV6RTOedWpFLfKOAt6qZ4WrVdUEJ9zpjxlQXLDqDCBh0J+?= =?us-ascii?Q?ezNusMY4a4t7NswQCvadEcEBOnBioOJCCt6UGzAQD/H/BrsCfWD4XCZp0tfT?= =?us-ascii?Q?EULFoHpySZJhm4uB3emvTCWK/j5+lxJeiTeQw/1CjXBU0aKD4c16fIx1uNTy?= =?us-ascii?Q?klNqZKvPQziyLOq3TnyQwvKM71VomPGR2X+u+A6iiMHyjUA7IH6zpwu9QBR3?= =?us-ascii?Q?b0r5OkIbfLdhTwM2A0nXUqD+irVHV4A7q1QL3qTjw5yDUpLacD4ijM6bV8Bv?= =?us-ascii?Q?rBYcaZmJTTXObVsENclxZ2UBbarLLzm0bO3J2wudtfgTSFUpMgfrQyhpT5Oh?= =?us-ascii?Q?LSFlwWCE6RGBw/93xICxyDsFZvg/MRW70GwC0S5Cf3jpzotwjesgVw5rpA3s?= =?us-ascii?Q?/9APQXRZTzm2Kq4h8TeuKrF4bzZPXIaPVdbaBR8F2o/lZVpgBzEcMUK8GUxW?= =?us-ascii?Q?XKuCo1UbTKdzepdAaYEcbDXevENC+T0w4KZSBik4bDYEKU+zGloC1+F+cPOC?= =?us-ascii?Q?h25DLSSrh3hJU5y6PrTBODluxb8N24eHCYEyFciCAXjVH0kdqYXLP1yJaO0k?= =?us-ascii?Q?J/lRO+0qHlOazNYrpHW8YiB+qfpsLVj/sFtS45jFsRPyup9OWSBwcrzLpPKJ?= =?us-ascii?Q?N+KVkU18Fhs5ZQZ69Zd4uP/OaDnwVpc/BtVg9IWGqW4FkNaJQV+05S/yaZ5U?= =?us-ascii?Q?LXOe8tAMvgkY6TFXESarC+vDuYk4adH5bRr/1b7nTak2LdmGijQ3rMw/kFtI?= =?us-ascii?Q?TtFixXerj86OVQfNLMaIFCpx794qB9UoAbUQFiHCZWZTOyEV3suw6JOLC32w?= =?us-ascii?Q?fY91V8efSHtM4+v5pzsPy91T0x7Of1r3n25NMnSkn4ZCWlsmQRYHGGUE/3ub?= =?us-ascii?Q?ItUlGZANvIwtSMrm+EooZPK0hYasxAz/l6gbq4gABgwD9Hvx/y5LNctYeQt5?= =?us-ascii?Q?yhn9e6m6xYgyrJCkzy6ZzP0hT3stm4o7Idv26L9l+eFguRZlue0d2s1Hof4y?= =?us-ascii?Q?S2e3Cod7ZUuNOzLN3tX3oKXahnaGfCyXLBVDpup8nmeTfdNx1lWSYOq2sSK6?= =?us-ascii?Q?gkzTNHj46+eYVWhmhMMqFqkamz9GjPxMgJdKjNKy0nZ5WhxfveHH4oS+To+m?= =?us-ascii?Q?j+ua246RQtGLCJ6wazas+R5Cb0YPICAhIn0AnBi4caj4Ux8DvAYjBfP+WYkf?= =?us-ascii?Q?oHqzPjzd9eenrxd256TeFWgdGeHXlt7U3XBMAkyjwjqKEFrDCjsd5Ldy6hBI?= =?us-ascii?Q?r+5a5m3xsM9TcKGHRkdBp5ObMtH2SOMtGgA5WyZHlniWAVykPco91Xy6MHAa?= =?us-ascii?Q?dQhTCZmFMN7ZoU06xpG5BZ57eV4kEqfU7/T/7aX9513R3yOxG7KSfJqeXwXj?= =?us-ascii?Q?2w/qLglegm9zoxaO2wDYpn0YEfXZYM2+dcZz1W3pENehLP+65Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2024 07:58:32.9113 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ccb904a5-f23a-41ad-82b5-08dcee817f17 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6801 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch extens the mlx5_traffic interface with a couple of functions: - mlx5_traffic_mac_add() - Create an unicast DMAC flow rule, without recreating all control flow rules. - mlx5_traffic_mac_remove() - Remove an unicast DMAC flow rule, without recreating all control flow rules. - mlx5_traffic_mac_vlan_add() - Create an unicast DMAC with VLAN flow rule, without recreating all control flow rules. - mlx5_traffic_mac_vlan_remove() - Remove an unicast DMAC with VLAN flow rule, without recreating all control flow rules. These functions will be used in the follow up commit, which will modify the behavior of adding/removing MAC address and enabling/disabling VLAN filter in mlx5 PMD. Signed-off-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5.h | 4 + drivers/net/mlx5/mlx5_trigger.c | 236 ++++++++++++++++++++++++++++++++ 2 files changed, 240 insertions(+) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index a51727526f..0e026f7bbb 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -2372,6 +2372,10 @@ int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, size_t len, uint32_t direction); +int mlx5_traffic_mac_add(struct rte_eth_dev *dev, const struct rte_ether_addr *addr); +int mlx5_traffic_mac_remove(struct rte_eth_dev *dev, const struct rte_ether_addr *addr); +int mlx5_traffic_vlan_add(struct rte_eth_dev *dev, const uint16_t vid); +int mlx5_traffic_vlan_remove(struct rte_eth_dev *dev, const uint16_t vid); /* mlx5_flow.c */ diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 4fa9319c4d..cac532b1a1 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1804,3 +1804,239 @@ mlx5_traffic_restart(struct rte_eth_dev *dev) } return 0; } + +static bool +mac_flows_update_needed(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + + if (!dev->data->dev_started) + return false; + if (dev->data->promiscuous) + return false; + if (priv->isolated) + return false; + + return true; +} + +static int +traffic_dmac_create(struct rte_eth_dev *dev, const struct rte_ether_addr *addr) +{ + struct mlx5_priv *priv = dev->data->dev_private; + + if (priv->sh->config.dv_flow_en == 2) + return mlx5_flow_hw_ctrl_flow_dmac(dev, addr); + else + return mlx5_legacy_dmac_flow_create(dev, addr); +} + +static int +traffic_dmac_destroy(struct rte_eth_dev *dev, const struct rte_ether_addr *addr) +{ + struct mlx5_priv *priv = dev->data->dev_private; + + if (priv->sh->config.dv_flow_en == 2) + return mlx5_flow_hw_ctrl_flow_dmac_destroy(dev, addr); + else + return mlx5_legacy_dmac_flow_destroy(dev, addr); +} + +static int +traffic_dmac_vlan_create(struct rte_eth_dev *dev, + const struct rte_ether_addr *addr, + const uint16_t vid) +{ + struct mlx5_priv *priv = dev->data->dev_private; + + if (priv->sh->config.dv_flow_en == 2) + return mlx5_flow_hw_ctrl_flow_dmac_vlan(dev, addr, vid); + else + return mlx5_legacy_dmac_vlan_flow_create(dev, addr, vid); +} + +static int +traffic_dmac_vlan_destroy(struct rte_eth_dev *dev, + const struct rte_ether_addr *addr, + const uint16_t vid) +{ + struct mlx5_priv *priv = dev->data->dev_private; + + if (priv->sh->config.dv_flow_en == 2) + return mlx5_flow_hw_ctrl_flow_dmac_vlan_destroy(dev, addr, vid); + else + return mlx5_legacy_dmac_vlan_flow_destroy(dev, addr, vid); +} + +/** + * Adjust Rx control flow rules to allow traffic on provided MAC address. + */ +int +mlx5_traffic_mac_add(struct rte_eth_dev *dev, const struct rte_ether_addr *addr) +{ + struct mlx5_priv *priv = dev->data->dev_private; + + if (!mac_flows_update_needed(dev)) + return 0; + + if (priv->vlan_filter_n > 0) { + unsigned int i; + + for (i = 0; i < priv->vlan_filter_n; ++i) { + uint16_t vlan = priv->vlan_filter[i]; + int ret; + + if (mlx5_ctrl_flow_uc_dmac_vlan_exists(dev, addr, vlan)) + continue; + + ret = traffic_dmac_vlan_create(dev, addr, vlan); + if (ret != 0) + return ret; + } + + return 0; + } + + if (mlx5_ctrl_flow_uc_dmac_exists(dev, addr)) + return 0; + + return traffic_dmac_create(dev, addr); +} + +/** + * Adjust Rx control flow rules to disallow traffic with removed MAC address. + */ +int +mlx5_traffic_mac_remove(struct rte_eth_dev *dev, const struct rte_ether_addr *addr) +{ + struct mlx5_priv *priv = dev->data->dev_private; + + if (!mac_flows_update_needed(dev)) + return 0; + + if (priv->vlan_filter_n > 0) { + unsigned int i; + + for (i = 0; i < priv->vlan_filter_n; ++i) { + uint16_t vlan = priv->vlan_filter[i]; + int ret; + + if (!mlx5_ctrl_flow_uc_dmac_vlan_exists(dev, addr, vlan)) + continue; + + ret = traffic_dmac_vlan_destroy(dev, addr, vlan); + if (ret != 0) + return ret; + } + + return 0; + } + + if (!mlx5_ctrl_flow_uc_dmac_exists(dev, addr)) + return 0; + + return traffic_dmac_destroy(dev, addr); +} + +/** + * Adjust Rx control flow rules to allow traffic on provided VLAN. + * + * Assumptions: + * - Called when VLAN is added. + * - At least one VLAN is enabled before function call. + * + * This functions assumes that VLAN is new and was not included in + * Rx control flow rules set up before calling it. + */ +int +mlx5_traffic_vlan_add(struct rte_eth_dev *dev, const uint16_t vid) +{ + struct mlx5_priv *priv = dev->data->dev_private; + unsigned int i; + int ret; + + if (!mac_flows_update_needed(dev)) + return 0; + + /* Add all unicast DMAC flow rules with new VLAN attached. */ + for (i = 0; i != MLX5_MAX_MAC_ADDRESSES; ++i) { + struct rte_ether_addr *mac = &dev->data->mac_addrs[i]; + + if (rte_is_zero_ether_addr(mac)) + continue; + + ret = traffic_dmac_vlan_create(dev, mac, vid); + if (ret != 0) + return ret; + } + + if (priv->vlan_filter_n == 1) { + /* + * Adding first VLAN. Need to remove unicast DMAC rules before adding new rules. + * Removing after creating VLAN rules so that traffic "gap" is not introduced. + */ + + for (i = 0; i != MLX5_MAX_MAC_ADDRESSES; ++i) { + struct rte_ether_addr *mac = &dev->data->mac_addrs[i]; + + if (rte_is_zero_ether_addr(mac)) + continue; + + ret = traffic_dmac_destroy(dev, mac); + if (ret != 0) + return ret; + } + } + + return 0; +} + +/** + * Adjust Rx control flow rules to disallow traffic with removed VLAN. + * + * Assumptions: + * + * - VLAN was really removed. + */ +int +mlx5_traffic_vlan_remove(struct rte_eth_dev *dev, const uint16_t vid) +{ + struct mlx5_priv *priv = dev->data->dev_private; + unsigned int i; + int ret; + + if (!mac_flows_update_needed(dev)) + return 0; + + if (priv->vlan_filter_n == 0) { + /* + * If there are no VLANs as a result, unicast DMAC flow rules must be recreated. + * Recreating first to ensure no traffic "gap". + */ + + for (i = 0; i != MLX5_MAX_MAC_ADDRESSES; ++i) { + struct rte_ether_addr *mac = &dev->data->mac_addrs[i]; + + if (rte_is_zero_ether_addr(mac)) + continue; + + ret = traffic_dmac_create(dev, mac); + if (ret != 0) + return ret; + } + } + + /* Remove all unicast DMAC flow rules with this VLAN. */ + for (i = 0; i != MLX5_MAX_MAC_ADDRESSES; ++i) { + struct rte_ether_addr *mac = &dev->data->mac_addrs[i]; + + if (rte_is_zero_ether_addr(mac)) + continue; + + ret = traffic_dmac_vlan_destroy(dev, mac, vid); + if (ret != 0) + return ret; + } + + return 0; +} -- 2.39.5