From: Dariusz Sosnowski <dsosnowski@nvidia.com>
To: Viacheslav Ovsiienko <viacheslavo@nvidia.com>,
Bing Zhao <bingz@nvidia.com>, Ori Kam <orika@nvidia.com>,
Suanming Mou <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>
Cc: <dev@dpdk.org>
Subject: [PATCH 05/10] net/mlx5: rename control flow rules types
Date: Thu, 17 Oct 2024 09:57:33 +0200 [thread overview]
Message-ID: <20241017075738.190064-6-dsosnowski@nvidia.com> (raw)
In-Reply-To: <20241017075738.190064-1-dsosnowski@nvidia.com>
All structs and enumerations used for managenement of
HWS control flow rules do not really depend on HWS itself.
In order to allow their reuse with Verbs and DV flow engines and
allow fine-grained creation/destruction of unicast DMAC (with VLAN)
flow rules with these flow engines, this patch renames all related
structs and enumerations.
All are renamed as follows:
- Enum mlx5_hw_ctrl_flow_type renamed to mlx5_ctrl_flow_type.
- Enum prefix MLX5_HW_CTRL_FLOW_TYPE_ changes to
MLX5_CTRL_FLOW_TYPE_
- Struct mlx5_hw_ctrl_flow_info renamed to mlx5_ctrl_flow_info.
- Struct mlx5_hw_ctrl_flow renamed to mlx5_ctrl_flow_entry.
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
drivers/net/mlx5/mlx5.h | 36 ++++++++--------
drivers/net/mlx5/mlx5_flow.c | 8 ++--
drivers/net/mlx5/mlx5_flow_hw.c | 74 ++++++++++++++++-----------------
3 files changed, 59 insertions(+), 59 deletions(-)
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 3551b793d6..a51727526f 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1787,23 +1787,23 @@ struct mlx5_obj_ops {
#define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
-enum mlx5_hw_ctrl_flow_type {
- MLX5_HW_CTRL_FLOW_TYPE_GENERAL,
- MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
- MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS,
- MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_JUMP,
- MLX5_HW_CTRL_FLOW_TYPE_TX_META_COPY,
- MLX5_HW_CTRL_FLOW_TYPE_TX_REPR_MATCH,
- MLX5_HW_CTRL_FLOW_TYPE_LACP_RX,
- MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
- MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
- MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
+enum mlx5_ctrl_flow_type {
+ MLX5_CTRL_FLOW_TYPE_GENERAL,
+ MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
+ MLX5_CTRL_FLOW_TYPE_SQ_MISS,
+ MLX5_CTRL_FLOW_TYPE_DEFAULT_JUMP,
+ MLX5_CTRL_FLOW_TYPE_TX_META_COPY,
+ MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH,
+ MLX5_CTRL_FLOW_TYPE_LACP_RX,
+ MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
+ MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
+ MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
};
/** Additional info about control flow rule. */
-struct mlx5_hw_ctrl_flow_info {
+struct mlx5_ctrl_flow_info {
/** Determines the kind of control flow rule. */
- enum mlx5_hw_ctrl_flow_type type;
+ enum mlx5_ctrl_flow_type type;
union {
/**
* If control flow is a SQ miss flow (root or not),
@@ -1843,8 +1843,8 @@ bool mlx5_ctrl_flow_uc_dmac_vlan_exists(struct rte_eth_dev *dev,
const uint16_t vid);
/** Entry for tracking control flow rules in HWS. */
-struct mlx5_hw_ctrl_flow {
- LIST_ENTRY(mlx5_hw_ctrl_flow) next;
+struct mlx5_ctrl_flow_entry {
+ LIST_ENTRY(mlx5_ctrl_flow_entry) next;
/**
* Owner device is a port on behalf of which flow rule was created.
*
@@ -1856,7 +1856,7 @@ struct mlx5_hw_ctrl_flow {
/** Pointer to flow rule handle. */
struct rte_flow *flow;
/** Additional information about the control flow rule. */
- struct mlx5_hw_ctrl_flow_info info;
+ struct mlx5_ctrl_flow_info info;
};
/* HW Steering port configuration passed to rte_flow_configure(). */
@@ -1965,8 +1965,8 @@ struct mlx5_priv {
struct mlx5_drop drop_queue; /* Flow drop queues. */
void *root_drop_action; /* Pointer to root drop action. */
rte_spinlock_t hw_ctrl_lock;
- LIST_HEAD(hw_ctrl_flow, mlx5_hw_ctrl_flow) hw_ctrl_flows;
- LIST_HEAD(hw_ext_ctrl_flow, mlx5_hw_ctrl_flow) hw_ext_ctrl_flows;
+ LIST_HEAD(hw_ctrl_flow, mlx5_ctrl_flow_entry) hw_ctrl_flows;
+ LIST_HEAD(hw_ext_ctrl_flow, mlx5_ctrl_flow_entry) hw_ext_ctrl_flows;
struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb;
struct rte_flow_pattern_template *hw_tx_repr_tagging_pt;
struct rte_flow_actions_template *hw_tx_repr_tagging_at;
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 69f8bd8d97..af79956eaa 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -12185,11 +12185,11 @@ bool
mlx5_ctrl_flow_uc_dmac_exists(struct rte_eth_dev *dev, const struct rte_ether_addr *addr)
{
struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_hw_ctrl_flow *entry;
+ struct mlx5_ctrl_flow_entry *entry;
bool exists = false;
LIST_FOREACH(entry, &priv->hw_ctrl_flows, next) {
- if (entry->info.type == MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC &&
+ if (entry->info.type == MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC &&
rte_is_same_ether_addr(addr, &entry->info.uc.dmac)) {
exists = true;
break;
@@ -12204,11 +12204,11 @@ mlx5_ctrl_flow_uc_dmac_vlan_exists(struct rte_eth_dev *dev,
const uint16_t vid)
{
struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_hw_ctrl_flow *entry;
+ struct mlx5_ctrl_flow_entry *entry;
bool exists = false;
LIST_FOREACH(entry, &priv->hw_ctrl_flows, next) {
- if (entry->info.type == MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN &&
+ if (entry->info.type == MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN &&
rte_is_same_ether_addr(addr, &entry->info.uc.dmac) &&
vid == entry->info.uc.vlan) {
exists = true;
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 35e9eead7e..0d8224b8de 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -15086,7 +15086,7 @@ flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,
uint8_t item_template_idx,
struct rte_flow_action actions[],
uint8_t action_template_idx,
- struct mlx5_hw_ctrl_flow_info *info,
+ struct mlx5_ctrl_flow_info *info,
bool external)
{
struct mlx5_priv *priv = proxy_dev->data->dev_private;
@@ -15095,7 +15095,7 @@ flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,
.postpone = 0,
};
struct rte_flow *flow = NULL;
- struct mlx5_hw_ctrl_flow *entry = NULL;
+ struct mlx5_ctrl_flow_entry *entry = NULL;
int ret;
rte_spinlock_lock(&priv->hw_ctrl_lock);
@@ -15131,7 +15131,7 @@ flow_hw_create_ctrl_flow(struct rte_eth_dev *owner_dev,
if (info)
entry->info = *info;
else
- entry->info.type = MLX5_HW_CTRL_FLOW_TYPE_GENERAL;
+ entry->info.type = MLX5_CTRL_FLOW_TYPE_GENERAL;
if (external)
LIST_INSERT_HEAD(&priv->hw_ext_ctrl_flows, entry, next);
else
@@ -15208,8 +15208,8 @@ static int
flow_hw_flush_ctrl_flows_owned_by(struct rte_eth_dev *dev, struct rte_eth_dev *owner)
{
struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_hw_ctrl_flow *cf;
- struct mlx5_hw_ctrl_flow *cf_next;
+ struct mlx5_ctrl_flow_entry *cf;
+ struct mlx5_ctrl_flow_entry *cf_next;
int ret;
cf = LIST_FIRST(&priv->hw_ctrl_flows);
@@ -15287,8 +15287,8 @@ static int
flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev)
{
struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_hw_ctrl_flow *cf;
- struct mlx5_hw_ctrl_flow *cf_next;
+ struct mlx5_ctrl_flow_entry *cf;
+ struct mlx5_ctrl_flow_entry *cf_next;
int ret;
cf = LIST_FIRST(&priv->hw_ctrl_flows);
@@ -15344,8 +15344,8 @@ mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool
};
struct rte_flow_item items[3] = { { 0 } };
struct rte_flow_action actions[3] = { { 0 } };
- struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
+ struct mlx5_ctrl_flow_info flow_info = {
+ .type = MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
.esw_mgr_sq = sqn,
};
struct rte_eth_dev *proxy_dev;
@@ -15434,7 +15434,7 @@ mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool
actions[1] = (struct rte_flow_action){
.type = RTE_FLOW_ACTION_TYPE_END,
};
- flow_info.type = MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS;
+ flow_info.type = MLX5_CTRL_FLOW_TYPE_SQ_MISS;
ret = flow_hw_create_ctrl_flow(dev, proxy_dev,
proxy_priv->hw_ctrl_fdb->hw_esw_sq_miss_tbl,
items, 0, actions, 0, &flow_info, external);
@@ -15447,15 +15447,15 @@ mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn, bool
}
static bool
-flow_hw_is_matching_sq_miss_flow(struct mlx5_hw_ctrl_flow *cf,
+flow_hw_is_matching_sq_miss_flow(struct mlx5_ctrl_flow_entry *cf,
struct rte_eth_dev *dev,
uint32_t sqn)
{
if (cf->owner_dev != dev)
return false;
- if (cf->info.type == MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS_ROOT && cf->info.esw_mgr_sq == sqn)
+ if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT && cf->info.esw_mgr_sq == sqn)
return true;
- if (cf->info.type == MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS && cf->info.esw_mgr_sq == sqn)
+ if (cf->info.type == MLX5_CTRL_FLOW_TYPE_SQ_MISS && cf->info.esw_mgr_sq == sqn)
return true;
return false;
}
@@ -15467,8 +15467,8 @@ mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)
uint16_t proxy_port_id = dev->data->port_id;
struct rte_eth_dev *proxy_dev;
struct mlx5_priv *proxy_priv;
- struct mlx5_hw_ctrl_flow *cf;
- struct mlx5_hw_ctrl_flow *cf_next;
+ struct mlx5_ctrl_flow_entry *cf;
+ struct mlx5_ctrl_flow_entry *cf_next;
int ret;
ret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);
@@ -15529,8 +15529,8 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)
.type = RTE_FLOW_ACTION_TYPE_END,
}
};
- struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_JUMP,
+ struct mlx5_ctrl_flow_info flow_info = {
+ .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_JUMP,
};
struct rte_eth_dev *proxy_dev;
struct mlx5_priv *proxy_priv;
@@ -15610,8 +15610,8 @@ mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev)
.type = RTE_FLOW_ACTION_TYPE_END,
},
};
- struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_TX_META_COPY,
+ struct mlx5_ctrl_flow_info flow_info = {
+ .type = MLX5_CTRL_FLOW_TYPE_TX_META_COPY,
};
MLX5_ASSERT(priv->master);
@@ -15650,8 +15650,8 @@ mlx5_flow_hw_tx_repr_matching_flow(struct rte_eth_dev *dev, uint32_t sqn, bool e
{ .type = RTE_FLOW_ACTION_TYPE_END },
{ .type = RTE_FLOW_ACTION_TYPE_END },
};
- struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_TX_REPR_MATCH,
+ struct mlx5_ctrl_flow_info flow_info = {
+ .type = MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH,
.tx_repr_sq = sqn,
};
@@ -15708,8 +15708,8 @@ mlx5_flow_hw_lacp_rx_flow(struct rte_eth_dev *dev)
.type = RTE_FLOW_ACTION_TYPE_END,
},
};
- struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_LACP_RX,
+ struct mlx5_ctrl_flow_info flow_info = {
+ .type = MLX5_CTRL_FLOW_TYPE_LACP_RX,
};
if (!priv->dr_ctx || !priv->hw_ctrl_fdb || !priv->hw_ctrl_fdb->hw_lacp_rx_tbl)
@@ -15831,8 +15831,8 @@ __flow_hw_ctrl_flows_single(struct rte_eth_dev *dev,
{ .type = RTE_FLOW_ACTION_TYPE_RSS },
{ .type = RTE_FLOW_ACTION_TYPE_END },
};
- struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
+ struct mlx5_ctrl_flow_info flow_info = {
+ .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
};
if (!eth_spec)
@@ -15863,8 +15863,8 @@ __flow_hw_ctrl_flows_single_vlan(struct rte_eth_dev *dev,
{ .type = RTE_FLOW_ACTION_TYPE_RSS },
{ .type = RTE_FLOW_ACTION_TYPE_END },
};
- struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
+ struct mlx5_ctrl_flow_info flow_info = {
+ .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS,
};
unsigned int i;
@@ -15909,8 +15909,8 @@ __flow_hw_ctrl_flows_unicast_create(struct rte_eth_dev *dev,
{ .type = RTE_FLOW_ACTION_TYPE_RSS },
{ .type = RTE_FLOW_ACTION_TYPE_END },
};
- struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
+ struct mlx5_ctrl_flow_info flow_info = {
+ .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC,
.uc = {
.dmac = *addr,
},
@@ -15971,8 +15971,8 @@ __flow_hw_ctrl_flows_unicast_vlan_create(struct rte_eth_dev *dev,
{ .type = RTE_FLOW_ACTION_TYPE_RSS },
{ .type = RTE_FLOW_ACTION_TYPE_END },
};
- struct mlx5_hw_ctrl_flow_info flow_info = {
- .type = MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
+ struct mlx5_ctrl_flow_info flow_info = {
+ .type = MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN,
.uc = {
.dmac = *addr,
.vlan = vid,
@@ -16216,8 +16216,8 @@ mlx5_flow_hw_ctrl_flow_dmac_destroy(struct rte_eth_dev *dev,
const struct rte_ether_addr *addr)
{
struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_hw_ctrl_flow *entry;
- struct mlx5_hw_ctrl_flow *tmp;
+ struct mlx5_ctrl_flow_entry *entry;
+ struct mlx5_ctrl_flow_entry *tmp;
int ret;
/*
@@ -16229,7 +16229,7 @@ mlx5_flow_hw_ctrl_flow_dmac_destroy(struct rte_eth_dev *dev,
while (entry != NULL) {
tmp = LIST_NEXT(entry, next);
- if (entry->info.type != MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC ||
+ if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC ||
!rte_is_same_ether_addr(addr, &entry->info.uc.dmac)) {
entry = tmp;
continue;
@@ -16261,8 +16261,8 @@ mlx5_flow_hw_ctrl_flow_dmac_vlan_destroy(struct rte_eth_dev *dev,
const uint16_t vlan)
{
struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_hw_ctrl_flow *entry;
- struct mlx5_hw_ctrl_flow *tmp;
+ struct mlx5_ctrl_flow_entry *entry;
+ struct mlx5_ctrl_flow_entry *tmp;
int ret;
/*
@@ -16274,7 +16274,7 @@ mlx5_flow_hw_ctrl_flow_dmac_vlan_destroy(struct rte_eth_dev *dev,
while (entry != NULL) {
tmp = LIST_NEXT(entry, next);
- if (entry->info.type != MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN ||
+ if (entry->info.type != MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN ||
!rte_is_same_ether_addr(addr, &entry->info.uc.dmac) ||
vlan != entry->info.uc.vlan) {
entry = tmp;
--
2.39.5
next prev parent reply other threads:[~2024-10-17 7:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-17 7:57 [PATCH 00/10] net/mlx5: improve MAC address and VLAN add latency Dariusz Sosnowski
2024-10-17 7:57 ` [PATCH 01/10] net/mlx5: track unicast DMAC control flow rules Dariusz Sosnowski
2024-10-17 7:57 ` [PATCH 02/10] net/mlx5: add checking if unicast flow rule exists Dariusz Sosnowski
2024-10-17 7:57 ` [PATCH 03/10] net/mlx5: rework creation of unicast flow rules Dariusz Sosnowski
2024-10-17 7:57 ` [PATCH 04/10] net/mlx5: support destroying " Dariusz Sosnowski
2024-10-17 7:57 ` Dariusz Sosnowski [this message]
2024-10-17 7:57 ` [PATCH 06/10] net/mlx5: shared init of control " Dariusz Sosnowski
2024-10-17 7:57 ` [PATCH 07/10] net/mlx5: add legacy unicast flow rules management Dariusz Sosnowski
2024-10-17 7:57 ` [PATCH 08/10] net/mlx5: add legacy unicast flow rule registration Dariusz Sosnowski
2024-10-17 7:57 ` [PATCH 09/10] net/mlx5: add dynamic unicast flow rule management Dariusz Sosnowski
2024-10-17 7:57 ` [PATCH 10/10] net/mlx5: optimize MAC address and VLAN filter handling Dariusz Sosnowski
2024-10-17 8:01 ` [PATCH 00/10] net/mlx5: improve MAC address and VLAN add latency Slava Ovsiienko
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