From: Serhii Iliushyk <sil-plv@napatech.com>
To: dev@dpdk.org
Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com,
andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com,
Oleksandr Kolomeiets <okl-plv@napatech.com>
Subject: [PATCH v1 40/73] net/ntnic: sort FPGA registers alphanumerically
Date: Mon, 21 Oct 2024 23:04:42 +0200 [thread overview]
Message-ID: <20241021210527.2075431-41-sil-plv@napatech.com> (raw)
In-Reply-To: <20241021210527.2075431-1-sil-plv@napatech.com>
From: Oleksandr Kolomeiets <okl-plv@napatech.com>
Beatification commit. It is required for pretty supporting different FPGA
Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
.../supported/nthw_fpga_9563_055_049_0000.c | 364 +++++++++---------
1 file changed, 182 insertions(+), 182 deletions(-)
diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
index 6df7208649..e076697a92 100644
--- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
+++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c
@@ -270,6 +270,187 @@ static nthw_fpga_register_init_s cat_registers[] = {
{ CAT_RCK_DATA, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0, 32, cat_rck_data_fields },
};
+static nthw_fpga_field_init_s dbs_rx_am_ctrl_fields[] = {
+ { DBS_RX_AM_CTRL_ADR, 7, 0, 0x0000 },
+ { DBS_RX_AM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_am_data_fields[] = {
+ { DBS_RX_AM_DATA_ENABLE, 1, 72, 0x0000 }, { DBS_RX_AM_DATA_GPA, 64, 0, 0x0000 },
+ { DBS_RX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS_RX_AM_DATA_INT, 1, 74, 0x0000 },
+ { DBS_RX_AM_DATA_PCKED, 1, 73, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_control_fields[] = {
+ { DBS_RX_CONTROL_AME, 1, 7, 0 }, { DBS_RX_CONTROL_AMS, 4, 8, 8 },
+ { DBS_RX_CONTROL_LQ, 7, 0, 0 }, { DBS_RX_CONTROL_QE, 1, 17, 0 },
+ { DBS_RX_CONTROL_UWE, 1, 12, 0 }, { DBS_RX_CONTROL_UWS, 4, 13, 5 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_dr_ctrl_fields[] = {
+ { DBS_RX_DR_CTRL_ADR, 7, 0, 0x0000 },
+ { DBS_RX_DR_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_dr_data_fields[] = {
+ { DBS_RX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS_RX_DR_DATA_HDR, 1, 88, 0x0000 },
+ { DBS_RX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS_RX_DR_DATA_PCKED, 1, 87, 0x0000 },
+ { DBS_RX_DR_DATA_QS, 15, 72, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_idle_fields[] = {
+ { DBS_RX_IDLE_BUSY, 1, 8, 0 },
+ { DBS_RX_IDLE_IDLE, 1, 0, 0x0000 },
+ { DBS_RX_IDLE_QUEUE, 7, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_init_fields[] = {
+ { DBS_RX_INIT_BUSY, 1, 8, 0 },
+ { DBS_RX_INIT_INIT, 1, 0, 0x0000 },
+ { DBS_RX_INIT_QUEUE, 7, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_init_val_fields[] = {
+ { DBS_RX_INIT_VAL_IDX, 16, 0, 0x0000 },
+ { DBS_RX_INIT_VAL_PTR, 15, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_ptr_fields[] = {
+ { DBS_RX_PTR_PTR, 16, 0, 0x0000 },
+ { DBS_RX_PTR_QUEUE, 7, 16, 0x0000 },
+ { DBS_RX_PTR_VALID, 1, 23, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_uw_ctrl_fields[] = {
+ { DBS_RX_UW_CTRL_ADR, 7, 0, 0x0000 },
+ { DBS_RX_UW_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_rx_uw_data_fields[] = {
+ { DBS_RX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS_RX_UW_DATA_HID, 8, 64, 0x0000 },
+ { DBS_RX_UW_DATA_INT, 1, 88, 0x0000 }, { DBS_RX_UW_DATA_ISTK, 1, 92, 0x0000 },
+ { DBS_RX_UW_DATA_PCKED, 1, 87, 0x0000 }, { DBS_RX_UW_DATA_QS, 15, 72, 0x0000 },
+ { DBS_RX_UW_DATA_VEC, 3, 89, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_am_ctrl_fields[] = {
+ { DBS_TX_AM_CTRL_ADR, 7, 0, 0x0000 },
+ { DBS_TX_AM_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_am_data_fields[] = {
+ { DBS_TX_AM_DATA_ENABLE, 1, 72, 0x0000 }, { DBS_TX_AM_DATA_GPA, 64, 0, 0x0000 },
+ { DBS_TX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS_TX_AM_DATA_INT, 1, 74, 0x0000 },
+ { DBS_TX_AM_DATA_PCKED, 1, 73, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_control_fields[] = {
+ { DBS_TX_CONTROL_AME, 1, 7, 0 }, { DBS_TX_CONTROL_AMS, 4, 8, 5 },
+ { DBS_TX_CONTROL_LQ, 7, 0, 0 }, { DBS_TX_CONTROL_QE, 1, 17, 0 },
+ { DBS_TX_CONTROL_UWE, 1, 12, 0 }, { DBS_TX_CONTROL_UWS, 4, 13, 8 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_dr_ctrl_fields[] = {
+ { DBS_TX_DR_CTRL_ADR, 7, 0, 0x0000 },
+ { DBS_TX_DR_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_dr_data_fields[] = {
+ { DBS_TX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS_TX_DR_DATA_HDR, 1, 88, 0x0000 },
+ { DBS_TX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS_TX_DR_DATA_PCKED, 1, 87, 0x0000 },
+ { DBS_TX_DR_DATA_PORT, 1, 89, 0x0000 }, { DBS_TX_DR_DATA_QS, 15, 72, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_idle_fields[] = {
+ { DBS_TX_IDLE_BUSY, 1, 8, 0 },
+ { DBS_TX_IDLE_IDLE, 1, 0, 0x0000 },
+ { DBS_TX_IDLE_QUEUE, 7, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_init_fields[] = {
+ { DBS_TX_INIT_BUSY, 1, 8, 0 },
+ { DBS_TX_INIT_INIT, 1, 0, 0x0000 },
+ { DBS_TX_INIT_QUEUE, 7, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_init_val_fields[] = {
+ { DBS_TX_INIT_VAL_IDX, 16, 0, 0x0000 },
+ { DBS_TX_INIT_VAL_PTR, 15, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_ptr_fields[] = {
+ { DBS_TX_PTR_PTR, 16, 0, 0x0000 },
+ { DBS_TX_PTR_QUEUE, 7, 16, 0x0000 },
+ { DBS_TX_PTR_VALID, 1, 23, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_qos_ctrl_fields[] = {
+ { DBS_TX_QOS_CTRL_ADR, 1, 0, 0x0000 },
+ { DBS_TX_QOS_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_qos_data_fields[] = {
+ { DBS_TX_QOS_DATA_BS, 27, 17, 0x0000 },
+ { DBS_TX_QOS_DATA_EN, 1, 0, 0x0000 },
+ { DBS_TX_QOS_DATA_IR, 16, 1, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_qos_rate_fields[] = {
+ { DBS_TX_QOS_RATE_DIV, 19, 16, 2 },
+ { DBS_TX_QOS_RATE_MUL, 16, 0, 1 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_qp_ctrl_fields[] = {
+ { DBS_TX_QP_CTRL_ADR, 7, 0, 0x0000 },
+ { DBS_TX_QP_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_qp_data_fields[] = {
+ { DBS_TX_QP_DATA_VPORT, 1, 0, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_uw_ctrl_fields[] = {
+ { DBS_TX_UW_CTRL_ADR, 7, 0, 0x0000 },
+ { DBS_TX_UW_CTRL_CNT, 16, 16, 0x0000 },
+};
+
+static nthw_fpga_field_init_s dbs_tx_uw_data_fields[] = {
+ { DBS_TX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS_TX_UW_DATA_HID, 8, 64, 0x0000 },
+ { DBS_TX_UW_DATA_INO, 1, 93, 0x0000 }, { DBS_TX_UW_DATA_INT, 1, 88, 0x0000 },
+ { DBS_TX_UW_DATA_ISTK, 1, 92, 0x0000 }, { DBS_TX_UW_DATA_PCKED, 1, 87, 0x0000 },
+ { DBS_TX_UW_DATA_QS, 15, 72, 0x0000 }, { DBS_TX_UW_DATA_VEC, 3, 89, 0x0000 },
+};
+
+static nthw_fpga_register_init_s dbs_registers[] = {
+ { DBS_RX_AM_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_am_ctrl_fields },
+ { DBS_RX_AM_DATA, 11, 75, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_rx_am_data_fields },
+ { DBS_RX_CONTROL, 0, 18, NTHW_FPGA_REG_TYPE_RW, 43008, 6, dbs_rx_control_fields },
+ { DBS_RX_DR_CTRL, 18, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_dr_ctrl_fields },
+ { DBS_RX_DR_DATA, 19, 89, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_rx_dr_data_fields },
+ { DBS_RX_IDLE, 8, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_idle_fields },
+ { DBS_RX_INIT, 2, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_init_fields },
+ { DBS_RX_INIT_VAL, 3, 31, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_init_val_fields },
+ { DBS_RX_PTR, 4, 24, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_ptr_fields },
+ { DBS_RX_UW_CTRL, 14, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_uw_ctrl_fields },
+ { DBS_RX_UW_DATA, 15, 93, NTHW_FPGA_REG_TYPE_WO, 0, 7, dbs_rx_uw_data_fields },
+ { DBS_TX_AM_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_am_ctrl_fields },
+ { DBS_TX_AM_DATA, 13, 75, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_tx_am_data_fields },
+ { DBS_TX_CONTROL, 1, 18, NTHW_FPGA_REG_TYPE_RW, 66816, 6, dbs_tx_control_fields },
+ { DBS_TX_DR_CTRL, 20, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_dr_ctrl_fields },
+ { DBS_TX_DR_DATA, 21, 90, NTHW_FPGA_REG_TYPE_WO, 0, 6, dbs_tx_dr_data_fields },
+ { DBS_TX_IDLE, 9, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_idle_fields },
+ { DBS_TX_INIT, 5, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_init_fields },
+ { DBS_TX_INIT_VAL, 6, 31, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_init_val_fields },
+ { DBS_TX_PTR, 7, 24, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_ptr_fields },
+ { DBS_TX_QOS_CTRL, 24, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_qos_ctrl_fields },
+ { DBS_TX_QOS_DATA, 25, 44, NTHW_FPGA_REG_TYPE_WO, 0, 3, dbs_tx_qos_data_fields },
+ { DBS_TX_QOS_RATE, 26, 35, NTHW_FPGA_REG_TYPE_RW, 131073, 2, dbs_tx_qos_rate_fields },
+ { DBS_TX_QP_CTRL, 22, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_qp_ctrl_fields },
+ { DBS_TX_QP_DATA, 23, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, dbs_tx_qp_data_fields },
+ { DBS_TX_UW_CTRL, 16, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_uw_ctrl_fields },
+ { DBS_TX_UW_DATA, 17, 94, NTHW_FPGA_REG_TYPE_WO, 0, 8, dbs_tx_uw_data_fields },
+};
+
static nthw_fpga_field_init_s gfg_burstsize0_fields[] = {
{ GFG_BURSTSIZE0_VAL, 24, 0, 0 },
};
@@ -1541,192 +1722,11 @@ static nthw_fpga_register_init_s rst9563_registers[] = {
{ RST9563_STICKY, 3, 6, NTHW_FPGA_REG_TYPE_RC1, 0, 6, rst9563_sticky_fields },
};
-static nthw_fpga_field_init_s dbs_rx_am_ctrl_fields[] = {
- { DBS_RX_AM_CTRL_ADR, 7, 0, 0x0000 },
- { DBS_RX_AM_CTRL_CNT, 16, 16, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_rx_am_data_fields[] = {
- { DBS_RX_AM_DATA_ENABLE, 1, 72, 0x0000 }, { DBS_RX_AM_DATA_GPA, 64, 0, 0x0000 },
- { DBS_RX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS_RX_AM_DATA_INT, 1, 74, 0x0000 },
- { DBS_RX_AM_DATA_PCKED, 1, 73, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_rx_control_fields[] = {
- { DBS_RX_CONTROL_AME, 1, 7, 0 }, { DBS_RX_CONTROL_AMS, 4, 8, 8 },
- { DBS_RX_CONTROL_LQ, 7, 0, 0 }, { DBS_RX_CONTROL_QE, 1, 17, 0 },
- { DBS_RX_CONTROL_UWE, 1, 12, 0 }, { DBS_RX_CONTROL_UWS, 4, 13, 5 },
-};
-
-static nthw_fpga_field_init_s dbs_rx_dr_ctrl_fields[] = {
- { DBS_RX_DR_CTRL_ADR, 7, 0, 0x0000 },
- { DBS_RX_DR_CTRL_CNT, 16, 16, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_rx_dr_data_fields[] = {
- { DBS_RX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS_RX_DR_DATA_HDR, 1, 88, 0x0000 },
- { DBS_RX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS_RX_DR_DATA_PCKED, 1, 87, 0x0000 },
- { DBS_RX_DR_DATA_QS, 15, 72, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_rx_idle_fields[] = {
- { DBS_RX_IDLE_BUSY, 1, 8, 0 },
- { DBS_RX_IDLE_IDLE, 1, 0, 0x0000 },
- { DBS_RX_IDLE_QUEUE, 7, 1, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_rx_init_fields[] = {
- { DBS_RX_INIT_BUSY, 1, 8, 0 },
- { DBS_RX_INIT_INIT, 1, 0, 0x0000 },
- { DBS_RX_INIT_QUEUE, 7, 1, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_rx_init_val_fields[] = {
- { DBS_RX_INIT_VAL_IDX, 16, 0, 0x0000 },
- { DBS_RX_INIT_VAL_PTR, 15, 16, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_rx_ptr_fields[] = {
- { DBS_RX_PTR_PTR, 16, 0, 0x0000 },
- { DBS_RX_PTR_QUEUE, 7, 16, 0x0000 },
- { DBS_RX_PTR_VALID, 1, 23, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_rx_uw_ctrl_fields[] = {
- { DBS_RX_UW_CTRL_ADR, 7, 0, 0x0000 },
- { DBS_RX_UW_CTRL_CNT, 16, 16, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_rx_uw_data_fields[] = {
- { DBS_RX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS_RX_UW_DATA_HID, 8, 64, 0x0000 },
- { DBS_RX_UW_DATA_INT, 1, 88, 0x0000 }, { DBS_RX_UW_DATA_ISTK, 1, 92, 0x0000 },
- { DBS_RX_UW_DATA_PCKED, 1, 87, 0x0000 }, { DBS_RX_UW_DATA_QS, 15, 72, 0x0000 },
- { DBS_RX_UW_DATA_VEC, 3, 89, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_am_ctrl_fields[] = {
- { DBS_TX_AM_CTRL_ADR, 7, 0, 0x0000 },
- { DBS_TX_AM_CTRL_CNT, 16, 16, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_am_data_fields[] = {
- { DBS_TX_AM_DATA_ENABLE, 1, 72, 0x0000 }, { DBS_TX_AM_DATA_GPA, 64, 0, 0x0000 },
- { DBS_TX_AM_DATA_HID, 8, 64, 0x0000 }, { DBS_TX_AM_DATA_INT, 1, 74, 0x0000 },
- { DBS_TX_AM_DATA_PCKED, 1, 73, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_control_fields[] = {
- { DBS_TX_CONTROL_AME, 1, 7, 0 }, { DBS_TX_CONTROL_AMS, 4, 8, 5 },
- { DBS_TX_CONTROL_LQ, 7, 0, 0 }, { DBS_TX_CONTROL_QE, 1, 17, 0 },
- { DBS_TX_CONTROL_UWE, 1, 12, 0 }, { DBS_TX_CONTROL_UWS, 4, 13, 8 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_dr_ctrl_fields[] = {
- { DBS_TX_DR_CTRL_ADR, 7, 0, 0x0000 },
- { DBS_TX_DR_CTRL_CNT, 16, 16, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_dr_data_fields[] = {
- { DBS_TX_DR_DATA_GPA, 64, 0, 0x0000 }, { DBS_TX_DR_DATA_HDR, 1, 88, 0x0000 },
- { DBS_TX_DR_DATA_HID, 8, 64, 0x0000 }, { DBS_TX_DR_DATA_PCKED, 1, 87, 0x0000 },
- { DBS_TX_DR_DATA_PORT, 1, 89, 0x0000 }, { DBS_TX_DR_DATA_QS, 15, 72, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_idle_fields[] = {
- { DBS_TX_IDLE_BUSY, 1, 8, 0 },
- { DBS_TX_IDLE_IDLE, 1, 0, 0x0000 },
- { DBS_TX_IDLE_QUEUE, 7, 1, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_init_fields[] = {
- { DBS_TX_INIT_BUSY, 1, 8, 0 },
- { DBS_TX_INIT_INIT, 1, 0, 0x0000 },
- { DBS_TX_INIT_QUEUE, 7, 1, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_init_val_fields[] = {
- { DBS_TX_INIT_VAL_IDX, 16, 0, 0x0000 },
- { DBS_TX_INIT_VAL_PTR, 15, 16, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_ptr_fields[] = {
- { DBS_TX_PTR_PTR, 16, 0, 0x0000 },
- { DBS_TX_PTR_QUEUE, 7, 16, 0x0000 },
- { DBS_TX_PTR_VALID, 1, 23, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_qos_ctrl_fields[] = {
- { DBS_TX_QOS_CTRL_ADR, 1, 0, 0x0000 },
- { DBS_TX_QOS_CTRL_CNT, 16, 16, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_qos_data_fields[] = {
- { DBS_TX_QOS_DATA_BS, 27, 17, 0x0000 },
- { DBS_TX_QOS_DATA_EN, 1, 0, 0x0000 },
- { DBS_TX_QOS_DATA_IR, 16, 1, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_qos_rate_fields[] = {
- { DBS_TX_QOS_RATE_DIV, 19, 16, 2 },
- { DBS_TX_QOS_RATE_MUL, 16, 0, 1 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_qp_ctrl_fields[] = {
- { DBS_TX_QP_CTRL_ADR, 7, 0, 0x0000 },
- { DBS_TX_QP_CTRL_CNT, 16, 16, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_qp_data_fields[] = {
- { DBS_TX_QP_DATA_VPORT, 1, 0, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_uw_ctrl_fields[] = {
- { DBS_TX_UW_CTRL_ADR, 7, 0, 0x0000 },
- { DBS_TX_UW_CTRL_CNT, 16, 16, 0x0000 },
-};
-
-static nthw_fpga_field_init_s dbs_tx_uw_data_fields[] = {
- { DBS_TX_UW_DATA_GPA, 64, 0, 0x0000 }, { DBS_TX_UW_DATA_HID, 8, 64, 0x0000 },
- { DBS_TX_UW_DATA_INO, 1, 93, 0x0000 }, { DBS_TX_UW_DATA_INT, 1, 88, 0x0000 },
- { DBS_TX_UW_DATA_ISTK, 1, 92, 0x0000 }, { DBS_TX_UW_DATA_PCKED, 1, 87, 0x0000 },
- { DBS_TX_UW_DATA_QS, 15, 72, 0x0000 }, { DBS_TX_UW_DATA_VEC, 3, 89, 0x0000 },
-};
-
-static nthw_fpga_register_init_s dbs_registers[] = {
- { DBS_RX_AM_CTRL, 10, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_am_ctrl_fields },
- { DBS_RX_AM_DATA, 11, 75, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_rx_am_data_fields },
- { DBS_RX_CONTROL, 0, 18, NTHW_FPGA_REG_TYPE_RW, 43008, 6, dbs_rx_control_fields },
- { DBS_RX_DR_CTRL, 18, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_dr_ctrl_fields },
- { DBS_RX_DR_DATA, 19, 89, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_rx_dr_data_fields },
- { DBS_RX_IDLE, 8, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_idle_fields },
- { DBS_RX_INIT, 2, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_init_fields },
- { DBS_RX_INIT_VAL, 3, 31, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_init_val_fields },
- { DBS_RX_PTR, 4, 24, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_rx_ptr_fields },
- { DBS_RX_UW_CTRL, 14, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_rx_uw_ctrl_fields },
- { DBS_RX_UW_DATA, 15, 93, NTHW_FPGA_REG_TYPE_WO, 0, 7, dbs_rx_uw_data_fields },
- { DBS_TX_AM_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_am_ctrl_fields },
- { DBS_TX_AM_DATA, 13, 75, NTHW_FPGA_REG_TYPE_WO, 0, 5, dbs_tx_am_data_fields },
- { DBS_TX_CONTROL, 1, 18, NTHW_FPGA_REG_TYPE_RW, 66816, 6, dbs_tx_control_fields },
- { DBS_TX_DR_CTRL, 20, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_dr_ctrl_fields },
- { DBS_TX_DR_DATA, 21, 90, NTHW_FPGA_REG_TYPE_WO, 0, 6, dbs_tx_dr_data_fields },
- { DBS_TX_IDLE, 9, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_idle_fields },
- { DBS_TX_INIT, 5, 9, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_init_fields },
- { DBS_TX_INIT_VAL, 6, 31, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_init_val_fields },
- { DBS_TX_PTR, 7, 24, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, dbs_tx_ptr_fields },
- { DBS_TX_QOS_CTRL, 24, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_qos_ctrl_fields },
- { DBS_TX_QOS_DATA, 25, 44, NTHW_FPGA_REG_TYPE_WO, 0, 3, dbs_tx_qos_data_fields },
- { DBS_TX_QOS_RATE, 26, 35, NTHW_FPGA_REG_TYPE_RW, 131073, 2, dbs_tx_qos_rate_fields },
- { DBS_TX_QP_CTRL, 22, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_qp_ctrl_fields },
- { DBS_TX_QP_DATA, 23, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, dbs_tx_qp_data_fields },
- { DBS_TX_UW_CTRL, 16, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, dbs_tx_uw_ctrl_fields },
- { DBS_TX_UW_DATA, 17, 94, NTHW_FPGA_REG_TYPE_WO, 0, 8, dbs_tx_uw_data_fields },
-};
-
static nthw_fpga_module_init_s fpga_modules[] = {
{ MOD_CAT, 0, MOD_CAT, 0, 21, NTHW_FPGA_BUS_TYPE_RAB1, 768, 34, cat_registers },
+ { MOD_DBS, 0, MOD_DBS, 0, 11, NTHW_FPGA_BUS_TYPE_RAB2, 12832, 27, dbs_registers },
{ MOD_GFG, 0, MOD_GFG, 1, 1, NTHW_FPGA_BUS_TYPE_RAB2, 8704, 10, gfg_registers },
{ MOD_GMF, 0, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9216, 12, gmf_registers },
- { MOD_DBS, 0, MOD_DBS, 0, 11, NTHW_FPGA_BUS_TYPE_RAB2, 12832, 27, dbs_registers},
{ MOD_GMF, 1, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9728, 12, gmf_registers },
{
MOD_GPIO_PHY, 0, MOD_GPIO_PHY, 1, 0, NTHW_FPGA_BUS_TYPE_RAB0, 16386, 2,
--
2.45.0
next prev parent reply other threads:[~2024-10-21 21:09 UTC|newest]
Thread overview: 229+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-21 21:04 [PATCH v1 00/73] Provide flow filter API and statistics Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 01/73] net/ntnic: add API for configuration NT flow dev Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 02/73] net/ntnic: add flow filter API Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 03/73] net/ntnic: add minimal create/destroy flow operations Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 04/73] net/ntnic: add internal flow create/destroy API Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 05/73] net/ntnic: add minimal NT flow inline profile Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 06/73] net/ntnic: add management API for NT flow profile Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 07/73] net/ntnic: add NT flow profile management implementation Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 08/73] net/ntnic: add create/destroy implementation for NT flows Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 09/73] net/ntnic: add infrastructure for for flow actions and items Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 10/73] net/ntnic: add action queue Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 11/73] net/ntnic: add action mark Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 12/73] net/ntnic: add ation jump Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 13/73] net/ntnic: add action drop Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 14/73] net/ntnic: add item eth Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 15/73] net/ntnic: add item IPv4 Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 16/73] net/ntnic: add item ICMP Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 17/73] net/ntnic: add item port ID Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 18/73] net/ntnic: add item void Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 19/73] net/ntnic: add item UDP Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 20/73] net/ntnic: add action TCP Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 21/73] net/ntnic: add action VLAN Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 22/73] net/ntnic: add item SCTP Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 23/73] net/ntnic: add items IPv6 and ICMPv6 Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 24/73] net/ntnic: add action modify filed Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 25/73] net/ntnic: add items gtp and actions raw encap/decap Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 26/73] net/ntnic: add cat module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 27/73] net/ntnic: add SLC LR module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 28/73] net/ntnic: add PDB module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 29/73] net/ntnic: add QSL module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 30/73] net/ntnic: add KM module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 31/73] net/ntnic: add hash API Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 32/73] net/ntnic: add TPE module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 33/73] net/ntnic: add FLM module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 34/73] net/ntnic: add flm rcp module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 35/73] net/ntnic: add learn flow queue handling Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 36/73] net/ntnic: match and action db attributes were added Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 37/73] net/ntnic: add flow dump feature Serhii Iliushyk
2024-10-21 23:10 ` Stephen Hemminger
2024-10-21 21:04 ` [PATCH v1 38/73] net/ntnic: add flow flush Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 39/73] net/ntnic: add GMF (Generic MAC Feeder) module Serhii Iliushyk
2024-10-21 21:04 ` Serhii Iliushyk [this message]
2024-10-21 21:04 ` [PATCH v1 41/73] net/ntnic: add MOD CSU Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 42/73] net/ntnic: add MOD FLM Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 43/73] net/ntnic: add HFU module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 44/73] net/ntnic: add IFR module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 45/73] net/ntnic: add MAC Rx module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 46/73] net/ntnic: add MAC Tx module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 47/73] net/ntnic: add RPP LR module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 48/73] net/ntnic: add MOD SLC LR Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 49/73] net/ntnic: add Tx CPY module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 50/73] net/ntnic: add Tx INS module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 51/73] net/ntnic: add Tx RPL module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 52/73] net/ntnic: update alignment for virt queue structs Serhii Iliushyk
2024-10-21 23:12 ` Stephen Hemminger
2024-10-21 21:04 ` [PATCH v1 53/73] net/ntnic: enable RSS feature Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 54/73] net/ntnic: add statistics API Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 55/73] net/ntnic: add rpf module Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 56/73] net/ntnic: add statistics poll Serhii Iliushyk
2024-10-21 21:04 ` [PATCH v1 57/73] net/ntnic: added flm stat interface Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 58/73] net/ntnic: add tsm module Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 59/73] net/ntnic: add STA module Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 60/73] net/ntnic: add TSM module Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 61/73] net/ntnic: add xstats Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 62/73] net/ntnic: added flow statistics Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 63/73] net/ntnic: add scrub registers Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 64/73] net/ntnic: update documentation Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 65/73] net/ntnic: added flow aged APIs Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 66/73] net/ntnic: add aged API to the inline profile Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 67/73] net/ntnic: add info and configure flow API Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 68/73] net/ntnic: add aged flow event Serhii Iliushyk
2024-10-21 23:22 ` Stephen Hemminger
2024-10-21 21:05 ` [PATCH v1 69/73] net/ntnic: add thread termination Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 70/73] net/ntnic: add age documentation Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 71/73] net/ntnic: add meter API Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 72/73] net/ntnic: add meter module Serhii Iliushyk
2024-10-21 21:05 ` [PATCH v1 73/73] net/ntnic: add meter documentation Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 00/73] Provide flow filter API and statistics Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 01/73] net/ntnic: add API for configuration NT flow dev Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 02/73] net/ntnic: add flow filter API Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 03/73] net/ntnic: add minimal create/destroy flow operations Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 04/73] net/ntnic: add internal flow create/destroy API Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 05/73] net/ntnic: add minimal NT flow inline profile Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 06/73] net/ntnic: add management API for NT flow profile Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 07/73] net/ntnic: add NT flow profile management implementation Serhii Iliushyk
2024-10-22 17:17 ` Stephen Hemminger
2024-10-22 16:54 ` [PATCH v2 08/73] net/ntnic: add create/destroy implementation for NT flows Serhii Iliushyk
2024-10-22 17:20 ` Stephen Hemminger
2024-10-23 16:09 ` Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 09/73] net/ntnic: add infrastructure for for flow actions and items Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 10/73] net/ntnic: add action queue Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 11/73] net/ntnic: add action mark Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 12/73] net/ntnic: add ation jump Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 13/73] net/ntnic: add action drop Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 14/73] net/ntnic: add item eth Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 15/73] net/ntnic: add item IPv4 Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 16/73] net/ntnic: add item ICMP Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 17/73] net/ntnic: add item port ID Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 18/73] net/ntnic: add item void Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 19/73] net/ntnic: add item UDP Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 20/73] net/ntnic: add action TCP Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 21/73] net/ntnic: add action VLAN Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 22/73] net/ntnic: add item SCTP Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 23/73] net/ntnic: add items IPv6 and ICMPv6 Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 24/73] net/ntnic: add action modify filed Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 25/73] net/ntnic: add items gtp and actions raw encap/decap Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 26/73] net/ntnic: add cat module Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 27/73] net/ntnic: add SLC LR module Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 28/73] net/ntnic: add PDB module Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 29/73] net/ntnic: add QSL module Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 30/73] net/ntnic: add KM module Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 31/73] net/ntnic: add hash API Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 32/73] net/ntnic: add TPE module Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 33/73] net/ntnic: add FLM module Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 34/73] net/ntnic: add flm rcp module Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 35/73] net/ntnic: add learn flow queue handling Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 36/73] net/ntnic: match and action db attributes were added Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 37/73] net/ntnic: add flow dump feature Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 38/73] net/ntnic: add flow flush Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 39/73] net/ntnic: add GMF (Generic MAC Feeder) module Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 40/73] net/ntnic: sort FPGA registers alphanumerically Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 41/73] net/ntnic: add MOD CSU Serhii Iliushyk
2024-10-22 16:54 ` [PATCH v2 42/73] net/ntnic: add MOD FLM Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 43/73] net/ntnic: add HFU module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 44/73] net/ntnic: add IFR module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 45/73] net/ntnic: add MAC Rx module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 46/73] net/ntnic: add MAC Tx module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 47/73] net/ntnic: add RPP LR module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 48/73] net/ntnic: add MOD SLC LR Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 49/73] net/ntnic: add Tx CPY module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 50/73] net/ntnic: add Tx INS module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 51/73] net/ntnic: add Tx RPL module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 52/73] net/ntnic: update alignment for virt queue structs Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 53/73] net/ntnic: enable RSS feature Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 54/73] net/ntnic: add statistics API Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 55/73] net/ntnic: add rpf module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 56/73] net/ntnic: add statistics poll Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 57/73] net/ntnic: added flm stat interface Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 58/73] net/ntnic: add tsm module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 59/73] net/ntnic: add STA module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 60/73] net/ntnic: add TSM module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 61/73] net/ntnic: add xstats Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 62/73] net/ntnic: added flow statistics Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 63/73] net/ntnic: add scrub registers Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 64/73] net/ntnic: update documentation Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 65/73] net/ntnic: added flow aged APIs Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 66/73] net/ntnic: add aged API to the inline profile Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 67/73] net/ntnic: add info and configure flow API Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 68/73] net/ntnic: add aged flow event Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 69/73] net/ntnic: add thread termination Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 70/73] net/ntnic: add age documentation Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 71/73] net/ntnic: add meter API Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 72/73] net/ntnic: add meter module Serhii Iliushyk
2024-10-22 16:55 ` [PATCH v2 73/73] net/ntnic: add meter documentation Serhii Iliushyk
2024-10-22 17:11 ` [PATCH v2 00/73] Provide flow filter API and statistics Stephen Hemminger
2024-10-23 16:59 ` [PATCH v3 " Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 01/73] net/ntnic: add API for configuration NT flow dev Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 02/73] net/ntnic: add flow filter API Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 03/73] net/ntnic: add minimal create/destroy flow operations Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 04/73] net/ntnic: add internal flow create/destroy API Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 05/73] net/ntnic: add minimal NT flow inline profile Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 06/73] net/ntnic: add management API for NT flow profile Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 07/73] net/ntnic: add NT flow profile management implementation Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 08/73] net/ntnic: add create/destroy implementation for NT flows Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 09/73] net/ntnic: add infrastructure for for flow actions and items Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 10/73] net/ntnic: add action queue Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 11/73] net/ntnic: add action mark Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 12/73] net/ntnic: add ation jump Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 13/73] net/ntnic: add action drop Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 14/73] net/ntnic: add item eth Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 15/73] net/ntnic: add item IPv4 Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 16/73] net/ntnic: add item ICMP Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 17/73] net/ntnic: add item port ID Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 18/73] net/ntnic: add item void Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 19/73] net/ntnic: add item UDP Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 20/73] net/ntnic: add action TCP Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 21/73] net/ntnic: add action VLAN Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 22/73] net/ntnic: add item SCTP Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 23/73] net/ntnic: add items IPv6 and ICMPv6 Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 24/73] net/ntnic: add action modify filed Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 25/73] net/ntnic: add items gtp and actions raw encap/decap Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 26/73] net/ntnic: add cat module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 27/73] net/ntnic: add SLC LR module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 28/73] net/ntnic: add PDB module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 29/73] net/ntnic: add QSL module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 30/73] net/ntnic: add KM module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 31/73] net/ntnic: add hash API Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 32/73] net/ntnic: add TPE module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 33/73] net/ntnic: add FLM module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 34/73] net/ntnic: add flm rcp module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 35/73] net/ntnic: add learn flow queue handling Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 36/73] net/ntnic: match and action db attributes were added Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 37/73] net/ntnic: add flow dump feature Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 38/73] net/ntnic: add flow flush Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 39/73] net/ntnic: add GMF (Generic MAC Feeder) module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 40/73] net/ntnic: sort FPGA registers alphanumerically Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 41/73] net/ntnic: add MOD CSU Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 42/73] net/ntnic: add MOD FLM Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 43/73] net/ntnic: add HFU module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 44/73] net/ntnic: add IFR module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 45/73] net/ntnic: add MAC Rx module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 46/73] net/ntnic: add MAC Tx module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 47/73] net/ntnic: add RPP LR module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 48/73] net/ntnic: add MOD SLC LR Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 49/73] net/ntnic: add Tx CPY module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 50/73] net/ntnic: add Tx INS module Serhii Iliushyk
2024-10-23 16:59 ` [PATCH v3 51/73] net/ntnic: add Tx RPL module Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 52/73] net/ntnic: update alignment for virt queue structs Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 53/73] net/ntnic: enable RSS feature Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 54/73] net/ntnic: add statistics API Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 55/73] net/ntnic: add rpf module Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 56/73] net/ntnic: add statistics poll Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 57/73] net/ntnic: added flm stat interface Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 58/73] net/ntnic: add tsm module Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 59/73] net/ntnic: add STA module Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 60/73] net/ntnic: add TSM module Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 61/73] net/ntnic: add xstats Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 62/73] net/ntnic: added flow statistics Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 63/73] net/ntnic: add scrub registers Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 64/73] net/ntnic: update documentation Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 65/73] net/ntnic: add flow aging API Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 66/73] net/ntnic: add aging API to the inline profile Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 67/73] net/ntnic: add flow info and flow configure APIs Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 68/73] net/ntnic: add flow aging event Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 69/73] net/ntnic: add termination thread Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 70/73] net/ntnic: add aging documentation Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 71/73] net/ntnic: add meter API Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 72/73] net/ntnic: add meter module Serhii Iliushyk
2024-10-23 17:00 ` [PATCH v3 73/73] net/ntnic: update meter documentation Serhii Iliushyk
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241021210527.2075431-41-sil-plv@napatech.com \
--to=sil-plv@napatech.com \
--cc=andrew.rybchenko@oktetlabs.ru \
--cc=ckm@napatech.com \
--cc=dev@dpdk.org \
--cc=ferruh.yigit@amd.com \
--cc=mko-plv@napatech.com \
--cc=okl-plv@napatech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).