From: <pbhagavatula@marvell.com>
To: <jerinj@marvell.com>, <stephen@networkplumber.org>,
<mattias.ronnblom@ericsson.com>,
Pavan Nikhilesh <pbhagavatula@marvell.com>,
Shijith Thotton <sthotton@marvell.com>
Cc: <dev@dpdk.org>
Subject: [PATCH v3 12/22] event/cnxk: add CN20K device start
Date: Tue, 22 Oct 2024 14:16:30 +0530 [thread overview]
Message-ID: <20241022084641.14497-12-pbhagavatula@marvell.com> (raw)
In-Reply-To: <20241022084641.14497-1-pbhagavatula@marvell.com>
From: Pavan Nikhilesh <pbhagavatula@marvell.com>
Add CN20K start function along with few cleanup API's to maintain
sanity.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
drivers/event/cnxk/cn10k_eventdev.c | 103 +--------------------------
drivers/event/cnxk/cn20k_eventdev.c | 76 ++++++++++++++++++++
drivers/event/cnxk/cnxk_common.h | 104 ++++++++++++++++++++++++++++
3 files changed, 183 insertions(+), 100 deletions(-)
diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c
index 82d973a420..087560f43f 100644
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -153,83 +153,6 @@ cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
return 0;
}
-static void
-cn10k_sso_hws_reset(void *arg, void *hws)
-{
- struct cnxk_sso_evdev *dev = arg;
- struct cn10k_sso_hws *ws = hws;
- uintptr_t base = ws->base;
- uint64_t pend_state;
- union {
- __uint128_t wdata;
- uint64_t u64[2];
- } gw;
- uint8_t pend_tt;
- bool is_pend;
-
- roc_sso_hws_gwc_invalidate(&dev->sso, &ws->hws_id, 1);
- plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
- /* Wait till getwork/swtp/waitw/desched completes. */
- is_pend = false;
- /* Work in WQE0 is always consumed, unless its a SWTAG. */
- pend_state = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
- if (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) ||
- ws->swtag_req)
- is_pend = true;
-
- do {
- pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
- } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
- BIT_ULL(56) | BIT_ULL(54)));
- pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
- if (is_pend && pend_tt != SSO_TT_EMPTY) { /* Work was pending */
- if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
- cnxk_sso_hws_swtag_untag(base +
- SSOW_LF_GWS_OP_SWTAG_UNTAG);
- plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
- } else if (pend_tt != SSO_TT_EMPTY) {
- plt_write64(0, base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
- }
-
- /* Wait for desched to complete. */
- do {
- pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
- } while (pend_state & (BIT_ULL(58) | BIT_ULL(56)));
-
- switch (dev->gw_mode) {
- case CNXK_GW_MODE_PREF:
- case CNXK_GW_MODE_PREF_WFE:
- while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
- ;
- break;
- case CNXK_GW_MODE_NONE:
- default:
- break;
- }
-
- if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
- SSO_TT_EMPTY) {
- plt_write64(BIT_ULL(16) | 1,
- ws->base + SSOW_LF_GWS_OP_GET_WORK0);
- do {
- roc_load_pair(gw.u64[0], gw.u64[1],
- ws->base + SSOW_LF_GWS_WQE0);
- } while (gw.u64[0] & BIT_ULL(63));
- pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
- if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
- if (pend_tt == SSO_TT_ATOMIC ||
- pend_tt == SSO_TT_ORDERED)
- cnxk_sso_hws_swtag_untag(
- base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
- plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
- }
- }
-
- plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
- roc_sso_hws_gwc_invalidate(&dev->sso, &ws->hws_id, 1);
- rte_mb();
-}
-
static void
cn10k_sso_set_rsrc(void *arg)
{
@@ -707,24 +630,6 @@ cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, uint8_t queues
return cn10k_sso_port_unlink_profile(event_dev, port, queues, nb_unlinks, 0);
}
-static void
-cn10k_sso_configure_queue_stash(struct rte_eventdev *event_dev)
-{
- struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
- struct roc_sso_hwgrp_stash stash[dev->stash_cnt];
- int i, rc;
-
- plt_sso_dbg();
- for (i = 0; i < dev->stash_cnt; i++) {
- stash[i].hwgrp = dev->stash_parse_data[i].queue;
- stash[i].stash_offset = dev->stash_parse_data[i].stash_offset;
- stash[i].stash_count = dev->stash_parse_data[i].stash_length;
- }
- rc = roc_sso_hwgrp_stash_config(&dev->sso, stash, dev->stash_cnt);
- if (rc < 0)
- plt_warn("failed to configure HWGRP WQE stashing rc = %d", rc);
-}
-
static int
cn10k_sso_start(struct rte_eventdev *event_dev)
{
@@ -736,9 +641,8 @@ cn10k_sso_start(struct rte_eventdev *event_dev)
if (rc < 0)
return rc;
- cn10k_sso_configure_queue_stash(event_dev);
- rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
- cn10k_sso_hws_flush_events);
+ cnxk_sso_configure_queue_stash(event_dev);
+ rc = cnxk_sso_start(event_dev, cnxk_sso_hws_reset, cn10k_sso_hws_flush_events);
if (rc < 0)
return rc;
cn10k_sso_fp_fns_set(event_dev);
@@ -759,8 +663,7 @@ cn10k_sso_stop(struct rte_eventdev *event_dev)
for (i = 0; i < event_dev->data->nb_ports; i++)
hws[i] = i;
roc_sso_hws_gwc_invalidate(&dev->sso, hws, event_dev->data->nb_ports);
- cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
- cn10k_sso_hws_flush_events);
+ cnxk_sso_stop(event_dev, cnxk_sso_hws_reset, cn10k_sso_hws_flush_events);
}
static int
diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c
index 34636c77ce..90902bce40 100644
--- a/drivers/event/cnxk/cn20k_eventdev.c
+++ b/drivers/event/cnxk/cn20k_eventdev.c
@@ -86,6 +86,61 @@ cn20k_sso_hws_release(void *arg, void *hws)
memset(ws, 0, sizeof(*ws));
}
+static int
+cn20k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base, cnxk_handle_event_t fn,
+ void *arg)
+{
+ struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(arg);
+ uint64_t retry = CNXK_SSO_FLUSH_RETRY_MAX;
+ struct cn20k_sso_hws *ws = hws;
+ uint64_t cq_ds_cnt = 1;
+ uint64_t aq_cnt = 1;
+ uint64_t ds_cnt = 1;
+ struct rte_event ev;
+ uint64_t val, req;
+
+ plt_write64(0, base + SSO_LF_GGRP_QCTL);
+
+ roc_sso_hws_gwc_invalidate(&dev->sso, &ws->hws_id, 1);
+ plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
+ req = queue_id; /* GGRP ID */
+ req |= BIT_ULL(18); /* Grouped */
+ req |= BIT_ULL(16); /* WAIT */
+
+ aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
+ ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
+ cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
+ cq_ds_cnt &= 0x3FFF3FFF0000;
+
+ while (aq_cnt || cq_ds_cnt || ds_cnt) {
+ plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
+ cn20k_sso_hws_get_work_empty(ws, &ev, 0);
+ if (fn != NULL && ev.u64 != 0)
+ fn(arg, ev);
+ if (ev.sched_type != SSO_TT_EMPTY)
+ cnxk_sso_hws_swtag_flush(ws->base);
+ else if (retry-- == 0)
+ break;
+ do {
+ val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
+ } while (val & BIT_ULL(56));
+ aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
+ ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
+ cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
+ /* Extract cq and ds count */
+ cq_ds_cnt &= 0x3FFF3FFF0000;
+ }
+
+ if (aq_cnt || cq_ds_cnt || ds_cnt)
+ return -EAGAIN;
+
+ plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
+ roc_sso_hws_gwc_invalidate(&dev->sso, &ws->hws_id, 1);
+ rte_mb();
+
+ return 0;
+}
+
static void
cn20k_sso_set_rsrc(void *arg)
{
@@ -314,6 +369,25 @@ cn20k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, uint8_t queues
return cn20k_sso_port_unlink_profile(event_dev, port, queues, nb_unlinks, 0);
}
+static int
+cn20k_sso_start(struct rte_eventdev *event_dev)
+{
+ struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+ uint8_t hws[RTE_EVENT_MAX_PORTS_PER_DEV];
+ int rc, i;
+
+ cnxk_sso_configure_queue_stash(event_dev);
+ rc = cnxk_sso_start(event_dev, cnxk_sso_hws_reset, cn20k_sso_hws_flush_events);
+ if (rc < 0)
+ return rc;
+ cn20k_sso_fp_fns_set(event_dev);
+ for (i = 0; i < event_dev->data->nb_ports; i++)
+ hws[i] = i;
+ roc_sso_hws_gwc_invalidate(&dev->sso, hws, event_dev->data->nb_ports);
+
+ return rc;
+}
+
static struct eventdev_ops cn20k_sso_dev_ops = {
.dev_infos_get = cn20k_sso_info_get,
.dev_configure = cn20k_sso_dev_configure,
@@ -332,6 +406,8 @@ static struct eventdev_ops cn20k_sso_dev_ops = {
.port_link_profile = cn20k_sso_port_link_profile,
.port_unlink_profile = cn20k_sso_port_unlink_profile,
.timeout_ticks = cnxk_sso_timeout_ticks,
+
+ .dev_start = cn20k_sso_start,
};
static int
diff --git a/drivers/event/cnxk/cnxk_common.h b/drivers/event/cnxk/cnxk_common.h
index 712d82bee7..c361d0530d 100644
--- a/drivers/event/cnxk/cnxk_common.h
+++ b/drivers/event/cnxk/cnxk_common.h
@@ -8,6 +8,15 @@
#include "cnxk_eventdev.h"
#include "cnxk_worker.h"
+struct cnxk_sso_hws_prf {
+ uint64_t base;
+ uint32_t gw_wdata;
+ void *lookup_mem;
+ uint64_t gw_rdata;
+ uint8_t swtag_req;
+ uint8_t hws_id;
+};
+
static uint32_t
cnxk_sso_hws_prf_wdata(struct cnxk_sso_evdev *dev)
{
@@ -52,4 +61,99 @@ cnxk_sso_hws_preschedule_get(uint8_t preschedule_type)
return gw_mode;
}
+static void
+cnxk_sso_hws_reset(void *arg, void *ws)
+{
+ struct cnxk_sso_evdev *dev = arg;
+ struct cnxk_sso_hws_prf *ws_prf;
+ uint64_t pend_state;
+ uint8_t swtag_req;
+ uintptr_t base;
+ uint8_t hws_id;
+ union {
+ __uint128_t wdata;
+ uint64_t u64[2];
+ } gw;
+ uint8_t pend_tt;
+ bool is_pend;
+
+ ws_prf = ws;
+ base = ws_prf->base;
+ hws_id = ws_prf->hws_id;
+ swtag_req = ws_prf->swtag_req;
+
+ roc_sso_hws_gwc_invalidate(&dev->sso, &hws_id, 1);
+ plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
+ /* Wait till getwork/swtp/waitw/desched completes. */
+ is_pend = false;
+ /* Work in WQE0 is always consumed, unless its a SWTAG. */
+ pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
+ if (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(54)) || swtag_req)
+ is_pend = true;
+
+ do {
+ pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
+ } while (pend_state &
+ (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) | BIT_ULL(56) | BIT_ULL(54)));
+ pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
+ if (is_pend && pend_tt != SSO_TT_EMPTY) { /* Work was pending */
+ if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
+ cnxk_sso_hws_swtag_untag(base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
+ plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
+ } else if (pend_tt != SSO_TT_EMPTY) {
+ plt_write64(0, base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
+ }
+
+ /* Wait for desched to complete. */
+ do {
+ pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
+ } while (pend_state & (BIT_ULL(58) | BIT_ULL(56)));
+
+ switch (dev->gw_mode) {
+ case CNXK_GW_MODE_PREF:
+ case CNXK_GW_MODE_PREF_WFE:
+ while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
+ ;
+ break;
+ case CNXK_GW_MODE_NONE:
+ default:
+ break;
+ }
+
+ if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) != SSO_TT_EMPTY) {
+ plt_write64(BIT_ULL(16) | 1, base + SSOW_LF_GWS_OP_GET_WORK0);
+ do {
+ roc_load_pair(gw.u64[0], gw.u64[1], base + SSOW_LF_GWS_WQE0);
+ } while (gw.u64[0] & BIT_ULL(63));
+ pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
+ if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
+ if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
+ cnxk_sso_hws_swtag_untag(base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
+ plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
+ }
+ }
+
+ plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
+ roc_sso_hws_gwc_invalidate(&dev->sso, &hws_id, 1);
+ rte_mb();
+}
+
+static void
+cnxk_sso_configure_queue_stash(struct rte_eventdev *event_dev)
+{
+ struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
+ struct roc_sso_hwgrp_stash stash[dev->stash_cnt];
+ int i, rc;
+
+ plt_sso_dbg();
+ for (i = 0; i < dev->stash_cnt; i++) {
+ stash[i].hwgrp = dev->stash_parse_data[i].queue;
+ stash[i].stash_offset = dev->stash_parse_data[i].stash_offset;
+ stash[i].stash_count = dev->stash_parse_data[i].stash_length;
+ }
+ rc = roc_sso_hwgrp_stash_config(&dev->sso, stash, dev->stash_cnt);
+ if (rc < 0)
+ plt_warn("failed to configure HWGRP WQE stashing rc = %d", rc);
+}
+
#endif /* __CNXK_COMMON_H__ */
--
2.25.1
next prev parent reply other threads:[~2024-10-22 9:19 UTC|newest]
Thread overview: 91+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-03 13:22 [PATCH 01/20] common/cnxk: implement SSO HW info pbhagavatula
2024-10-03 13:22 ` [PATCH 02/20] event/cnxk: add CN20K specific device probe pbhagavatula
2024-10-15 16:17 ` Stephen Hemminger
2024-10-03 13:22 ` [PATCH 03/20] event/cnxk: add CN20K device config pbhagavatula
2024-10-03 13:22 ` [PATCH 04/20] event/cnxk: add CN20k event queue config pbhagavatula
2024-10-03 13:22 ` [PATCH 05/20] event/cnxk: add CN20K event port configuration pbhagavatula
2024-10-03 13:22 ` [PATCH 06/20] event/cnxk: add CN20K SSO enqueue fast path pbhagavatula
2024-10-22 1:46 ` Stephen Hemminger
2024-10-03 13:22 ` [PATCH 07/20] event/cnxk: add CN20K SSO dequeue " pbhagavatula
2024-10-22 1:49 ` Stephen Hemminger
2024-10-22 8:54 ` [EXTERNAL] " Pavan Nikhilesh Bhagavatula
2024-10-03 13:22 ` [PATCH 08/20] event/cnxk: add CN20K event port quiesce pbhagavatula
2024-10-03 13:22 ` [PATCH 09/20] event/cnxk: add CN20K event port profile switch pbhagavatula
2024-10-03 13:22 ` [PATCH 10/20] event/cnxk: add CN20K device start pbhagavatula
2024-10-03 13:22 ` [PATCH 11/20] event/cnxk: add CN20K device stop and close pbhagavatula
2024-10-03 13:22 ` [PATCH 12/20] event/cnxk: add CN20K xstats, selftest and dump pbhagavatula
2024-10-03 13:22 ` [PATCH 13/20] event/cnxk: support CN20K Rx adapter pbhagavatula
2024-10-03 13:22 ` [PATCH 14/20] event/cnxk: support CN20K Rx adapter fast path pbhagavatula
2024-10-03 13:22 ` [PATCH 15/20] event/cnxk: support CN20K Tx adapter pbhagavatula
2024-10-03 13:22 ` [PATCH 16/20] event/cnxk: support CN20K Tx adapter fast path pbhagavatula
2024-10-03 13:22 ` [PATCH 17/20] common/cnxk: add SSO event aggregator pbhagavatula
2024-10-03 13:22 ` [PATCH 18/20] event/cnxk: add Rx/Tx event vector support pbhagavatula
2024-10-03 13:22 ` [PATCH 19/20] common/cnxk: update timer base code pbhagavatula
2024-10-03 13:22 ` [PATCH 20/20] event/cnxk: add CN20K timer adapter pbhagavatula
2024-10-21 20:57 ` [PATCH v2 01/21] common/cnxk: implement SSO HW info pbhagavatula
2024-10-21 20:57 ` [PATCH v2 02/21] event/cnxk: add CN20K specific device probe pbhagavatula
2024-10-21 20:57 ` [PATCH v2 03/21] event/cnxk: add CN20K device config pbhagavatula
2024-10-21 20:57 ` [PATCH v2 04/21] event/cnxk: add CN20k event queue configuration pbhagavatula
2024-10-21 20:57 ` [PATCH v2 05/21] event/cnxk: add CN20K event port configuration pbhagavatula
2024-10-21 20:57 ` [PATCH v2 06/21] event/cnxk: add CN20K SSO enqueue fast path pbhagavatula
2024-10-21 20:57 ` [PATCH v2 07/21] event/cnxk: add CN20K SSO dequeue " pbhagavatula
2024-10-21 20:57 ` [PATCH v2 08/21] event/cnxk: add CN20K event port quiesce pbhagavatula
2024-10-21 20:57 ` [PATCH v2 09/21] event/cnxk: add CN20K event port profile switch pbhagavatula
2024-10-21 20:57 ` [PATCH v2 10/21] event/cnxk: add CN20K event port preschedule pbhagavatula
2024-10-21 20:57 ` [PATCH v2 11/21] event/cnxk: add CN20K device start pbhagavatula
2024-10-21 20:57 ` [PATCH v2 12/21] event/cnxk: add CN20K device stop and close pbhagavatula
2024-10-21 20:57 ` [PATCH v2 13/21] event/cnxk: add CN20K xstats, selftest and dump pbhagavatula
2024-10-21 20:57 ` [PATCH v2 14/21] event/cnxk: support CN20K Rx adapter pbhagavatula
2024-10-21 20:57 ` [PATCH v2 15/21] event/cnxk: support CN20K Rx adapter fast path pbhagavatula
2024-10-21 20:57 ` [PATCH v2 16/21] event/cnxk: support CN20K Tx adapter pbhagavatula
2024-10-21 20:57 ` [PATCH v2 17/21] event/cnxk: support CN20K Tx adapter fast path pbhagavatula
2024-10-21 20:57 ` [PATCH v2 18/21] common/cnxk: add SSO event aggregator pbhagavatula
2024-10-21 20:57 ` [PATCH v2 19/21] event/cnxk: add Rx/Tx event vector support pbhagavatula
2024-10-21 20:57 ` [PATCH v2 20/21] common/cnxk: update timer base code pbhagavatula
2024-10-21 20:57 ` [PATCH v2 21/21] event/cnxk: add CN20K timer adapter pbhagavatula
2024-10-22 8:46 ` [PATCH v3 01/22] event/cnxk: use stdatomic API pbhagavatula
2024-10-22 8:46 ` [PATCH v3 02/22] common/cnxk: implement SSO HW info pbhagavatula
2024-10-22 8:46 ` [PATCH v3 03/22] event/cnxk: add CN20K specific device probe pbhagavatula
2024-10-22 8:46 ` [PATCH v3 04/22] event/cnxk: add CN20K device config pbhagavatula
2024-10-22 8:46 ` [PATCH v3 05/22] event/cnxk: add CN20k event queue configuration pbhagavatula
2024-10-22 8:46 ` [PATCH v3 06/22] event/cnxk: add CN20K event port configuration pbhagavatula
2024-10-22 8:46 ` [PATCH v3 07/22] event/cnxk: add CN20K SSO enqueue fast path pbhagavatula
2024-10-22 8:46 ` [PATCH v3 08/22] event/cnxk: add CN20K SSO dequeue " pbhagavatula
2024-10-22 8:46 ` [PATCH v3 09/22] event/cnxk: add CN20K event port quiesce pbhagavatula
2024-10-22 8:46 ` [PATCH v3 10/22] event/cnxk: add CN20K event port profile switch pbhagavatula
2024-10-22 8:46 ` [PATCH v3 11/22] event/cnxk: add CN20K event port preschedule pbhagavatula
2024-10-22 8:46 ` pbhagavatula [this message]
2024-10-22 8:46 ` [PATCH v3 13/22] event/cnxk: add CN20K device stop and close pbhagavatula
2024-10-22 8:46 ` [PATCH v3 14/22] event/cnxk: add CN20K xstats, selftest and dump pbhagavatula
2024-10-22 8:46 ` [PATCH v3 15/22] event/cnxk: support CN20K Rx adapter pbhagavatula
2024-10-22 8:46 ` [PATCH v3 16/22] event/cnxk: support CN20K Rx adapter fast path pbhagavatula
2024-10-22 8:46 ` [PATCH v3 17/22] event/cnxk: support CN20K Tx adapter pbhagavatula
2024-10-22 8:46 ` [PATCH v3 18/22] event/cnxk: support CN20K Tx adapter fast path pbhagavatula
2024-10-22 8:46 ` [PATCH v3 19/22] common/cnxk: add SSO event aggregator pbhagavatula
2024-10-22 8:46 ` [PATCH v3 20/22] event/cnxk: add Rx/Tx event vector support pbhagavatula
2024-10-22 8:46 ` [PATCH v3 21/22] common/cnxk: update timer base code pbhagavatula
2024-10-22 8:46 ` [PATCH v3 22/22] event/cnxk: add CN20K timer adapter pbhagavatula
2024-10-22 19:34 ` [PATCH v4 01/22] event/cnxk: use stdatomic API pbhagavatula
2024-10-22 19:34 ` [PATCH v4 02/22] common/cnxk: implement SSO HW info pbhagavatula
2024-10-22 19:34 ` [PATCH v4 03/22] event/cnxk: add CN20K specific device probe pbhagavatula
2024-10-22 19:34 ` [PATCH v4 04/22] event/cnxk: add CN20K device config pbhagavatula
2024-10-22 19:34 ` [PATCH v4 05/22] event/cnxk: add CN20k event queue configuration pbhagavatula
2024-10-22 19:34 ` [PATCH v4 06/22] event/cnxk: add CN20K event port configuration pbhagavatula
2024-10-22 19:34 ` [PATCH v4 07/22] event/cnxk: add CN20K SSO enqueue fast path pbhagavatula
2024-10-22 19:34 ` [PATCH v4 08/22] event/cnxk: add CN20K SSO dequeue " pbhagavatula
2024-10-22 19:34 ` [PATCH v4 09/22] event/cnxk: add CN20K event port quiesce pbhagavatula
2024-10-22 19:34 ` [PATCH v4 10/22] event/cnxk: add CN20K event port profile switch pbhagavatula
2024-10-22 19:34 ` [PATCH v4 11/22] event/cnxk: add CN20K event port preschedule pbhagavatula
2024-10-22 19:34 ` [PATCH v4 12/22] event/cnxk: add CN20K device start pbhagavatula
2024-10-22 19:34 ` [PATCH v4 13/22] event/cnxk: add CN20K device stop and close pbhagavatula
2024-10-22 19:34 ` [PATCH v4 14/22] event/cnxk: add CN20K xstats, selftest and dump pbhagavatula
2024-10-22 19:34 ` [PATCH v4 15/22] event/cnxk: support CN20K Rx adapter pbhagavatula
2024-10-22 19:34 ` [PATCH v4 16/22] event/cnxk: support CN20K Rx adapter fast path pbhagavatula
2024-10-22 19:35 ` [PATCH v4 17/22] event/cnxk: support CN20K Tx adapter pbhagavatula
2024-10-22 19:35 ` [PATCH v4 18/22] event/cnxk: support CN20K Tx adapter fast path pbhagavatula
2024-10-22 19:35 ` [PATCH v4 19/22] common/cnxk: add SSO event aggregator pbhagavatula
2024-10-22 19:35 ` [PATCH v4 20/22] event/cnxk: add Rx/Tx event vector support pbhagavatula
2024-10-22 19:35 ` [PATCH v4 21/22] common/cnxk: update timer base code pbhagavatula
2024-10-22 19:35 ` [PATCH v4 22/22] event/cnxk: add CN20K timer adapter pbhagavatula
2024-10-22 1:52 ` [PATCH 01/20] common/cnxk: implement SSO HW info Stephen Hemminger
2024-10-22 8:53 ` [EXTERNAL] " Pavan Nikhilesh Bhagavatula
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241022084641.14497-12-pbhagavatula@marvell.com \
--to=pbhagavatula@marvell.com \
--cc=dev@dpdk.org \
--cc=jerinj@marvell.com \
--cc=mattias.ronnblom@ericsson.com \
--cc=stephen@networkplumber.org \
--cc=sthotton@marvell.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).