From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E14E245B9E; Tue, 22 Oct 2024 11:18:54 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 53D1140A6B; Tue, 22 Oct 2024 11:18:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 2EF0240611 for ; Tue, 22 Oct 2024 11:17:51 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49M8PRKX017624; Tue, 22 Oct 2024 02:17:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=5 13BZzBj2LaLUJe4ZlUtydX+/Ry2FAkvm8CTGLx2d+o=; b=WttTGXRohDsyta+UX m9ooA6qTy2j3P2c9rLw0rYkPYtouZgdwC5JrHY3FXJqe1zU3sa0k9JZBPog0XA6V s/QboUqRP+LgRmRV8fHT90htn2f5AwhNFPds3HBSGO6tl31YuImDU0TfIMIQcIsQ dhPCeKVKMUGQkEb5Q3Hkv3Bl/enK5Zd6xc1s6BuAShwelfCTOry7UaJPrPvKcWC/ 3QBmDkRnPhsvQXszz8dCL4Crcd0BnT5EiqrZR90MMD2evDPhYFgg12D3w1aY6199 6DA2VCblKJ3r+UWroPuz0S6SQgPYMXbZBbRLUzlJQs7mvieyZVXZ4QHQPEcRAlBr 74gxQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42e8hag3k2-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Oct 2024 02:17:50 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 22 Oct 2024 02:17:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 22 Oct 2024 02:17:48 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 60F105E6A08; Tue, 22 Oct 2024 01:46:59 -0700 (PDT) From: To: , , , Pavan Nikhilesh , Shijith Thotton CC: Subject: [PATCH v3 05/22] event/cnxk: add CN20k event queue configuration Date: Tue, 22 Oct 2024 14:16:23 +0530 Message-ID: <20241022084641.14497-5-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241022084641.14497-1-pbhagavatula@marvell.com> References: <20241021205745.7310-1-pbhagavatula@marvell.com> <20241022084641.14497-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 4sZsXPdGoMJ1YilU1fh8xfkRsvK3X7A2 X-Proofpoint-GUID: 4sZsXPdGoMJ1YilU1fh8xfkRsvK3X7A2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add setup and release functions for event queues i.e. SSO HWGRPs. Allocate buffers in DRAM that hold inflight events. Register device args to modify inflight event buffer count, HWGRP QoS and stash. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 2 +- drivers/event/cnxk/cn20k_eventdev.c | 14 ++++++++++++++ drivers/event/cnxk/cnxk_eventdev.c | 4 ++-- drivers/event/cnxk/cnxk_eventdev.h | 2 +- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index b6c4896c69..25ba7e4133 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -1319,7 +1319,7 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" CNXK_SSO_FORCE_BP "=1" - CN10K_SSO_STASH "=" + CNXK_SSO_STASH "=" CNXK_TIM_DISABLE_NPA "=1" CNXK_TIM_CHNK_SLOTS "=" CNXK_TIM_RINGS_LMT "=" diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c index 753a976cd3..b876c36806 100644 --- a/drivers/event/cnxk/cn20k_eventdev.c +++ b/drivers/event/cnxk/cn20k_eventdev.c @@ -56,6 +56,12 @@ cn20k_sso_dev_configure(const struct rte_eventdev *event_dev) return -ENODEV; } + rc = cnxk_sso_xaq_allocate(dev); + if (rc < 0) + goto cnxk_rsrc_fini; + +cnxk_rsrc_fini: + roc_sso_rsrc_fini(&dev->sso); return rc; } @@ -64,6 +70,10 @@ static struct eventdev_ops cn20k_sso_dev_ops = { .dev_configure = cn20k_sso_dev_configure, .queue_def_conf = cnxk_sso_queue_def_conf, + .queue_setup = cnxk_sso_queue_setup, + .queue_release = cnxk_sso_queue_release, + .queue_attr_set = cnxk_sso_queue_attribute_set, + .port_def_conf = cnxk_sso_port_def_conf, }; @@ -127,3 +137,7 @@ static struct rte_pci_driver cn20k_pci_sso = { RTE_PMD_REGISTER_PCI(event_cn20k, cn20k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn20k, cn20k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn20k, "vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(event_cn20k, + CNXK_SSO_XAE_CNT "=" + CNXK_SSO_GGRP_QOS "=" + CNXK_SSO_STASH "="); diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index ab7420ab79..be6a487b59 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -624,8 +624,8 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) &dev->force_ena_bp); rte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_flag, &single_ws); - rte_kvargs_process(kvlist, CN10K_SSO_STASH, - &parse_sso_kvargs_stash_dict, dev); + rte_kvargs_process(kvlist, CNXK_SSO_STASH, &parse_sso_kvargs_stash_dict, + dev); dev->dual_ws = !single_ws; rte_kvargs_free(kvlist); } diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 904a9b022d..ba08fa2173 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -27,7 +27,7 @@ #define CNXK_SSO_GGRP_QOS "qos" #define CNXK_SSO_FORCE_BP "force_rx_bp" #define CN9K_SSO_SINGLE_WS "single_ws" -#define CN10K_SSO_STASH "stash" +#define CNXK_SSO_STASH "stash" #define CNXK_SSO_MAX_PROFILES 2 -- 2.25.1