From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EAE5E45B9E; Tue, 22 Oct 2024 11:20:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 644B040DDB; Tue, 22 Oct 2024 11:18:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BE6AE40649 for ; Tue, 22 Oct 2024 11:17:58 +0200 (CEST) Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49M6SSwF020805; Tue, 22 Oct 2024 02:17:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=x P4MlWiGkxNZd3iybFsvWCkwQwQmMYVeC8wBPhqCpi0=; b=g5JpHxymwolVAsYKo dUoQve0m6Ne1ffrDxiUGqempqpfi8PKT9mtQeuN4LoXUv2rBS68iF/rwGLE0P9Et K8N4z76UDQ3CCc/f5eriDTLWwW+WKU5nMmc2XSvcjDn+tT1h4x3B+G+53NQ36tno zz5Nzy7b0VIxbW42s/NNxGuYWaj7ZTK7sa/gQzRC97vJcDRBaoZaJr0RBEu2lJLD TfHXfnFt6Zh63fojUQJdS6p49EWyFopSxOYGY+H7hn/YMO04Bfkdq/BxoiHghhoq YieWa2h3IYounuq1rRpiWgAdwvsRVD6r2vaAuxBwTW3jjOdYYLnYrwdEJ+yypbJ/ 4wgng== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 42e6tf0bky-17 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Oct 2024 02:17:57 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 22 Oct 2024 02:17:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 22 Oct 2024 02:17:48 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 6F1045E6A0E; Tue, 22 Oct 2024 01:47:02 -0700 (PDT) From: To: , , , Pavan Nikhilesh , Shijith Thotton CC: Subject: [PATCH v3 06/22] event/cnxk: add CN20K event port configuration Date: Tue, 22 Oct 2024 14:16:24 +0530 Message-ID: <20241022084641.14497-6-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241022084641.14497-1-pbhagavatula@marvell.com> References: <20241021205745.7310-1-pbhagavatula@marvell.com> <20241022084641.14497-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: vEDD6VtuLBqTivETu4x72Jf9OqqH6aAc X-Proofpoint-GUID: vEDD6VtuLBqTivETu4x72Jf9OqqH6aAc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add SSO HWS a.k.a event port setup, release, link, unlink functions. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 61 ++----- drivers/event/cnxk/cn20k_eventdev.c | 173 ++++++++++++++++++++ drivers/event/cnxk/cn20k_eventdev.h | 26 +++ drivers/event/cnxk/cnxk_common.h | 55 +++++++ drivers/event/cnxk/cnxk_eventdev.h | 6 +- drivers/event/cnxk/cnxk_eventdev_selftest.c | 6 +- 6 files changed, 274 insertions(+), 53 deletions(-) create mode 100644 drivers/event/cnxk/cn20k_eventdev.h create mode 100644 drivers/event/cnxk/cnxk_common.h diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 25ba7e4133..82d973a420 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -2,15 +2,16 @@ * Copyright(C) 2021 Marvell. */ +#include + +#include "cn10k_cryptodev_ops.h" +#include "cn10k_ethdev.h" #include "cn10k_tx_worker.h" #include "cn10k_worker.h" -#include "cn10k_ethdev.h" -#include "cn10k_cryptodev_ops.h" +#include "cnxk_common.h" +#include "cnxk_dma_event_dp.h" #include "cnxk_eventdev.h" #include "cnxk_worker.h" -#include "cnxk_dma_event_dp.h" - -#include #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \ deq_op = deq_ops[dev->rx_offloads & (NIX_RX_OFFLOAD_MAX - 1)] @@ -18,29 +19,6 @@ #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \ enq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)] -static uint32_t -cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev) -{ - uint32_t wdata = 1; - - if (dev->deq_tmo_ns) - wdata |= BIT(16); - - switch (dev->gw_mode) { - case CN10K_GW_MODE_NONE: - default: - break; - case CN10K_GW_MODE_PREF: - wdata |= BIT(19); - break; - case CN10K_GW_MODE_PREF_WFE: - wdata |= BIT(20) | BIT(19); - break; - } - - return wdata; -} - static void * cn10k_sso_init_hws_mem(void *arg, uint8_t port_id) { @@ -61,7 +39,7 @@ cn10k_sso_init_hws_mem(void *arg, uint8_t port_id) ws->base = roc_sso_hws_base_get(&dev->sso, port_id); ws->hws_id = port_id; ws->swtag_req = 0; - ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev); + ws->gw_wdata = cnxk_sso_hws_prf_wdata(dev); ws->gw_rdata = SSO_TT_EMPTY << 32; ws->lmt_base = dev->sso.lmt_base; ws->xae_waes = dev->sso.feat.xaq_wq_entries; @@ -219,12 +197,12 @@ cn10k_sso_hws_reset(void *arg, void *hws) } while (pend_state & (BIT_ULL(58) | BIT_ULL(56))); switch (dev->gw_mode) { - case CN10K_GW_MODE_PREF: - case CN10K_GW_MODE_PREF_WFE: + case CNXK_GW_MODE_PREF: + case CNXK_GW_MODE_PREF_WFE: while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63)) ; break; - case CN10K_GW_MODE_NONE: + case CNXK_GW_MODE_NONE: default: break; } @@ -571,18 +549,7 @@ cn10k_sso_dev_configure(const struct rte_eventdev *event_dev) if (rc < 0) goto cnxk_rsrc_fini; - switch (event_dev->data->dev_conf.preschedule_type) { - default: - case RTE_EVENT_PRESCHEDULE_NONE: - dev->gw_mode = CN10K_GW_MODE_NONE; - break; - case RTE_EVENT_PRESCHEDULE: - dev->gw_mode = CN10K_GW_MODE_PREF; - break; - case RTE_EVENT_PRESCHEDULE_ADAPTIVE: - dev->gw_mode = CN10K_GW_MODE_PREF_WFE; - break; - } + dev->gw_mode = cnxk_sso_hws_preschedule_get(event_dev->data->dev_conf.preschedule_type); rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem, cn10k_sso_hws_setup); @@ -665,13 +632,13 @@ cn10k_sso_port_quiesce(struct rte_eventdev *event_dev, void *port, /* Check if we have work in PRF_WQE0, if so extract it. */ switch (dev->gw_mode) { - case CN10K_GW_MODE_PREF: - case CN10K_GW_MODE_PREF_WFE: + case CNXK_GW_MODE_PREF: + case CNXK_GW_MODE_PREF_WFE: while (plt_read64(ws->base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63)) ; break; - case CN10K_GW_MODE_NONE: + case CNXK_GW_MODE_NONE: default: break; } diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c index b876c36806..d275cebe52 100644 --- a/drivers/event/cnxk/cn20k_eventdev.c +++ b/drivers/event/cnxk/cn20k_eventdev.c @@ -4,7 +4,86 @@ #include "roc_api.h" +#include "cn20k_eventdev.h" +#include "cnxk_common.h" #include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +static void * +cn20k_sso_init_hws_mem(void *arg, uint8_t port_id) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn20k_sso_hws *ws; + + /* Allocate event port memory */ + ws = rte_zmalloc("cn20k_ws", sizeof(struct cn20k_sso_hws) + RTE_CACHE_LINE_SIZE, + RTE_CACHE_LINE_SIZE); + if (ws == NULL) { + plt_err("Failed to alloc memory for port=%d", port_id); + return NULL; + } + + /* First cache line is reserved for cookie */ + ws = (struct cn20k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE); + ws->base = roc_sso_hws_base_get(&dev->sso, port_id); + ws->hws_id = port_id; + ws->swtag_req = 0; + ws->gw_wdata = cnxk_sso_hws_prf_wdata(dev); + ws->gw_rdata = SSO_TT_EMPTY << 32; + ws->xae_waes = dev->sso.feat.xaq_wq_entries; + + return ws; +} + +static int +cn20k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link, uint8_t profile) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn20k_sso_hws *ws = port; + + return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link, profile, 0); +} + +static int +cn20k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link, uint8_t profile) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn20k_sso_hws *ws = port; + + return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link, profile, 0); +} + +static void +cn20k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn20k_sso_hws *ws = hws; + uint64_t val; + + ws->grp_base = grp_base; + ws->fc_mem = (int64_t __rte_atomic *)dev->fc_iova; + ws->xaq_lmt = dev->xaq_lmt; + ws->fc_cache_space = (int64_t __rte_atomic *)dev->fc_cache_space; + ws->aw_lmt = dev->sso.lmt_base; + + /* Set get_work timeout for HWS */ + val = NSEC2USEC(dev->deq_tmo_ns); + val = val ? val - 1 : 0; + plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM); +} + +static void +cn20k_sso_hws_release(void *arg, void *hws) +{ + struct cnxk_sso_evdev *dev = arg; + struct cn20k_sso_hws *ws = hws; + uint16_t i, j; + + for (i = 0; i < CNXK_SSO_MAX_PROFILES; i++) + for (j = 0; j < dev->nb_event_queues; j++) + roc_sso_hws_unlink(&dev->sso, ws->hws_id, &j, 1, i, 0); + memset(ws, 0, sizeof(*ws)); +} static void cn20k_sso_set_rsrc(void *arg) @@ -60,11 +139,98 @@ cn20k_sso_dev_configure(const struct rte_eventdev *event_dev) if (rc < 0) goto cnxk_rsrc_fini; + dev->gw_mode = cnxk_sso_hws_preschedule_get(event_dev->data->dev_conf.preschedule_type); + + rc = cnxk_setup_event_ports(event_dev, cn20k_sso_init_hws_mem, cn20k_sso_hws_setup); + if (rc < 0) + goto cnxk_rsrc_fini; + + /* Restore any prior port-queue mapping. */ + cnxk_sso_restore_links(event_dev, cn20k_sso_hws_link); + + dev->configured = 1; + rte_mb(); + + return 0; cnxk_rsrc_fini: roc_sso_rsrc_fini(&dev->sso); + dev->nb_event_ports = 0; return rc; } +static int +cn20k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, + const struct rte_event_port_conf *port_conf) +{ + + RTE_SET_USED(port_conf); + return cnxk_sso_port_setup(event_dev, port_id, cn20k_sso_hws_setup); +} + +static void +cn20k_sso_port_release(void *port) +{ + struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port); + struct cnxk_sso_evdev *dev; + + if (port == NULL) + return; + + dev = cnxk_sso_pmd_priv(gws_cookie->event_dev); + if (!gws_cookie->configured) + goto free; + + cn20k_sso_hws_release(dev, port); + memset(gws_cookie, 0, sizeof(*gws_cookie)); +free: + rte_free(gws_cookie); +} + +static int +cn20k_sso_port_link_profile(struct rte_eventdev *event_dev, void *port, const uint8_t queues[], + const uint8_t priorities[], uint16_t nb_links, uint8_t profile) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t hwgrp_ids[nb_links]; + uint16_t link; + + RTE_SET_USED(priorities); + for (link = 0; link < nb_links; link++) + hwgrp_ids[link] = queues[link]; + nb_links = cn20k_sso_hws_link(dev, port, hwgrp_ids, nb_links, profile); + + return (int)nb_links; +} + +static int +cn20k_sso_port_unlink_profile(struct rte_eventdev *event_dev, void *port, uint8_t queues[], + uint16_t nb_unlinks, uint8_t profile) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + uint16_t hwgrp_ids[nb_unlinks]; + uint16_t unlink; + + for (unlink = 0; unlink < nb_unlinks; unlink++) + hwgrp_ids[unlink] = queues[unlink]; + nb_unlinks = cn20k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks, profile); + + return (int)nb_unlinks; +} + +static int +cn20k_sso_port_link(struct rte_eventdev *event_dev, void *port, const uint8_t queues[], + const uint8_t priorities[], uint16_t nb_links) +{ + return cn20k_sso_port_link_profile(event_dev, port, queues, priorities, nb_links, 0); +} + +static int +cn20k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, uint8_t queues[], + uint16_t nb_unlinks) +{ + return cn20k_sso_port_unlink_profile(event_dev, port, queues, nb_unlinks, 0); +} + static struct eventdev_ops cn20k_sso_dev_ops = { .dev_infos_get = cn20k_sso_info_get, .dev_configure = cn20k_sso_dev_configure, @@ -75,6 +241,13 @@ static struct eventdev_ops cn20k_sso_dev_ops = { .queue_attr_set = cnxk_sso_queue_attribute_set, .port_def_conf = cnxk_sso_port_def_conf, + .port_setup = cn20k_sso_port_setup, + .port_release = cn20k_sso_port_release, + .port_link = cn20k_sso_port_link, + .port_unlink = cn20k_sso_port_unlink, + .port_link_profile = cn20k_sso_port_link_profile, + .port_unlink_profile = cn20k_sso_port_unlink_profile, + .timeout_ticks = cnxk_sso_timeout_ticks, }; static int diff --git a/drivers/event/cnxk/cn20k_eventdev.h b/drivers/event/cnxk/cn20k_eventdev.h new file mode 100644 index 0000000000..5b6c558d5a --- /dev/null +++ b/drivers/event/cnxk/cn20k_eventdev.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2022 Marvell. + */ + +#ifndef __CN20K_EVENTDEV_H__ +#define __CN20K_EVENTDEV_H__ + +#define CN20K_SSO_DEFAULT_STASH_OFFSET -1 +#define CN20K_SSO_DEFAULT_STASH_LENGTH 2 + +struct __rte_cache_aligned cn20k_sso_hws { + uint64_t base; + uint32_t gw_wdata; + uint64_t gw_rdata; + uint8_t swtag_req; + uint8_t hws_id; + /* Add Work Fastpath data */ + alignas(RTE_CACHE_LINE_SIZE) int64_t __rte_atomic *fc_mem; + int64_t __rte_atomic *fc_cache_space; + uintptr_t aw_lmt; + uintptr_t grp_base; + uint16_t xae_waes; + int32_t xaq_lmt; +}; + +#endif /* __CN20K_EVENTDEV_H__ */ diff --git a/drivers/event/cnxk/cnxk_common.h b/drivers/event/cnxk/cnxk_common.h new file mode 100644 index 0000000000..712d82bee7 --- /dev/null +++ b/drivers/event/cnxk/cnxk_common.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2024 Marvell. + */ + +#ifndef __CNXK_COMMON_H__ +#define __CNXK_COMMON_H__ + +#include "cnxk_eventdev.h" +#include "cnxk_worker.h" + +static uint32_t +cnxk_sso_hws_prf_wdata(struct cnxk_sso_evdev *dev) +{ + uint32_t wdata = 1; + + if (dev->deq_tmo_ns) + wdata |= BIT(16); + + switch (dev->gw_mode) { + case CNXK_GW_MODE_NONE: + default: + break; + case CNXK_GW_MODE_PREF: + wdata |= BIT(19); + break; + case CNXK_GW_MODE_PREF_WFE: + wdata |= BIT(20) | BIT(19); + break; + } + + return wdata; +} + +static uint8_t +cnxk_sso_hws_preschedule_get(uint8_t preschedule_type) +{ + uint8_t gw_mode = 0; + + switch (preschedule_type) { + default: + case RTE_EVENT_PRESCHEDULE_NONE: + gw_mode = CNXK_GW_MODE_NONE; + break; + case RTE_EVENT_PRESCHEDULE: + gw_mode = CNXK_GW_MODE_PREF; + break; + case RTE_EVENT_PRESCHEDULE_ADAPTIVE: + gw_mode = CNXK_GW_MODE_PREF_WFE; + break; + } + + return gw_mode; +} + +#endif /* __CNXK_COMMON_H__ */ diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index ba08fa2173..4066497e6b 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -38,9 +38,9 @@ #define CN9K_SSOW_GET_BASE_ADDR(_GW) ((_GW)-SSOW_LF_GWS_OP_GET_WORK0) #define CN9K_DUAL_WS_NB_WS 2 -#define CN10K_GW_MODE_NONE 0 -#define CN10K_GW_MODE_PREF 1 -#define CN10K_GW_MODE_PREF_WFE 2 +#define CNXK_GW_MODE_NONE 0 +#define CNXK_GW_MODE_PREF 1 +#define CNXK_GW_MODE_PREF_WFE 2 #define CNXK_QOS_NORMALIZE(val, min, max, cnt) \ (min + val / ((max + cnt - 1) / cnt)) diff --git a/drivers/event/cnxk/cnxk_eventdev_selftest.c b/drivers/event/cnxk/cnxk_eventdev_selftest.c index 311de3d92b..7a3262bcff 100644 --- a/drivers/event/cnxk/cnxk_eventdev_selftest.c +++ b/drivers/event/cnxk/cnxk_eventdev_selftest.c @@ -1568,15 +1568,15 @@ cnxk_sso_selftest(const char *dev_name) if (roc_model_runtime_is_cn10k()) { printf("Verifying CN10K workslot getwork mode none\n"); - dev->gw_mode = CN10K_GW_MODE_NONE; + dev->gw_mode = CNXK_GW_MODE_NONE; if (cnxk_sso_testsuite_run(dev_name)) return rc; printf("Verifying CN10K workslot getwork mode prefetch\n"); - dev->gw_mode = CN10K_GW_MODE_PREF; + dev->gw_mode = CNXK_GW_MODE_PREF; if (cnxk_sso_testsuite_run(dev_name)) return rc; printf("Verifying CN10K workslot getwork mode smart prefetch\n"); - dev->gw_mode = CN10K_GW_MODE_PREF_WFE; + dev->gw_mode = CNXK_GW_MODE_PREF_WFE; if (cnxk_sso_testsuite_run(dev_name)) return rc; } -- 2.25.1