From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3F61045BA3; Tue, 22 Oct 2024 19:31:46 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 37B2E40E54; Tue, 22 Oct 2024 19:30:52 +0200 (CEST) Received: from egress-ip42b.ess.de.barracuda.com (egress-ip42b.ess.de.barracuda.com [18.185.115.246]) by mails.dpdk.org (Postfix) with ESMTP id 37E6940A80 for ; Tue, 22 Oct 2024 19:30:49 +0200 (CEST) Received: from EUR02-VI1-obe.outbound.protection.outlook.com (mail-vi1eur02lp2046.outbound.protection.outlook.com [104.47.11.46]) by mx-outbound19-119.eu-central-1b.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 22 Oct 2024 17:30:48 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=bzhESKyd8mM7Ztd1dOvZK/wU50cef+5LLSAaEagQzwzXk8ygm2q7I9G/14exeWQdvSjnC9s0NNMNX6pJsCARHH52mScQ4SQ7O5xqy1zTYp6GekzTeMJS45JGMUsgRAmoVpObPzwWmUL+eqxnJV0NwVt6NLeio6LgSmQfZnQkwWSbBjEGsN011r/+NZrq+kd4QwZTgCtJwI5Q6Lls6ZwXmucqBvLYPdgLw2L+uzNG56FRdTXYlJ3nUvEFpYBRE5lLLjFWZKk8ILzQ8GCQu9kGBiawdBihz5TJwquCISiC/0ElGSQfXOVBhyeblqUEHXHzqT371NBkXjBqSQ1S/R5g1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5l0KkoOxVp7ip2k2uvWXmwkqVh/Jw1Yjxg3ON7t76sA=; b=zDx8NRaJkq9BC3iSRY6BqldO8F3Rl7FKo7Oab6CDac25KhBvXgGN2OvaRmEeAijs1hNLHfj82fFATRnVkq1axRG5LN0vvDnl/jyHwRP+0vef0crDeNXz0Ue3e3TgtUKsIo72Dci4LJ/+nRCs0vvTzl7NoN5X/t3+GLtnmWHwKyWS3gqdYrDrbgGdjqfIxt+3i6csthJ9ZW1S7v5sInpoUpSb//JvmBvBxpl7H7yMr4Q76mz9vKVXjebhjPSQpVxTVusNzHOZOwHCHop2MLNS5dfhZE63/jaekrqd4+NkaxJdDKQY2Kb6do0rJglxmBBDvVbZcYBSelAHWub0IvUQCA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 178.72.21.4) smtp.rcpttodomain=dpdk.org smtp.mailfrom=napatech.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=napatech.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=napatech.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5l0KkoOxVp7ip2k2uvWXmwkqVh/Jw1Yjxg3ON7t76sA=; b=AltZctYvsO/UhD784WQvjTmT6oOyd46jGzrs6rvdrt5VtW65O0sr6ZwUtFfcX+YNpEb1nMObV5nbuvIXg/8gZLOrzrjEaXK0r1GK3wqWNPlWRnTQ5+lKnC/QX3EQk9QGGYgqsK59G7imyg2QAQDi77pjcUJqRIrzGmsj/Pri2CM= Received: from DB9PR06CA0029.eurprd06.prod.outlook.com (2603:10a6:10:1db::34) by AM0P190MB0755.EURP190.PROD.OUTLOOK.COM (2603:10a6:208:192::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.16; Tue, 22 Oct 2024 16:57:03 +0000 Received: from DU2PEPF0001E9C2.eurprd03.prod.outlook.com (2603:10a6:10:1db:cafe::6e) by DB9PR06CA0029.outlook.office365.com (2603:10a6:10:1db::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8069.29 via Frontend Transport; Tue, 22 Oct 2024 16:57:03 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 178.72.21.4) smtp.mailfrom=napatech.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=napatech.com; Received-SPF: Fail (protection.outlook.com: domain of napatech.com does not designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com; client-ip=178.72.21.4; helo=localhost.localdomain; Received: from localhost.localdomain (178.72.21.4) by DU2PEPF0001E9C2.mail.protection.outlook.com (10.167.8.71) with Microsoft SMTP Server id 15.20.8093.14 via Frontend Transport; Tue, 22 Oct 2024 16:57:03 +0000 From: Serhii Iliushyk To: dev@dpdk.org Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com, andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com, stephen@networkplumber.org, Danylo Vodopianov Subject: [PATCH v2 55/73] net/ntnic: add rpf module Date: Tue, 22 Oct 2024 18:55:12 +0200 Message-ID: <20241022165541.3186140-56-sil-plv@napatech.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241022165541.3186140-1-sil-plv@napatech.com> References: <20241021210527.2075431-1-sil-plv@napatech.com> <20241022165541.3186140-1-sil-plv@napatech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PEPF0001E9C2:EE_|AM0P190MB0755:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 624fd61c-0e65-4cca-0f95-08dcf2ba8da3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?fhxFZBvZIR8KIXpOAh8VMgdTeV9E4Fyy1JEhBfUq1m4zL8b6G7jt+haI3hmp?= =?us-ascii?Q?S3yOndz9M5U6PyJGa/SlNWvFF+xoz0rKaLoN9Th2FLcWmCrPBAzjwtDKHrMS?= =?us-ascii?Q?Vcaazxr2KIvaAdv1ts5mmb4QN2bQ3f1/ftVqJ4GUz4JfjINvYwnjZUlhJExS?= =?us-ascii?Q?Epb34cNbxm0XSRTe2Y0hKdB6OxH/sf5NHSL0PvIrS4/FlV2ciOD5bQPDs2YP?= =?us-ascii?Q?at+u3M9SChjZVInN8t4A90UZKWHFvtE6utgusPdYw1udB0+5ec2T662+QsPM?= =?us-ascii?Q?rkfQ9Pw/ZCOgnCsLZqe46flUuh4+fzxiaulQItQzaox+P5cTc8/ZqCUEsYxb?= =?us-ascii?Q?S8vE3vFxioZaE+b4UCKR+tDu5oTUdIllHdcZkFZQP39eZkoBmG92yOsOi4Ng?= =?us-ascii?Q?+IU7WojNyr1irkVhAGyDWWSMM09E6GKEdYXVal/LNKwJseihikSwHbSYkkMl?= =?us-ascii?Q?npGmq/L/ks60YlrX4pi36ozevlIKriD9QYSjZf3ZiauR0+sv5CU90h1eN7jC?= =?us-ascii?Q?H0H+qMp53+zqiU9zEaKuWE4pvBQEOSd/0Gg8usszzLC0ADFJ+vJYr8SeqYKv?= =?us-ascii?Q?P8vboAiXam9gZroZ9WSh/MrafLgdzVjgRQIl3xnOw0171eLrk9/mbbX1pXdz?= =?us-ascii?Q?kz0po7kwhNoQf5yFUBizk/xR1go2svRJeQhjVrfSBTuD5o1Av1Zd3pg2gx4T?= =?us-ascii?Q?yHqRZuqnFZMl8+wDMNy9XGmTEQhUxfBM4YP/nmXk+h2TCHU/8pUKPcOS5dhJ?= =?us-ascii?Q?8ssovaJDWc2ggMemmzNl7XGdADEaxx7T3ZqP1Q9o1kbC5mgDpuvwmOP/jvzC?= =?us-ascii?Q?V2r/Sj5J2sDW4dAwH/56/VI8y3IzVx2U4UmGfMc1phh/m3A35q+rT7Nvvh72?= =?us-ascii?Q?kmaF6KkoXVbeCR8lwGa33zYkA4rC1/68v23VdFm3YA/cMcYFffOdglccSlDx?= =?us-ascii?Q?Pgz7rB2QZ6XA9epjWWpWAh1k3cLetqOSFPPvSd9vV6o+EgWv1H+eKkjz1KE8?= =?us-ascii?Q?FJhODGaWhYyVVTpGffecFhBLo01jQlava7OoYgEqsI04ZI92DsGNuDqOENmW?= =?us-ascii?Q?r7clgzz974JRpWH3rX835HAuGtH3dZ823BGTsKUqvVqRlJ3PCpo4fvXMaCYT?= =?us-ascii?Q?ZmtXUBqdhbC4E6n8ZcNWHsGd3UHExGwQ+AbIqEIwhhSu+G7A8Vu1MKkoC4gL?= =?us-ascii?Q?NykkbppPWuHO+xg3lTwTlAQBfx2d7bE7bZCaWH0kJj9hxtoW+QEvJaCg7+/E?= =?us-ascii?Q?cbjQWPnUNFOzqPQsUNeQyrTTKdY3qKMlUnzJZba0UN+qHhjMpVPyo0C6k/V8?= =?us-ascii?Q?yzw1JxL/9nMEhu8N1l0UW40Xo5WAu94bswniCF3RS7xguuk8fTvmpyWEPzFV?= =?us-ascii?Q?mtXHKt1W+sRAtoFnN+Yk4dCU0MqEWZYGlwUtU1hzVKVIwV+2RQ=3D=3D?= X-Forefront-Antispam-Report: CIP:178.72.21.4; CTRY:DK; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:localhost.localdomain; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: N+bbE6a6Zrh7UuXjeA3SaaRIFmkDPkEjP0rsLCwWtxDwKFs1KCQ25uU8x6JGjZNkkg2CYPan/0WAIcdamwtMVKpJyoEQYzE6TcKS6m4qnxApolCdvkQ5bsNg+xJ/WYWUOJHJkQ9BJTazOWq2AHW94u54NNmOcnR5XxuzrVN979ZfKxfKfEqNZaKcK13TKk33FV5YfvFQ021KG3Owf4uGm8hDTRCRavkDyALaGnboXYsW4pfICYxMtBc8Ku+mRKqZfM4WEauDP6WT1SGAs2y5xyMyIk7wyMc4LaF7A8PmYuTlZ/FsPMtikYFiPHhIvJpCeAgCh1LghBiJkWuijRN3+MDs5B1o+lEgfBmeQPFa4yL6Ul4jht+OjMF7jo3H958gX7qGf1TuhGsJjNTMnnGNp0OTlHvZEDkcMpqoNa7PDlAd9hoMjbEb690GVqEF1eUh5F806s29NhXxbp31FQj/ZMvVoZKJerUpUXee4stJaezJiG6h48O4VzUeplQGlyYpT5iAuGdj3LxFm1kl2fuWFT+jGyMjEMuaq8NRy6h7J1TJx3hubGA7ltVFLCOE1scFtsHYVZkOfJun0odmdUawgF55F0NPbFXJic4N6UvuXwRQaswqhJveVjoeMDO+BdhYF8YzLj7pzmrJz2fnKL60DCIkvkKu9sJQXSDJf/ebDww= X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2024 16:57:03.0911 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 624fd61c-0e65-4cca-0f95-08dcf2ba8da3 X-MS-Exchange-CrossTenant-Id: c4540d0b-728a-4233-9da5-9ea30c7ec3ed X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=c4540d0b-728a-4233-9da5-9ea30c7ec3ed; Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C2.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0P190MB0755 X-OriginatorOrg: napatech.com X-BESS-ID: 1729618248-304983-12653-16005-1 X-BESS-VER: 2019.1_20241018.1852 X-BESS-Apparent-Source-IP: 104.47.11.46 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVoZGlqaGQGYGUDTZ2NIoxcQi1T TV2DDZwDzRwMggMc0sNTXNINXSwsLQWKk2FgBzOjPhQgAAAA== X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.259902 [from cloudscan18-120.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE_7582B META: Custom Rule 7582B 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_RULE_7582B, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Danylo Vodopianov The Receive Port FIFO module controls the small FPGA FIFO that packets are stored in before they enter the packet processor pipeline. Signed-off-by: Danylo Vodopianov --- .../net/ntnic/adapter/nt4ga_stat/nt4ga_stat.c | 25 +++- drivers/net/ntnic/include/ntnic_stat.h | 2 + drivers/net/ntnic/meson.build | 1 + .../net/ntnic/nthw/core/include/nthw_rpf.h | 48 +++++++ drivers/net/ntnic/nthw/core/nthw_rpf.c | 119 ++++++++++++++++++ .../net/ntnic/nthw/model/nthw_fpga_model.c | 12 ++ .../net/ntnic/nthw/model/nthw_fpga_model.h | 1 + .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 1 + .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 + .../nthw/supported/nthw_fpga_reg_defs_rpf.h | 19 +++ 10 files changed, 228 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_rpf.h create mode 100644 drivers/net/ntnic/nthw/core/nthw_rpf.c create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h diff --git a/drivers/net/ntnic/adapter/nt4ga_stat/nt4ga_stat.c b/drivers/net/ntnic/adapter/nt4ga_stat/nt4ga_stat.c index 0e20f3ea45..f733fd5459 100644 --- a/drivers/net/ntnic/adapter/nt4ga_stat/nt4ga_stat.c +++ b/drivers/net/ntnic/adapter/nt4ga_stat/nt4ga_stat.c @@ -11,6 +11,7 @@ #include "nt4ga_adapter.h" #include "ntnic_nim.h" #include "flow_filter.h" +#include "ntnic_stat.h" #include "ntnic_mod_reg.h" #define DEFAULT_MAX_BPS_SPEED 100e9 @@ -43,7 +44,7 @@ static int nt4ga_stat_init(struct adapter_info_s *p_adapter_info) if (!p_nthw_rmc) { nthw_stat_delete(p_nthw_stat); - NT_LOG(ERR, NTNIC, "%s: ERROR ", p_adapter_id_str); + NT_LOG(ERR, NTNIC, "%s: ERROR rmc allocation", p_adapter_id_str); return -1; } @@ -54,6 +55,22 @@ static int nt4ga_stat_init(struct adapter_info_s *p_adapter_info) p_nt4ga_stat->mp_nthw_rmc = NULL; } + if (nthw_rpf_init(NULL, p_fpga, p_adapter_info->adapter_no) == 0) { + nthw_rpf_t *p_nthw_rpf = nthw_rpf_new(); + + if (!p_nthw_rpf) { + nthw_stat_delete(p_nthw_stat); + NT_LOG_DBGX(ERR, NTNIC, "%s: ERROR", p_adapter_id_str); + return -1; + } + + nthw_rpf_init(p_nthw_rpf, p_fpga, p_adapter_info->adapter_no); + p_nt4ga_stat->mp_nthw_rpf = p_nthw_rpf; + + } else { + p_nt4ga_stat->mp_nthw_rpf = NULL; + } + p_nt4ga_stat->mp_nthw_stat = p_nthw_stat; nthw_stat_init(p_nthw_stat, p_fpga, 0); @@ -77,6 +94,9 @@ static int nt4ga_stat_setup(struct adapter_info_s *p_adapter_info) if (p_nt4ga_stat->mp_nthw_rmc) nthw_rmc_block(p_nt4ga_stat->mp_nthw_rmc); + if (p_nt4ga_stat->mp_nthw_rpf) + nthw_rpf_block(p_nt4ga_stat->mp_nthw_rpf); + /* Allocate and map memory for fpga statistics */ { uint32_t n_stat_size = (uint32_t)(p_nthw_stat->m_nb_counters * sizeof(uint32_t) + @@ -112,6 +132,9 @@ static int nt4ga_stat_setup(struct adapter_info_s *p_adapter_info) if (p_nt4ga_stat->mp_nthw_rmc) nthw_rmc_unblock(p_nt4ga_stat->mp_nthw_rmc, false); + if (p_nt4ga_stat->mp_nthw_rpf) + nthw_rpf_unblock(p_nt4ga_stat->mp_nthw_rpf); + p_nt4ga_stat->mp_stat_structs_color = calloc(p_nthw_stat->m_nb_color_counters, sizeof(struct color_counters)); diff --git a/drivers/net/ntnic/include/ntnic_stat.h b/drivers/net/ntnic/include/ntnic_stat.h index 2aee3f8425..ed24a892ec 100644 --- a/drivers/net/ntnic/include/ntnic_stat.h +++ b/drivers/net/ntnic/include/ntnic_stat.h @@ -8,6 +8,7 @@ #include "common_adapter_defs.h" #include "nthw_rmc.h" +#include "nthw_rpf.h" #include "nthw_fpga_model.h" #define NT_MAX_COLOR_FLOW_STATS 0x400 @@ -102,6 +103,7 @@ struct flm_counters_v1 { struct nt4ga_stat_s { nthw_stat_t *mp_nthw_stat; nthw_rmc_t *mp_nthw_rmc; + nthw_rpf_t *mp_nthw_rpf; struct nt_dma_s *p_stat_dma; uint32_t *p_stat_dma_virtual; uint32_t n_stat_size; diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 216341bb11..ed5a201fd5 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -47,6 +47,7 @@ sources = files( 'nthw/core/nthw_iic.c', 'nthw/core/nthw_mac_pcs.c', 'nthw/core/nthw_pcie3.c', + 'nthw/core/nthw_rpf.c', 'nthw/core/nthw_rmc.c', 'nthw/core/nthw_sdc.c', 'nthw/core/nthw_si5340.c', diff --git a/drivers/net/ntnic/nthw/core/include/nthw_rpf.h b/drivers/net/ntnic/nthw/core/include/nthw_rpf.h new file mode 100644 index 0000000000..4c6c57ba55 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_rpf.h @@ -0,0 +1,48 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NTHW_RPF_HPP_ +#define NTHW_RPF_HPP_ + +#include "nthw_fpga_model.h" +#include "pthread.h" +struct nthw_rpf { + nthw_fpga_t *mp_fpga; + + nthw_module_t *m_mod_rpf; + + int mn_instance; + + nthw_register_t *mp_reg_control; + nthw_field_t *mp_fld_control_pen; + nthw_field_t *mp_fld_control_rpp_en; + nthw_field_t *mp_fld_control_st_tgl_en; + nthw_field_t *mp_fld_control_keep_alive_en; + + nthw_register_t *mp_ts_sort_prg; + nthw_field_t *mp_fld_ts_sort_prg_maturing_delay; + nthw_field_t *mp_fld_ts_sort_prg_ts_at_eof; + + int m_default_maturing_delay; + bool m_administrative_block; /* used to enforce license expiry */ + + pthread_mutex_t rpf_mutex; +}; + +typedef struct nthw_rpf nthw_rpf_t; +typedef struct nthw_rpf nt_rpf; + +nthw_rpf_t *nthw_rpf_new(void); +void nthw_rpf_delete(nthw_rpf_t *p); +int nthw_rpf_init(nthw_rpf_t *p, nthw_fpga_t *p_fpga, int n_instance); +void nthw_rpf_administrative_block(nthw_rpf_t *p); +void nthw_rpf_block(nthw_rpf_t *p); +void nthw_rpf_unblock(nthw_rpf_t *p); +void nthw_rpf_set_maturing_delay(nthw_rpf_t *p, int32_t delay); +int32_t nthw_rpf_get_maturing_delay(nthw_rpf_t *p); +void nthw_rpf_set_ts_at_eof(nthw_rpf_t *p, bool enable); +bool nthw_rpf_get_ts_at_eof(nthw_rpf_t *p); + +#endif diff --git a/drivers/net/ntnic/nthw/core/nthw_rpf.c b/drivers/net/ntnic/nthw/core/nthw_rpf.c new file mode 100644 index 0000000000..81c704d01a --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_rpf.c @@ -0,0 +1,119 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" +#include "nthw_rpf.h" + +nthw_rpf_t *nthw_rpf_new(void) +{ + nthw_rpf_t *p = malloc(sizeof(nthw_rpf_t)); + + if (p) + memset(p, 0, sizeof(nthw_rpf_t)); + + return p; +} + +void nthw_rpf_delete(nthw_rpf_t *p) +{ + if (p) { + memset(p, 0, sizeof(nthw_rpf_t)); + free(p); + } +} + +int nthw_rpf_init(nthw_rpf_t *p, nthw_fpga_t *p_fpga, int n_instance) +{ + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_RPF, n_instance); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: MOD_RPF %d: no such instance", + p->mp_fpga->p_fpga_info->mp_adapter_id_str, p->mn_instance); + return -1; + } + + p->m_mod_rpf = p_mod; + + p->mp_fpga = p_fpga; + + p->m_administrative_block = false; + + /* CONTROL */ + p->mp_reg_control = nthw_module_get_register(p->m_mod_rpf, RPF_CONTROL); + p->mp_fld_control_pen = nthw_register_get_field(p->mp_reg_control, RPF_CONTROL_PEN); + p->mp_fld_control_rpp_en = nthw_register_get_field(p->mp_reg_control, RPF_CONTROL_RPP_EN); + p->mp_fld_control_st_tgl_en = + nthw_register_get_field(p->mp_reg_control, RPF_CONTROL_ST_TGL_EN); + p->mp_fld_control_keep_alive_en = + nthw_register_get_field(p->mp_reg_control, RPF_CONTROL_KEEP_ALIVE_EN); + + /* TS_SORT_PRG */ + p->mp_ts_sort_prg = nthw_module_get_register(p->m_mod_rpf, RPF_TS_SORT_PRG); + p->mp_fld_ts_sort_prg_maturing_delay = + nthw_register_get_field(p->mp_ts_sort_prg, RPF_TS_SORT_PRG_MATURING_DELAY); + p->mp_fld_ts_sort_prg_ts_at_eof = + nthw_register_get_field(p->mp_ts_sort_prg, RPF_TS_SORT_PRG_TS_AT_EOF); + p->m_default_maturing_delay = + nthw_fpga_get_product_param(p_fpga, NT_RPF_MATURING_DEL_DEFAULT, 0); + + /* Initialize mutex */ + pthread_mutex_init(&p->rpf_mutex, NULL); + return 0; +} + +void nthw_rpf_administrative_block(nthw_rpf_t *p) +{ + /* block all MAC ports */ + nthw_register_update(p->mp_reg_control); + nthw_field_set_val_flush32(p->mp_fld_control_pen, 0); + + p->m_administrative_block = true; +} + +void nthw_rpf_block(nthw_rpf_t *p) +{ + nthw_register_update(p->mp_reg_control); + nthw_field_set_val_flush32(p->mp_fld_control_pen, 0); +} + +void nthw_rpf_unblock(nthw_rpf_t *p) +{ + nthw_register_update(p->mp_reg_control); + + nthw_field_set_val32(p->mp_fld_control_pen, ~0U); + nthw_field_set_val32(p->mp_fld_control_rpp_en, ~0U); + nthw_field_set_val32(p->mp_fld_control_st_tgl_en, 1); + nthw_field_set_val_flush32(p->mp_fld_control_keep_alive_en, 1); +} + +void nthw_rpf_set_maturing_delay(nthw_rpf_t *p, int32_t delay) +{ + nthw_register_update(p->mp_ts_sort_prg); + nthw_field_set_val_flush32(p->mp_fld_ts_sort_prg_maturing_delay, (uint32_t)delay); +} + +int32_t nthw_rpf_get_maturing_delay(nthw_rpf_t *p) +{ + nthw_register_update(p->mp_ts_sort_prg); + /* Maturing delay is a two's complement 18 bit value, so we retrieve it as signed */ + return nthw_field_get_signed(p->mp_fld_ts_sort_prg_maturing_delay); +} + +void nthw_rpf_set_ts_at_eof(nthw_rpf_t *p, bool enable) +{ + nthw_register_update(p->mp_ts_sort_prg); + nthw_field_set_val_flush32(p->mp_fld_ts_sort_prg_ts_at_eof, enable); +} + +bool nthw_rpf_get_ts_at_eof(nthw_rpf_t *p) +{ + return nthw_field_get_updated(p->mp_fld_ts_sort_prg_ts_at_eof); +} diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.c b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c index 4d495f5b96..9eaaeb550d 100644 --- a/drivers/net/ntnic/nthw/model/nthw_fpga_model.c +++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c @@ -1050,6 +1050,18 @@ uint32_t nthw_field_get_val32(const nthw_field_t *p) return val; } +int32_t nthw_field_get_signed(const nthw_field_t *p) +{ + uint32_t val; + + nthw_field_get_val(p, &val, 1); + + if (val & (1U << nthw_field_get_bit_pos_high(p))) /* check sign */ + val = val | ~nthw_field_get_mask(p); /* sign extension */ + + return (int32_t)val; /* cast to signed value */ +} + uint32_t nthw_field_get_updated(const nthw_field_t *p) { uint32_t val; diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.h b/drivers/net/ntnic/nthw/model/nthw_fpga_model.h index 7956f0689e..d4e7ab3edd 100644 --- a/drivers/net/ntnic/nthw/model/nthw_fpga_model.h +++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.h @@ -227,6 +227,7 @@ void nthw_field_get_val(const nthw_field_t *p, uint32_t *p_data, uint32_t len); void nthw_field_set_val(const nthw_field_t *p, const uint32_t *p_data, uint32_t len); void nthw_field_set_val_flush(const nthw_field_t *p, const uint32_t *p_data, uint32_t len); uint32_t nthw_field_get_val32(const nthw_field_t *p); +int32_t nthw_field_get_signed(const nthw_field_t *p); uint32_t nthw_field_get_updated(const nthw_field_t *p); void nthw_field_update_register(const nthw_field_t *p); void nthw_field_flush_register(const nthw_field_t *p); diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h index ddc144dc02..03122acaf5 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -41,6 +41,7 @@ #define MOD_RAC (0xae830b42UL) #define MOD_RMC (0x236444eUL) #define MOD_RPL (0x6de535c3UL) +#define MOD_RPF (0x8d30dcddUL) #define MOD_RPP_LR (0xba7f945cUL) #define MOD_RST9563 (0x385d6d1dUL) #define MOD_SDC (0xd2369530UL) diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h index 8f196f885f..7067f4b1d0 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h @@ -39,6 +39,7 @@ #include "nthw_fpga_reg_defs_qsl.h" #include "nthw_fpga_reg_defs_rac.h" #include "nthw_fpga_reg_defs_rmc.h" +#include "nthw_fpga_reg_defs_rpf.h" #include "nthw_fpga_reg_defs_rpl.h" #include "nthw_fpga_reg_defs_rpp_lr.h" #include "nthw_fpga_reg_defs_rst9563.h" diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h new file mode 100644 index 0000000000..72f450b85d --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rpf.h @@ -0,0 +1,19 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +#ifndef _NTHW_FPGA_REG_DEFS_RPF_ +#define _NTHW_FPGA_REG_DEFS_RPF_ + +/* RPF */ +#define RPF_CONTROL (0x7a5bdb50UL) +#define RPF_CONTROL_KEEP_ALIVE_EN (0x80be3ffcUL) +#define RPF_CONTROL_PEN (0xb23137b8UL) +#define RPF_CONTROL_RPP_EN (0xdb51f109UL) +#define RPF_CONTROL_ST_TGL_EN (0x45a6ecfaUL) +#define RPF_TS_SORT_PRG (0xff1d137eUL) +#define RPF_TS_SORT_PRG_MATURING_DELAY (0x2a38e127UL) +#define RPF_TS_SORT_PRG_TS_AT_EOF (0x9f27d433UL) + +#endif /* _NTHW_FPGA_REG_DEFS_RPF_ */ -- 2.45.0