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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C2.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1P190MB2019 X-OriginatorOrg: napatech.com X-BESS-ID: 1729621738-303894-12663-17485-1 X-BESS-VER: 2019.1_20241018.1852 X-BESS-Apparent-Source-IP: 104.47.30.108 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVmYWlkZAVgZQMDEl1TQx0dTMxC jNMCk5JTnZxNDU0izZ2CAxMSXJItFSqTYWABnGg75BAAAA X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.259903 [from cloudscan12-62.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Oleksandr Kolomeiets fpga map was extended with STA module support which enable statistics functionality. Signed-off-by: Oleksandr Kolomeiets --- .../supported/nthw_fpga_9563_055_049_0000.c | 92 ++++++++++++++++++- .../nthw/supported/nthw_fpga_mod_str_map.c | 1 + .../nthw/supported/nthw_fpga_reg_defs_sta.h | 8 ++ 3 files changed, 100 insertions(+), 1 deletion(-) diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c index a3d9f94fc6..efdb084cd6 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c @@ -2486,6 +2486,95 @@ static nthw_fpga_register_init_s slc_registers[] = { { SLC_RCP_DATA, 1, 36, NTHW_FPGA_REG_TYPE_WO, 0, 7, slc_rcp_data_fields }, }; +static nthw_fpga_field_init_s sta_byte_fields[] = { + { STA_BYTE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_cfg_fields[] = { + { STA_CFG_CNT_CLEAR, 1, 1, 0 }, + { STA_CFG_DMA_ENA, 1, 0, 0 }, +}; + +static nthw_fpga_field_init_s sta_cv_err_fields[] = { + { STA_CV_ERR_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_fcs_err_fields[] = { + { STA_FCS_ERR_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_host_adr_lsb_fields[] = { + { STA_HOST_ADR_LSB_LSB, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s sta_host_adr_msb_fields[] = { + { STA_HOST_ADR_MSB_MSB, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s sta_load_bin_fields[] = { + { STA_LOAD_BIN_BIN, 32, 0, 8388607 }, +}; + +static nthw_fpga_field_init_s sta_load_bps_rx_0_fields[] = { + { STA_LOAD_BPS_RX_0_BPS, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_load_bps_rx_1_fields[] = { + { STA_LOAD_BPS_RX_1_BPS, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_load_bps_tx_0_fields[] = { + { STA_LOAD_BPS_TX_0_BPS, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_load_bps_tx_1_fields[] = { + { STA_LOAD_BPS_TX_1_BPS, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_load_pps_rx_0_fields[] = { + { STA_LOAD_PPS_RX_0_PPS, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_load_pps_rx_1_fields[] = { + { STA_LOAD_PPS_RX_1_PPS, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_load_pps_tx_0_fields[] = { + { STA_LOAD_PPS_TX_0_PPS, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_load_pps_tx_1_fields[] = { + { STA_LOAD_PPS_TX_1_PPS, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_pckt_fields[] = { + { STA_PCKT_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s sta_status_fields[] = { + { STA_STATUS_STAT_TOGGLE_MISSED, 1, 0, 0x0000 }, +}; + +static nthw_fpga_register_init_s sta_registers[] = { + { STA_BYTE, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_byte_fields }, + { STA_CFG, 0, 2, NTHW_FPGA_REG_TYPE_RW, 0, 2, sta_cfg_fields }, + { STA_CV_ERR, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_cv_err_fields }, + { STA_FCS_ERR, 6, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_fcs_err_fields }, + { STA_HOST_ADR_LSB, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, sta_host_adr_lsb_fields }, + { STA_HOST_ADR_MSB, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, sta_host_adr_msb_fields }, + { STA_LOAD_BIN, 8, 32, NTHW_FPGA_REG_TYPE_WO, 8388607, 1, sta_load_bin_fields }, + { STA_LOAD_BPS_RX_0, 11, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_bps_rx_0_fields }, + { STA_LOAD_BPS_RX_1, 13, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_bps_rx_1_fields }, + { STA_LOAD_BPS_TX_0, 15, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_bps_tx_0_fields }, + { STA_LOAD_BPS_TX_1, 17, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_bps_tx_1_fields }, + { STA_LOAD_PPS_RX_0, 10, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_pps_rx_0_fields }, + { STA_LOAD_PPS_RX_1, 12, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_pps_rx_1_fields }, + { STA_LOAD_PPS_TX_0, 14, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_pps_tx_0_fields }, + { STA_LOAD_PPS_TX_1, 16, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_load_pps_tx_1_fields }, + { STA_PCKT, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, sta_pckt_fields }, + { STA_STATUS, 7, 1, NTHW_FPGA_REG_TYPE_RC1, 0, 1, sta_status_fields }, +}; + static nthw_fpga_module_init_s fpga_modules[] = { { MOD_CAT, 0, MOD_CAT, 0, 21, NTHW_FPGA_BUS_TYPE_RAB1, 768, 34, cat_registers }, { MOD_CSU, 0, MOD_CSU, 0, 0, NTHW_FPGA_BUS_TYPE_RAB1, 9728, 2, csu_registers }, @@ -2537,6 +2626,7 @@ static nthw_fpga_module_init_s fpga_modules[] = { { MOD_TX_CPY, 0, MOD_CPY, 0, 4, NTHW_FPGA_BUS_TYPE_RAB1, 9216, 26, cpy_registers }, { MOD_TX_INS, 0, MOD_INS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB1, 8704, 2, ins_registers }, { MOD_TX_RPL, 0, MOD_RPL, 0, 4, NTHW_FPGA_BUS_TYPE_RAB1, 8960, 6, rpl_registers }, + { MOD_STA, 0, MOD_STA, 0, 9, NTHW_FPGA_BUS_TYPE_RAB0, 2048, 17, sta_registers }, }; static nthw_fpga_prod_param_s product_parameters[] = { @@ -2695,5 +2785,5 @@ static nthw_fpga_prod_param_s product_parameters[] = { }; nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = { - 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 35, fpga_modules, + 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 36, fpga_modules, }; diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c index 150b9dd976..a2ab266931 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c @@ -19,5 +19,6 @@ const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[] = { { MOD_RAC, "RAC" }, { MOD_RST9563, "RST9563" }, { MOD_SDC, "SDC" }, + { MOD_STA, "STA" }, { 0UL, NULL } }; diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h index 640ffcbc52..0cd183fcaa 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sta.h @@ -7,11 +7,17 @@ #define _NTHW_FPGA_REG_DEFS_STA_ /* STA */ +#define STA_BYTE (0xa08364d4UL) +#define STA_BYTE_CNT (0x3119e6bcUL) #define STA_CFG (0xcecaf9f4UL) #define STA_CFG_CNT_CLEAR (0xc325e12eUL) #define STA_CFG_CNT_FRZ (0x8c27a596UL) #define STA_CFG_DMA_ENA (0x940dbacUL) #define STA_CFG_TX_DISABLE (0x30f43250UL) +#define STA_CV_ERR (0x7db7db5dUL) +#define STA_CV_ERR_CNT (0x2c02fbbeUL) +#define STA_FCS_ERR (0xa0de1647UL) +#define STA_FCS_ERR_CNT (0xc68c37d1UL) #define STA_HOST_ADR_LSB (0xde569336UL) #define STA_HOST_ADR_LSB_LSB (0xb6f2f94bUL) #define STA_HOST_ADR_MSB (0xdf94f901UL) @@ -34,6 +40,8 @@ #define STA_LOAD_PPS_TX_0_PPS (0x788a7a7bUL) #define STA_LOAD_PPS_TX_1 (0xd37d1c89UL) #define STA_LOAD_PPS_TX_1_PPS (0x45ea53cbUL) +#define STA_PCKT (0xecc8f30aUL) +#define STA_PCKT_CNT (0x63291d16UL) #define STA_STATUS (0x91c5c51cUL) #define STA_STATUS_STAT_TOGGLE_MISSED (0xf7242b11UL) -- 2.45.0