From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E285D45BD6; Fri, 25 Oct 2024 14:31:02 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA66E4067C; Fri, 25 Oct 2024 14:30:30 +0200 (CEST) Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C3CFB402EB for ; Fri, 25 Oct 2024 14:30:21 +0200 (CEST) Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49PAs7xa020321; Fri, 25 Oct 2024 05:30:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=D BCOKEZmNgiToCSlkrMtJBAZQPhvCU3/4z7QPudQEuw=; b=eQYsMcagsyReGzNrv OVEVkSmM2kxK9CRRb9bkHMsnOQuTjP+Z1HP+MYd5SSxL5iQnRc5dYesVz2HhE1m5 v8mubugHndnIOM/wNZJNr+MC8+XzCZMn5exH0M2rKHDo9kb1lbwWWbpYZC167H2H VLQrR3KZbrwWGJf7qWZYdh1wiLkRQ8limEM/RRenYNFCWfGx+D08nuWE79Gcq8X7 psB9tOhU+nbreLl/L9QtbXPXaUSN2LhkxLTqYdZ114PFA8CRRwfLZY1E73wEO72V Uoq0oe+k6UPV8mOvDsYKdoUZnJHqkpKk4LhMQ1/YQnKJTAj6oU5Ws599/mgYUREH WADfA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42g9y584qn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 05:30:20 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 05:30:19 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 05:30:19 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 171B63F709F; Fri, 25 Oct 2024 05:30:15 -0700 (PDT) From: To: , , , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH v6 11/22] event/cnxk: add CN20K event port preschedule Date: Fri, 25 Oct 2024 17:59:33 +0530 Message-ID: <20241025122944.27745-11-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025122944.27745-1-pbhagavatula@marvell.com> References: <20241025081353.25759-1-pbhagavatula@marvell.com> <20241025122944.27745-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: xkiQuldWqkt4OSX9jO4lf0rIFJ1gsYZF X-Proofpoint-ORIG-GUID: xkiQuldWqkt4OSX9jO4lf0rIFJ1gsYZF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add CN20K event port preschedule modify and preschedule functions. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/hw/ssow.h | 1 + drivers/event/cnxk/cn20k_eventdev.c | 2 ++ drivers/event/cnxk/cn20k_worker.c | 30 +++++++++++++++++++++++++++++ drivers/event/cnxk/cn20k_worker.h | 3 +++ 4 files changed, 36 insertions(+) diff --git a/drivers/common/cnxk/hw/ssow.h b/drivers/common/cnxk/hw/ssow.h index c146a8c3ef..ec6bd7896b 100644 --- a/drivers/common/cnxk/hw/ssow.h +++ b/drivers/common/cnxk/hw/ssow.h @@ -37,6 +37,7 @@ #define SSOW_LF_GWS_PRF_WQE1 (0x448ull) /* [CN10K, .) */ #define SSOW_LF_GWS_OP_GET_WORK0 (0x600ull) #define SSOW_LF_GWS_OP_GET_WORK1 (0x608ull) /* [CN10K, .) */ +#define SSOW_LF_GWS_OP_PRF_GETWORK (0x610ull) /* [CN20K, .) */ #define SSOW_LF_GWS_OP_SWTAG_FLUSH (0x800ull) #define SSOW_LF_GWS_OP_SWTAG_UNTAG (0x810ull) #define SSOW_LF_GWS_OP_SWTP_CLR (0x820ull) diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c index 53b0b43199..a788eeed63 100644 --- a/drivers/event/cnxk/cn20k_eventdev.c +++ b/drivers/event/cnxk/cn20k_eventdev.c @@ -125,6 +125,8 @@ cn20k_sso_fp_fns_set(struct rte_eventdev *event_dev) event_dev->dequeue_burst = cn20k_sso_hws_tmo_deq_burst; event_dev->profile_switch = cn20k_sso_hws_profile_switch; + event_dev->preschedule_modify = cn20k_sso_hws_preschedule_modify; + event_dev->preschedule = cn20k_sso_hws_preschedule; #else RTE_SET_USED(event_dev); #endif diff --git a/drivers/event/cnxk/cn20k_worker.c b/drivers/event/cnxk/cn20k_worker.c index 2c723523d2..ebfe863bc5 100644 --- a/drivers/event/cnxk/cn20k_worker.c +++ b/drivers/event/cnxk/cn20k_worker.c @@ -394,6 +394,36 @@ cn20k_sso_hws_profile_switch(void *port, uint8_t profile) return 0; } +int __rte_hot +cn20k_sso_hws_preschedule_modify(void *port, enum rte_event_dev_preschedule_type type) +{ + struct cn20k_sso_hws *ws = port; + + ws->gw_wdata &= ~(BIT(19) | BIT(20)); + switch (type) { + default: + case RTE_EVENT_PRESCHEDULE_NONE: + break; + case RTE_EVENT_PRESCHEDULE: + ws->gw_wdata |= BIT(19); + break; + case RTE_EVENT_PRESCHEDULE_ADAPTIVE: + ws->gw_wdata |= BIT(19) | BIT(20); + break; + } + + return 0; +} + +void __rte_hot +cn20k_sso_hws_preschedule(void *port, enum rte_event_dev_preschedule_type type) +{ + struct cn20k_sso_hws *ws = port; + + RTE_SET_USED(type); + plt_write64(ws->gw_wdata, ws->base + SSOW_LF_GWS_OP_PRF_GETWORK); +} + uint16_t __rte_hot cn20k_sso_hws_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks) { diff --git a/drivers/event/cnxk/cn20k_worker.h b/drivers/event/cnxk/cn20k_worker.h index 447f28f0f2..dd8b72bc53 100644 --- a/drivers/event/cnxk/cn20k_worker.h +++ b/drivers/event/cnxk/cn20k_worker.h @@ -146,6 +146,9 @@ uint16_t __rte_hot cn20k_sso_hws_enq_new_burst(void *port, const struct rte_even uint16_t __rte_hot cn20k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[], uint16_t nb_events); int __rte_hot cn20k_sso_hws_profile_switch(void *port, uint8_t profile); +int __rte_hot cn20k_sso_hws_preschedule_modify(void *port, + enum rte_event_dev_preschedule_type type); +void __rte_hot cn20k_sso_hws_preschedule(void *port, enum rte_event_dev_preschedule_type type); uint16_t __rte_hot cn20k_sso_hws_deq(void *port, struct rte_event *ev, uint64_t timeout_ticks); uint16_t __rte_hot cn20k_sso_hws_deq_burst(void *port, struct rte_event ev[], uint16_t nb_events, -- 2.25.1