From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 137E045BD6; Fri, 25 Oct 2024 15:06:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E4C3740A76; Fri, 25 Oct 2024 15:05:59 +0200 (CEST) Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id BFE1E40A81 for ; Fri, 25 Oct 2024 15:04:21 +0200 (CEST) Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49PAqBXS017656; Fri, 25 Oct 2024 06:04:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=L mVo8otYCdcZ049OmsX78cs+5jFSECrFq7XZ0myAnVs=; b=X9eyWJGMkKSXyOo/I MdQeEs+QUojDdw+gfTAq7/qas5QFua4IjBYEYOi7SqIFnDiGxUh/RGTy5pJ3uiUm 548iLBXvEF4Nqi0h8+0aHT77x6D31/KJl+EJofM+JBSnishc3g5+mIwSFC0riC98 mhUluOh0MmytcyM3Z7MzFQu3RaC9ibpLwC86jnDnk2dpVP0aCNOo7TwrjBTZihgk wb/sjnbAFyoIHeonOwXy3kA+egqZFLZGP80IhgOrPbtoSGfp8ecgYB4mFHf2i+6I CSJcLqeXxep7/hRXAH+cIqnuDVDVc2G0grbTepwEtv67uSu5WmyJdr506KWk+wKJ BgngQ== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42g9y586sx-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 06:04:20 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 06:04:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 06:04:18 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 2AC283F70A2; Fri, 25 Oct 2024 06:04:14 -0700 (PDT) From: To: , , , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Pavan Nikhilesh Subject: [PATCH v7 19/22] common/cnxk: add SSO event aggregator Date: Fri, 25 Oct 2024 18:33:18 +0530 Message-ID: <20241025130321.29105-19-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025130321.29105-1-pbhagavatula@marvell.com> References: <20241025122944.27745-1-pbhagavatula@marvell.com> <20241025130321.29105-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: ngz5hoENKunmWZ4fNIFmKsgZ8Zfu5WEO X-Proofpoint-ORIG-GUID: ngz5hoENKunmWZ4fNIFmKsgZ8Zfu5WEO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add configuration APIs for CN20K SSO event aggregator which allows SSO to generate event vectors. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/hw/sso.h | 33 ++++ drivers/common/cnxk/roc_mbox.h | 21 +++ drivers/common/cnxk/roc_model.h | 13 ++ drivers/common/cnxk/roc_nix_queue.c | 5 - drivers/common/cnxk/roc_sso.c | 230 +++++++++++++++++++++++++++- drivers/common/cnxk/roc_sso.h | 19 ++- drivers/common/cnxk/roc_sso_priv.h | 4 + drivers/common/cnxk/version.map | 4 + 8 files changed, 321 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/hw/sso.h b/drivers/common/cnxk/hw/sso.h index 09b8d4955f..79337a8a3b 100644 --- a/drivers/common/cnxk/hw/sso.h +++ b/drivers/common/cnxk/hw/sso.h @@ -146,6 +146,7 @@ #define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull) #define SSO_LF_GGRP_OP_ADD_WORK1 (0x8ull) #define SSO_LF_GGRP_QCTL (0x20ull) +#define SSO_LF_GGRP_TAG_CFG (0x40ull) #define SSO_LF_GGRP_EXE_DIS (0x80ull) #define SSO_LF_GGRP_INT (0x100ull) #define SSO_LF_GGRP_INT_W1S (0x108ull) @@ -159,6 +160,10 @@ #define SSO_LF_GGRP_MISC_CNT (0x200ull) #define SSO_LF_GGRP_OP_AW_LMTST (0x400ull) +#define SSO_LF_GGRP_AGGR_CFG (0x300ull) +#define SSO_LF_GGRP_AGGR_CTX_BASE (0x308ull) +#define SSO_LF_GGRP_AGGR_CTX_INSTOP (0x310ull) + #define SSO_AF_IAQ_FREE_CNT_MASK 0x3FFFull #define SSO_AF_IAQ_RSVD_FREE_MASK 0x3FFFull #define SSO_AF_IAQ_RSVD_FREE_SHIFT 16 @@ -230,5 +235,33 @@ #define SSO_TT_ATOMIC (0x1ull) #define SSO_TT_UNTAGGED (0x2ull) #define SSO_TT_EMPTY (0x3ull) +#define SSO_TT_AGG (0x3ull) + +#define SSO_LF_AGGR_INSTOP_FLUSH (0x0ull) +#define SSO_LF_AGGR_INSTOP_EVICT (0x1ull) +#define SSO_LF_AGGR_INSTOP_GLOBAL_FLUSH (0x2ull) +#define SSO_LF_AGGR_INSTOP_GLOBAL_EVICT (0x3ull) + +#define SSO_AGGR_CTX_SZ 16 +#define SSO_AGGR_NUM_CTX(a) (1 << (a + 6)) +#define SSO_AGGR_MIN_CTX SSO_AGGR_NUM_CTX(0) +#define SSO_AGGR_MAX_CTX SSO_AGGR_NUM_CTX(10) +#define SSO_AGGR_DEF_TMO 0x3Full + +struct sso_agq_ctx { + uint64_t ena : 1; + uint64_t rsvd_1_3 : 3; + uint64_t vwqe_aura : 17; + uint64_t rsvd_21_31 : 11; + uint64_t tag : 32; + uint64_t tt : 2; + uint64_t rsvd_66_67 : 2; + uint64_t swqe_tag : 12; + uint64_t max_vsize_exp : 4; + uint64_t vtimewait : 12; + uint64_t xqe_type : 4; + uint64_t cnt_ena : 1; + uint64_t rsvd_101_127 : 27; +}; #endif /* __SSO_HW_H__ */ diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 63139b5517..db6e8f07b3 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -147,6 +147,10 @@ struct mbox_msghdr { msg_rsp) \ M(SSO_GRP_STASH_CONFIG, 0x614, sso_grp_stash_config, \ sso_grp_stash_cfg, msg_rsp) \ + M(SSO_AGGR_SET_CONFIG, 0x615, sso_aggr_setconfig, sso_aggr_setconfig, \ + msg_rsp) \ + M(SSO_AGGR_GET_STATS, 0x616, sso_aggr_get_stats, sso_info_req, \ + sso_aggr_stats) \ M(SSO_GET_HW_INFO, 0x617, sso_get_hw_info, msg_req, sso_hw_info) \ /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \ @@ -2191,6 +2195,13 @@ struct sso_grp_stash_cfg { uint8_t __io num_linesm1 : 4; }; +struct sso_aggr_setconfig { + struct mbox_msghdr hdr; + uint16_t __io npa_pf_func; + uint16_t __io hwgrp; + uint64_t __io rsvd[2]; +}; + struct sso_grp_stats { struct mbox_msghdr hdr; uint16_t __io grp; @@ -2210,6 +2221,16 @@ struct sso_hws_stats { uint64_t __io arbitration; }; +struct sso_aggr_stats { + struct mbox_msghdr hdr; + uint16_t __io grp; + uint64_t __io flushed; + uint64_t __io completed; + uint64_t __io npa_fail; + uint64_t __io timeout; + uint64_t __io rsvd[4]; +}; + /* CPT mailbox error codes * Range 901 - 1000. */ diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index 4e686bea2c..0de141b0cc 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -8,6 +8,7 @@ #include #include "roc_bits.h" +#include "roc_constants.h" extern struct roc_model *roc_model; @@ -157,6 +158,18 @@ roc_model_is_cn20k(void) return roc_model_runtime_is_cn20k(); } +static inline uint16_t +roc_model_optimal_align_sz(void) +{ + if (roc_model_is_cn9k()) + return ROC_ALIGN; + if (roc_model_is_cn10k()) + return ROC_ALIGN; + if (roc_model_is_cn20k()) + return ROC_ALIGN << 1; + return 128; +} + static inline uint64_t roc_model_is_cn98xx(void) { diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 06029275af..e852211ba4 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -794,9 +794,6 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, boo aq->rq.good_utag = rq->tag_mask >> 24; aq->rq.bad_utag = rq->tag_mask >> 24; aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0); - - if (rq->vwqe_ena) - aq->rq.wqe_aura = roc_npa_aura_handle_to_aura(rq->vwqe_aura_handle); } else { /* CQ mode */ aq->rq.sso_ena = 0; @@ -881,8 +878,6 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg, boo aq->rq_mask.good_utag = ~aq->rq_mask.good_utag; aq->rq_mask.bad_utag = ~aq->rq_mask.bad_utag; aq->rq_mask.ltag = ~aq->rq_mask.ltag; - if (rq->vwqe_ena) - aq->rq_mask.wqe_aura = ~aq->rq_mask.wqe_aura; } else { /* CQ mode */ aq->rq_mask.sso_ena = ~aq->rq_mask.sso_ena; diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 45cf6fc39e..4996329018 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -500,9 +500,231 @@ roc_sso_hws_gwc_invalidate(struct roc_sso *roc_sso, uint8_t *hws, mbox_put(mbox); } +static void +sso_agq_op_wait(struct roc_sso *roc_sso, uint16_t hwgrp) +{ + uint64_t reg; + + reg = plt_read64(roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CTX_INSTOP); + while (reg & BIT_ULL(2)) { + plt_delay_us(100); + reg = plt_read64(roc_sso_hwgrp_base_get(roc_sso, hwgrp) + + SSO_LF_GGRP_AGGR_CTX_INSTOP); + } +} + +int +roc_sso_hwgrp_agq_alloc(struct roc_sso *roc_sso, uint16_t hwgrp, struct roc_sso_agq_data *data) +{ + struct sso *sso = roc_sso_to_sso_priv(roc_sso); + struct sso_aggr_setconfig *req; + struct sso_agq_ctx *ctx; + uint32_t cnt, off; + struct mbox *mbox; + uintptr_t ptr; + uint64_t reg; + int rc; + + if (sso->agg_mem[hwgrp] == 0) { + mbox = mbox_get(sso->dev.mbox); + req = mbox_alloc_msg_sso_aggr_setconfig(mbox); + if (req == NULL) { + mbox_process(mbox); + req = mbox_alloc_msg_sso_aggr_setconfig(mbox); + if (req == NULL) { + plt_err("Failed to allocate AGQ config mbox."); + mbox_put(mbox); + return -EIO; + } + } + + req->hwgrp = hwgrp; + req->npa_pf_func = idev_npa_pffunc_get(); + rc = mbox_process(mbox); + if (rc < 0) { + plt_err("Failed to set HWGRP AGQ config rc=%d", rc); + mbox_put(mbox); + return rc; + } + + mbox_put(mbox); + + sso->agg_mem[hwgrp] = + (uintptr_t)plt_zmalloc(SSO_AGGR_MIN_CTX * sizeof(struct sso_agq_ctx), + roc_model_optimal_align_sz()); + if (sso->agg_mem[hwgrp] == 0) + return -ENOMEM; + sso->agg_cnt[hwgrp] = SSO_AGGR_MIN_CTX; + sso->agg_used[hwgrp] = 0; + plt_wmb(); + plt_write64(sso->agg_mem[hwgrp], + roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CTX_BASE); + reg = (plt_log2_u32(SSO_AGGR_MIN_CTX) - 6) << 16; + reg |= (SSO_AGGR_DEF_TMO << 4) | 1; + plt_write64(reg, roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CFG); + } + + if (sso->agg_cnt[hwgrp] >= SSO_AGGR_MAX_CTX) + return -ENOSPC; + + if (sso->agg_cnt[hwgrp] == sso->agg_used[hwgrp]) { + ptr = sso->agg_mem[hwgrp]; + cnt = sso->agg_cnt[hwgrp] << 1; + sso->agg_mem[hwgrp] = (uintptr_t)plt_zmalloc(cnt * sizeof(struct sso_agq_ctx), + roc_model_optimal_align_sz()); + if (sso->agg_mem[hwgrp] == 0) { + sso->agg_mem[hwgrp] = ptr; + return -ENOMEM; + } + + memcpy((void *)sso->agg_mem[hwgrp], (void *)ptr, + sso->agg_cnt[hwgrp] * sizeof(struct sso_agq_ctx)); + plt_wmb(); + sso_agq_op_wait(roc_sso, hwgrp); + /* Base address has changed, evict old entries. */ + plt_write64(sso->agg_mem[hwgrp], + roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CTX_BASE); + reg = plt_read64(roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CFG); + reg &= ~GENMASK_ULL(19, 16); + reg |= (uint64_t)(plt_log2_u32(cnt) - 6) << 16; + plt_write64(reg, roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CFG); + reg = SSO_LF_AGGR_INSTOP_GLOBAL_EVICT << 4; + plt_write64(reg, + roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CTX_INSTOP); + sso_agq_op_wait(roc_sso, hwgrp); + plt_free((void *)ptr); + + sso->agg_cnt[hwgrp] = cnt; + off = sso->agg_used[hwgrp]; + } else { + ctx = (struct sso_agq_ctx *)sso->agg_mem[hwgrp]; + for (cnt = 0; cnt < sso->agg_cnt[hwgrp]; cnt++) { + if (!ctx[cnt].ena) + break; + } + if (cnt == sso->agg_cnt[hwgrp]) + return -EINVAL; + off = cnt; + } + + ctx = (struct sso_agq_ctx *)sso->agg_mem[hwgrp]; + ctx += off; + ctx->ena = 1; + ctx->tt = data->tt; + ctx->tag = data->tag; + ctx->swqe_tag = data->stag; + ctx->cnt_ena = data->cnt_ena; + ctx->xqe_type = data->xqe_type; + ctx->vtimewait = data->vwqe_wait_tmo; + ctx->vwqe_aura = data->vwqe_aura; + ctx->max_vsize_exp = data->vwqe_max_sz_exp - 2; + + plt_wmb(); + sso->agg_used[hwgrp]++; + + return 0; +} + +void +roc_sso_hwgrp_agq_free(struct roc_sso *roc_sso, uint16_t hwgrp, uint32_t agq_id) +{ + struct sso *sso = roc_sso_to_sso_priv(roc_sso); + struct sso_agq_ctx *ctx; + uint64_t reg; + + ctx = (struct sso_agq_ctx *)sso->agg_mem[hwgrp]; + ctx += agq_id; + + if (!ctx->ena) + return; + + reg = SSO_LF_AGGR_INSTOP_FLUSH << 4; + reg |= (uint64_t)(agq_id << 8); + + plt_write64(reg, roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CTX_INSTOP); + sso_agq_op_wait(roc_sso, hwgrp); + + memset(ctx, 0, sizeof(struct sso_agq_ctx)); + plt_wmb(); + sso->agg_used[hwgrp]--; + + /* Flush the context from CTX Cache */ + reg = SSO_LF_AGGR_INSTOP_EVICT << 4; + reg |= (uint64_t)(agq_id << 8); + + plt_write64(reg, roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CTX_INSTOP); + sso_agq_op_wait(roc_sso, hwgrp); +} + +void +roc_sso_hwgrp_agq_release(struct roc_sso *roc_sso, uint16_t hwgrp) +{ + struct sso *sso = roc_sso_to_sso_priv(roc_sso); + struct sso_aggr_setconfig *req; + struct sso_agq_ctx *ctx; + struct mbox *mbox; + uint32_t cnt; + int rc; + + if (!roc_sso->feat.eva_present) + return; + + plt_write64(0, roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CFG); + ctx = (struct sso_agq_ctx *)sso->agg_mem[hwgrp]; + for (cnt = 0; cnt < sso->agg_cnt[hwgrp]; cnt++) { + if (!ctx[cnt].ena) + continue; + roc_sso_hwgrp_agq_free(roc_sso, hwgrp, cnt); + } + + plt_write64(0, roc_sso_hwgrp_base_get(roc_sso, hwgrp) + SSO_LF_GGRP_AGGR_CTX_BASE); + plt_free((void *)sso->agg_mem[hwgrp]); + sso->agg_mem[hwgrp] = 0; + sso->agg_cnt[hwgrp] = 0; + sso->agg_used[hwgrp] = 0; + + mbox = mbox_get(sso->dev.mbox); + req = mbox_alloc_msg_sso_aggr_setconfig(mbox); + if (req == NULL) { + mbox_process(mbox); + req = mbox_alloc_msg_sso_aggr_setconfig(mbox); + if (req == NULL) { + plt_err("Failed to allocate AGQ config mbox."); + mbox_put(mbox); + return; + } + } + + req->hwgrp = hwgrp; + req->npa_pf_func = 0; + rc = mbox_process(mbox); + if (rc < 0) + plt_err("Failed to set HWGRP AGQ config rc=%d", rc); + mbox_put(mbox); +} + +uint32_t +roc_sso_hwgrp_agq_from_tag(struct roc_sso *roc_sso, uint16_t hwgrp, uint32_t tag_mask, + uint8_t xqe_type) +{ + struct sso *sso = roc_sso_to_sso_priv(roc_sso); + struct sso_agq_ctx *ctx; + uint32_t i; + + plt_rmb(); + ctx = (struct sso_agq_ctx *)sso->agg_mem[hwgrp]; + for (i = 0; i < sso->agg_used[hwgrp]; i++) { + if (!ctx[i].ena) + continue; + if (ctx[i].tag == tag_mask && ctx[i].xqe_type == xqe_type) + return i; + } + + return UINT32_MAX; +} + int -roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp, - struct roc_sso_hwgrp_stats *stats) +roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint16_t hwgrp, struct roc_sso_hwgrp_stats *stats) { struct sso *sso = roc_sso_to_sso_priv(roc_sso); struct sso_grp_stats *req_rsp; @@ -1058,10 +1280,14 @@ void roc_sso_rsrc_fini(struct roc_sso *roc_sso) { struct sso *sso = roc_sso_to_sso_priv(roc_sso); + uint32_t cnt; if (!roc_sso->nb_hws && !roc_sso->nb_hwgrp) return; + for (cnt = 0; cnt < roc_sso->nb_hwgrp; cnt++) + roc_sso_hwgrp_agq_release(roc_sso, cnt); + sso_unregister_irqs_priv(roc_sso, sso->pci_dev->intr_handle, roc_sso->nb_hws, roc_sso->nb_hwgrp); sso_lf_free(&sso->dev, SSO_LF_TYPE_HWS, roc_sso->nb_hws); diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index 021db22c86..f73128087a 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -47,6 +47,17 @@ struct roc_sso_xaq_data { void *mem; }; +struct roc_sso_agq_data { + uint8_t tt; + uint8_t cnt_ena; + uint8_t xqe_type; + uint16_t stag; + uint32_t tag; + uint32_t vwqe_max_sz_exp; + uint64_t vwqe_wait_tmo; + uint64_t vwqe_aura; +}; + struct roc_sso { struct plt_pci_device *pci_dev; /* Public data. */ @@ -100,6 +111,12 @@ int __roc_api roc_sso_hwgrp_stash_config(struct roc_sso *roc_sso, uint16_t nb_stash); void __roc_api roc_sso_hws_gwc_invalidate(struct roc_sso *roc_sso, uint8_t *hws, uint8_t nb_hws); +int __roc_api roc_sso_hwgrp_agq_alloc(struct roc_sso *roc_sso, uint16_t hwgrp, + struct roc_sso_agq_data *data); +void __roc_api roc_sso_hwgrp_agq_free(struct roc_sso *roc_sso, uint16_t hwgrp, uint32_t agq_id); +void __roc_api roc_sso_hwgrp_agq_release(struct roc_sso *roc_sso, uint16_t hwgrp); +uint32_t __roc_api roc_sso_hwgrp_agq_from_tag(struct roc_sso *roc_sso, uint16_t hwgrp, uint32_t tag, + uint8_t xqe_type); /* Utility function */ uint16_t __roc_api roc_sso_pf_func_get(void); @@ -107,7 +124,7 @@ uint16_t __roc_api roc_sso_pf_func_get(void); /* Debug */ void __roc_api roc_sso_dump(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t hwgrp, FILE *f); -int __roc_api roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp, +int __roc_api roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint16_t hwgrp, struct roc_sso_hwgrp_stats *stats); int __roc_api roc_sso_hws_stats_get(struct roc_sso *roc_sso, uint8_t hws, struct roc_sso_hws_stats *stats); diff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h index 21c59c57e6..d6dc6dedd3 100644 --- a/drivers/common/cnxk/roc_sso_priv.h +++ b/drivers/common/cnxk/roc_sso_priv.h @@ -13,6 +13,10 @@ struct sso_rsrc { struct sso { struct plt_pci_device *pci_dev; struct dev dev; + /* EVA memory area */ + uintptr_t agg_mem[MAX_RVU_BLKLF_CNT]; + uint32_t agg_used[MAX_RVU_BLKLF_CNT]; + uint32_t agg_cnt[MAX_RVU_BLKLF_CNT]; /* Interrupt handler args. */ struct sso_rsrc hws_rsrc[MAX_RVU_BLKLF_CNT]; struct sso_rsrc hwgrp_rsrc[MAX_RVU_BLKLF_CNT]; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index de748ac409..14ee6031e2 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -500,6 +500,10 @@ INTERNAL { roc_sso_dev_fini; roc_sso_dev_init; roc_sso_dump; + roc_sso_hwgrp_agq_alloc; + roc_sso_hwgrp_agq_free; + roc_sso_hwgrp_agq_from_tag; + roc_sso_hwgrp_agq_release; roc_sso_hwgrp_alloc_xaq; roc_sso_hwgrp_base_get; roc_sso_hwgrp_free_xaq_aura; -- 2.25.1