From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4CE1C45BD6; Fri, 25 Oct 2024 15:04:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 759EC4066E; Fri, 25 Oct 2024 15:04:11 +0200 (CEST) Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 717394065F for ; Fri, 25 Oct 2024 15:03:41 +0200 (CEST) Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49PAs71E020321; Fri, 25 Oct 2024 06:03:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=8 NFeMCX7XX8GLfQESynFR7kGAeu68tNw78brtKNKh60=; b=Zfb5FYGjiYRxb5OFC hASKtUGJdlGDrB25FoLFjO146Ilh4USPraZ/IvSeW79Utq/4JWoUcoLS6Q3q5qnJ szR9jV5Vtmw3e9EuQDxCUDzFZJnQv7YLRy3Ul11pBUxSAtLZ9pTtBbm+9xuCddXD fxs7YFfp1c8+mTVOrtAp4t86cp1PgN1KMr0VXRFgMRS0XfBW414tpIcns7Kwr3Ga EaodhqD2w8n5yTxVYqfQdgms7JpwPRBewriGn+tBJt01SROiqOuAZQjvrmAWo6jQ H7xqUNUU6IiVxWUE7jPm8DoVHvLi68fQZCbBXQILjAnnev2ra1d+Ds8BhUV30nB6 Aa/HA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 42g9y586r8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Oct 2024 06:03:40 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 06:03:39 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 06:03:39 -0700 Received: from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com [10.28.164.106]) by maili.marvell.com (Postfix) with ESMTP id 5C3023F7090; Fri, 25 Oct 2024 06:03:37 -0700 (PDT) From: To: , , , Pavan Nikhilesh , Shijith Thotton CC: Subject: [PATCH v7 05/22] event/cnxk: add CN20k event queue configuration Date: Fri, 25 Oct 2024 18:33:04 +0530 Message-ID: <20241025130321.29105-5-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241025130321.29105-1-pbhagavatula@marvell.com> References: <20241025122944.27745-1-pbhagavatula@marvell.com> <20241025130321.29105-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: f5maO1vuJU-MaB7zDqQY-YI0g9vZ-J5g X-Proofpoint-ORIG-GUID: f5maO1vuJU-MaB7zDqQY-YI0g9vZ-J5g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Add setup and release functions for event queues i.e. SSO HWGRPs. Allocate buffers in DRAM that hold inflight events. Register device args to modify inflight event buffer count, HWGRP QoS and stash. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 2 +- drivers/event/cnxk/cn20k_eventdev.c | 14 ++++++++++++++ drivers/event/cnxk/cnxk_eventdev.c | 4 ++-- drivers/event/cnxk/cnxk_eventdev.h | 2 +- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index c7af0fac11..49805dd91d 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -1251,7 +1251,7 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" CNXK_SSO_FORCE_BP "=1" - CN10K_SSO_STASH "=" + CNXK_SSO_STASH "=" CNXK_TIM_DISABLE_NPA "=1" CNXK_TIM_CHNK_SLOTS "=" CNXK_TIM_RINGS_LMT "=" diff --git a/drivers/event/cnxk/cn20k_eventdev.c b/drivers/event/cnxk/cn20k_eventdev.c index 753a976cd3..b876c36806 100644 --- a/drivers/event/cnxk/cn20k_eventdev.c +++ b/drivers/event/cnxk/cn20k_eventdev.c @@ -56,6 +56,12 @@ cn20k_sso_dev_configure(const struct rte_eventdev *event_dev) return -ENODEV; } + rc = cnxk_sso_xaq_allocate(dev); + if (rc < 0) + goto cnxk_rsrc_fini; + +cnxk_rsrc_fini: + roc_sso_rsrc_fini(&dev->sso); return rc; } @@ -64,6 +70,10 @@ static struct eventdev_ops cn20k_sso_dev_ops = { .dev_configure = cn20k_sso_dev_configure, .queue_def_conf = cnxk_sso_queue_def_conf, + .queue_setup = cnxk_sso_queue_setup, + .queue_release = cnxk_sso_queue_release, + .queue_attr_set = cnxk_sso_queue_attribute_set, + .port_def_conf = cnxk_sso_port_def_conf, }; @@ -127,3 +137,7 @@ static struct rte_pci_driver cn20k_pci_sso = { RTE_PMD_REGISTER_PCI(event_cn20k, cn20k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn20k, cn20k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn20k, "vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(event_cn20k, + CNXK_SSO_XAE_CNT "=" + CNXK_SSO_GGRP_QOS "=" + CNXK_SSO_STASH "="); diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index ab7420ab79..be6a487b59 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -624,8 +624,8 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) &dev->force_ena_bp); rte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_flag, &single_ws); - rte_kvargs_process(kvlist, CN10K_SSO_STASH, - &parse_sso_kvargs_stash_dict, dev); + rte_kvargs_process(kvlist, CNXK_SSO_STASH, &parse_sso_kvargs_stash_dict, + dev); dev->dual_ws = !single_ws; rte_kvargs_free(kvlist); } diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 904a9b022d..ba08fa2173 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -27,7 +27,7 @@ #define CNXK_SSO_GGRP_QOS "qos" #define CNXK_SSO_FORCE_BP "force_rx_bp" #define CN9K_SSO_SINGLE_WS "single_ws" -#define CN10K_SSO_STASH "stash" +#define CNXK_SSO_STASH "stash" #define CNXK_SSO_MAX_PROFILES 2 -- 2.25.1