From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F190045C0B; Tue, 29 Oct 2024 14:44:37 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A5BEE42E85; Tue, 29 Oct 2024 14:44:22 +0100 (CET) Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2045.outbound.protection.outlook.com [40.107.92.45]) by mails.dpdk.org (Postfix) with ESMTP id 3118F42E98 for ; Tue, 29 Oct 2024 14:44:06 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=StpK2Tuf2EDt8JSZivUutVgf6xHnd89mk8l80Kt9aTakRGuS9fOYbe/yVJvbrQtmy1pUgKMpnhwerhlooL1roL/6DvpZtN/0flpYKNV+OwWpAjv6lWpP+SCtZz/6ZNz/604STtpkV/wUIjw2LcBZzxAnTrNn9PGGATcpGgrKlgKkinrep8XTff/bwluhSCLQjaruLTxI3As/xb5sYrtHW1Lk3rR3YYTVPW81DEsZQeJJc6MxxTIg6/N03QpXgfIeCrA4F57J8flJHg0RrsmCKdMUKlJqnx87lHexsfgBB4sVAIzxr7lMcpkEafeuePj0xkhVVhEkDFr8aozY4aF8Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xLDr2buUNtE+Uyii/EuXeFTjM7RxBJd/YQPkycZZiVs=; b=Kqih36dIhDtgX0DIP5PP2AG1Xtte48yErdx6do0z8aprrZhbj5F952aIDdNmpctT8YCBVYYvn4O6dwFtwvB5G70mLjn9um69tNiGs5sgO6Xf5VwBEn9qlCj+TpMWi5QwvDYzcf+Me1eYDtsk0HCk1by8kqAlLun9bxlrohRluF3tdMntyXiUgeMpkVVbnCuMYWqjwBWauz7+tWmPveV7EcwJop0s9TOFiHn4iYXJnczb5kNQPy+jQVrPoj7g3dNmUUdazuMaPyqCgZ6zYgm7KxPazoWWcmk63a+RYl13P7iJdbzpErJOlqYBXY8C5eIqwilxIvpt6vDJy0m4g74ETA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xLDr2buUNtE+Uyii/EuXeFTjM7RxBJd/YQPkycZZiVs=; b=XOXX2HpHRAiuDhNwloKl9nOoSABP4nF3iVO4pc7ao8aNQ9IpXNlFXXuc60FioVSIn5Q8t2+FIdYV/WfH9YmM5eNtbJadqP5/73jnT2Y7nLiFdMt8ITAx2tfHT5Hg4P1/ABsVyRq2w52J7iSXxEb6T6GEs/cAVEs0GQEiK1eh0HVgnUIZg4PTQu3Y8y5ILznC/r3mS0LaJE0NA3BhaTnnVRMnI/1lv+D2j9dhrpMNRkmjvoTs5dTUss9i84PM79+CGjLGpLMNB7F9WOmHXeugKa8+dJoRLAZ9+dhd6DYa/TuC52APP7SeCBXh23BM8/U6qDZcHnWTBWK3BW0sRqZZxQ== Received: from SJ0PR03CA0183.namprd03.prod.outlook.com (2603:10b6:a03:2ef::8) by SA1PR12MB8162.namprd12.prod.outlook.com (2603:10b6:806:33a::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.32; Tue, 29 Oct 2024 13:44:02 +0000 Received: from SJ1PEPF0000231A.namprd03.prod.outlook.com (2603:10b6:a03:2ef:cafe::f) by SJ0PR03CA0183.outlook.office365.com (2603:10b6:a03:2ef::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.25 via Frontend Transport; Tue, 29 Oct 2024 13:44:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SJ1PEPF0000231A.mail.protection.outlook.com (10.167.242.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.16 via Frontend Transport; Tue, 29 Oct 2024 13:44:01 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 06:43:37 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 29 Oct 2024 06:43:34 -0700 From: "Minggang Li(Gavin)" To: , , , , Dariusz Sosnowski , Bing Zhao , Suanming Mou CC: , Subject: [PATCH V3 7/7] mlx5: add backward compatibility for RDMA monitor Date: Tue, 29 Oct 2024 15:42:56 +0200 Message-ID: <20241029134256.874767-8-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241029134256.874767-1-gavinl@nvidia.com> References: <20241028091822.860660-8-gavinl@nvidia.com> <20241029134256.874767-1-gavinl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231A:EE_|SA1PR12MB8162:EE_ X-MS-Office365-Filtering-Correlation-Id: d8a55915-3b45-4771-03a5-08dcf81fbf61 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?geOAUpNy9myGjLFtaojwIz+3IMNqjsO72Ia/JLLKSk0e3L/Zdrsf4WDSmEUb?= =?us-ascii?Q?iRHebdvulINAdbecLIddanKd7nzTyFa5DpI5XY9JbPy2DVKGTM28ICPio+IK?= =?us-ascii?Q?YJESfg+FRWEii7TqEPH5rPk2nAZXnCNEQwPw4+hfugr8CLqLmDJqqsg8Blr+?= =?us-ascii?Q?JBDVwVYXs5PrUbngQ+bbySMk2ZiA2ggrq0/XWdOjDjywrKpP1V1Zv1Q+EzcA?= =?us-ascii?Q?OSGIIF/2ziKy3dNlOfYmWGVg1xogLZcNJiLtlwZgRwLDFXtXhhmqZAFOIXex?= =?us-ascii?Q?zJuVK1HCwUjg5U3NrjpbTZUrR9L9pfgafx6IXjDe5VKwunmgpSV3Pok3khNW?= =?us-ascii?Q?LylYmdEAwptZks7IZSmZgEAao3dXGO0GRyIx44mAR0Sa/Mn063/eolxMuZ98?= =?us-ascii?Q?wOGUw7Nga723KCkjOt8g+9TjVjfeoeTEtcmoOLxcKauZbAbMJ6k4MV02HMWa?= =?us-ascii?Q?MyzewaCC7+TfBkoHooHKnnVFzkZaUgFOhtQwZvGFv1XhujV6/oHgLM3V93pj?= =?us-ascii?Q?IliE2c5jeB+Z1E7+dcNQnUvVhcl0mCXCKfl/nrOuZmPDqTb11bRqfpWtElJt?= =?us-ascii?Q?vfmQYQ3MpcBTE29+23XtlbSVlDTLb6nOP7WK4vOHc1CY48t6Wi7x0SKhS9hi?= =?us-ascii?Q?ijMvklW2zdsdYU53Z/aMcsyTpzJs87+2svxrbh9CojpexXqb1rUunQba29Ur?= =?us-ascii?Q?9ZmLTIDe0im9txFxk375A0oRE6XPbn0puDKP1yL9jnpGkT+hyCkyYusl0SOd?= =?us-ascii?Q?3Z2N2kjmpswCPdOKqeRgUfEg9PIpu+J2UwzsRLkLrvvUIAU/Uvl1Wwm49Q36?= =?us-ascii?Q?8ZHAv1tE904OAZppwDWvhCpADcV4zupQ1+LG18+7J6YWOBlFPxowLhtF5NIg?= =?us-ascii?Q?9/SjyryI/dBDUBV/sYlWK4c/e6oRDLwUTe7od05vsoqZURrRwQXNrgPP2Lec?= =?us-ascii?Q?02mS+3B9Evc1imP5V6l0pjktoIVxX+q3cG4xav1jwFitB8Ru3q6OILuhyzXI?= =?us-ascii?Q?2QkfX1XvIh2BU0NeqHKiNXyT5GccYdBjA2bFTp4vAgKz1aaINzhVPbJlr2ZC?= =?us-ascii?Q?j8E5rPX2rk/f5mBJsq/aN+Nd3UutbnJk9bINW3zV7rZiovigd3N+NwwtGrRg?= =?us-ascii?Q?tA8S16M6fbpwL4Gn6AnNtqbcumoxuOS34NVDiFPWQZWr1CaahP6yybhQObTx?= =?us-ascii?Q?Prqk+UClRMqCK79HOCJ4/9trHq4t+DZVUT/qv9Z6SpqQjHXgFMU1Bk3O1aEO?= =?us-ascii?Q?BbHSlN+Uj1CNEd6OsoKlTnzpi3XW5dlnMBKOp48B7UwVmzjM1mTe9mn2Bf+W?= =?us-ascii?Q?54TOjXb5TCQri1IL+utmAu/s2dcdq3oBwHdV3kCPLlETwTIf4qLl3Lz5FB+y?= =?us-ascii?Q?+XDewdDbIeO2jWW5J4I5+zyOFpkNTzHC7Brfc2cPn2X3+YYX3w=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2024 13:44:01.6061 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8a55915-3b45-4771-03a5-08dcf81fbf61 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8162 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fallback to the old way to update port information if the kernel driver does not support RDMA monitor. Signed-off-by: Minggang Li(Gavin) Acked-by: Viacheslav Ovsiienko --- doc/guides/rel_notes/release_24_11.rst | 14 +++++ drivers/common/mlx5/linux/mlx5_nl.c | 73 +++++++++++++++++++++++++ drivers/common/mlx5/version.map | 1 + drivers/net/mlx5/linux/mlx5_ethdev_os.c | 2 +- drivers/net/mlx5/linux/mlx5_os.c | 27 +++++++-- drivers/net/mlx5/mlx5.h | 1 + 6 files changed, 111 insertions(+), 7 deletions(-) diff --git a/doc/guides/rel_notes/release_24_11.rst b/doc/guides/rel_notes/release_24_11.rst index fa4822d928..6fc32ff8a4 100644 --- a/doc/guides/rel_notes/release_24_11.rst +++ b/doc/guides/rel_notes/release_24_11.rst @@ -247,6 +247,20 @@ New Features Added ability for node to advertise and update multiple xstat counters, that can be retrieved using ``rte_graph_cluster_stats_get``. +* **Updated NVIDIA mlx5 driver.** + + Optimized port probe in large scale. + This feature enhances the efficiency of probing VF/SFs on a large scale + by significantly reducing the probing time. To activate this feature, + set ``probe_opt_en`` to a non-zero value during device probing. It + leverages a capability from the RDMA driver, expected to be released in + the upcoming kernel version 6.13 or its equivalent in OFED 24.10, + specifically the RDMA monitor. For additional details on the limitations + of devargs, refer to "doc/guides/nics/mlx5.rst". + + If there are lots of VFs/SFs to be probed by the application, eg, 300 + VFs/SFs, the option should be enabled to save probing time. + Removed Items ------------- diff --git a/drivers/common/mlx5/linux/mlx5_nl.c b/drivers/common/mlx5/linux/mlx5_nl.c index ce1c2a8e75..12f1a620f3 100644 --- a/drivers/common/mlx5/linux/mlx5_nl.c +++ b/drivers/common/mlx5/linux/mlx5_nl.c @@ -2152,3 +2152,76 @@ mlx5_nl_rdma_monitor_info_get(struct nlmsghdr *hdr, struct mlx5_nl_port_info *da error: rte_errno = EINVAL; } + +static int +mlx5_nl_rdma_monitor_cap_get_cb(struct nlmsghdr *hdr, void *arg) +{ + size_t off = NLMSG_HDRLEN; + uint8_t *cap = arg; + + if (hdr->nlmsg_type != RDMA_NL_GET_TYPE(RDMA_NL_NLDEV, RDMA_NLDEV_CMD_SYS_GET)) + goto error; + + *cap = 0; + while (off < hdr->nlmsg_len) { + struct nlattr *na = (void *)((uintptr_t)hdr + off); + void *payload = (void *)((uintptr_t)na + NLA_HDRLEN); + + if (na->nla_len > hdr->nlmsg_len - off) + goto error; + switch (na->nla_type) { + case RDMA_NLDEV_SYS_ATTR_MONITOR_MODE: + *cap = *(uint8_t *)payload; + return 0; + default: + break; + } + off += NLA_ALIGN(na->nla_len); + } + + return 0; + +error: + return -EINVAL; +} + +/** + * Get RDMA monitor support in driver. + * + * + * @param nl + * Netlink socket of the RDMA kind (NETLINK_RDMA). + * @param[out] cap + * Pointer to port info. + * @return + * 0 on success, negative on error and rte_errno is set. + */ +int +mlx5_nl_rdma_monitor_cap_get(int nl, uint8_t *cap) +{ + union { + struct nlmsghdr nh; + uint8_t buf[NLMSG_HDRLEN]; + } req = { + .nh = { + .nlmsg_len = NLMSG_LENGTH(0), + .nlmsg_type = RDMA_NL_GET_TYPE(RDMA_NL_NLDEV, + RDMA_NLDEV_CMD_SYS_GET), + .nlmsg_flags = NLM_F_REQUEST | NLM_F_ACK, + }, + }; + uint32_t sn = MLX5_NL_SN_GENERATE; + int ret; + + ret = mlx5_nl_send(nl, &req.nh, sn); + if (ret < 0) { + rte_errno = -ret; + return ret; + } + ret = mlx5_nl_recv(nl, sn, mlx5_nl_rdma_monitor_cap_get_cb, cap); + if (ret < 0) { + rte_errno = -ret; + return ret; + } + return 0; +} diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 5230576006..8301485839 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -148,6 +148,7 @@ INTERNAL { mlx5_nl_vlan_vmwa_delete; # WINDOWS_NO_EXPORT mlx5_nl_rdma_monitor_init; # WINDOWS_NO_EXPORT mlx5_nl_rdma_monitor_info_get; # WINDOWS_NO_EXPORT + mlx5_nl_rdma_monitor_cap_get; # WINDOWS_NO_EXPORT mlx5_os_umem_dereg; mlx5_os_umem_reg; diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 5156d96b3a..6b2c25a7c2 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -736,7 +736,7 @@ mlx5_dev_interrupt_nl_cb(struct nlmsghdr *hdr, void *cb_arg) if (mlx5_nl_parse_link_status_update(hdr, &if_index) < 0) return; - if (sh->cdev->config.probe_opt && sh->cdev->dev_info.port_num > 1) + if (sh->cdev->config.probe_opt && sh->cdev->dev_info.port_num > 1 && !sh->rdma_monitor_supp) mlx5_handle_port_info_update(&sh->cdev->dev_info, if_index, hdr->nlmsg_type); for (i = 0; i < sh->max_port; i++) { diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 16b275c71e..d3fd77af58 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -3017,6 +3017,7 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) { struct ibv_context *ctx = sh->cdev->ctx; int nlsk_fd; + uint8_t rdma_monitor_supp = 0; sh->intr_handle = mlx5_os_interrupt_handler_create (RTE_INTR_INSTANCE_F_SHARED, true, @@ -3025,20 +3026,34 @@ mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh) DRV_LOG(ERR, "Failed to allocate intr_handle."); return; } - if (sh->cdev->config.probe_opt && sh->cdev->dev_info.port_num > 1) { + if (sh->cdev->config.probe_opt && + sh->cdev->dev_info.port_num > 1 && + !sh->rdma_monitor_supp) { nlsk_fd = mlx5_nl_rdma_monitor_init(); if (nlsk_fd < 0) { DRV_LOG(ERR, "Failed to create a socket for RDMA Netlink events: %s", rte_strerror(rte_errno)); return; } - sh->intr_handle_ib = mlx5_os_interrupt_handler_create - (RTE_INTR_INSTANCE_F_SHARED, true, - nlsk_fd, mlx5_dev_interrupt_handler_ib, sh); - if (sh->intr_handle_ib == NULL) { - DRV_LOG(ERR, "Fail to allocate intr_handle"); + if (mlx5_nl_rdma_monitor_cap_get(nlsk_fd, &rdma_monitor_supp)) { + DRV_LOG(ERR, "Failed to query RDMA monitor support: %s", + rte_strerror(rte_errno)); + close(nlsk_fd); return; } + sh->rdma_monitor_supp = rdma_monitor_supp; + if (sh->rdma_monitor_supp) { + sh->intr_handle_ib = mlx5_os_interrupt_handler_create + (RTE_INTR_INSTANCE_F_SHARED, true, + nlsk_fd, mlx5_dev_interrupt_handler_ib, sh); + if (sh->intr_handle_ib == NULL) { + DRV_LOG(ERR, "Fail to allocate intr_handle"); + close(nlsk_fd); + return; + } + } else { + close(nlsk_fd); + } } nlsk_fd = mlx5_nl_init(NETLINK_ROUTE, RTMGRP_LINK); if (nlsk_fd < 0) { diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index adc21c272b..b6be4646ef 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1517,6 +1517,7 @@ struct mlx5_dev_ctx_shared { uint32_t lag_rx_port_affinity_en:1; /* lag_rx_port_affinity is supported. */ uint32_t hws_max_log_bulk_sz:5; + uint32_t rdma_monitor_supp:1; /* Log of minimal HWS counters created hard coded. */ uint32_t hws_max_nb_counters; /* Maximal number for HWS counters. */ uint32_t max_port; /* Maximal IB device port index. */ -- 2.34.1