From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3941545BC0; Tue, 29 Oct 2024 17:49:01 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B69BC43003; Tue, 29 Oct 2024 17:44:32 +0100 (CET) Received: from egress-ip11a.ess.de.barracuda.com (egress-ip11a.ess.de.barracuda.com [18.184.203.234]) by mails.dpdk.org (Postfix) with ESMTP id C055B42EC8 for ; Tue, 29 Oct 2024 17:43:38 +0100 (CET) Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05lp2176.outbound.protection.outlook.com [104.47.17.176]) by mx-outbound12-25.eu-central-1a.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 29 Oct 2024 16:43:36 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oAwxPsYyktYxLY6ozP0aVaijuSGyCyphlzmAurE5EL6hCC/hW7TUfavuwjZ25Li4/e9jiryJ/0FkMX7H21DDjhUyQ6sOnW9TM193cK5YC+rDurQ4YXaQfssZ4hQzZ5lmu+iJNlGQ3gQGVO6x5byu9e3eXBqHrTLpKopKZA+A5yQ0AcOlHZAKAGPrhytQK0si/9m8YAx48necPZQHD/KbYicHhLtyzcvT6Wp37WpfiJ6Pwnurik8YDqo1RoYpPnWYODQeBsc0zFq1yAIevvRkblwmeGzyj8NKRB/jC+X7MU1j0TrxunaewLOXTh1qs78isl6tl16OPQiE54WwKhWtpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Wml7F8E+41vF6bpSz8rFg7R7K4n2n/5Rq9n4nbEQJDI=; b=Sin9WlrH4vWbeYSwRWRQx9tw/YHCNYfFmzlh1J+I3d6YNfWED2LS2Az5JDYUXnqeBAxqlRhNE1G/tNzIyJpzT2yiSO3C8aKLPAJWvv75LeJLYqShP7nyyW5u53MMtIXqhbqQ4aQXGG9W5/6fLIwi8XawkchxyMdR8PRU9isuA8z2oOSgFR7tl3R3Wvs6k7Opf1qjdB9MGub0NmlR5C1FdNaDEWzQDe9ySn1PiqRyhdOsDbKr9w8429YvCPaCIUlkaML8BeYGiFZM617esibFItgKnzKl7qw5G5qEGM6mYKufHCKnHKEqmjXUzdK0Wvqe+pu7hzY9IvKMzWMVzhWkNw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=fail (sender ip is 178.72.21.4) smtp.rcpttodomain=dpdk.org smtp.mailfrom=napatech.com; dmarc=fail (p=reject sp=reject pct=100) action=oreject header.from=napatech.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=napatech.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Wml7F8E+41vF6bpSz8rFg7R7K4n2n/5Rq9n4nbEQJDI=; b=U2piflFxpLa1+UB/O2JmygXM7T8IvWVqsDTIHWXklteubpgWG/jUqqwsKleWSZkj3jtTDMVcXBrxftpBgGdKOH4bHUccWsV5cd/AS04zI7hyG3faPnE+bVAnqa3U1v5wJtaORa9hC06NXCCy/DXeZ5Bl7A9GBN3zTkZCIDYh6Cg= Received: from DUZPR01CA0194.eurprd01.prod.exchangelabs.com (2603:10a6:10:4b6::19) by AM9P190MB1204.EURP190.PROD.OUTLOOK.COM (2603:10a6:20b:26e::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.20; Tue, 29 Oct 2024 16:43:34 +0000 Received: from DU2PEPF00028D06.eurprd03.prod.outlook.com (2603:10a6:10:4b6:cafe::23) by DUZPR01CA0194.outlook.office365.com (2603:10a6:10:4b6::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.29 via Frontend Transport; Tue, 29 Oct 2024 16:43:34 +0000 X-MS-Exchange-Authentication-Results: spf=fail (sender IP is 178.72.21.4) smtp.mailfrom=napatech.com; dkim=none (message not signed) header.d=none;dmarc=fail action=oreject header.from=napatech.com; Received-SPF: Fail (protection.outlook.com: domain of napatech.com does not designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com; client-ip=178.72.21.4; helo=localhost.localdomain; Received: from localhost.localdomain (178.72.21.4) by DU2PEPF00028D06.mail.protection.outlook.com (10.167.242.166) with Microsoft SMTP Server id 15.20.8114.16 via Frontend Transport; Tue, 29 Oct 2024 16:43:33 +0000 From: Serhii Iliushyk To: dev@dpdk.org Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com, andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com, stephen@networkplumber.org, Oleksandr Kolomeiets Subject: [PATCH v4 42/86] net/ntnic: add FLM module registers Date: Tue, 29 Oct 2024 17:41:46 +0100 Message-ID: <20241029164243.1648775-43-sil-plv@napatech.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241029164243.1648775-1-sil-plv@napatech.com> References: <20241021210527.2075431-1-sil-plv@napatech.com> <20241029164243.1648775-1-sil-plv@napatech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PEPF00028D06:EE_|AM9P190MB1204:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: b331d935-37a2-4951-2cfe-08dcf838d426 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?eeTVR4s5+nwNQgfAeNA1M3FWx/XV3LR+F+pnK+8zgkjrF3uoZryTYuNFmdyW?= =?us-ascii?Q?MW4A095I5ZewrujTpfALbsWHJaSMarLvm36s8Mt28jM3Dc4zohbbciFL8Azg?= =?us-ascii?Q?WzPB69yo7aYnQwCH+YzG88kANICrkBxBPDS1KoWaq1iaIZD7oZtvt9z1m4Xv?= =?us-ascii?Q?JLhfpiMKvb6+3s3YPZx2FGLkmHn36KcvpW2+FG6cqEn3lPxez2V2KreS5ji9?= =?us-ascii?Q?lVuCHUAmta3LrX+8ZZDc2fhZl4o+W8OMrGt+leEFtubMcB7u47MUjFrT2f+j?= =?us-ascii?Q?janlHrfwApPu3suLmfGUrXKQZ+sKxmkXDTVd48oWlwwF1IFjBRrWiVTroIKv?= =?us-ascii?Q?eq5j5I1VjQACuecl8y3dSnRtx9z6jqrlOBfc0nsOakDs1OZEO6U0rIt5K6OL?= =?us-ascii?Q?0imcDy37KUKkwvmU+pQdzYlIJ6EEq3itBIORwlHc4x4rSBSDSEfk7fztxaXQ?= =?us-ascii?Q?WHPe/ytw2yXJXm329UdvAoxaeBPb4TgnSmOmRuLTlIwj7R/Vg4XDGyKxX8vl?= =?us-ascii?Q?tdSgOKKLgmBHE8QeTkRaA+5E9zNgrMZaM1fdlQr18tvJS/Yy08JYGv/cbVbT?= =?us-ascii?Q?y98xU8AcSWCQXyCiTVjur0Gy94ZgoEbPO3pXGG51TODogIc18XnMfqb1whOx?= =?us-ascii?Q?FOObpVRwninQsR0d8pJw/TZBBmwRXzRs9317stq/djZMGUz6kgH6L3s76mMN?= =?us-ascii?Q?hsw2+1HnVyByiQEH4KWlnCHUg2w5QIglOCBDZLKoAJi4O4W8YwVzxawNNyEt?= =?us-ascii?Q?UDh9zdWhlsoUS67AoonYSGnRoy6en80cjvvhSwSKwlXEJlGlXgebP8KaQUiG?= =?us-ascii?Q?fs+/49jnC7NhpjU6gFaQK0Eh+z/Z165KKRTLFBjH9hu1RWlUlWObMkYhl58l?= =?us-ascii?Q?PFC0BVf7UxK/knqmwwWqgI5vnabtG3i2MIKFTGjI3obXIJf9dPGBsucCPPA+?= =?us-ascii?Q?i0y/Z88Z/2AyWaS7BysVwhoSHFk6FwzMbCg4GnVDjBcK5BqGOTMwyDtUezSZ?= =?us-ascii?Q?+iVG6yA+qCefKoWrMNhqbqgXL+A+h3HSWJkP01ebi5MUR55r8ks7Tw0YiVyY?= =?us-ascii?Q?IvO9/JZpi+o/7Gj3qUOPBIUh2f7Ii5ueFNLk8JcR3rIPffvR7Go7osQjCxpM?= =?us-ascii?Q?RKRtNTDqVvmWLg15d9ZEGwj2VjmP8OGR2bSzdDa0IJYtVdpqo1nrWOfFtjDy?= =?us-ascii?Q?Im+HRpXKC53ZLn0sxFTZ36sEvUzUmr96ERCxpu0Fmkx/v+rKg/YvX57lUbiE?= =?us-ascii?Q?+RrBzB0urnYoDant1ERej0KD6xb61UkBbOcBrYiZRx/2b6QLxOp1ZDvl+ixf?= =?us-ascii?Q?0lhsq7cG/fi6bAdkxLLqnXxhuhjMC6Chei7HUiGC4UYeGJnXDi8MAXBy93nc?= =?us-ascii?Q?NztWcLIGivzOkO7Geci+zfCFceiUvabT+gR+FGOKzjqOhS+D3Q=3D=3D?= X-Forefront-Antispam-Report: CIP:178.72.21.4; CTRY:DK; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:localhost.localdomain; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: 2+Nk0FctMwF0KlNDSSMu2pWHHGqhayMwUgrRN/ldbm2G3XzKuK4onAm+eZnUFSLQh+ncPToL1JP0LXwId+D+oyO/pZnlG5ONZftDZI+PriAWPg3f9GK7i7cMx9c+XOKEx1en5a8WvY654lfD3ZwLTdZw2YnyKZ1D/LBLewI64CcjeJ8uj5g1XYOOs3LJaT16LzxwqYDewJGkAr0EgR9IxGBR57kMA9tWKXw5j+WXQtOR0I/WGgv4dltQzJbbWmCzNKu2nz440EgoI8UNqvNHSchltm8+ZF+d7uE+qGSzN/GvD0HAPQmC468zpQ9MZfzWRCCfYFVr38WqzM48qT0MoStoT/myGVzeLgLnjfWpaMYEE0yaNPhZUz6RiqJZS/VUlto3vC7Abix6kufrxlT7bTedYsV0TvYcnH43TJXjE+g+1hovadbP6V6tjF2Dn6lh27/twEvTsziZtNsyOGUC1eFuw936t1zTBEJ6cE98RFqrrZPBSkmR3jV4BpJjgHs0DcuPgDHGADaSugIOxem8asZ07g+JN3emUvdb8B02FtdTOxmkMMesOHhbNP2NfbLqhXh8kRa/+5dFgjTziz97hfQGhsSC7mKqefiVolyDYyJRo4Vk6Usms3+b6K7ZyFwCDD2a300jC+KXgFxcibA4kET7BkI5TLvoHSkoNRtORZw= X-OriginatorOrg: napatech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2024 16:43:33.7927 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b331d935-37a2-4951-2cfe-08dcf838d426 X-MS-Exchange-CrossTenant-Id: c4540d0b-728a-4233-9da5-9ea30c7ec3ed X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=c4540d0b-728a-4233-9da5-9ea30c7ec3ed; Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D06.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P190MB1204 X-BESS-ID: 1730220216-303097-12765-29352-1 X-BESS-VER: 2019.1_20241018.1852 X-BESS-Apparent-Source-IP: 104.47.17.176 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVoYmRuZmQGYGUNTIJNEy0czIyC TZ0sAs1cTSKNUgySDR2MggzdwwBYiVamMByfWwUkIAAAA= X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.260063 [from cloudscan16-169.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Oleksandr Kolomeiets The Flow Matcher module is a high-performance stateful SDRAM lookup and programming engine which supported exact match lookup in line-rate of up to hundreds of millions of flows. Signed-off-by: Oleksandr Kolomeiets --- .../supported/nthw_fpga_9563_055_049_0000.c | 286 +++++++++++++++++- 1 file changed, 284 insertions(+), 2 deletions(-) diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c index efa7b306bc..739cabfb1c 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c @@ -468,6 +468,288 @@ static nthw_fpga_register_init_s dbs_registers[] = { { DBS_TX_UW_DATA, 17, 94, NTHW_FPGA_REG_TYPE_WO, 0, 8, dbs_tx_uw_data_fields }, }; +static nthw_fpga_field_init_s flm_buf_ctrl_fields[] = { + { FLM_BUF_CTRL_INF_AVAIL, 16, 16, 0x0000 }, + { FLM_BUF_CTRL_LRN_FREE, 16, 0, 0x0000 }, + { FLM_BUF_CTRL_STA_AVAIL, 16, 32, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_control_fields[] = { + { FLM_CONTROL_CALIB_RECALIBRATE, 3, 28, 0 }, + { FLM_CONTROL_CRCRD, 1, 12, 0x0000 }, + { FLM_CONTROL_CRCWR, 1, 11, 0x0000 }, + { FLM_CONTROL_EAB, 5, 18, 0 }, + { FLM_CONTROL_ENABLE, 1, 0, 0 }, + { FLM_CONTROL_INIT, 1, 1, 0x0000 }, + { FLM_CONTROL_LDS, 1, 2, 0x0000 }, + { FLM_CONTROL_LFS, 1, 3, 0x0000 }, + { FLM_CONTROL_LIS, 1, 4, 0x0000 }, + { FLM_CONTROL_PDS, 1, 9, 0x0000 }, + { FLM_CONTROL_PIS, 1, 10, 0x0000 }, + { FLM_CONTROL_RBL, 4, 13, 0 }, + { FLM_CONTROL_RDS, 1, 7, 0x0000 }, + { FLM_CONTROL_RIS, 1, 8, 0x0000 }, + { FLM_CONTROL_SPLIT_SDRAM_USAGE, 5, 23, 16 }, + { FLM_CONTROL_UDS, 1, 5, 0x0000 }, + { FLM_CONTROL_UIS, 1, 6, 0x0000 }, + { FLM_CONTROL_WPD, 1, 17, 0 }, +}; + +static nthw_fpga_field_init_s flm_inf_data_fields[] = { + { FLM_INF_DATA_BYTES, 64, 0, 0x0000 }, { FLM_INF_DATA_CAUSE, 3, 224, 0x0000 }, + { FLM_INF_DATA_EOR, 1, 287, 0x0000 }, { FLM_INF_DATA_ID, 32, 192, 0x0000 }, + { FLM_INF_DATA_PACKETS, 64, 64, 0x0000 }, { FLM_INF_DATA_TS, 64, 128, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_load_aps_fields[] = { + { FLM_LOAD_APS_APS, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_load_bin_fields[] = { + { FLM_LOAD_BIN_BIN, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_load_lps_fields[] = { + { FLM_LOAD_LPS_LPS, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_lrn_data_fields[] = { + { FLM_LRN_DATA_ADJ, 32, 480, 0x0000 }, { FLM_LRN_DATA_COLOR, 32, 448, 0x0000 }, + { FLM_LRN_DATA_DSCP, 6, 698, 0x0000 }, { FLM_LRN_DATA_ENT, 1, 693, 0x0000 }, + { FLM_LRN_DATA_EOR, 1, 767, 0x0000 }, { FLM_LRN_DATA_FILL, 16, 544, 0x0000 }, + { FLM_LRN_DATA_FT, 4, 560, 0x0000 }, { FLM_LRN_DATA_FT_MBR, 4, 564, 0x0000 }, + { FLM_LRN_DATA_FT_MISS, 4, 568, 0x0000 }, { FLM_LRN_DATA_ID, 32, 512, 0x0000 }, + { FLM_LRN_DATA_KID, 8, 328, 0x0000 }, { FLM_LRN_DATA_MBR_ID1, 28, 572, 0x0000 }, + { FLM_LRN_DATA_MBR_ID2, 28, 600, 0x0000 }, { FLM_LRN_DATA_MBR_ID3, 28, 628, 0x0000 }, + { FLM_LRN_DATA_MBR_ID4, 28, 656, 0x0000 }, { FLM_LRN_DATA_NAT_EN, 1, 711, 0x0000 }, + { FLM_LRN_DATA_NAT_IP, 32, 336, 0x0000 }, { FLM_LRN_DATA_NAT_PORT, 16, 400, 0x0000 }, + { FLM_LRN_DATA_NOFI, 1, 716, 0x0000 }, { FLM_LRN_DATA_OP, 4, 694, 0x0000 }, + { FLM_LRN_DATA_PRIO, 2, 691, 0x0000 }, { FLM_LRN_DATA_PROT, 8, 320, 0x0000 }, + { FLM_LRN_DATA_QFI, 6, 704, 0x0000 }, { FLM_LRN_DATA_QW0, 128, 192, 0x0000 }, + { FLM_LRN_DATA_QW4, 128, 64, 0x0000 }, { FLM_LRN_DATA_RATE, 16, 416, 0x0000 }, + { FLM_LRN_DATA_RQI, 1, 710, 0x0000 }, + { FLM_LRN_DATA_SIZE, 16, 432, 0x0000 }, { FLM_LRN_DATA_STAT_PROF, 4, 687, 0x0000 }, + { FLM_LRN_DATA_SW8, 32, 32, 0x0000 }, { FLM_LRN_DATA_SW9, 32, 0, 0x0000 }, + { FLM_LRN_DATA_TEID, 32, 368, 0x0000 }, { FLM_LRN_DATA_VOL_IDX, 3, 684, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_prio_fields[] = { + { FLM_PRIO_FT0, 4, 4, 1 }, { FLM_PRIO_FT1, 4, 12, 1 }, { FLM_PRIO_FT2, 4, 20, 1 }, + { FLM_PRIO_FT3, 4, 28, 1 }, { FLM_PRIO_LIMIT0, 4, 0, 0 }, { FLM_PRIO_LIMIT1, 4, 8, 0 }, + { FLM_PRIO_LIMIT2, 4, 16, 0 }, { FLM_PRIO_LIMIT3, 4, 24, 0 }, +}; + +static nthw_fpga_field_init_s flm_pst_ctrl_fields[] = { + { FLM_PST_CTRL_ADR, 4, 0, 0x0000 }, + { FLM_PST_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_pst_data_fields[] = { + { FLM_PST_DATA_BP, 5, 0, 0x0000 }, + { FLM_PST_DATA_PP, 5, 5, 0x0000 }, + { FLM_PST_DATA_TP, 5, 10, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_rcp_ctrl_fields[] = { + { FLM_RCP_CTRL_ADR, 5, 0, 0x0000 }, + { FLM_RCP_CTRL_CNT, 16, 16, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_rcp_data_fields[] = { + { FLM_RCP_DATA_AUTO_IPV4_MASK, 1, 402, 0x0000 }, + { FLM_RCP_DATA_BYT_DYN, 5, 387, 0x0000 }, + { FLM_RCP_DATA_BYT_OFS, 8, 392, 0x0000 }, + { FLM_RCP_DATA_IPN, 1, 386, 0x0000 }, + { FLM_RCP_DATA_KID, 8, 377, 0x0000 }, + { FLM_RCP_DATA_LOOKUP, 1, 0, 0x0000 }, + { FLM_RCP_DATA_MASK, 320, 57, 0x0000 }, + { FLM_RCP_DATA_OPN, 1, 385, 0x0000 }, + { FLM_RCP_DATA_QW0_DYN, 5, 1, 0x0000 }, + { FLM_RCP_DATA_QW0_OFS, 8, 6, 0x0000 }, + { FLM_RCP_DATA_QW0_SEL, 2, 14, 0x0000 }, + { FLM_RCP_DATA_QW4_DYN, 5, 16, 0x0000 }, + { FLM_RCP_DATA_QW4_OFS, 8, 21, 0x0000 }, + { FLM_RCP_DATA_SW8_DYN, 5, 29, 0x0000 }, + { FLM_RCP_DATA_SW8_OFS, 8, 34, 0x0000 }, + { FLM_RCP_DATA_SW8_SEL, 2, 42, 0x0000 }, + { FLM_RCP_DATA_SW9_DYN, 5, 44, 0x0000 }, + { FLM_RCP_DATA_SW9_OFS, 8, 49, 0x0000 }, + { FLM_RCP_DATA_TXPLM, 2, 400, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_scan_fields[] = { + { FLM_SCAN_I, 16, 0, 0 }, +}; + +static nthw_fpga_field_init_s flm_status_fields[] = { + { FLM_STATUS_CACHE_BUFFER_CRITICAL, 1, 12, 0x0000 }, + { FLM_STATUS_CALIB_FAIL, 3, 3, 0 }, + { FLM_STATUS_CALIB_SUCCESS, 3, 0, 0 }, + { FLM_STATUS_CRCERR, 1, 10, 0x0000 }, + { FLM_STATUS_CRITICAL, 1, 8, 0x0000 }, + { FLM_STATUS_EFT_BP, 1, 11, 0x0000 }, + { FLM_STATUS_IDLE, 1, 7, 0x0000 }, + { FLM_STATUS_INITDONE, 1, 6, 0x0000 }, + { FLM_STATUS_PANIC, 1, 9, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_aul_done_fields[] = { + { FLM_STAT_AUL_DONE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_aul_fail_fields[] = { + { FLM_STAT_AUL_FAIL_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_aul_ignore_fields[] = { + { FLM_STAT_AUL_IGNORE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_csh_hit_fields[] = { + { FLM_STAT_CSH_HIT_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_csh_miss_fields[] = { + { FLM_STAT_CSH_MISS_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_csh_unh_fields[] = { + { FLM_STAT_CSH_UNH_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_cuc_move_fields[] = { + { FLM_STAT_CUC_MOVE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_cuc_start_fields[] = { + { FLM_STAT_CUC_START_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_flows_fields[] = { + { FLM_STAT_FLOWS_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_inf_done_fields[] = { + { FLM_STAT_INF_DONE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_inf_skip_fields[] = { + { FLM_STAT_INF_SKIP_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_lrn_done_fields[] = { + { FLM_STAT_LRN_DONE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_lrn_fail_fields[] = { + { FLM_STAT_LRN_FAIL_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_lrn_ignore_fields[] = { + { FLM_STAT_LRN_IGNORE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_pck_dis_fields[] = { + { FLM_STAT_PCK_DIS_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_pck_hit_fields[] = { + { FLM_STAT_PCK_HIT_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_pck_miss_fields[] = { + { FLM_STAT_PCK_MISS_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_pck_unh_fields[] = { + { FLM_STAT_PCK_UNH_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_prb_done_fields[] = { + { FLM_STAT_PRB_DONE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_prb_ignore_fields[] = { + { FLM_STAT_PRB_IGNORE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_rel_done_fields[] = { + { FLM_STAT_REL_DONE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_rel_ignore_fields[] = { + { FLM_STAT_REL_IGNORE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_sta_done_fields[] = { + { FLM_STAT_STA_DONE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_tul_done_fields[] = { + { FLM_STAT_TUL_DONE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_unl_done_fields[] = { + { FLM_STAT_UNL_DONE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_stat_unl_ignore_fields[] = { + { FLM_STAT_UNL_IGNORE_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s flm_sta_data_fields[] = { + { FLM_STA_DATA_EOR, 1, 95, 0x0000 }, { FLM_STA_DATA_ID, 32, 0, 0x0000 }, + { FLM_STA_DATA_LDS, 1, 32, 0x0000 }, { FLM_STA_DATA_LFS, 1, 33, 0x0000 }, + { FLM_STA_DATA_LIS, 1, 34, 0x0000 }, { FLM_STA_DATA_PDS, 1, 39, 0x0000 }, + { FLM_STA_DATA_PIS, 1, 40, 0x0000 }, { FLM_STA_DATA_RDS, 1, 37, 0x0000 }, + { FLM_STA_DATA_RIS, 1, 38, 0x0000 }, { FLM_STA_DATA_UDS, 1, 35, 0x0000 }, + { FLM_STA_DATA_UIS, 1, 36, 0x0000 }, +}; + +static nthw_fpga_register_init_s flm_registers[] = { + { FLM_BUF_CTRL, 14, 48, NTHW_FPGA_REG_TYPE_RW, 0, 3, flm_buf_ctrl_fields }, + { FLM_CONTROL, 0, 31, NTHW_FPGA_REG_TYPE_MIXED, 134217728, 18, flm_control_fields }, + { FLM_INF_DATA, 16, 288, NTHW_FPGA_REG_TYPE_RO, 0, 6, flm_inf_data_fields }, + { FLM_LOAD_APS, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_load_aps_fields }, + { FLM_LOAD_BIN, 3, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, flm_load_bin_fields }, + { FLM_LOAD_LPS, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_load_lps_fields }, + { FLM_LRN_DATA, 15, 768, NTHW_FPGA_REG_TYPE_WO, 0, 34, flm_lrn_data_fields }, + { FLM_PRIO, 6, 32, NTHW_FPGA_REG_TYPE_WO, 269488144, 8, flm_prio_fields }, + { FLM_PST_CTRL, 12, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, flm_pst_ctrl_fields }, + { FLM_PST_DATA, 13, 15, NTHW_FPGA_REG_TYPE_WO, 0, 3, flm_pst_data_fields }, + { FLM_RCP_CTRL, 8, 32, NTHW_FPGA_REG_TYPE_WO, 0, 2, flm_rcp_ctrl_fields }, + { FLM_RCP_DATA, 9, 403, NTHW_FPGA_REG_TYPE_WO, 0, 19, flm_rcp_data_fields }, + { FLM_SCAN, 2, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, flm_scan_fields }, + { FLM_STATUS, 1, 17, NTHW_FPGA_REG_TYPE_MIXED, 0, 9, flm_status_fields }, + { FLM_STAT_AUL_DONE, 41, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_aul_done_fields }, + { FLM_STAT_AUL_FAIL, 43, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_aul_fail_fields }, + { FLM_STAT_AUL_IGNORE, 42, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_aul_ignore_fields }, + { FLM_STAT_CSH_HIT, 52, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_csh_hit_fields }, + { FLM_STAT_CSH_MISS, 53, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_csh_miss_fields }, + { FLM_STAT_CSH_UNH, 54, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_csh_unh_fields }, + { FLM_STAT_CUC_MOVE, 56, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_cuc_move_fields }, + { FLM_STAT_CUC_START, 55, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_cuc_start_fields }, + { FLM_STAT_FLOWS, 18, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_flows_fields }, + { FLM_STAT_INF_DONE, 46, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_inf_done_fields }, + { FLM_STAT_INF_SKIP, 47, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_inf_skip_fields }, + { FLM_STAT_LRN_DONE, 32, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_lrn_done_fields }, + { FLM_STAT_LRN_FAIL, 34, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_lrn_fail_fields }, + { FLM_STAT_LRN_IGNORE, 33, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_lrn_ignore_fields }, + { FLM_STAT_PCK_DIS, 51, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_pck_dis_fields }, + { FLM_STAT_PCK_HIT, 48, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_pck_hit_fields }, + { FLM_STAT_PCK_MISS, 49, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_pck_miss_fields }, + { FLM_STAT_PCK_UNH, 50, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_pck_unh_fields }, + { FLM_STAT_PRB_DONE, 39, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_prb_done_fields }, + { FLM_STAT_PRB_IGNORE, 40, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_prb_ignore_fields }, + { FLM_STAT_REL_DONE, 37, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_rel_done_fields }, + { FLM_STAT_REL_IGNORE, 38, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_rel_ignore_fields }, + { FLM_STAT_STA_DONE, 45, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_sta_done_fields }, + { FLM_STAT_TUL_DONE, 44, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_tul_done_fields }, + { FLM_STAT_UNL_DONE, 35, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_unl_done_fields }, + { FLM_STAT_UNL_IGNORE, 36, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, flm_stat_unl_ignore_fields }, + { FLM_STA_DATA, 17, 96, NTHW_FPGA_REG_TYPE_RO, 0, 11, flm_sta_data_fields }, +}; + static nthw_fpga_field_init_s gfg_burstsize0_fields[] = { { GFG_BURSTSIZE0_VAL, 24, 0, 0 }, }; @@ -1743,6 +2025,7 @@ static nthw_fpga_module_init_s fpga_modules[] = { { MOD_CAT, 0, MOD_CAT, 0, 21, NTHW_FPGA_BUS_TYPE_RAB1, 768, 34, cat_registers }, { MOD_CSU, 0, MOD_CSU, 0, 0, NTHW_FPGA_BUS_TYPE_RAB1, 9728, 2, csu_registers }, { MOD_DBS, 0, MOD_DBS, 0, 11, NTHW_FPGA_BUS_TYPE_RAB2, 12832, 27, dbs_registers }, + { MOD_FLM, 0, MOD_FLM, 0, 25, NTHW_FPGA_BUS_TYPE_RAB1, 1280, 43, flm_registers }, { MOD_GFG, 0, MOD_GFG, 1, 1, NTHW_FPGA_BUS_TYPE_RAB2, 8704, 10, gfg_registers }, { MOD_GMF, 0, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9216, 12, gmf_registers }, { MOD_GMF, 1, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9728, 12, gmf_registers }, @@ -1817,7 +2100,6 @@ static nthw_fpga_prod_param_s product_parameters[] = { { NT_FLM_PRESENT, 1 }, { NT_FLM_PRIOS, 4 }, { NT_FLM_PST_PROFILES, 16 }, - { NT_FLM_SCRUB_PROFILES, 16 }, { NT_FLM_SIZE_MB, 12288 }, { NT_FLM_STATEFUL, 1 }, { NT_FLM_VARIANT, 2 }, @@ -1937,5 +2219,5 @@ static nthw_fpga_prod_param_s product_parameters[] = { }; nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = { - 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 23, fpga_modules, + 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 24, fpga_modules, }; -- 2.45.0