[PATCH v3 2/2] net/ice: increase the maximum of RX/TX descriptors

[Lukas Sismis <sismis@cesnet.cz>]

Intel PMDs are capped by default to only 4096 RX/TX descriptors.
This can be limiting for applications requiring a bigger buffer
capabilities. By bufferring more packets with RX/TX
descriptors, the applications can better handle the processing
peaks.

Setting ice max descriptors to 8192 - 32 as per datasheet:
Register name: QLEN (Rx-Queue)
Description: Receive Queue Length
Defines the size of the descriptor queue in descriptors units
from eight descriptors (QLEN=0x8) up to 8K descriptors minus
32 (QLEN=0x1FE0).
QLEN Restrictions: When the PXE_MODE flag in the
GLLAN_RCTL_0 register is cleared, the QLEN must be whole
number of 32 descriptors. When the PXE_MODE flag is set, the
QLEN can be one of the following options:
Up to 4 PFs, QLEN can be set to: 8, 16, 24 or 32 descriptors.
Up to 8 PFs, QLEN can be set to: 8 or 16 descriptors

Signed-off-by: Lukas Sismis <sismis@cesnet.cz>
---
 drivers/net/ice/ice_rxtx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h
index f7276cfc9f..45f25b3609 100644
--- a/drivers/net/ice/ice_rxtx.h
+++ b/drivers/net/ice/ice_rxtx.h
@@ -9,7 +9,7 @@
 
 #define ICE_ALIGN_RING_DESC  32
 #define ICE_MIN_RING_DESC    64
-#define ICE_MAX_RING_DESC    4096
+#define ICE_MAX_RING_DESC    (8192 - 32)
 #define ICE_DMA_MEM_ALIGN    4096
 #define ICE_RING_BASE_ALIGN  128
 
-- 
2.34.1