From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6B55E45C16; Wed, 30 Oct 2024 16:43:16 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EFD7143431; Wed, 30 Oct 2024 16:43:10 +0100 (CET) Received: from luks-14ITL5.cesnet.cz (rt-tmc-kou.liberouter.org [195.113.172.126]) by mails.dpdk.org (Postfix) with ESMTP id 3B8B14342E for ; Wed, 30 Oct 2024 16:43:10 +0100 (CET) Received: by luks-14ITL5.cesnet.cz (Postfix, from userid 1000) id 0FBD028C4071; Wed, 30 Oct 2024 16:43:10 +0100 (CET) From: Lukas Sismis To: dev@dpdk.org Cc: stephen@networkplumber.org, mb@smartsharesystems.com, anatoly.burakov@intel.com, ian.stokes@intel.com, Lukas Sismis Subject: [PATCH v3 2/2] net/ice: increase the maximum of RX/TX descriptors Date: Wed, 30 Oct 2024 16:42:56 +0100 Message-Id: <20241030154256.379249-3-sismis@cesnet.cz> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241030154256.379249-1-sismis@cesnet.cz> References: <20241029124832.224112-1-sismis@cesnet.cz> <20241030154256.379249-1-sismis@cesnet.cz> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Intel PMDs are capped by default to only 4096 RX/TX descriptors. This can be limiting for applications requiring a bigger buffer capabilities. By bufferring more packets with RX/TX descriptors, the applications can better handle the processing peaks. Setting ice max descriptors to 8192 - 32 as per datasheet: Register name: QLEN (Rx-Queue) Description: Receive Queue Length Defines the size of the descriptor queue in descriptors units from eight descriptors (QLEN=0x8) up to 8K descriptors minus 32 (QLEN=0x1FE0). QLEN Restrictions: When the PXE_MODE flag in the GLLAN_RCTL_0 register is cleared, the QLEN must be whole number of 32 descriptors. When the PXE_MODE flag is set, the QLEN can be one of the following options: Up to 4 PFs, QLEN can be set to: 8, 16, 24 or 32 descriptors. Up to 8 PFs, QLEN can be set to: 8 or 16 descriptors Signed-off-by: Lukas Sismis --- drivers/net/ice/ice_rxtx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h index f7276cfc9f..45f25b3609 100644 --- a/drivers/net/ice/ice_rxtx.h +++ b/drivers/net/ice/ice_rxtx.h @@ -9,7 +9,7 @@ #define ICE_ALIGN_RING_DESC 32 #define ICE_MIN_RING_DESC 64 -#define ICE_MAX_RING_DESC 4096 +#define ICE_MAX_RING_DESC (8192 - 32) #define ICE_DMA_MEM_ALIGN 4096 #define ICE_RING_BASE_ALIGN 128 -- 2.34.1