From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8421C45C17; Wed, 30 Oct 2024 19:56:04 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DED4C42F9D; Wed, 30 Oct 2024 19:56:01 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by mails.dpdk.org (Postfix) with ESMTP id C027442EF3; Wed, 30 Oct 2024 19:55:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730314559; x=1761850559; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PWEl3RBn/xw4KrS8yOOVp4xsF6/W6b8WkFHfUX2Axis=; b=l/IP7O7+mHU+nIMp9N8TT0BolNiYXyprYUnQinHbdI7ghwCFH7wI5H2n yt4HZNvkRoFM/JQhJJANB7RYtjaGPe/cgbA36tLRB5HNs0ErYFsj45o2w 9EXruaUyQSKI/NO7hzSmxcVlh0AG3PTOYdEUY461Ue9S/RWZCWwSfx/B7 VQ2Qvh+T4Ql6rzYP7VBn8bI/Ik3Fd6sngMbfdeNogzFi+R2SJt4s0/+r4 UU1UPTGvNT5wd29qQ/57s0dfD/TN3c2ZM4HMAIgY53dvAvUnkfiU+DJTi GJ7381HsX/kD7l+YL+xhZdDVw2iOj0KwslGtjzAezOXwqiHZtoj2X3/7k A==; X-CSE-ConnectionGUID: 9EHZE8V/SBqqAsKgcB1KYQ== X-CSE-MsgGUID: eqCagTBmSE+nryvNtcdTWA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="29889019" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="29889019" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2024 11:55:57 -0700 X-CSE-ConnectionGUID: 5WyQx88IRXSQfuL+c1QTVA== X-CSE-MsgGUID: vEt0WVJKSUasu2EQRx1yeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,245,1725346800"; d="scan'208";a="82054131" Received: from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..) ([10.233.181.123]) by fmviesa007.fm.intel.com with ESMTP; 30 Oct 2024 11:55:56 -0700 From: Nicolas Chautru To: dev@dpdk.org, maxime.coquelin@redhat.com Cc: hemant.agrawal@nxp.com, hernan.vargas@intel.com, Nicolas Chautru , stable@dpdk.org Subject: [PATCH v1 1/1] baseband/acc: fix ring memory allocation logic Date: Wed, 30 Oct 2024 11:56:14 -0700 Message-Id: <20241030185614.1605876-2-nicolas.chautru@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241030185614.1605876-1-nicolas.chautru@intel.com> References: <20241030185614.1605876-1-nicolas.chautru@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allowing ring memory allocation whose end address is aligned with 64 MB. Previous logic was off by one. Fixes: 060e76729302 ("baseband/acc100: add queue configuration") Cc: stable@dpdk.org Signed-off-by: Nicolas Chautru --- drivers/baseband/acc/acc_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 4c60b7896b..55b43bab4e 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -800,7 +800,7 @@ alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc_device *d, /* Check if the end of the sw ring memory block is before the * start of next 64MB aligned mem address */ - if (sw_ring_iova_end_addr < next_64mb_align_addr_iova) { + if (sw_ring_iova_end_addr <= next_64mb_align_addr_iova) { d->sw_rings_iova = sw_rings_base_iova; d->sw_rings = sw_rings_base; d->sw_rings_base = sw_rings_base; -- 2.34.1