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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D13.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1P190MB0990 X-OriginatorOrg: napatech.com X-BESS-ID: 1730329984-302901-12800-46801-1 X-BESS-VER: 2019.1_20241018.1852 X-BESS-Apparent-Source-IP: 104.47.11.41 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVmam5sZAVgZQ0CzNINncyNQi1S jFwMQkMTUlOdEozSTJMM0gLS01Mc1UqTYWACaVYgRBAAAA X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.260092 [from cloudscan20-80.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Oleksandr Kolomeiets The IP Fragmenter module can fragment outgoing packets based on a programmable MTU. Signed-off-by: Oleksandr Kolomeiets --- .../supported/nthw_fpga_9563_055_049_0000.c | 61 ++++++++++++++++++- .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 3 +- .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 1 + .../supported/nthw_fpga_reg_defs_mac_rx.h | 29 +++++++++ 4 files changed, 92 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c index 509e1f6860..eecd6342c0 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_049_0000.c @@ -1774,6 +1774,63 @@ static nthw_fpga_register_init_s mac_pcs_registers[] = { }, }; +static nthw_fpga_field_init_s mac_rx_bad_fcs_fields[] = { + { MAC_RX_BAD_FCS_COUNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_rx_fragment_fields[] = { + { MAC_RX_FRAGMENT_COUNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_rx_packet_bad_fcs_fields[] = { + { MAC_RX_PACKET_BAD_FCS_COUNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_rx_packet_small_fields[] = { + { MAC_RX_PACKET_SMALL_COUNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_rx_total_bytes_fields[] = { + { MAC_RX_TOTAL_BYTES_COUNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_rx_total_good_bytes_fields[] = { + { MAC_RX_TOTAL_GOOD_BYTES_COUNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_rx_total_good_packets_fields[] = { + { MAC_RX_TOTAL_GOOD_PACKETS_COUNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_rx_total_packets_fields[] = { + { MAC_RX_TOTAL_PACKETS_COUNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_rx_undersize_fields[] = { + { MAC_RX_UNDERSIZE_COUNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_register_init_s mac_rx_registers[] = { + { MAC_RX_BAD_FCS, 0, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_bad_fcs_fields }, + { MAC_RX_FRAGMENT, 6, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_fragment_fields }, + { + MAC_RX_PACKET_BAD_FCS, 7, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_rx_packet_bad_fcs_fields + }, + { MAC_RX_PACKET_SMALL, 3, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_packet_small_fields }, + { MAC_RX_TOTAL_BYTES, 4, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_total_bytes_fields }, + { + MAC_RX_TOTAL_GOOD_BYTES, 5, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_rx_total_good_bytes_fields + }, + { + MAC_RX_TOTAL_GOOD_PACKETS, 2, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_rx_total_good_packets_fields + }, + { MAC_RX_TOTAL_PACKETS, 1, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_total_packets_fields }, + { MAC_RX_UNDERSIZE, 8, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_rx_undersize_fields }, +}; + static nthw_fpga_field_init_s pci_rd_tg_tg_ctrl_fields[] = { { PCI_RD_TG_TG_CTRL_TG_RD_RDY, 1, 0, 0 }, }; @@ -2123,6 +2180,8 @@ static nthw_fpga_module_init_s fpga_modules[] = { MOD_MAC_PCS, 1, MOD_MAC_PCS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB2, 11776, 44, mac_pcs_registers }, + { MOD_MAC_RX, 0, MOD_MAC_RX, 0, 0, NTHW_FPGA_BUS_TYPE_RAB2, 10752, 9, mac_rx_registers }, + { MOD_MAC_RX, 1, MOD_MAC_RX, 0, 0, NTHW_FPGA_BUS_TYPE_RAB2, 12288, 9, mac_rx_registers }, { MOD_PCI_RD_TG, 0, MOD_PCI_RD_TG, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 2320, 6, pci_rd_tg_registers @@ -2294,5 +2353,5 @@ static nthw_fpga_prod_param_s product_parameters[] = { }; nthw_fpga_prod_init_s nthw_fpga_9563_055_049_0000 = { - 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 26, fpga_modules, + 200, 9563, 55, 49, 0, 0, 1726740521, 152, product_parameters, 28, fpga_modules, }; diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h index b6be02f45e..5983ba7095 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -29,6 +29,7 @@ #define MOD_IIC (0x7629cddbUL) #define MOD_KM (0xcfbd9dbeUL) #define MOD_MAC_PCS (0x7abe24c7UL) +#define MOD_MAC_RX (0x6347b490UL) #define MOD_PCIE3 (0xfbc48c18UL) #define MOD_PCI_RD_TG (0x9ad9eed2UL) #define MOD_PCI_WR_TG (0x274b69e1UL) @@ -43,7 +44,7 @@ #define MOD_TX_CPY (0x60acf217UL) #define MOD_TX_INS (0x59afa100UL) #define MOD_TX_RPL (0x1095dfbbUL) -#define MOD_IDX_COUNT (14) +#define MOD_IDX_COUNT (31) /* aliases - only aliases go below this point */ #endif /* _NTHW_FPGA_MOD_DEFS_H_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h index 3560eeda7d..5ebbec6c7e 100644 --- a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h @@ -30,6 +30,7 @@ #include "nthw_fpga_reg_defs_ins.h" #include "nthw_fpga_reg_defs_km.h" #include "nthw_fpga_reg_defs_mac_pcs.h" +#include "nthw_fpga_reg_defs_mac_rx.h" #include "nthw_fpga_reg_defs_pcie3.h" #include "nthw_fpga_reg_defs_pci_rd_tg.h" #include "nthw_fpga_reg_defs_pci_wr_tg.h" diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h new file mode 100644 index 0000000000..3829c10f3b --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_rx.h @@ -0,0 +1,29 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2024 Napatech A/S + */ + +#ifndef _NTHW_FPGA_REG_DEFS_MAC_RX_ +#define _NTHW_FPGA_REG_DEFS_MAC_RX_ + +/* MAC_RX */ +#define MAC_RX_BAD_FCS (0xca07f618UL) +#define MAC_RX_BAD_FCS_COUNT (0x11d5ba0eUL) +#define MAC_RX_FRAGMENT (0x5363b736UL) +#define MAC_RX_FRAGMENT_COUNT (0xf664c9aUL) +#define MAC_RX_PACKET_BAD_FCS (0x4cb8b34cUL) +#define MAC_RX_PACKET_BAD_FCS_COUNT (0xb6701e28UL) +#define MAC_RX_PACKET_SMALL (0xed318a65UL) +#define MAC_RX_PACKET_SMALL_COUNT (0x72095ec7UL) +#define MAC_RX_TOTAL_BYTES (0x831313e2UL) +#define MAC_RX_TOTAL_BYTES_COUNT (0xe5d8be59UL) +#define MAC_RX_TOTAL_GOOD_BYTES (0x912c2d1cUL) +#define MAC_RX_TOTAL_GOOD_BYTES_COUNT (0x63bb5f3eUL) +#define MAC_RX_TOTAL_GOOD_PACKETS (0xfbb4f497UL) +#define MAC_RX_TOTAL_GOOD_PACKETS_COUNT (0xae9d21b0UL) +#define MAC_RX_TOTAL_PACKETS (0xb0ea3730UL) +#define MAC_RX_TOTAL_PACKETS_COUNT (0x532c885dUL) +#define MAC_RX_UNDERSIZE (0xb6fa4bdbUL) +#define MAC_RX_UNDERSIZE_COUNT (0x471945ffUL) + +#endif /* _NTHW_FPGA_REG_DEFS_MAC_RX_ */ -- 2.45.0