From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C874B45C9A; Fri, 8 Nov 2024 01:32:05 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6C53E42EAB; Fri, 8 Nov 2024 01:32:01 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by mails.dpdk.org (Postfix) with ESMTP id 1DC4B40290; Fri, 8 Nov 2024 01:31:57 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731025919; x=1762561919; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dND+uSsM/gNbKZYqFC/1iSI3YrssE4vDzntz8/gCXio=; b=PBGgutLyuyX1lT9GIKAZD/z7Ap6P62ohNz/b16KSAbSv9nk2sxHgo8WZ gaiKOebVZwn9KY8N4BVSUjQ9IPq1edgufRLCT5c5BtvD7MJaNO0oQCvj+ fBYY25jnr17CR16PDO3y9SdCR30S0+dE1GCwN5FB6PK3LvcA3GPhLMrAn hkqd4G5HvwNDAQRzu8gBv30N2VADu632TQaxCPYWAUMtUQ/gYmX3+M2QT sQGm1pUZNC0mzpsW5jMMqxqZDcaBrFVP6sd2JzPL+c1SLt48bKqK/d7IA AE/NydD7mrdd1Zk6OI9t5J0af/ZRrti5KnDPkwUtcUdzI2pUXclAQrliy w==; X-CSE-ConnectionGUID: It+CoNxLT62zcf9xbEvq5A== X-CSE-MsgGUID: 7rWv3/8IT7S8doAZgIsc5g== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="41456079" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41456079" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 16:31:57 -0800 X-CSE-ConnectionGUID: T3qF9HuGTWSGdRuu2/yUWQ== X-CSE-MsgGUID: ycFk04hmTfWZfftVdahB5g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,136,1728975600"; d="scan'208";a="116157630" Received: from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..) ([10.233.181.123]) by orviesa002.jf.intel.com with ESMTP; 07 Nov 2024 16:31:56 -0800 From: Nicolas Chautru To: dev@dpdk.org, maxime.coquelin@redhat.com Cc: hemant.agrawal@nxp.com, hernan.vargas@intel.com, Nicolas Chautru , stable@dpdk.org Subject: [PATCH v2 1/1] baseband/acc: fix ring memory allocation logic Date: Thu, 7 Nov 2024 16:32:38 -0800 Message-Id: <20241108003238.1921588-2-nicolas.chautru@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241108003238.1921588-1-nicolas.chautru@intel.com> References: <20241108003238.1921588-1-nicolas.chautru@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allowing ring memory allocation whose end address is aligned with 64 MB. Previous logic was off by one. Fixes: 060e76729302 ("baseband/acc100: add queue configuration") Cc: stable@dpdk.org Signed-off-by: Nicolas Chautru --- drivers/baseband/acc/acc_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 4c60b7896b..bf218332be 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -795,7 +795,7 @@ alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc_device *d, sw_rings_base, ACC_SIZE_64MBYTE); next_64mb_align_addr_iova = sw_rings_base_iova + next_64mb_align_offset; - sw_ring_iova_end_addr = sw_rings_base_iova + dev_sw_ring_size; + sw_ring_iova_end_addr = sw_rings_base_iova + dev_sw_ring_size - 1; /* Check if the end of the sw ring memory block is before the * start of next 64MB aligned mem address -- 2.34.1