[PATCH v19 05/13] common/zsda: add definition and use of msg chan.

[Hanxiao Li <li.hanxiao@zte.com.cn>]

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Add msg chan functions and the use to get
hardware information or operate hardware.

Signed-off-by: Hanxiao Li <li.hanxiao@zte.com.cn>
---
 drivers/common/zsda/zsda_qp.c        | 309 +++++++++++++++++++++++++++
 drivers/common/zsda/zsda_qp.h        |  91 ++++++++
 drivers/common/zsda/zsda_qp_common.h |   1 -
 3 files changed, 400 insertions(+), 1 deletion(-)

diff --git a/drivers/common/zsda/zsda_qp.c b/drivers/common/zsda/zsda_qp.c
index 8060d89ea1..0bb0f598b7 100644
--- a/drivers/common/zsda/zsda_qp.c
+++ b/drivers/common/zsda/zsda_qp.c
@@ -11,8 +11,48 @@
 #include "zsda_qp.h"
 #include "zsda_qp_common.h"
 
+
+#define MAGIC_SEND 0xab
+#define MAGIC_RECV 0xcd
+#define ADMIN_VER 1
+
 static uint8_t zsda_num_used_qps;
 
+static const uint8_t crc8_table[256] = {
+	0x00, 0x41, 0x13, 0x52, 0x26, 0x67, 0x35, 0x74, 0x4c, 0x0d, 0x5f, 0x1e,
+	0x6a, 0x2b, 0x79, 0x38, 0x09, 0x48, 0x1a, 0x5b, 0x2f, 0x6e, 0x3c, 0x7d,
+	0x45, 0x04, 0x56, 0x17, 0x63, 0x22, 0x70, 0x31, 0x12, 0x53, 0x01, 0x40,
+	0x34, 0x75, 0x27, 0x66, 0x5e, 0x1f, 0x4d, 0x0c, 0x78, 0x39, 0x6b, 0x2a,
+	0x1b, 0x5a, 0x08, 0x49, 0x3d, 0x7c, 0x2e, 0x6f, 0x57, 0x16, 0x44, 0x05,
+	0x71, 0x30, 0x62, 0x23, 0x24, 0x65, 0x37, 0x76, 0x02, 0x43, 0x11, 0x50,
+	0x68, 0x29, 0x7b, 0x3a, 0x4e, 0x0f, 0x5d, 0x1c, 0x2d, 0x6c, 0x3e, 0x7f,
+	0x0b, 0x4a, 0x18, 0x59, 0x61, 0x20, 0x72, 0x33, 0x47, 0x06, 0x54, 0x15,
+	0x36, 0x77, 0x25, 0x64, 0x10, 0x51, 0x03, 0x42, 0x7a, 0x3b, 0x69, 0x28,
+	0x5c, 0x1d, 0x4f, 0x0e, 0x3f, 0x7e, 0x2c, 0x6d, 0x19, 0x58, 0x0a, 0x4b,
+	0x73, 0x32, 0x60, 0x21, 0x55, 0x14, 0x46, 0x07, 0x48, 0x09, 0x5b, 0x1a,
+	0x6e, 0x2f, 0x7d, 0x3c, 0x04, 0x45, 0x17, 0x56, 0x22, 0x63, 0x31, 0x70,
+	0x41, 0x00, 0x52, 0x13, 0x67, 0x26, 0x74, 0x35, 0x0d, 0x4c, 0x1e, 0x5f,
+	0x2b, 0x6a, 0x38, 0x79, 0x5a, 0x1b, 0x49, 0x08, 0x7c, 0x3d, 0x6f, 0x2e,
+	0x16, 0x57, 0x05, 0x44, 0x30, 0x71, 0x23, 0x62, 0x53, 0x12, 0x40, 0x01,
+	0x75, 0x34, 0x66, 0x27, 0x1f, 0x5e, 0x0c, 0x4d, 0x39, 0x78, 0x2a, 0x6b,
+	0x6c, 0x2d, 0x7f, 0x3e, 0x4a, 0x0b, 0x59, 0x18, 0x20, 0x61, 0x33, 0x72,
+	0x06, 0x47, 0x15, 0x54, 0x65, 0x24, 0x76, 0x37, 0x43, 0x02, 0x50, 0x11,
+	0x29, 0x68, 0x3a, 0x7b, 0x0f, 0x4e, 0x1c, 0x5d, 0x7e, 0x3f, 0x6d, 0x2c,
+	0x58, 0x19, 0x4b, 0x0a, 0x32, 0x73, 0x21, 0x60, 0x14, 0x55, 0x07, 0x46,
+	0x77, 0x36, 0x64, 0x25, 0x51, 0x10, 0x42, 0x03, 0x3b, 0x7a, 0x28, 0x69,
+	0x1d, 0x5c, 0x0e, 0x4f};
+
+static uint8_t
+zsda_crc8(const uint8_t *message, const int length)
+{
+	uint8_t crc = 0;
+	int i;
+
+	for (i = 0; i < length; i++)
+		crc = crc8_table[crc ^ message[i]];
+	return crc;
+}
+
 static uint8_t
 zsda_get_num_used_qps(const struct rte_pci_device *pci_dev)
 {
@@ -173,6 +213,262 @@ zsda_queue_clear(const struct rte_pci_device *pci_dev)
 	return ret;
 }
 
+static uint32_t
+zsda_set_reg_8(void *addr, const uint8_t val0, const uint8_t val1,
+	  const uint8_t val2, const uint8_t val3)
+{
+	uint8_t val[4];
+
+	val[0] = val0;
+	val[1] = val1;
+	val[2] = val2;
+	val[3] = val3;
+	ZSDA_CSR_WRITE32(addr, *(uint32_t *)val);
+	return *(uint32_t *)val;
+}
+
+static uint8_t
+zsda_get_reg_8(void *addr, const int offset)
+{
+	uint32_t val = ZSDA_CSR_READ32(addr);
+
+	return *(((uint8_t *)&val) + offset);
+}
+
+static inline uint32_t
+zsda_modulo_32(uint32_t data, uint32_t modulo_mask)
+{
+	return (data) & (modulo_mask);
+}
+static inline uint16_t
+zsda_modulo_16(uint16_t data, uint16_t modulo_mask)
+{
+	return (data) & (modulo_mask);
+}
+static inline uint8_t
+zsda_modulo_8(uint8_t data, uint8_t modulo_mask)
+{
+	return (data) & (modulo_mask);
+}
+
+static int
+zsda_send_admin_msg(const struct rte_pci_device *pci_dev, void *req,
+		    const uint32_t len)
+{
+	uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+	uint8_t wq_flag;
+	uint8_t crc;
+	uint16_t admin_db;
+	uint32_t retry = ZSDA_TIME_NUM;
+	int i;
+	uint16_t db;
+	int repeat = sizeof(struct zsda_admin_req) / sizeof(uint32_t);
+
+	if (len > ADMIN_BUF_DATA_LEN)
+		return -EINVAL;
+
+	for (i = 0; i < repeat; i++) {
+		ZSDA_CSR_WRITE32(((uint32_t *)(mmio_base + ZSDA_ADMIN_WQ) + i),
+				 *((uint32_t *)req + i));
+	}
+
+	crc = zsda_crc8((uint8_t *)req, ADMIN_BUF_DATA_LEN);
+	zsda_set_reg_8(mmio_base + ZSDA_ADMIN_WQ_BASE7, crc, ADMIN_VER, MAGIC_SEND, 0);
+	rte_delay_us_sleep(ZSDA_TIME_SLEEP_US);
+	rte_wmb();
+
+	admin_db = ZSDA_CSR_READ32(mmio_base + ZSDA_ADMIN_WQ_TAIL);
+	db = zsda_modulo_32(admin_db, 0x1ff);
+	ZSDA_CSR_WRITE32(mmio_base + ZSDA_ADMIN_WQ_TAIL, db);
+
+	do {
+		rte_delay_us_sleep(ZSDA_TIME_SLEEP_US);
+		wq_flag = zsda_get_reg_8(mmio_base + ZSDA_ADMIN_WQ_BASE7, 2);
+		if (wq_flag == MAGIC_RECV)
+			break;
+
+		retry--;
+		if (!retry) {
+			ZSDA_LOG(ERR, "wq_flag 0x%X", wq_flag);
+			zsda_set_reg_8(mmio_base + ZSDA_ADMIN_WQ_BASE7, 0, crc,
+				  ADMIN_VER, 0);
+			return -EIO;
+		}
+	} while (1);
+
+	return ZSDA_SUCCESS;
+}
+
+static int
+zsda_recv_admin_msg(const struct rte_pci_device *pci_dev, void *resp,
+		    const uint32_t len)
+{
+	uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+	uint8_t cq_flag;
+	uint32_t retry = ZSDA_TIME_NUM;
+	uint8_t crc;
+	uint8_t buf[ADMIN_BUF_TOTAL_LEN] = {0};
+	uint32_t i;
+
+	if (len > ADMIN_BUF_DATA_LEN)
+		return -EINVAL;
+
+	do {
+		rte_delay_us_sleep(ZSDA_TIME_SLEEP_US);
+
+		cq_flag = zsda_get_reg_8(mmio_base + ZSDA_ADMIN_CQ_BASE7, 2);
+		if (cq_flag == MAGIC_SEND)
+			break;
+
+		retry--;
+		if (!retry)
+			return -EIO;
+	} while (1);
+
+	for (i = 0; i < len; i++)
+		buf[i] = ZSDA_CSR_READ8(mmio_base + ZSDA_ADMIN_CQ + i);
+
+	crc = ZSDA_CSR_READ8(mmio_base + ZSDA_ADMIN_CQ_CRC);
+	rte_rmb();
+	ZSDA_CSR_WRITE8(mmio_base + ZSDA_ADMIN_CQ_FLAG, MAGIC_RECV);
+	if (crc != zsda_crc8(buf, ADMIN_BUF_DATA_LEN)) {
+		ZSDA_LOG(ERR, "[%d] Failed! crc error!", __LINE__);
+		return -EIO;
+	}
+
+	memcpy(resp, buf, len);
+
+	return ZSDA_SUCCESS;
+}
+
+static int
+zsda_admin_msg_init(const struct rte_pci_device *pci_dev)
+{
+	uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+
+	zsda_set_reg_8(mmio_base + ZSDA_ADMIN_WQ_BASE7, 0, 0, MAGIC_RECV, 0);
+	zsda_set_reg_8(mmio_base + ZSDA_ADMIN_CQ_BASE7, 0, 0, MAGIC_RECV, 0);
+	return 0;
+}
+
+static void
+zsda_set_queue_head_tail(const struct zsda_pci_device *zsda_pci_dev,
+			 const uint8_t qid)
+{
+	struct rte_pci_device *pci_dev =
+		zsda_devs[zsda_pci_dev->zsda_dev_id].pci_dev;
+	uint8_t *mmio_base = pci_dev->mem_resource[0].addr;
+
+	ZSDA_CSR_WRITE32(mmio_base + IO_DB_INITIAL_CONFIG + (qid * 4),
+			 SET_HEAD_INTI);
+}
+
+static int
+zsda_get_queue_cfg_by_id(const struct zsda_pci_device *zsda_pci_dev,
+			 const uint8_t qid, struct qinfo *qcfg)
+{
+	struct zsda_admin_req_qcfg req = {0};
+	struct zsda_admin_resp_qcfg resp = {0};
+	int ret;
+	struct rte_pci_device *pci_dev =
+		zsda_devs[zsda_pci_dev->zsda_dev_id].pci_dev;
+
+	if (qid >= MAX_QPS_ON_FUNCTION) {
+		ZSDA_LOG(ERR, "qid beyond limit!");
+		return ZSDA_FAILED;
+	}
+
+	zsda_admin_msg_init(pci_dev);
+	req.msg_type = ZSDA_ADMIN_QUEUE_CFG_REQ;
+	req.qid = qid;
+
+	ret = zsda_send_admin_msg(pci_dev, &req, sizeof(req));
+	if (ret) {
+		ZSDA_LOG(ERR, "Failed! Send msg");
+		return ret;
+	}
+
+	ret = zsda_recv_admin_msg(pci_dev, &resp, sizeof(resp));
+	if (ret) {
+		ZSDA_LOG(ERR, "Failed! Receive msg");
+		return ret;
+	}
+
+	*qcfg = resp.qcfg;
+
+	return ZSDA_SUCCESS;
+}
+
+static struct ring_size zsda_qp_hw_ring_size[ZSDA_MAX_SERVICES] = {
+
+};
+
+static int
+zsda_get_queue_cfg(struct zsda_pci_device *zsda_pci_dev)
+{
+	uint8_t i;
+	uint32_t index;
+	enum zsda_service_type type;
+	struct zsda_qp_hw *zsda_hw_qps = zsda_pci_dev->zsda_hw_qps;
+	struct qinfo qcfg = {0};
+	int ret;
+
+	for (i = 0; i < zsda_num_used_qps; i++) {
+		zsda_set_queue_head_tail(zsda_pci_dev, i);
+		ret = zsda_get_queue_cfg_by_id(zsda_pci_dev, i, &qcfg);
+		type = qcfg.q_type;
+		if (ret) {
+			ZSDA_LOG(ERR, "get queue cfg!");
+			return ret;
+		}
+		if (type >= ZSDA_SERVICE_INVALID)
+			continue;
+
+		index = zsda_pci_dev->zsda_qp_hw_num[type];
+		zsda_hw_qps[type].data[index].used = true;
+		zsda_hw_qps[type].data[index].tx_ring_num = i;
+		zsda_hw_qps[type].data[index].rx_ring_num = i;
+		zsda_hw_qps[type].data[index].tx_msg_size =
+			zsda_qp_hw_ring_size[type].tx_msg_size;
+		zsda_hw_qps[type].data[index].rx_msg_size =
+			zsda_qp_hw_ring_size[type].rx_msg_size;
+
+		zsda_pci_dev->zsda_qp_hw_num[type]++;
+	}
+
+	return ret;
+}
+
+static int
+zsda_unmask_flr(const struct zsda_pci_device *zsda_pci_dev)
+{
+	struct zsda_admin_req_qcfg req = {0};
+	struct zsda_admin_resp_qcfg resp = {0};
+
+	int ret = 0;
+	struct rte_pci_device *pci_dev =
+		zsda_devs[zsda_pci_dev->zsda_dev_id].pci_dev;
+
+	zsda_admin_msg_init(pci_dev);
+
+	req.msg_type = ZSDA_FLR_SET_FUNCTION;
+
+	ret = zsda_send_admin_msg(pci_dev, &req, sizeof(req));
+	if (ret) {
+		ZSDA_LOG(ERR, "Failed! Send msg");
+		return ret;
+	}
+
+	ret = zsda_recv_admin_msg(pci_dev, &resp, sizeof(resp));
+	if (ret) {
+		ZSDA_LOG(ERR, "Failed! Receive msg");
+		return ret;
+	}
+
+	return ZSDA_SUCCESS;
+}
+
+
 int
 zsda_queue_init(struct zsda_pci_device *zsda_pci_dev)
 {
@@ -192,5 +488,18 @@ zsda_queue_init(struct zsda_pci_device *zsda_pci_dev)
 		ZSDA_LOG(ERR, "Failed! used zsda_io q clear");
 		return ret;
 	}
+
+	ret = zsda_get_queue_cfg(zsda_pci_dev);
+	if (ret) {
+		ZSDA_LOG(ERR, "Failed! zsda_get_queue_cfg");
+		return ret;
+	}
+
+	ret = zsda_unmask_flr(zsda_pci_dev);
+	if (ret) {
+		ZSDA_LOG(ERR, "Failed! zsda_unmask_flr");
+		return ret;
+	}
+
 	return ret;
 }
diff --git a/drivers/common/zsda/zsda_qp.h b/drivers/common/zsda/zsda_qp.h
index 9861606ac8..1eb193e99c 100644
--- a/drivers/common/zsda/zsda_qp.h
+++ b/drivers/common/zsda/zsda_qp.h
@@ -17,6 +17,19 @@
 #define ZSDA_IO_Q_CLR			0x600
 #define ZSDA_IO_Q_CLR_RESP		0x800
 
+#define ZSDA_ADMIN_WQ			0x40
+#define ZSDA_ADMIN_WQ_BASE7		0x5C
+#define ZSDA_ADMIN_WQ_CRC		0x5C
+#define ZSDA_ADMIN_WQ_VERSION	0x5D
+#define ZSDA_ADMIN_WQ_FLAG		0x5E
+#define ZSDA_ADMIN_CQ			0x60
+#define ZSDA_ADMIN_CQ_BASE7		0x7C
+#define ZSDA_ADMIN_CQ_CRC		0x7C
+#define ZSDA_ADMIN_CQ_VERSION	0x7D
+#define ZSDA_ADMIN_CQ_FLAG		0x7E
+#define ZSDA_ADMIN_WQ_TAIL		0x80
+#define ZSDA_ADMIN_CQ_HEAD		0x84
+
 #define ZSDA_Q_START		0x1
 #define ZSDA_Q_STOP			0x0
 #define ZSDA_CLEAR_VALID	0x1
@@ -24,11 +37,89 @@
 #define ZSDA_RESP_VALID		0x1
 #define ZSDA_RESP_INVALID	0x0
 
+#define ADMIN_BUF_DATA_LEN		0x1C
+#define ADMIN_BUF_TOTAL_LEN		0x20
+
+#define IO_DB_INITIAL_CONFIG	0x1C00
+#define SET_CYCLE			0xff
+#define SET_HEAD_INTI		0x0
+
+
 #define ZSDA_TIME_SLEEP_US	100
 #define ZSDA_TIME_NUM		500
 
 extern struct zsda_num_qps zsda_nb_qps;
 
+enum zsda_admin_msg_id {
+	/* Version information */
+	ZSDA_ADMIN_VERSION_REQ = 0,
+	ZSDA_ADMIN_VERSION_RESP,
+	/* algo type */
+	ZSDA_ADMIN_QUEUE_CFG_REQ,
+	ZSDA_ADMIN_QUEUE_CFG_RESP,
+	/* get cycle */
+	ZSDA_ADMIN_QUEUE_CYCLE_REQ,
+	ZSDA_ADMIN_QUEUE_CYCLE_RESP,
+	/* set cyclr */
+	ZSDA_ADMIN_SET_CYCLE_REQ,
+	ZSDA_ADMIN_SET_CYCLE_RESP,
+
+	ZSDA_MIG_STATE_WARNING,
+	ZSDA_ADMIN_RESERVE,
+	/* set close flr register */
+	ZSDA_FLR_SET_FUNCTION,
+	ZSDA_ADMIN_MSG_VALID,
+	ZSDA_ADMIN_INT_TEST
+};
+
+enum zsda_service_type {
+	ZSDA_SERVICE_INVALID,
+};
+
+struct ring_size {
+	uint16_t tx_msg_size;
+	uint16_t rx_msg_size;
+};
+
+struct zsda_admin_req {
+	uint16_t msg_type;
+	uint8_t data[26];
+} __rte_packed;
+
+struct zsda_admin_resp {
+	uint16_t msg_type;
+	uint8_t data[26];
+} __rte_packed;
+
+struct zsda_admin_req_qcfg {
+	uint16_t msg_type;
+	uint8_t qid;
+	uint8_t data[25];
+} __rte_packed;
+
+struct zsda_test_msg {
+	uint32_t msg_type;
+	uint32_t data_in;
+	uint8_t data[20];
+} __rte_packed;
+
+struct qinfo {
+	uint16_t q_type;
+	uint16_t wq_tail;
+	uint16_t wq_head;
+	uint16_t cq_tail;
+	uint16_t cq_head;
+	uint16_t cycle;
+} __rte_packed;
+
+struct zsda_admin_resp_qcfg {
+	uint16_t msg_type;
+	struct qinfo qcfg;
+	uint8_t data[14];
+} __rte_packed;
+
+
+
 int zsda_queue_start(const struct rte_pci_device *pci_dev);
 int zsda_queue_stop(const struct rte_pci_device *pci_dev);
 
diff --git a/drivers/common/zsda/zsda_qp_common.h b/drivers/common/zsda/zsda_qp_common.h
index 34a35a1206..9c09a227a3 100644
--- a/drivers/common/zsda/zsda_qp_common.h
+++ b/drivers/common/zsda/zsda_qp_common.h
@@ -13,7 +13,6 @@
 #include <rte_mbuf.h>
 
 #include "zsda_logs.h"
-#include "zsda_device.h"
 
 #define ZSDA_SUCCESS			0
 #define ZSDA_FAILED				(-1)
-- 
2.27.0

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