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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1PEPF000044F1.mail.protection.outlook.com (10.167.241.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8158.14 via Frontend Transport; Wed, 13 Nov 2024 07:23:27 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 12 Nov 2024 23:23:08 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 12 Nov 2024 23:23:06 -0800 From: Bing Zhao To: , , , CC: , , , Subject: [PATCH] net/mlx5: fix Rx queue ref count in flushing user flows Date: Wed, 13 Nov 2024 09:22:44 +0200 Message-ID: <20241113072244.7627-1-bingz@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F1:EE_|MN0PR12MB5788:EE_ X-MS-Office365-Filtering-Correlation-Id: ddf0cc99-faf4-41df-2cc2-08dd03b4114f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2024 07:23:27.4939 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddf0cc99-faf4-41df-2cc2-08dd03b4114f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5788 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some indirect table and hrxq is created in the rule creation with QUEUE or RSS action. When stopping a port, the 'dev_started' is set to 0 in the beginning. The mlx5_ind_table_obj_release() should still do the dereference of the queue(s) when it is called in the polling of flow rule deletion, due to the fact that a flow with Q/RSS action is always referring to the active Rx queues. The callback now can only pass one input parameter. Using a global flag per device to indicate that the user flows flushing is in progress. Then the reference count of the queue(s) should be decreased. Fixes: 3a2f674b6aa8 ("net/mlx5: add queue and RSS HW steering action") Cc: stable@dpdk.org Signed-off-by: Bing Zhao Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_flow.c | 3 +++ drivers/net/mlx5/mlx5_rxq.c | 8 +++++--- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 503366580b..80e59a6cb5 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -2033,6 +2033,7 @@ struct mlx5_priv { RTE_ATOMIC(uint32_t) hws_mark_refcnt; /* HWS mark action reference counter. */ struct rte_pmd_mlx5_flow_engine_mode_info mode_info; /* Process set flow engine info. */ struct mlx5_flow_hw_attr *hw_attr; /* HW Steering port configuration. */ + bool hws_rule_flushing; /**< Whether this port is in rules flushing stage. */ #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) /* Item template list. */ LIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt; diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index f8cfa661ec..533ae7a63d 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -8118,7 +8118,10 @@ mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, #ifdef HAVE_IBV_FLOW_DV_SUPPORT if (priv->sh->config.dv_flow_en == 2 && type == MLX5_FLOW_TYPE_GEN) { + priv->hws_rule_flushing = true; flow_hw_q_flow_flush(dev, NULL); + priv->hws_rule_flushing = false; + return; } #endif MLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) { diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 5eac224b76..3f492ef163 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2894,6 +2894,7 @@ static void __mlx5_hrxq_remove(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq) { struct mlx5_priv *priv = dev->data->dev_private; + bool deref_rxqs = true; #ifdef HAVE_IBV_FLOW_DV_SUPPORT if (hrxq->hws_flags) @@ -2903,9 +2904,10 @@ __mlx5_hrxq_remove(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq) #endif priv->obj_ops.hrxq_destroy(hrxq); if (!hrxq->standalone) { - mlx5_ind_table_obj_release(dev, hrxq->ind_table, - hrxq->hws_flags ? - (!!dev->data->dev_started) : true); + if (!dev->data->dev_started && hrxq->hws_flags && + !priv->hws_rule_flushing) + deref_rxqs = false; + mlx5_ind_table_obj_release(dev, hrxq->ind_table, deref_rxqs); } mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq->idx); } -- 2.34.1