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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea06f4856esm2123781a91.23.2024.11.14.22.08.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 22:08:02 -0800 (PST) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , akhil.goyal@nxp.com, stable@dpdk.org, Gagandeep Singh , Hemant Agrawal , Akhil Goyal Subject: [PATCH 13/16] crypto/dpaa_sec: fix bitmask truncation Date: Thu, 14 Nov 2024 22:05:50 -0800 Message-ID: <20241115060738.313190-14-stephen@networkplumber.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115060738.313190-1-stephen@networkplumber.org> References: <20241115060738.313190-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The dqrr_held mask is 64 bit but updates were getting truncated because 1 is of type int (32 bit) and the result shift of int is of type int (32 bit); therefore any value >= 32 would get truncated. Link: https://pvs-studio.com/en/blog/posts/cpp/1183/ Fixes: fe3688ba7950 ("crypto/dpaa_sec: support event crypto adapter") Cc: akhil.goyal@nxp.com Cc: stable@dpdk.org Signed-off-by: Stephen Hemminger --- drivers/crypto/dpaa_sec/dpaa_sec.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c index 3fa88ca968..e117cd77a6 100644 --- a/drivers/crypto/dpaa_sec/dpaa_sec.c +++ b/drivers/crypto/dpaa_sec/dpaa_sec.c @@ -1907,13 +1907,12 @@ dpaa_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops, op = *(ops++); if (*dpaa_seqn(op->sym->m_src) != 0) { index = *dpaa_seqn(op->sym->m_src) - 1; - if (DPAA_PER_LCORE_DQRR_HELD & (1 << index)) { + if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << index)) { /* QM_EQCR_DCA_IDXMASK = 0x0f */ flags[loop] = ((index & 0x0f) << 8); flags[loop] |= QMAN_ENQUEUE_FLAG_DCA; DPAA_PER_LCORE_DQRR_SIZE--; - DPAA_PER_LCORE_DQRR_HELD &= - ~(1 << index); + DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << index); } } @@ -3500,7 +3499,7 @@ dpaa_sec_process_atomic_event(void *event, /* Save active dqrr entries */ index = ((uintptr_t)dqrr >> 6) & (16/*QM_DQRR_SIZE*/ - 1); DPAA_PER_LCORE_DQRR_SIZE++; - DPAA_PER_LCORE_DQRR_HELD |= 1 << index; + DPAA_PER_LCORE_DQRR_HELD |= UINT64_C(1) << index; DPAA_PER_LCORE_DQRR_MBUF(index) = ctx->op->sym->m_src; ev->impl_opaque = index + 1; *dpaa_seqn(ctx->op->sym->m_src) = (uint32_t)index + 1; -- 2.45.2