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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea06f4856esm2123781a91.23.2024.11.14.22.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 22:08:46 -0800 (PST) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , sunil.kori@nxp.com, stable@dpdk.org, Hemant Agrawal , Sachin Saxena , skori@marvell.com, Nipun Gupta Subject: [PATCH 15/16] net/dpaa: fix bitmask truncation Date: Thu, 14 Nov 2024 22:05:52 -0800 Message-ID: <20241115060738.313190-16-stephen@networkplumber.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241115060738.313190-1-stephen@networkplumber.org> References: <20241115060738.313190-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The dqrr_held mask is 64 bit but updates were getting truncated because 1 is of type int (32 bit) and the result shift of int is of type int (32 bit); therefore any value >= 32 would get truncated. Link: https://pvs-studio.com/en/blog/posts/cpp/1183/ Fixes: 5e7455931442 ("net/dpaa: support Rx queue configurations with eventdev") Cc: sunil.kori@nxp.com Cc: stable@dpdk.org Signed-off-by: Stephen Hemminger --- drivers/net/dpaa/dpaa_rxtx.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/net/dpaa/dpaa_rxtx.c b/drivers/net/dpaa/dpaa_rxtx.c index 247e7b92ba..05bd73becf 100644 --- a/drivers/net/dpaa/dpaa_rxtx.c +++ b/drivers/net/dpaa/dpaa_rxtx.c @@ -842,7 +842,7 @@ dpaa_rx_cb_atomic(void *event, /* Save active dqrr entries */ index = DQRR_PTR2IDX(dqrr); DPAA_PER_LCORE_DQRR_SIZE++; - DPAA_PER_LCORE_DQRR_HELD |= 1 << index; + DPAA_PER_LCORE_DQRR_HELD |= UINT64_C(1) << index; DPAA_PER_LCORE_DQRR_MBUF(index) = mbuf; ev->impl_opaque = index + 1; *dpaa_seqn(mbuf) = (uint32_t)index + 1; @@ -1338,13 +1338,12 @@ dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs) seqn = *dpaa_seqn(mbuf); if (seqn != DPAA_INVALID_MBUF_SEQN) { index = seqn - 1; - if (DPAA_PER_LCORE_DQRR_HELD & (1 << index)) { + if (DPAA_PER_LCORE_DQRR_HELD & (UINT64_C(1) << index)) { flags[loop] = ((index & QM_EQCR_DCA_IDXMASK) << 8); flags[loop] |= QMAN_ENQUEUE_FLAG_DCA; DPAA_PER_LCORE_DQRR_SIZE--; - DPAA_PER_LCORE_DQRR_HELD &= - ~(1 << index); + DPAA_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << index); } } -- 2.45.2