From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2543745D18; Sat, 16 Nov 2024 02:12:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 106F54068A; Sat, 16 Nov 2024 02:12:58 +0100 (CET) Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by mails.dpdk.org (Postfix) with ESMTP id 90937402BB for ; Sat, 16 Nov 2024 02:12:56 +0100 (CET) Received: by mail-pj1-f41.google.com with SMTP id 98e67ed59e1d1-2e9b4a4182dso1763786a91.0 for ; Fri, 15 Nov 2024 17:12:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1731719575; x=1732324375; darn=dpdk.org; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=4AlCxqBPtVrzsLq9U9XkwQuuvYwUcxhmr5HHKJJ/gOc=; b=ICy9rjXdgaODX4GTlkJ7Oz61V11FqXAtLQtDBBl/KBE9ka6qxT7Df3rFbGqzJLhQyR OBUHMx7rU08uS2CifXnMhx11Rgy+vdBYP1coKK2IGyAe6Q/iQxMTFJQrGCBZAM3t8n2D IZhCv9D0/Jc7TA+3EdRK8cDATkICJ/gdmQDms= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731719575; x=1732324375; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=4AlCxqBPtVrzsLq9U9XkwQuuvYwUcxhmr5HHKJJ/gOc=; b=TSO4cyk7+hvhfyesq0nXbkYOCgNNDXfoKlASfaX1JKW1+RPIhlJvOdSjgJytoDjRbq /XicfGnORR1NEyViP2UyEjhEI+xZrzTqd0rWdVtMphPIN7JMFyVSaelmzpc1XhqT8Yng av4NFyvA7XDEHGarcZebC0ghRd6yibJgUJoyhbzskWpPbptwf9/lRWFedoh9l2TH6e55 VbV9qr+CdkKSWRFxD3/x7H8NTGuYOj5Yc1r7XyZ873qeyuM7Rv+7g4GUebMojPtMqSYU a4lDIXZHefajoDuVclH/AkB9F1f2FcpKCcbzcxKf1p16+/1kzH6kOZ565xx8u35LubrL 6eMA== X-Gm-Message-State: AOJu0Ywts43AXVy2SxXH6ZMr9To0/MwK+aiBO2T5/YbTFZG6+yzRU911 gH4+Xs/Uxq+H5aEvHp4jkJhpbvxMi8dw2SDlL0ITD0qu/13MM0ufxzQAPFp/BrTmkKMQo42Nut9 CrG8atOCRZaOEhUCWQ4XNq47Itmjtqc4F/m7OSPajQhnA3bOt2jr9UINxl1rBkq6vBfPOZOm9Jq Cz8/dCBGOhUprczluBx1yUKWa8R5c1/JA= X-Google-Smtp-Source: AGHT+IECznkPc0/Gn9LRUHwiaqQsA2mX0MIseXNTFW0rPRtOImDLebKTI9G+RCRe1zyO98vWIG8ZjA== X-Received: by 2002:a17:90b:33c6:b0:2da:6e46:ad48 with SMTP id 98e67ed59e1d1-2ea14e04c4fmr7745720a91.1.1731719575061; Fri, 15 Nov 2024 17:12:55 -0800 (PST) Received: from localhost.localdomain ([136.52.21.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea06f9c677sm3818233a91.36.2024.11.15.17.12.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2024 17:12:54 -0800 (PST) From: Ajit Khaparde To: dev@dpdk.org Subject: [PATCH 1/2] net/bnxt: update HWRM API Date: Fri, 15 Nov 2024 17:12:48 -0800 Message-Id: <20241116011249.48013-1-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update HWRM API to select ring profile. Signed-off-by: Ajit Khaparde --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 71 +++++++++++++++++++++++++- 1 file changed, 69 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 8f348c20fb..737bf2693b 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -15617,7 +15617,46 @@ struct hwrm_func_qcaps_output { * (SR-IOV) disabled or on a VF. */ uint32_t roce_vf_max_gid; - uint8_t unused_3[3]; + uint32_t flags_ext3; + /* + * When this bit is '1', firmware supports the driver using + * FUNC_CFG (or FUNC_VF_CFG) to decrease resource reservations + * while some resources are still allocated. An error is returned + * if the driver tries to set the reservation to be less than the + * number of allocated resources. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP \ + UINT32_C(0x1) + /* + * When this bit is '1', the PF requires an L2 filter to be + * allocated by the driver using HWRM_CFA_L2_FILTER_ALLOC after + * bringing the interface up, before traffic is sent. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_REQUIRE_L2_FILTER \ + UINT32_C(0x2) + /* + * When set to 1, indicates the field max_roce_vfs in the structure + * is valid. If this bit is 0, the driver should not use the + * 'max_roce_vfs' field. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED \ + UINT32_C(0x4) + /* + * When set to 1, indicates the field 'rx_rate_profile_sel' in + * RING_ALLOC can specify a valid RX rate profile when allocating + * RX or RX aggregation rings. If this bit is 0, the driver + * should not use the 'rx_rate_profile_sel' field. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RX_RATE_PROFILE_SEL_SUPPORTED \ + UINT32_C(0x8) + /* + * The number of VFs that can be used for RoCE on the function. If less + * than max_vfs, roce vfs will be assigned to the first VF of the + * function and be contiguous. + * This is valid only on the PF with SR-IOV and RDMA enabled. + */ + uint16_t max_roce_vfs; + uint8_t unused_3[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -45026,6 +45065,14 @@ struct hwrm_ring_alloc_input { */ #define HWRM_RING_ALLOC_INPUT_ENABLES_STEERING_TAG_VALID \ UINT32_C(0x800) + /* + * This bit must be '1' for the rx_rate_profile_sel field to + * be configured. This should only be used when + * 'rx_rate_profile_sel_supported' bit is set in flags_ext3 + * field of FUNC_QCAPS response. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RATE_PROFILE_VALID \ + UINT32_C(0x1000) /* Ring Type. */ uint8_t ring_type; /* L2 Completion Ring (CR) */ @@ -45362,7 +45409,27 @@ struct hwrm_ring_alloc_input { #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4) #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \ HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE - uint8_t unused_4[2]; + /* RX rate profile select */ + uint8_t rx_rate_profile_sel; + /* + * Indicate default RX rate profile when allocating + * RX or RX aggregation rings. This should only be + * used when 'rx_rate_profile_sel_supported' bit is + * set in flags_ext3 field of FUNC_QCAPS response. + */ + #define HWRM_RING_ALLOC_INPUT_RX_RATE_PROFILE_SEL_DEFAULT \ + UINT32_C(0x0) + /* + * Indicate poll_mode RX rate profile when allocating + * RX or RX aggregation rings. This should only be + * used when 'rx_rate_profile_sel_supported' bit is + * set in flags_ext3 field of FUNC_QCAPS response. + */ + #define HWRM_RING_ALLOC_INPUT_RX_RATE_PROFILE_SEL_POLL_MODE \ + UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_RX_RATE_PROFILE_SEL_LAST \ + HWRM_RING_ALLOC_INPUT_RX_RATE_PROFILE_SEL_POLL_MODE + uint8_t unused_4; /* * The cq_handle is specified when allocating a completion ring. For * devices that support NQs, this cq_handle will be included in the -- 2.39.5 (Apple Git-154)