From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DDD5545D39; Mon, 18 Nov 2024 22:13:24 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 121A940EE3; Mon, 18 Nov 2024 22:13:21 +0100 (CET) Received: from mail-qk1-f181.google.com (mail-qk1-f181.google.com [209.85.222.181]) by mails.dpdk.org (Postfix) with ESMTP id 51BBD40E35 for ; Mon, 18 Nov 2024 22:13:19 +0100 (CET) Received: by mail-qk1-f181.google.com with SMTP id af79cd13be357-7b152a23e9aso12798085a.0 for ; Mon, 18 Nov 2024 13:13:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1731964398; x=1732569198; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4AlCxqBPtVrzsLq9U9XkwQuuvYwUcxhmr5HHKJJ/gOc=; b=hspQN/a73YrkhZvOYXdcidXrTq0y+WgfRHNKWgaZuLVGp/zuH36kMVr6gbCBZt/xMU MzTe2OdMb3XzAZa17ny0+/AZM7RK2VQQ8siccZ4plL7ptSBVu83T+NCzhxuhkjbh3Qyn 7SoTU/nMMFG7bdsyRtf9UHMtA8W34LL4Jc/yU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731964398; x=1732569198; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4AlCxqBPtVrzsLq9U9XkwQuuvYwUcxhmr5HHKJJ/gOc=; b=E1gezuJM308NMyV4n9ezRrVTX6ZwMANFW3IlLSA659pJ1AS5CSr4+2BQQkIjbSn1Zo +FNXD0uObvnyM8FhBVWokd8vqfLyjQ4JRbu2/kBrRCfVczsnB4SUt55ComdC2B4JXC0O bchX2FCvcbSvZ0wigOoD+ikKfku6+DpFt1Ul33JhkgdLh4qI/rOBH0cY5IDuqKgsNzoZ 9iUY0kRWH0Vv0uhK1CYmTc9mr6VJ0VxOUI4aOzxDjvHP9fb2A5opLWLd+WaVsl+rT+0b lhkQdL8uLEWzYMBGCo9l1uYtx/4GwMvoHEJoK7BkJm5F6ZUxx7xsZ8dCHZPwdNTJyk4Z iS1Q== X-Gm-Message-State: AOJu0Yw5EprtP6qCA4/gi59HESOF9mCoHm8rtBSKESiPgFKq7sbCPMeg EnJUDnxTlfUtR17aLzxuawwYpYpkUBI3Oq0c3MjJKiBgBt8BO+oCrjsb5Idow8BXeI/2rBEi3uP /+HYWAvyygY3D8gxBXWqsynz5CZgKzrMkA19nRLDz5nwvjuCifAiSjocWtO7egkEroyaLop58LR SeBGWIldGsgr+T7agqQStTBo3nMp7L X-Google-Smtp-Source: AGHT+IHzbvOaFAO+HOKV/SGzvvfD1OBS/CaO6Hr0QSKKXAVAxPTy7IMrFG+qlW+pxxBrd9yWsKn9Eg== X-Received: by 2002:a05:620a:1a83:b0:7a9:c160:c80b with SMTP id af79cd13be357-7b362298c87mr1602115085a.8.1731964397774; Mon, 18 Nov 2024 13:13:17 -0800 (PST) Received: from C02GC2QQMD6T.wifi.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7b37a8963aesm26346685a.88.2024.11.18.13.13.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2024 13:13:17 -0800 (PST) From: Ajit Khaparde To: dev@dpdk.org Subject: [PATCH v3 1/2] net/bnxt: update HWRM API Date: Mon, 18 Nov 2024 13:13:11 -0800 Message-Id: <20241118211312.6181-2-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20241118211312.6181-1-ajit.khaparde@broadcom.com> References: <20241118211312.6181-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update HWRM API to select ring profile. Signed-off-by: Ajit Khaparde --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 71 +++++++++++++++++++++++++- 1 file changed, 69 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 8f348c20fb..737bf2693b 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -15617,7 +15617,46 @@ struct hwrm_func_qcaps_output { * (SR-IOV) disabled or on a VF. */ uint32_t roce_vf_max_gid; - uint8_t unused_3[3]; + uint32_t flags_ext3; + /* + * When this bit is '1', firmware supports the driver using + * FUNC_CFG (or FUNC_VF_CFG) to decrease resource reservations + * while some resources are still allocated. An error is returned + * if the driver tries to set the reservation to be less than the + * number of allocated resources. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP \ + UINT32_C(0x1) + /* + * When this bit is '1', the PF requires an L2 filter to be + * allocated by the driver using HWRM_CFA_L2_FILTER_ALLOC after + * bringing the interface up, before traffic is sent. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_REQUIRE_L2_FILTER \ + UINT32_C(0x2) + /* + * When set to 1, indicates the field max_roce_vfs in the structure + * is valid. If this bit is 0, the driver should not use the + * 'max_roce_vfs' field. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED \ + UINT32_C(0x4) + /* + * When set to 1, indicates the field 'rx_rate_profile_sel' in + * RING_ALLOC can specify a valid RX rate profile when allocating + * RX or RX aggregation rings. If this bit is 0, the driver + * should not use the 'rx_rate_profile_sel' field. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RX_RATE_PROFILE_SEL_SUPPORTED \ + UINT32_C(0x8) + /* + * The number of VFs that can be used for RoCE on the function. If less + * than max_vfs, roce vfs will be assigned to the first VF of the + * function and be contiguous. + * This is valid only on the PF with SR-IOV and RDMA enabled. + */ + uint16_t max_roce_vfs; + uint8_t unused_3[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -45026,6 +45065,14 @@ struct hwrm_ring_alloc_input { */ #define HWRM_RING_ALLOC_INPUT_ENABLES_STEERING_TAG_VALID \ UINT32_C(0x800) + /* + * This bit must be '1' for the rx_rate_profile_sel field to + * be configured. This should only be used when + * 'rx_rate_profile_sel_supported' bit is set in flags_ext3 + * field of FUNC_QCAPS response. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RATE_PROFILE_VALID \ + UINT32_C(0x1000) /* Ring Type. */ uint8_t ring_type; /* L2 Completion Ring (CR) */ @@ -45362,7 +45409,27 @@ struct hwrm_ring_alloc_input { #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4) #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \ HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE - uint8_t unused_4[2]; + /* RX rate profile select */ + uint8_t rx_rate_profile_sel; + /* + * Indicate default RX rate profile when allocating + * RX or RX aggregation rings. This should only be + * used when 'rx_rate_profile_sel_supported' bit is + * set in flags_ext3 field of FUNC_QCAPS response. + */ + #define HWRM_RING_ALLOC_INPUT_RX_RATE_PROFILE_SEL_DEFAULT \ + UINT32_C(0x0) + /* + * Indicate poll_mode RX rate profile when allocating + * RX or RX aggregation rings. This should only be + * used when 'rx_rate_profile_sel_supported' bit is + * set in flags_ext3 field of FUNC_QCAPS response. + */ + #define HWRM_RING_ALLOC_INPUT_RX_RATE_PROFILE_SEL_POLL_MODE \ + UINT32_C(0x1) + #define HWRM_RING_ALLOC_INPUT_RX_RATE_PROFILE_SEL_LAST \ + HWRM_RING_ALLOC_INPUT_RX_RATE_PROFILE_SEL_POLL_MODE + uint8_t unused_4; /* * The cq_handle is specified when allocating a completion ring. For * devices that support NQs, this cq_handle will be included in the -- 2.39.5 (Apple Git-154)