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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1PEPF000042AB.mail.protection.outlook.com (10.167.243.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8207.12 via Frontend Transport; Mon, 25 Nov 2024 17:24:04 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 25 Nov 2024 09:23:33 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 25 Nov 2024 09:23:31 -0800 From: Bing Zhao To: , , , CC: , , , Subject: [PATCH] net/mlx5: fix Rx queue control deref Date: Mon, 25 Nov 2024 19:23:18 +0200 Message-ID: <20241125172318.302560-1-bingz@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AB:EE_|DM6PR12MB4388:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ac334a9-1fa3-4b72-2d68-08dd0d75f5cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2024 17:24:04.0827 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ac334a9-1fa3-4b72-2d68-08dd0d75f5cb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4388 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When the Rx queue is shared, only the control structure is shared and the private structure of each Rx queue is still independent. During the port stop stage, the hardware resource will be released, and the memory will be freed in the device close stage. Then the control structure reference count should be decreased when freeing a private structure. In the previous implementation, the decreasing action was wrongly put inside the owners list empty condition. Indeed, they should be in the same level. And since the reference count was set to 1 after the 1st queue is created, when checking the value, it should be subtracted firstly and then check the value. With this commit, the reference calculation and condition checking will be corrected. The shared Rx queues' control structures will be freed successlly to avoid the crash in the port restarting. Fixes: 3c9a82fa6edc ("net/mlx5: fix Rx queue control management") Cc: stable@dpdk.org Signed-off-by: Bing Zhao Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_rx.h | 2 +- drivers/net/mlx5/mlx5_rxq.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index da7c448948..1a6f174c40 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -157,7 +157,7 @@ struct mlx5_rxq_ctrl { bool is_hairpin; /* Whether RxQ type is Hairpin. */ unsigned int socket; /* CPU socket ID for allocations. */ LIST_ENTRY(mlx5_rxq_ctrl) share_entry; /* Entry in shared RXQ list. */ - RTE_ATOMIC(uint32_t) ctrl_ref; /* Reference counter. */ + RTE_ATOMIC(int32_t) ctrl_ref; /* Reference counter. */ uint32_t share_group; /* Group ID of shared RXQ. */ uint16_t share_qid; /* Shared RxQ ID in group. */ unsigned int started:1; /* Whether (shared) RXQ has been started. */ diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 0737f60272..126b1970e6 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -2268,6 +2268,7 @@ mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx) struct mlx5_rxq_priv *rxq; struct mlx5_rxq_ctrl *rxq_ctrl; uint32_t refcnt; + int32_t ctrl_ref; if (priv->rxq_privs == NULL) return 0; @@ -2293,15 +2294,14 @@ mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx) } } else { /* Refcnt zero, closing device. */ LIST_REMOVE(rxq, owner_entry); - if (LIST_EMPTY(&rxq_ctrl->owners)) { + ctrl_ref = rte_atomic_fetch_sub_explicit(&rxq_ctrl->ctrl_ref, 1, + rte_memory_order_relaxed) - 1; + if (ctrl_ref == 1 && LIST_EMPTY(&rxq_ctrl->owners)) { if (!rxq_ctrl->is_hairpin) mlx5_mr_btree_free (&rxq_ctrl->rxq.mr_ctrl.cache_bh); - if (rte_atomic_fetch_sub_explicit(&rxq_ctrl->ctrl_ref, 1, - rte_memory_order_relaxed) == 1) { - LIST_REMOVE(rxq_ctrl, share_entry); - mlx5_free(rxq_ctrl); - } + LIST_REMOVE(rxq_ctrl, share_entry); + mlx5_free(rxq_ctrl); } dev->data->rx_queues[idx] = NULL; mlx5_free(rxq); -- 2.34.1