From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0186645EC3; Mon, 16 Dec 2024 21:33:20 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8E751402AC; Mon, 16 Dec 2024 21:33:20 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by mails.dpdk.org (Postfix) with ESMTP id A18F8402A3 for ; Mon, 16 Dec 2024 21:33:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734381200; x=1765917200; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kFYZK7ef3LnmcxN2AHbdaubuoTM6kpvYxYbMXNQV74s=; b=lZmW/W9123bVuMLwD+2fXFoEZ6TJmmdOBUdSP36+355wSUbBBA3o7390 VJjCbY2UPd5NzCytjYr4A0EXoCcvlJPG5TjzIGWQ33mWsDuuNT/OlwrwZ Ef3r86IfEj4bK3d3qmyySN4fJsikrlj1VgORnJx5ingdbhBANsBnO5VuK tN+i7uaVV9mTn3OWBskpBPQl6A1fpQm7+LGEFHrGX2WgwoZaMEZRip8ae kZwyQJRsI4Sxj5tN4DgI/INuczuBvMnWUViUe36b5vYucRAixRwLAgBH0 UwKeso7oD1fR0M/8N1EVgBQN5txFA6ubQ/IANlxzWkpjzkhejxwzbA53P Q==; X-CSE-ConnectionGUID: rDNeHn8vRECJh+NfF6Dj7Q== X-CSE-MsgGUID: Dk8XHuSCSNmvrt3jFtiW7A== X-IronPort-AV: E=McAfee;i="6700,10204,11282"; a="45274444" X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="45274444" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 12:33:19 -0800 X-CSE-ConnectionGUID: +9Zf7PieRCmHQ6DeOkbFxg== X-CSE-MsgGUID: o27AL0soQPSamLXBwh0StA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="101462117" Received: from awylogin02.aw.intel.com ([10.228.148.185]) by fmviesa003.fm.intel.com with ESMTP; 16 Dec 2024 12:33:17 -0800 From: pravin.pathak@intel.com To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, bruce.richardson@intel.com, thomas@monjalon.net, david.marchand@redhat.com, tirthendu.sarkar@intel.com, pravin.pathak@intel.com Subject: [PATCH v2] eventdev: add port attribute for independent enqueue Date: Mon, 16 Dec 2024 15:33:13 -0500 Message-Id: <20241216203313.31730-1-pravin.pathak@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20241213043300.18015-1-pravin.pathak@intel.com> References: <20241213043300.18015-1-pravin.pathak@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pravin Pathak Independent Enqueue support is added to DPDK 24.11. Adding support for RTE_EVENT_PORT_ATTR_INDEPENDENT_ENQ attribute to rte_event_port_attr_get() which was missing Signed-off-by: Pravin Pathak --- lib/eventdev/rte_eventdev.c | 8 ++++++++ lib/eventdev/rte_eventdev.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/lib/eventdev/rte_eventdev.c b/lib/eventdev/rte_eventdev.c index ca295c87c4..61cff87b63 100644 --- a/lib/eventdev/rte_eventdev.c +++ b/lib/eventdev/rte_eventdev.c @@ -880,6 +880,14 @@ rte_event_port_attr_get(uint8_t dev_id, uint8_t port_id, uint32_t attr_id, *attr_value = !!(config & RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL); break; } + case RTE_EVENT_PORT_ATTR_INDEPENDENT_ENQ: + { + uint32_t config; + + config = dev->data->ports_cfg[port_id].event_port_cfg; + *attr_value = !!(config & RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ); + break; + } default: return -EINVAL; }; diff --git a/lib/eventdev/rte_eventdev.h b/lib/eventdev/rte_eventdev.h index fabd1490db..6400d6109f 100644 --- a/lib/eventdev/rte_eventdev.h +++ b/lib/eventdev/rte_eventdev.h @@ -1318,6 +1318,10 @@ rte_event_port_quiesce(uint8_t dev_id, uint8_t port_id, * Port attribute id for the implicit release disable attribute of the port. */ #define RTE_EVENT_PORT_ATTR_IMPLICIT_RELEASE_DISABLE 3 +/** + * Port attribute id for the Independent Enqueue feature. + */ +#define RTE_EVENT_PORT_ATTR_INDEPENDENT_ENQ 4 /** * Get an attribute from a port. -- 2.26.2