From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2156E45FD7; Fri, 3 Jan 2025 16:05:15 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C2EE4066A; Fri, 3 Jan 2025 16:04:33 +0100 (CET) Received: from lf-1-33.ptr.blmpb.com (lf-1-33.ptr.blmpb.com [103.149.242.33]) by mails.dpdk.org (Postfix) with ESMTP id ED2994065C for ; Fri, 3 Jan 2025 16:04:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2403070942; d=yunsilicon.com; t=1735916664; h=from:subject: mime-version:from:date:message-id:subject:to:cc:reply-to:content-type: mime-version:in-reply-to:message-id; bh=+cVDDmdwt+pMOkITj9EqgI4A/daiOkz9rhOstXlQKhw=; b=QIGvFRmZrYQb+YcgwLWc275DswXBEwArfFErwdPOByw1//we62DwKqYjU4OaVN1XeyuPuT tq5DpvpifSVlnRPTpnQbnLnf/PhZuGS3TtblpmttDduUX/75okMSre4xKo1TQMpwkETcJs 4z/TNF8iuVvSLaK6oklS6GltwTeHr2aCN8C4iXaWMPW9XRlHNStR5wSyVmf9vAJAEznQVP uv+VDIg2ZBurdfiM859V+TJbHpQRpwY+/y2h4qpEbD+wZ5+fhyD2HWXH+IqiHb5hwWFUNI XLdAVFOYIjMKJCdqtjUxykZd5VVCRIr4+F52Q+nVFt881f0JkJsBqtf4v4fefQ== Subject: [PATCH v4 08/15] net/xsc: add Rx and Tx queue setup Date: Fri, 03 Jan 2025 23:04:21 +0800 Received: from ubuntu-liun.yunsilicon.com ([58.34.192.114]) by smtp.feishu.cn with ESMTPS; Fri, 03 Jan 2025 23:04:21 +0800 X-Original-From: WanRenyong X-Mailer: git-send-email 2.25.1 References: <20250103150404.1529663-1-wanry@yunsilicon.com> To: Message-Id: <20250103150420.1529663-9-wanry@yunsilicon.com> X-Lms-Return-Path: Content-Type: text/plain; charset=UTF-8 Cc: , , , , , , , , , From: "WanRenyong" Mime-Version: 1.0 In-Reply-To: <20250103150404.1529663-1-wanry@yunsilicon.com> Content-Transfer-Encoding: 7bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement xsc ethdev Rx and Tx queue setup functions. Signed-off-by: WanRenyong Signed-off-by: Rong Qian --- drivers/net/xsc/xsc_defs.h | 4 ++ drivers/net/xsc/xsc_ethdev.c | 83 ++++++++++++++++++++++++++++++++++++ drivers/net/xsc/xsc_rx.h | 59 +++++++++++++++++++++++++ drivers/net/xsc/xsc_rxtx.h | 49 +++++++++++++++++++++ drivers/net/xsc/xsc_tx.h | 55 ++++++++++++++++++++++++ 5 files changed, 250 insertions(+) create mode 100644 drivers/net/xsc/xsc_rx.h create mode 100644 drivers/net/xsc/xsc_tx.h diff --git a/drivers/net/xsc/xsc_defs.h b/drivers/net/xsc/xsc_defs.h index c445eadca1..6497b53e1e 100644 --- a/drivers/net/xsc/xsc_defs.h +++ b/drivers/net/xsc/xsc_defs.h @@ -38,6 +38,10 @@ #define XSC_EPAT_RSS_HASH_FUNC_FLAG (1ULL << 6) #define XSC_EPAT_HAS_PPH_FLAG (1ULL << 9) +#define XSC_MAX_DESC_NUMBER 1024 +#define XSC_SEND_WQE_DS 3 +#define XSC_ESEG_EXTRA_DATA_SIZE 48u + #define XSC_PF_TX_DB_ADDR 0x4802000 #define XSC_PF_RX_DB_ADDR 0x4804000 #define XSC_PF_CQ_DB_ADDR 0x2120000 diff --git a/drivers/net/xsc/xsc_ethdev.c b/drivers/net/xsc/xsc_ethdev.c index 81ac062862..0a16b4338c 100644 --- a/drivers/net/xsc/xsc_ethdev.c +++ b/drivers/net/xsc/xsc_ethdev.c @@ -8,6 +8,8 @@ #include "xsc_log.h" #include "xsc_defs.h" #include "xsc_ethdev.h" +#include "xsc_rx.h" +#include "xsc_tx.h" static int xsc_ethdev_rss_hash_conf_get(struct rte_eth_dev *dev, @@ -108,6 +110,85 @@ xsc_ethdev_configure(struct rte_eth_dev *dev) return -rte_errno; } +static int +xsc_ethdev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, + uint32_t socket, const struct rte_eth_rxconf *conf, + struct rte_mempool *mp) +{ + struct xsc_ethdev_priv *priv = TO_XSC_ETHDEV_PRIV(dev); + struct xsc_rxq_data *rxq_data = NULL; + uint16_t desc_n; + uint16_t rx_free_thresh; + uint64_t offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads; + + desc = (desc > XSC_MAX_DESC_NUMBER) ? XSC_MAX_DESC_NUMBER : desc; + desc_n = desc; + + if (!rte_is_power_of_2(desc)) + desc_n = 1 << rte_log2_u32(desc); + + rxq_data = rte_malloc_socket(NULL, sizeof(*rxq_data) + desc_n * sizeof(struct rte_mbuf *), + RTE_CACHE_LINE_SIZE, socket); + if (rxq_data == NULL) { + PMD_DRV_LOG(ERR, "Port %u create rxq idx %d failure", + dev->data->port_id, idx); + rte_errno = ENOMEM; + return -rte_errno; + } + rxq_data->idx = idx; + rxq_data->priv = priv; + (*priv->rxqs)[idx] = rxq_data; + + rx_free_thresh = (conf->rx_free_thresh) ? conf->rx_free_thresh : XSC_RX_FREE_THRESH; + rxq_data->rx_free_thresh = rx_free_thresh; + + rxq_data->elts = (struct rte_mbuf *(*)[desc_n])(rxq_data + 1); + rxq_data->mp = mp; + rxq_data->socket = socket; + + rxq_data->csum = !!(offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM); + rxq_data->hw_timestamp = !!(offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP); + rxq_data->crc_present = 0; + + rxq_data->wqe_n = rte_log2_u32(desc_n); + rxq_data->wqe_s = desc_n; + rxq_data->wqe_m = desc_n - 1; + + rxq_data->port_id = dev->data->port_id; + dev->data->rx_queues[idx] = rxq_data; + return 0; +} + +static int +xsc_ethdev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, + uint32_t socket, const struct rte_eth_txconf *conf) +{ + struct xsc_ethdev_priv *priv = TO_XSC_ETHDEV_PRIV(dev); + struct xsc_txq_data *txq; + uint16_t desc_n; + + desc = (desc > XSC_MAX_DESC_NUMBER) ? XSC_MAX_DESC_NUMBER : desc; + desc_n = desc; + + if (!rte_is_power_of_2(desc)) + desc_n = 1 << rte_log2_u32(desc); + + txq = rte_malloc_socket(NULL, sizeof(*txq) + desc_n * sizeof(struct rte_mbuf *), + RTE_CACHE_LINE_SIZE, socket); + txq->offloads = conf->offloads | dev->data->dev_conf.txmode.offloads; + txq->priv = priv; + txq->socket = socket; + + txq->elts_n = rte_log2_u32(desc_n); + txq->elts_s = desc_n; + txq->elts_m = desc_n - 1; + txq->port_id = dev->data->port_id; + txq->idx = idx; + + (*priv->txqs)[idx] = txq; + return 0; +} + static int xsc_ethdev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, uint32_t index) { @@ -136,6 +217,8 @@ xsc_ethdev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, uin const struct eth_dev_ops xsc_eth_dev_ops = { .dev_configure = xsc_ethdev_configure, + .rx_queue_setup = xsc_ethdev_rx_queue_setup, + .tx_queue_setup = xsc_ethdev_tx_queue_setup, .rss_hash_update = xsc_ethdev_rss_hash_update, .rss_hash_conf_get = xsc_ethdev_rss_hash_conf_get, }; diff --git a/drivers/net/xsc/xsc_rx.h b/drivers/net/xsc/xsc_rx.h new file mode 100644 index 0000000000..3653c0e335 --- /dev/null +++ b/drivers/net/xsc/xsc_rx.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2025 Yunsilicon Technology Co., Ltd. + */ + +#ifndef _XSC_RX_H_ +#define _XSC_RX_H_ + +#define XSC_RX_FREE_THRESH 32 + +struct xsc_rxq_stats { + uint64_t rx_pkts; /* Total number of rx packets */ + uint64_t rx_bytes; /* Total number of rx bytes */ + uint64_t rx_errors; /* Total number of rx error packets */ + uint64_t rx_nombuf; /* Total number of rx mbuf alloc failed */ +}; + +struct __rte_cache_aligned xsc_rxq_data { + uint16_t idx; /*QP idx */ + uint16_t port_id; + void *cq; /* CQ pointer */ + void *qp; /* QP pointer */ + uint32_t cqn; /* CQ serial number */ + uint32_t qpn; /* QP serial number */ + uint16_t wqe_s; /* Number of WQE */ + uint16_t wqe_m; /* Mask of WQE number */ + uint16_t cqe_s; /* Number of CQE */ + uint16_t cqe_m; /* Mask of CQE number */ + uint16_t wqe_n:4; /* Log 2 of WQE number */ + uint16_t sge_n:4; /* Log 2 of each WQE DS number */ + uint16_t cqe_n:4; /* Log 2 of CQE number */ + uint16_t rsv0:4; + volatile uint32_t *rq_db; + volatile uint32_t *cq_db; + uint32_t rq_ci; + uint32_t rq_pi; + uint16_t cq_ci; + uint16_t rx_free_thresh; + uint16_t nb_rx_hold; + volatile void *wqes; + union { + volatile struct xsc_cqe(*cqes)[]; + volatile struct xsc_cqe_u64(*cqes_u64)[]; + }; + struct rte_mbuf *(*elts)[]; /* Record the mbuf of wqe addr */ + struct rte_mempool *mp; + const struct rte_memzone *rq_pas; /* Palist memory */ + uint32_t socket; + struct xsc_ethdev_priv *priv; + struct xsc_rxq_stats stats; + /* attr */ + uint16_t csum:1; /* Checksum offloading enable */ + uint16_t hw_timestamp:1; + uint16_t vlan_strip:1; + uint16_t crc_present:1; /* CRC flag */ + uint16_t rss_hash:1; /* RSS hash enabled */ + uint16_t rsv1:11; +}; + +#endif /* _XSC_RX_H_ */ diff --git a/drivers/net/xsc/xsc_rxtx.h b/drivers/net/xsc/xsc_rxtx.h index 725a5f18d1..6311ed12d2 100644 --- a/drivers/net/xsc/xsc_rxtx.h +++ b/drivers/net/xsc/xsc_rxtx.h @@ -7,6 +7,39 @@ #include +#define XSC_CQE_OWNER_MASK 0x1 +#define XSC_CQE_OWNER_HW 0x2 +#define XSC_CQE_OWNER_SW 0x4 +#define XSC_CQE_OWNER_ERR 0x8 +#define XSC_OPCODE_RAW 0x7 + +struct xsc_send_wqe_ctrl_seg { + rte_le32_t msg_opcode:8; + rte_le32_t with_immdt:1; + rte_le32_t csum_en:2; + rte_le32_t ds_data_num:5; + rte_le32_t wqe_id:16; + rte_le32_t msg_len; + union { + rte_le32_t opcode_data; + struct { + rte_le16_t has_pph:1; + rte_le16_t so_type:1; + rte_le16_t so_data_size:14; + rte_le16_t rsv1:8; + rte_le16_t so_hdr_len:8; + }; + struct { + rte_le16_t desc_id; + rte_le16_t is_last_wqe:1; + rte_le16_t dst_qp_id:15; + }; + }; + rte_le32_t se:1; + rte_le32_t ce:1; + rte_le32_t rsv2:30; +} __rte_packed; + struct xsc_wqe_data_seg { union { struct { @@ -27,6 +60,17 @@ struct xsc_wqe_data_seg { }; } __rte_packed; +struct xsc_wqe { + union { + struct xsc_send_wqe_ctrl_seg cseg; + uint32_t ctrl[4]; + }; + union { + struct xsc_wqe_data_seg dseg[XSC_SEND_WQE_DS]; + uint8_t data[XSC_ESEG_EXTRA_DATA_SIZE]; + }; +} __rte_packed; + struct xsc_cqe { union { uint8_t msg_opcode; @@ -53,6 +97,11 @@ struct xsc_cqe { rte_le16_t owner:1; } __rte_packed; +struct xsc_cqe_u64 { + struct xsc_cqe cqe0; + struct xsc_cqe cqe1; +}; + struct xsc_tx_cq_params { uint16_t port_id; uint16_t qp_id; diff --git a/drivers/net/xsc/xsc_tx.h b/drivers/net/xsc/xsc_tx.h new file mode 100644 index 0000000000..11e249a4e3 --- /dev/null +++ b/drivers/net/xsc/xsc_tx.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2025 Yunsilicon Technology Co., Ltd. + */ + +#ifndef _XSC_TX_H_ +#define _XSC_TX_H_ + +#define XSC_TX_COMP_CQE_HANDLE_MAX 2 + +struct xsc_txq_stats { + uint64_t tx_pkts; /* Total number of tx packets */ + uint64_t tx_bytes; /* Total number of tx bytes */ + uint64_t tx_errors; /* Total number of tx error packets */ +}; + +struct __rte_cache_aligned xsc_txq_data { + uint16_t idx; /*QP idx */ + uint16_t port_id; + void *cq; /* CQ pointer */ + void *qp; /* QP pointer */ + uint32_t cqn; /* CQ serial number */ + uint32_t qpn; /* QP serial number */ + uint16_t elts_head; /* Current pos in (*elts)[] */ + uint16_t elts_tail; /* Counter of first element awaiting completion */ + uint16_t elts_comp; /* Elts index since last completion request */ + uint16_t elts_s; /* Number of (*elts)[] */ + uint16_t elts_m; /* Mask of (*elts)[] number */ + uint16_t wqe_ci; /* Consumer index for TXQ */ + uint16_t wqe_pi; /* Producer index for TXQ */ + uint16_t wqe_s; /* Number of WQE */ + uint16_t wqe_m; /* Mask of WQE number */ + uint16_t wqe_comp; /* WQE index since last completion request */ + uint16_t cq_ci; /* Consumer index for CQ */ + uint16_t cq_pi; /* Production index for CQ */ + uint16_t cqe_s; /* Number of CQE */ + uint16_t cqe_m; /* Mask of CQE number */ + uint16_t elts_n:4; /* Log 2 of (*elts)[] number */ + uint16_t cqe_n:4; /* Log 2 of CQE number */ + uint16_t wqe_n:4; /* Log 2 of WQE number */ + uint16_t wqe_ds_n:4; /* Log 2 of each WQE DS number */ + uint64_t offloads; /* TXQ offloads */ + struct xsc_wqe *wqes; + volatile struct xsc_cqe *cqes; + volatile uint32_t *qp_db; + volatile uint32_t *cq_db; + struct xsc_ethdev_priv *priv; + struct xsc_txq_stats stats; + uint32_t socket; + uint8_t tso_en:1; /* TSO enable 0-off 1-on */ + uint8_t rsv:7; + uint16_t *fcqs; /* Free completion queue. */ + struct rte_mbuf *elts[]; /* Storage for queued packets, for free */ +}; + +#endif /* _XSC_TX_H_ */ -- 2.25.1