From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2A1D74608E; Wed, 15 Jan 2025 09:39:19 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AA8634025F; Wed, 15 Jan 2025 09:39:18 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by mails.dpdk.org (Postfix) with ESMTP id 835484003C for ; Wed, 15 Jan 2025 09:39:16 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1736930357; x=1768466357; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Vbi6S4ZL54w7e4/CEs4GMnvkzgx5hOouoN851wls/Vs=; b=aFfT+JhfxxgTUIGwwqpcllw2Dc3nVSWZUhlBm/BEy9XTNwWCvXCJDB8H 9kZmuBqGvRxT30c+vaQ7avVQ+DKa7I1+6FZh6qjXaWOVak55uFj1DBer3 iiIct16lQS2ddFZ2H0Cu4VAo1fxldF0jidMjgp37K1UbR+z3LHS3owIsg Y0PjC5KALWjhvjRxuP4T8OeNcq1071JNOkybBn8+XP8dXhKYR7Y/MY2Ji sWuwXXjKPORild3l2u/ugc4hSy2VYjlqxXwd7i9ewwMz+eSNQdPcEqiKx t23EgMZRZyMbO58jLLxJrQ2bdTjC5nAbUf0BeFyNQSlU8cLi8pKt+aELK A==; X-CSE-ConnectionGUID: BL3xKpyhRKKP+kG+I2h21w== X-CSE-MsgGUID: TvpcvaCtQeKGi3zZjGDzhw== X-IronPort-AV: E=McAfee;i="6700,10204,11315"; a="37138285" X-IronPort-AV: E=Sophos;i="6.12,316,1728975600"; d="scan'208";a="37138285" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2025 00:39:15 -0800 X-CSE-ConnectionGUID: pUG5gydsRw6lyGv86Sx6jA== X-CSE-MsgGUID: chzdFoPUTyeEhYherrXnDw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,316,1728975600"; d="scan'208";a="105143470" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa006.jf.intel.com with ESMTP; 15 Jan 2025 00:39:13 -0800 From: Soumyadeep Hore To: bruce.richardson@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, Jun Zhang Subject: [PATCH v1] common/iavf: introduce hardware clock ID in PTP caps Date: Wed, 15 Jan 2025 07:23:23 +0000 Message-ID: <20250115072323.1117429-1-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Jun Zhang When there are at least two VFs on a single adapter and both are used in the same VM, each of them will register its own PTP clock. However, every E810/E822 adapter has only one PHC clock that we use. In order to register only one PTP clock, VFs need to identify HW and make sure they come from the same board. This patch adds a @hardware_clock_id that helps in this identification. VFs from the same board should receive the same @hardware_clock_id and VFs from two different boards should receive different IDs. Signed-off-by: Jun Zhang Signed-off-by: Soumyadeep Hore --- drivers/common/iavf/virtchnl.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/common/iavf/virtchnl.h b/drivers/common/iavf/virtchnl.h index c0d52ddd32..f4ca2cc9f0 100644 --- a/drivers/common/iavf/virtchnl.h +++ b/drivers/common/iavf/virtchnl.h @@ -2224,6 +2224,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg); #define VIRTCHNL_1588_PTP_CAP_PHC_REGS BIT(4) #define VIRTCHNL_1588_PTP_CAP_SYNCE BIT(6) #define VIRTCHNL_1588_PTP_CAP_GNSS BIT(7) +#define VIRTCHNL_1588_PTP_CAP_HARDWARE_CLOCK_ID BIT(8) struct virtchnl_phc_regs { u32 clock_hi; @@ -2248,7 +2249,8 @@ struct virtchnl_ptp_caps { u8 n_per_out; u8 n_pins; u8 tx_tstamp_format; - u8 rsvd[11]; + u8 hardware_clock_id; + u8 rsvd[10]; }; VIRTCHNL_CHECK_STRUCT_LEN(48, virtchnl_ptp_caps); -- 2.43.0